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pxr40 microcontroller reference manual devices supported: pxr4030 pxr4040 PXR40RM rev. 1 06/2011
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? freescale semiconductor, inc. 2011. all rights reserved. PXR40RM rev. 1 06/2011
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor iii table of contents chapter 1 introduction 1.1 pxr40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.2 critical performance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.1.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.1 chip-level features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.2 module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.3 high-performance e200z7 core processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.4 on-chip flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.5 general-purpose static ram (sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.6 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.7 enhanced modular input output system (timer?emios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.2.8 enhanced timing processor unit (etpu2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.2.9 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.2.10 periodic interrupt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.2.11 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.2.12 enhanced queued analog to digital converter (eqadc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.2.13 serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.14 serial communication interface module (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.15 controller area network (can) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.16 enhanced direct memory access controller (edma2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.2.17 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.2.18 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.2.19 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.2.20 frequency-modulated pll (fmpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.2.21 system integration unit (siu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.2.22 boot assist module (bam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.2.23 dual-channel flexray controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.2.24 jtag controller (jtagc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.2.25 nexus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3 developer environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 chapter 2 memory map 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 chapter 3 signal descriptions 3.1 pin function selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 pad configuration register (pcr) pa definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.2 lvds signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 external signal descriptions, pin multiplexing, and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 detailed signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.3.1 etpu signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.3.2 irq and gpio signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 3.3.3 emios signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3.3.4 eqadc signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.3.5 flexray signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.3.6 flexcan signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.3.7 esci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.3.8 dspi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3.3.9 ebi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor iv 3.3.10 reset and clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 3.3.11 jtag and nexus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 3.3.12 pmc and power/voltage signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53 chapter 4 resets 4.1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.2 rstout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.4 fmpll lock gating signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.5 reset source descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.5.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5.3 loss of lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5.4 loss of clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.5.5 core watchdog timer/debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.5.6 jtag reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.5.7 software system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.5.8 software external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.6 reset registers in the siu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.7 reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.7.1 reset configuration half word (rchw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.7.1.1 rchw overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.7.1.2 rchw structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.7.2 reset configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.7.3 reset weak pull up/down configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 chapter 5 power management controller (pmc) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1.1 analog pmc_smps features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1.2 digital pmc_smps features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 pmc operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 external signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.1 signals information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3 signals details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3.1 vddreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3.2 vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.3 vddsyn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.4 vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.5 regctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.6 regsel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.7 vdd33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.4.1 configuration register (pmc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.4.2 trimming register (pmc_trimr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4.3 status register (pmc_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.5.1 pmc internal 1.2v voltage regulator selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.5.2 pmc bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.3 vddreg lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.4 3.3v internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5.5 3.3v vddsyn lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.5.6 1.2v voltage regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.5.7 1.2v vdd lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.5.8 trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor v 5.5.9 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.10 pmc power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.11 adc test mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.7.1 regulator example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.7.2 hardware design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 chapter 6 frequency modulated pha se-locked loop (fmpll) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3.2.1 fmpll synthesizer status register (synsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3.2.2 fmpll enhanced synthesizer control register 1 (esyncr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.3.2.3 fmpll enhanced synthesizer control register 2 (esyncr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.3.2.4 fmpll synthesizer fm control register (synfmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.4.2 pll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.4.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.4.3.1 pll lock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.4.3.2 loss-of-clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.4.3.3 pll normal mode without fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.4.3.4 pll normal mode with frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.5.1 clock mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.5.1.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.5.1.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.5.2 pll loss-of-lock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.5.3 pll loss-of-clock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.6.1 loss-of-lock interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.6.2 loss-of-clock interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 chapter 7 system integration unit (siu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1.1 reset input (reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1.2 reset output (rstout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.1.3 general-purpose i/o (gpio n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.1.4 boot configuration (bootcfg[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.1.5 i/o weak pullup reset configuration (wkpcfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.1.6 external interrupt request input (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.1.1 mcu id register (siu_midr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.1.2 reset status register (siu_rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.3.1.3 system reset control register (siu_srcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.1.4 external interrupt status register (siu_eisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor vi 7.3.1.5 dma/interrupt request enable register (siu_direr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.3.1.6 dma/interrupt request select register (siu_dirsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.3.1.7 overrun status register (siu_osr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7.3.1.8 overrun request enable register (siu_orer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.3.1.9 irq rising-edge event enable register (siu_ireer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.3.1.10 irq falling-edge event enable register (siu_ifeer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7.3.1.11 irq digital filter register (siu_idfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 7.3.1.12 irq filtered input register (siu_ifir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 7.3.1.13 pad configuration registers (siu_pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 7.3.1.14 gpio pin data output registers 0?512 (siu_gpdo n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 7.3.1.15 gpio pin data input registers 0?255 (siu_gpdi n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 7.3.1.16 external irq input select register (siu_eiisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 7.3.1.17 dspi input select register (siu_disr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 7.3.1.18 eqadc command fifo trigger source select - imux select registers (siu_isel[4-7]) . . . . . . . . . . . . . . . . . . . .7-46 7.3.1.19 etpu input select register (siu_isel 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-60 7.3.1.20 eqadc advance trigger selection (siu_isel9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-61 7.3.1.21 decimation filter register 1 (siu_decfil1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-62 7.3.1.22 decimation filter register 2 (siu_decfil2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-64 7.3.1.23 chip configuration register (siu_ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-66 7.3.1.24 external clock control register (siu_eccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-67 7.3.1.25 compare b register high (siu_cbrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-68 7.3.1.26 compare b register low (siu_cbrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-69 7.3.1.27 system clock register (siu_sysdiv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-69 7.3.1.28 halt register (siu_hlt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-70 7.3.1.29 halt acknowledge register (siu_hltack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-71 7.3.1.30 parallel gpio pin data output register (siu_pgpdo0 - siu_pgpdo15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73 7.3.1.31 parallel gpio pin data input register (siu_pgpdi0 - siu_pgpdi15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-74 7.3.1.32 masked parallel gpio pin data output register (siu_mpg pdo0 - siu_mpgpdo31) . . . . . . . . . . . . . . . . . . . . . 7 -75 7.3.1.33 siu dspi serialization registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-76 7.3.1.34 serialized output signal selection registers for dspi_d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-84 7.3.1.35 gpio pin data input registers (siu_gpdi0_3 - siu_gp di508_511) - standard . . . . . . . . . . . . . . . . . . . . . . . . . . 7-86 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-87 7.4.1 pad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-87 7.4.2 reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-88 7.4.2.1 reset boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-88 7.4.2.2 reset pin glitch detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-88 7.4.3 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-88 7.4.4 gpio operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-91 7.4.5 internal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-91 7.4.5.1 eqadc external trigger input multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-92 7.4.5.2 siu external interrupt input multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93 7.4.5.3 multiplexed inputs for dspi multiple transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93 chapter 8 system information module 8.1 sim overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 sim constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 chapter 9 boot assist module (bam) 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.3 internal boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.4 serial boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.5 development bus boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor vii 9.5.1 bam program flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.5.2 bam program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5.3 reset configuration half word (rchw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.5.3.1 application start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.5.4 internal boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.5.5 serial boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.5.5.1 can controller configuration in the fixed baud rate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.5.5.2 sci controller configuration in fixed baud rate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.5.5.3 serial boot mode download protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.5.5.4 download protocol execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.5.5.5 baud rate detection procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.5.5.6 can baud rate detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.5.6 booting from the development bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.5.6.1 ebi configuration for separate address and data development bus boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.5.6.2 ebi configuration for multiplexed address and data development bus boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.5.7 enabling debug of a censored device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 chapter 10 interrupts and interr upt controller (intc) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.1.4.1 software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.1.4.2 hardware vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.1.1 intc module configuration register (intc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.1.2 intc current priority register (intc_cpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.3.1.3 intc interrupt acknowledge register (intc_iackr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.3.1.4 intc end-of-interrupt register (intc_eoir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.3.1.5 intc software set/clear interrupt registers (intc_sscir0?7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10.3.1.6 intc priority select registers (intc_psr0?479) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.4.1 interrupt request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.4.1.1 peripheral interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.4.1.2 software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.4.1.3 unique vector for each interrupt request source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.4.2 priority management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.4.2.1 current priority and preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.4.2.2 lifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10.4.3 details on handshaking with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10.4.3.1 software vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10.4.3.2 hardware vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34 10.5 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35 10.5.1 initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35 10.5.2 interrupt exception handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36 10.5.2.1 software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36 10.5.2.2 hardware vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 10.5.3 isr, rtos, and task hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 10.5.4 order of execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38 10.5.5 priority ceiling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 10.5.5.1 elevating priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 10.5.5.2 ensuring coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 10.5.6 selecting priorities according to request rates and deadlines 10-42 10.5.7 software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42 10.5.7.1 scheduling a lower priority portion of an isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42 10.5.7.2 scheduling an isr on another processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.5.8 lowering priority within an isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor viii 10.5.9 negating an interrupt request outside of its isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.5.9.1 negating an interrupt request as a side effect of an isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.5.9.2 negating multiple interrupt requests in one isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.5.9.3 proper setting of interrupt request priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.5.10examining lifo contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 chapter 11 general-purpose static ram (sram) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 sram operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.4 register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.6 sram ecc mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.6.1 access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.6.2 reset effects on sram accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.7 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.7.1 example code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 chapter 12 flash memory array and control 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.1.1.1 flash memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.1.3.1 flash user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.1.3.2 user test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.2.2.1 module configuration register (flash_ x _mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12.2.2.2 low/mid address space block locking register (flash_ x _lmlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.2.2.3 high address space block locking r egister (flash_x_hlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.2.2.4 secondary low/mid address space bloc k locking register (flash_x_slmlr) . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12.2.2.5 low/mid address space block select register (flash_x_lmsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12.2.2.6 high address space block select register (flash_x_hsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.2.2.7 address register (flash_x_ar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.2.2.8 flash bus interface configuration register (flash_biucr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.2.2.9 flash bus interface acce ss protection register (flash_biuapr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.2.2.10 flash bus interface configuration register 2 (flash_biucr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12.2.2.11 user test register 0 (flash_x_ut0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 12.2.2.12 user test register 1 (flash_x_ut1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.2.2.13 user test register 2 (flash_x_ut2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.3.1 flash user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.3.2 flash read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.3.3 read while write (rww) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.3.4 flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 12.3.4.1 software locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.3.5 flash erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.3.5.1 flash erase suspend/resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33 12.3.6 flash shadow block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 12.3.7 flash reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 chapter 13 core (e200z7) overview 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor ix 13.2 register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.1 cache overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.2 cache registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.2.1 l1 cache control and status register 0 (l1csr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.2.2 l1 cache control and status register 1 (l1csr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.3.2.3 l1finv0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.3.2.4 l1finv1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.4 mmu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.4.2 mmu instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.4.3 tlb read entry instruction (tlbre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.4.4 tlb write entry instruction (tlbwe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.5 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.4.5.1 dear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.4.5.2 mmu control and status register 0 (mmucsr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.4.5.3 mmu assist registers (mas) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.5 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 13.5.1 exception syndrome register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.6 machine state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22 13.6.1 machine check syndrome register (mcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24 13.7 interrupt vector prefix registers (ivpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27 13.8 interrupt vector offset registers (ivorxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27 13.9 interrupt definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 13.9.1 critical input interrupt (ivor0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 13.9.2 machine check interrupt (ivor1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 13.9.2.1 machine check causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 13.9.2.2 machine check interrupt actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 13.9.3 data storage interrupt (ivor2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30 13.9.4 instruction storage interrupt (ivor3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.9.5 external input interrupt (ivor4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.9.6 alignment interrupt (ivor5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32 13.9.7 program interrupt (ivor6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33 13.9.8 floating-point unavailable interrupt (ivor7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34 13.9.9 system call interrupt (ivor8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34 13.9.10auxiliary processor unavailable interrupt (ivor9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35 13.9.11decrementer interrupt (ivor10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35 13.9.12fixed-interval timer interrupt (ivor11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35 13.9.13watchdog timer interrupt (ivor12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36 13.9.14data tlb error interrupt (ivor13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37 13.9.15instruction tlb error interrupt (ivor14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37 13.9.16debug interrupt (ivor15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38 13.9.17spe/efpu apu unavailable interrupt (ivor32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 13.9.18embedded floating-point data interrupt (ivor33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40 13.9.19embedded floating-point round interrupt (ivor34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41 13.9.20performance monitor interrupt (ivor35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41 13.10 special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42 13.10.1wait apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42 13.10.2volatile context save/restore apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-43 13.10.3performance monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-43 chapter 14 amba crossbar switch (xbar) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.1.4.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.1.4.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor x 14.2.1.1 master priority registers (xbar_mprn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2.1.2 slave general-purpose control registers (xbar_sgpcrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.3.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.3.3 master ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.3.4 slave ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.3.5 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.3.6 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.3.6.1 fixed priority operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 14.3.6.2 round-robin priority operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 chapter 15 peripheral bridge (pbridge) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.2 access protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3 memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.1.1 master privilege control register (pbridge_x_mpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.1.2 peripheral access control regist ers (pbridge_x_pacr) and off-platform peripheral access control registers (pbridge_x_opacr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.4.1 access support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.4.2 peripheral write buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.4.2.1 read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.4.2.2 write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.4.2.3 buffered write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.4.3 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 chapter 16 memory protection unit (mpu) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.2.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.2.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.2.2.1 mpu control/error status register (mpu_cesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.2.2.2 mpu error address register, mpu port 0 to 3 (mpu_ear n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.2.2.3 mpu error detail register, mpu port 0 to 3 (mpu_edr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.2.2.4 mpu region descriptor n (mpu_rgd n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.2.2.5 mpu region descriptor alternate access control n (mpu_rgdaac n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.3.1 access evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.3.1.1 access evaluation?hit determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.3.1.2 access evaluation?privilege violati on determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.3.2 ahb error terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.4 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 chapter 17 error correction status module (ecsm) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xi 17.2 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2.2.1 processor core type (ecsm_pct) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.2 revision (ecsm_rev) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.3 peripheral module configuration (ecsm_imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.4 miscellaneous reset status register (ecsm_mrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.5 ecc configuration register (ecsm_ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.2.2.6 ecc status register (ecsm_esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.2.2.7 ecc error generation register (ecsm_eegr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.2.2.8 flash ecc address register (ecsm_fear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.2.2.9 flash ecc master number register (ecsm_femr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.2.2.10 flash ecc attributes register (ecsm_feat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.2.2.11 flash ecc data register (ecsm_fedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.2.2.12 ram ecc address register (ecsm_rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.2.2.13 ram ecc syndrome register (ecsm_resr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17.2.2.14 ram ecc master number register (ecsm_remr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17.2.2.15 ram ecc attributes register (ecsm_reat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17.2.2.16 ram ecc data register (ecsm_redr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 chapter 18 software watchdog timer (swt) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.2.1 swt control register (swt_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.2.2 swt interrupt register (swt_ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.3.2.3 swt time-out register (swt_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.3.2.4 swt window register (swt_wn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.3.2.5 swt service register (swt_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.3.2.6 swt counter output register (swt_co) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.3.2.7 swt service key register (swt_sk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 chapter 19 system timer module (stm) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3.2.1 stm control register (stm_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3.2.2 stm count register (stm_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.2.3 stm channel control register (stm_ccrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.2.4 stm channel interrupt register (stm_cirn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.3.2.5 stm channel compare register (stm_cmpn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xii chapter 20 periodic interrupt timer (pit_rti) 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.2.1 pit module control register (pit_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.2.2 timer load value register (pit_rti_ldval, pit_chn_ldval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.3.2.3 current timer value register (pit_rti_cval, pit_chn_cval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.3.2.4 timer control register (pit_rti_tctrl, pit_chn_tctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.3.2.5 timer flag register (pit_rti_tflg, pit_chn_tflg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.4.1.1 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.4.1.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 20.4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5.1 example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5.2 low power mode ? using the rti for system wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5.2.1 low power mode without rti wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.5.2.2 low power mode with rti wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 chapter 21 enhanced direct memory access controller (edma) 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.1.3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.1.3.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 21.3.2.1 edma control register (edma_ x _mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 21.3.2.2 edma error status register (edma _x _esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.3.2.3 edma enable request registers (edma_a_erqrh, edma_ x _erqrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19 21.3.2.4 edma enable error interrupt registers (edma_a_eeirh, edma _x _eeirl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.3.2.5 edma set enable request register (edma _x _serqr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.3.2.6 edma clear enable request register (edma _x _cerqr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 21.3.2.7 edma set enable error interrupt register (edma _x _seeir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25 21.3.2.8 edma clear enable error interrupt register (edma _x _ceeir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 21.3.2.9 edma clear interrupt request register (edma _x _cirqr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 21.3.2.10 edma clear error register (edma _x _cer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 21.3.2.11 edma set start bit register (edma _x _ssbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 21.3.2.12 edma clear done status bit register (edma _x _cdsbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 21.3.2.13 edma interrupt request registers (edma_a_irqrh, edma _x _irqrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30 21.3.2.14 edma error registers (edma_ x _erh, edma _x _erl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.3.2.15 dma hardware request status (edma_a_hrsh, edma _x _hrsl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.3.2.16 edma global write registers (edma_ x _gwrh and edma_ x _gwrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.3.2.17 edma channel n priority registers (edma _x _cpr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.3.2.18 transfer control descriptor (tcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-34 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-40 21.4.1 edma basic data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42 21.5 initialization / applic ation information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 21.5.1 edma initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xiii 21.5.2 dma programming errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 21.5.3 dma request assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-48 21.5.4 dma arbitration mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52 21.5.4.1 fixed-group arbitration, fixed-channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52 21.5.4.2 round-robin group arbitration, fixed- channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52 21.5.4.3 round-robin group arbitration, round- robin channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52 21.5.4.4 fixed-group arbitration, round-robi n channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53 21.5.5 dma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53 21.5.5.1 single request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53 21.5.5.2 multiple requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-54 21.5.5.3 modulo feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-56 21.5.6 tcd status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-56 21.5.6.1 minor loop complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-56 21.5.6.2 active channel tcd reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-57 21.5.6.3 preemption status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-57 21.5.7 channel linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-58 21.5.8 dynamic programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-59 21.5.8.1 dynamic channel linking and dynamic scatter-gather operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-59 chapter 22 flexray communication controller (flexray) 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.2 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.3 color coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.4 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.5 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.1.6.1 disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.1.6.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.2.1.1 fr_a_rx ? receive data channel a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.2.1.2 fr_a_tx ? transmit data channel a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.2.1.3 fr_a_tx_en ? transmit enable channel a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.2.1.4 fr_b_rx ? receive data channel b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.2.1.5 fr_b_tx ? transmit data channel b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.2.1.6 fr_b_tx_en ? transmit enable channel b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.2.1.7 fr_dbg[3], fr_dbg[2], fr_dbg[1], fr_dbg[0] ? strobe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.3 controller host interface clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.4 protocol engine clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.4.1 oscillator clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.4.2 pll clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.5.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.5.2.1 register reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.5.2.2 register write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.5.2.3 module version register (mvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 22.5.2.4 module configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 22.5.2.5 system memory base address register (symbadr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 22.5.2.6 strobe signal control register (stbscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 22.5.2.7 message buffer data size register (mbdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17 22.5.2.8 message buffer segment size and utilization register (mbssutr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.5.2.9 protocol operation control register (pocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.5.2.10 global interrupt flag and enable register (gifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20 22.5.2.11 protocol interrupt flag register 0 (pifr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 22.5.2.12 protocol interrupt flag register 1 (pifr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.5.2.13 protocol interrupt enable register 0 (pier0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25 22.5.2.14 protocol interrupt enable register 1 (pier1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26 22.5.2.15 chi error flag register (chierfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27 22.5.2.16 message buffer interrupt vector register (mbivec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 22.5.2.17 channel a status error counter register (casercr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xiv 22.5.2.18 channel b status error counter register (cbsercr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 22.5.2.19 protocol status register 0 (psr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31 22.5.2.20 protocol status register 1 (psr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32 22.5.2.21 protocol status register 2 (psr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-33 22.5.2.22 protocol status register 3 (psr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35 22.5.2.23 macrotick counter register (mtctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36 22.5.2.24 cycle counter register (cyctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37 22.5.2.25 slot counter channel a register (sltctar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37 22.5.2.26 slot counter channel b register (sltctbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38 22.5.2.27 rate correction value register (rtcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38 22.5.2.28 offset correction value register (ofcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 22.5.2.29 combined interrupt flag register (cifrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 22.5.2.30 system memory access time-out register (symator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-40 22.5.2.31 sync frame counter register (sfcntr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-41 22.5.2.32 sync frame table offset register (sftor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-41 22.5.2.33 sync frame table configuration, control, status register (sftccsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-42 22.5.2.34 sync frame id rejection filter register (sfidrfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-43 22.5.2.35 sync frame id acceptance filter value register (sfidafvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 22.5.2.36 sync frame id acceptance filter mask register (sfidafmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 22.5.2.37 network management vector registers (nmvr0?nmvr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 22.5.2.38 network management vector length register (nmvlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-45 22.5.2.39 timer configuration and control register (ticcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-46 22.5.2.40 timer 1 cycle set register (ti1cysr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-47 22.5.2.41 timer 1 macrotick offset register (ti1mtor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-47 22.5.2.42 timer 2 configuration register 0 (ti2cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-48 22.5.2.43 timer 2 configuration register 1 (ti2cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-48 22.5.2.44 slot status selection register (sssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-49 22.5.2.45 slot status counter condition register (ssccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 22.5.2.46 slot status registers (ssr0?ssr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-52 22.5.2.47 slot status counter registers (sscr0?sscr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-53 22.5.2.48 mts a configuration register (mtsacfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54 22.5.2.49 mts b configuration register (mtsbcfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54 22.5.2.50 receive shadow buffer index register (rsbir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-55 22.5.2.51 receive fifo system memory base address register (rfsymbadr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-55 22.5.2.52 receive fifo periodic timer register (rfptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-56 22.5.2.53 receive fifo watermark and selection register (rfwmsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-57 22.5.2.54 receive fifo start index register (rfsir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-57 22.5.2.55 receive fifo depth and size register (rfdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-58 22.5.2.56 receive fifo a read index register (rfarir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-58 22.5.2.57 receive fifo b read index register (rfbrir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-59 22.5.2.58 receive fifo fill level and pop count register (rfflpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-59 22.5.2.59 receive fifo message id acceptance filter value register (rfmidafvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-60 22.5.2.60 receive fifo message id acceptance filter mask register (rfmiafmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-60 22.5.2.61 receive fifo frame id rejection filter value register (rffidrfvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-61 22.5.2.62 receive fifo frame id rejection filter mask register (rffidrfmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-61 22.5.2.63 receive fifo range filter configuration register (rfrfcfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-61 22.5.2.64 receive fifo range filter control register (rfrfctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-62 22.5.2.65 last dynamic transmit slot channel a register (ldtxslar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-63 22.5.2.66 last dynamic transmit slot channel b register (ldtxslbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-63 22.5.2.67 protocol configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-64 22.5.2.68 message buffer configuration, cont rol, status registers (mbccsrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-72 22.5.2.69 message buffer cycle counter filter registers (mbccfrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-74 22.5.2.70 message buffer frame id registers (mbfidrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-75 22.5.2.71 message buffer index registers (mbidxrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-75 22.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-76 22.6.1 message buffer concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-76 22.6.2 physical message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-76 22.6.2.1 message buffer header field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-76 22.6.2.2 message buffer data field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-77 22.6.3 message buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-77 22.6.3.1 individual message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-77 22.6.3.2 receive shadow buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-79 22.6.3.3 receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-79
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xv 22.6.3.4 message buffer configuration and control data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-81 22.6.3.5 individual message buffer control data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-82 22.6.3.6 receive shadow buffer configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-82 22.6.3.7 receive fifo control and configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-82 22.6.4 flexray memory layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-83 22.6.4.1 flexray memory layout (mcr[fam] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-83 22.6.4.2 flexray memory layout (mcr[fam] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-84 22.6.4.3 message buffer header area (mcr[fam] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-85 22.6.4.4 message buffer header area (mcr[fam] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-86 22.6.4.5 fifo message buffer header area (mcr[fam] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-86 22.6.4.6 message buffer data area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-86 22.6.4.7 sync frame table area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-86 22.6.5 physical message buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-86 22.6.5.1 message buffer protection and data c onsistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-86 22.6.5.2 message buffer header field descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-87 22.6.5.3 message buffer data field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-94 22.6.6 individual message buffer functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-95 22.6.6.1 individual message buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-96 22.6.6.2 single transmit message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-97 22.6.6.3 receive message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-105 22.6.6.4 double transmit message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-111 22.6.7 individual message buffer search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-120 22.6.7.1 message buffer cycle counter filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-121 22.6.7.2 message buffer channel assignment cons istency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-122 22.6.7.3 node related slot multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-122 22.6.7.4 message buffer search error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-122 22.6.8 individual message buffer reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-122 22.6.8.1 reconfiguration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-123 22.6.9 receive fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-123 22.6.9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-124 22.6.9.2 fifo configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-124 22.6.9.3 fifo periodic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-125 22.6.9.4 fifo reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-125 22.6.9.5 fifo almost-full interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-125 22.6.9.6 fifo overflow error generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-125 22.6.9.7 fifo message access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-125 22.6.9.8 fifo update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-126 22.6.9.9 fifo filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-126 22.6.10channel device modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-129 22.6.10.1 dual channel device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-129 22.6.10.2 single channel device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-130 22.6.11external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-131 22.6.12sync frame id and sync frame deviation tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-132 22.6.12.1 sync frame id table content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-133 22.6.12.2 sync frame deviation table content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-133 22.6.12.3 sync frame id and sync frame deviation table setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-133 22.6.12.4 sync frame id and sync frame devi ation table generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-134 22.6.12.5 sync frame table access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-135 22.6.13mts generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-135 22.6.14key slot transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-136 22.6.14.1 key slot assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-136 22.6.14.2 key slot transmission in poc:startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-136 22.6.14.3 key slot transmission in poc:normal active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-136 22.6.15sync frame filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-136 22.6.15.1 sync frame acceptance filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-137 22.6.15.2 sync frame rejection filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-137 22.6.16strobe signal support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-137 22.6.16.1 strobe signal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-137 22.6.16.2 strobe signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-138 22.6.17timer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-138 22.6.17.1 absolute timer t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-139 22.6.17.2 absolute / relative timer t2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-139 22.6.18slot status monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-140
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xvi 22.6.18.1 channel status error counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-141 22.6.18.2 protocol status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-142 22.6.18.3 slot status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-142 22.6.18.4 slot status counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-142 22.6.18.5 message buffer slot status field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-143 22.6.19system bus access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-143 22.6.19.1 system bus illegal address access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-144 22.6.19.2 system bus access timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-144 22.6.19.3 continue after system bus failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-144 22.6.19.4 freeze after system bus failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-144 22.6.20interrupt support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-144 22.6.20.1 individual interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-144 22.6.20.2 combined interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-145 22.6.21lower bit rate support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-148 22.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-149 22.7.1 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-149 22.7.1.1 module initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-149 22.7.1.2 protocol initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-150 22.7.2 shut down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-150 22.7.3 number of usable message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-150 22.7.4 protocol control command execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-151 22.7.5 message buffer search on simple mess age buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-152 22.7.5.1 simple message buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-152 22.7.5.2 behavior in static segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-154 22.7.5.3 behavior in dynamic segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-154 chapter 23 enhanced modular input/ou tput subsystem (emios200) 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.4 emios200 channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2.1 emios[ n ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2.2 output disable input ? emios200 output disable input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.3.2.1 emios200 module configuration regist er (emios_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.3.2.2 emios200 global flag register (emios_gfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.3.2.3 emios200 output update disable register (emios_oudr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 23.3.2.4 emios200 a register (emios_cadr[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 23.3.2.5 emios200 b register (emios_cbdr[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 23.3.2.6 emios200 counter register (emios_ccntr[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.3.2.7 emios200 control register (emios_ccr[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.3.2.8 emios200 status register (emios_csr[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 23.3.2.9 emios200 alternate a register (emios_alta[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-19 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20 23.4.1 unified channel (uc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20 23.4.1.1 unified channel modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 23.4.1.2 input programmable filter (ipf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-62 23.4.1.3 clock prescaler (cp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-62 23.4.1.4 effect of freeze on the unified channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-63 23.4.2 ip bus interface unit (biu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-63 23.4.2.1 effect of freeze on the biu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-63 23.4.3 stac client submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-63 23.4.3.1 effect of freeze on the stac client submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 23.4.4 global clock prescaler submodule (gcp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 23.4.4.1 effect of freeze on the gcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 23.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 23.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xvii 23.7 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 23.7.1 considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 23.7.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 23.7.3 time base generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 23.7.4 coherent accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-69 chapter 24 flexcan module 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.2 flexcan module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.2.1 can rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.2.2 can tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.3 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.3.1 flexcan memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.3.2 message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.3.3 rx fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.3.4.1 module configuration register (flexcan_x_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.3.4.2 control register (flexcan_x_ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18 24.3.4.3 free running timer (flexcan_x_timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.3.4.4 rx global mask (flexcan_x_rxgmask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22 24.3.4.5 rx 14 mask (flexcan_x_rx14mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22 24.3.4.6 rx 15 mask (flexcan_x_rx15mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24.3.4.7 error counter register (flexcan_x_ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24.3.4.8 error and status register (flexcan_x_esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25 24.3.4.9 interrupt masks 2 register (flexcan_x_imask2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.3.4.10 interrupt masks 1 register (flexcan_x_imask1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.3.4.11 interrupt flags 2 register (flexcan_x_iflag2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29 24.3.4.12 interrupt flags 1 register (flexcan_x_iflag1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30 24.3.4.13 rx individual mask registers (rximr0?rximr63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24.4.2 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.4.3 arbitration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.4.4 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24.4.5 matching process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36 24.4.6 data coherence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 24.4.6.1 transmission abort mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 24.4.6.2 message buffer deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38 24.4.6.3 message buffer lock mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39 24.4.7 rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39 24.4.7.1 precautions when using global mask and individual mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-40 24.4.8 can protocol related features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41 24.4.8.1 remote frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41 24.4.8.2 overload frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41 24.4.8.3 time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42 24.4.8.4 protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42 24.4.8.5 arbitration and matching timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-44 24.4.9 modes of operation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-45 24.4.9.1 freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-45 24.4.9.2 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-46 24.4.9.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-46 24.4.10interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-46 24.4.11bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-47 24.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-48 24.5.1 flexcan initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-48 24.5.2 flexcan addressing and ram size configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-49
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xviii chapter 25 deserial serial peripheral interface (dspi) 25.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.1.3 dspi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.1.3.1 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.1.3.2 dsi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.1.3.3 csi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.1.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.1.4.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.1.4.3 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.1.4.4 external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.1.4.5 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.2.2 detailed signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.2.2.1 pcs[0]/ss ? peripheral chip select/slave select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.2.2.2 pcs[1] - pcs[3] ? peripheral chip selects 1 - 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.2.2.3 pcs[4]/mtrig ? peripheral chip select 4/master trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.2.2.4 pcs[5]/pcss ? peripheral chip select 5/peripheral chip select strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.2.2.5 sin ? serial input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.2.2.6 sout ? serial output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.2.2.7 sck ? serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.2.2.8 ht ? hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.3.2.1 dspi module configuration register (dspi_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.3.2.2 dspi transfer count register (dspi_tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 25.3.2.3 dspi clock and transfer attributes registers 0?7 (dspi_ctar0?dspi_ctar7) . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.3.2.4 dspi status register (dspi_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 25.3.2.5 dspi dma/interrupt request select and enable register (dspi_rser) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.3.2.6 dspi push tx fifo register (dspi_pushr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.3.2.7 dspi pop rx fifo register (dspi_popr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.3.2.8 dspi transmit fifo registers 0?3 (dspi_txfr0?dspi_txfr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24 25.3.2.9 dspi receive fifo registers 0?3 (dspi_rxfr0?dspi_rxfr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25 25.3.2.10 dspi dsi configuration register (dspi_dsicr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25 25.3.2.11 dspi dsi serialization data register (dspi_sdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27 25.3.2.12 dspi dsi alternate serialization data register (dspi_asdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28 25.3.2.13 dspi dsi transmit comparison register (dspi_compr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29 25.3.2.14 dspi dsi deserialization data register (dspi_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29 25.3.2.15 dspi dsi configuration register 1 (dspi_dsicr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30 25.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31 25.4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 25.4.1.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 25.4.1.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 25.4.1.3 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34 25.4.1.4 external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34 25.4.1.5 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34 25.4.2 start and stop of dspi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34 25.4.3 serial peripheral interface (spi) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 25.4.3.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 25.4.3.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 25.4.3.3 fifo disable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 25.4.3.4 transmit first in first out (tx fi fo) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 25.4.3.5 receive first in first out (rx fifo ) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37 25.4.4 deserial serial interface (dsi) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-38 25.4.4.1 dsi master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-38 25.4.4.2 dsi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39 25.4.4.3 dsi serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xix 25.4.4.4 dsi deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-40 25.4.4.5 dsi transfer initiation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-40 25.4.4.6 multiple transfer operation (mto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41 25.4.5 combined serial interface (csi) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.5.1 csi serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44 25.4.5.2 csi deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45 25.4.6 dspi baud rate and clock delay generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.6.1 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.6.2 pcs to sck delay (t csc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.6.3 after sck delay (t asc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.6.4 delay after transfer (tdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-47 25.4.6.5 peripheral chip select strobe enable (pcss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48 25.4.7 transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.7.1 classic spi transfer format (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.7.2 classic spi transfer format (cpha = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-50 25.4.7.3 modified spi/dsi transfer format (mtfe = 1, cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51 25.4.7.4 modified spi/dsi transfer format (mtfe = 1, cpha = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-52 25.4.7.5 continuous selection format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-53 25.4.8 continuous serial communications clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-55 25.4.9 timed serial bus (tsb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-56 25.4.9.1 pcs switch over timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-58 25.4.9.2 tsb command frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-59 25.4.9.3 tsb data frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-59 25.4.10interrupts/dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-60 25.4.10.1 end of queue interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-60 25.4.10.2 transmit fifo fill interrupt or dma request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-60 25.4.10.3 transfer complete interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-61 25.4.10.4 transmit fifo underflow interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-61 25.4.10.5 receive fifo drain interrupt or dma request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-61 25.4.10.6 receive fifo overflow interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-61 25.4.11power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-61 25.4.11.1 stop mode (external stop mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-62 25.4.11.2 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-62 25.4.11.3 slave bus signal gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-63 25.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-63 25.5.1 how to change queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-63 25.5.2 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-64 25.5.3 delay settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-64 25.5.4 calculation of fifo pointer addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-65 25.5.4.1 address calculation for the first-in entry and last-in en try in the tx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-66 25.5.4.2 address calculation for the first-in entry and last-in en try in the rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-66 chapter 26 enhanced serial communication interface (esci) 26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.1 bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.2 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.3 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.4 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.1.5 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.6.1 sci mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.6.2 lin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.6.3 disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.6.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.2.1.1 esci transmit pin (txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.2.1.2 esci receive pin (rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3.2.1 baud rate register (esci_brr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xx 26.3.2.2 control register 1 (esci_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.3.2.3 control register 2 (esci_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10 26.3.2.4 sci data register (esci_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 26.3.2.5 interrupt flag and status register 1 (esci_ifsr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13 26.3.2.6 interrupt flag and status register 2 (esci_ifsr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14 26.3.2.7 lin control register 1 (esci_lcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15 26.3.2.8 lin control register 2 (esci_lcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17 26.3.2.9 lin transmit register (esci_ltr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17 26.3.2.10 lin receive register (esci_lrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19 26.3.2.11 lin crc polynomial register (esci_lpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19 26.3.2.12 control register 3 (esci_cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19 26.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 26.4.1 module control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 26.4.2 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 26.4.2.1 data frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 26.4.2.2 break character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 26.4.2.3 idle character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24 26.4.3 baud rate and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24 26.4.3.1 module clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25 26.4.3.2 transmitter clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25 26.4.3.3 receiver clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25 26.4.4 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26 26.4.4.1 faster receiver tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26 26.4.4.2 slower receiver tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.4.5 sci mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 26.4.5.1 sci mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 26.4.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 26.4.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32 26.4.5.4 reception error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-41 26.4.5.5 multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42 26.4.6 lin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43 26.4.6.1 lin mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43 26.4.6.2 lin frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44 26.4.6.3 lin tx frame generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44 26.4.6.4 lin rx frame generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-46 26.4.6.5 lin error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-48 26.4.6.6 lin wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-50 26.4.6.7 lin protocol engine reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-51 26.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-51 26.4.7.1 interrupt flags and enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-51 26.4.7.2 interrupt request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-52 26.5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-52 26.5.1 sci data frames separated by preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-52 chapter 27 enhanced queued analog-to- digital converter (eqadc) 27.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1.1 analog to digital conversion sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.3.2 streaming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.3.3 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.3.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.4.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.5 pin mapping to channel mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 27.6 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13 27.6.1 eqadc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13 27.6.2 eqadc register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxi 27.6.2.1 eqadc module configuration register (eqadc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16 27.6.2.2 eqadc external trigger digital filt er register (eqadc_etdfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17 27.6.2.3 eqadc cfifo push registers (eqadc_cfpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18 27.6.2.4 eqadc result fifo pop registers (eqadc_rfpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19 27.6.2.5 eqadc cfifo control registers (eqadc_cfcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19 27.6.2.6 eqadc interrupt and dma control registers (eqadc_idcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-22 27.6.2.7 eqadc fifo and interrupt status regi sters (eqadc_fisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-25 27.6.2.8 eqadc cfifo transfer counter registers (eqadc_cftcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-29 27.6.2.9 eqadc cfifo status snapshot registers (eqadc_cfssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30 27.6.2.10 eqadc cfifo status register (eqadc_cfsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-32 27.6.2.11 eqadc red line client configurati on register (eqadc_redlccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-33 27.6.2.12 eqadc cfifo registers (eqadc_cfxrw) (x=0, ..,5; w=0, .., 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-34 27.6.2.13 eqadc cfifo0 extension registers (eqadc_cf0erw) (w=0, .., 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-37 27.6.2.14 eqadc rfifo registers (eqadc_rfxrw) (x=0, .., 5; w=0, .., 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-37 27.6.3 on-chip adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-40 27.6.3.1 adc0/1 control registers (adc0_cr and adc1_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-42 27.6.3.2 adc time stamp control register (adc_tscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-46 27.6.3.3 adc time base counter registers (adc_tbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-47 27.6.3.4 adc0/1 gain calibration constant registers (adc0_gccr and adc1_gccr) . . . . . . . . . . . . . . . . . . . . . . . . . 27-47 27.6.3.5 adc0/1 offset calibration constant registers (adc0_occr and adc1_occr) . . . . . . . . . . . . . . . . . . . . . . . . 27-48 27.6.3.6 alternate configuration 1-8 control registers (adc_acr1-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-49 27.6.3.7 adc0/1 alternate gain registers (adc0_agr1-2 and adc1_agr1-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-51 27.6.3.8 adc0/1 alternate offset register (adc0_aor1-2 and adc1_aor1-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52 27.6.3.9 adc pull up/down control register x (adc_pudcrx, x=0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52 27.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-53 27.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-53 27.7.2 data flow in eqadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-54 27.7.2.1 overview and basic terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-54 27.7.2.2 message format in eqadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-56 27.7.3 command/result queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-67 27.7.4 eqadc command fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-67 27.7.4.1 cfifo basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-67 27.7.4.2 cfifo0 streaming mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-70 27.7.4.3 cfifo common prioritization and command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-75 27.7.4.4 cfifo prioritization in abort mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-77 27.7.4.5 hardware trigger event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-78 27.7.4.6 cfifo scan trigger modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-78 27.7.4.7 cfifo and trigger status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-83 27.7.5 eqadc result fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-91 27.7.5.1 rfifo basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-91 27.7.5.2 distributing result data into rfifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-94 27.7.6 on-chip adc configuration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-95 27.7.6.1 enabling and disabling the on-chip adcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-95 27.7.6.2 adc clock and conversion speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-96 27.7.6.3 time stamp feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-98 27.7.6.4 adc pre-gain feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-98 27.7.6.5 adc resolution selection feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-98 27.7.6.6 adc calibration feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-99 27.7.6.7 adc control logic overview and command execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-101 27.7.7 internal/external multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-104 27.7.7.1 channel assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-104 27.7.7.2 external multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-107 27.7.8 eqadc dma/interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-110 27.7.9 analog sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-113 27.7.9.1 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-113 27.8 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-116 27.8.1 multiple queues control setup example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-116 27.8.1.1 eqadc initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-117 27.8.1.2 configuring eqadc for applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-118 27.8.2 eqadc/dmac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-120 27.8.2.1 cqueue/cfifo transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-120 27.8.2.2 rqueue/rfifo transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-121 27.8.3 sending immediate command setup example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-122
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxii 27.8.4 modifying queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-123 27.8.5 cqueue and rqueues usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-124 27.8.6 adc result calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-126 27.8.6.1 mac configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-126 27.8.6.2 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-127 27.8.6.3 quantization error reduction during ca libration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-127 27.8.7 eqadc versus qadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-128 chapter 28 decimation filter 28.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.1.2 modes of operation overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.1.2.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.1.2.2 freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.1.2.3 disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.2 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.2.1 decimation filter memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.2.2 decimation filter register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.2.2.1 decimation filter module configurati on register (decfilt_x_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.2.2.2 decimation filter module status register (decfilt_x_msr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11 28.2.2.3 decimation filter module extended conf iguration register (decfilt_x_mxcr) . . . . . . . . . . . . . . . . . . . . . . . . . 28-13 28.2.2.4 decimation filter module extended status register (decfi lt_x_mxsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16 28.2.2.5 decimation filter interface input buffer register (decfi lt_x_ib) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19 28.2.2.6 decimation filter interface output buffer register (decfilt_x_ob) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20 28.2.2.7 decimation filter coefficient n register (decfilt_x_coefn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20 28.2.2.8 decimation filter tapn register (decfilt_x_tapn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-21 28.2.2.9 decimation filter interface enhanced debug input data regi ster (decfilt_x_edid) . . . . . . . . . . . . . . . . . . . . . 28-22 28.2.2.10 decimation filter final integration value register (decfilt_x_fintval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.2.2.11 decimation filter final integration count value register (decfilt_x_fintcnt) . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.2.2.12 decimation filter current integration value register (decfilt_x_cintval) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.2.2.13 decimation filter current integration count value register (decfilt_x_cintcnt) . . . . . . . . . . . . . . . . . . . . . . 28-24 28.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25 28.3.1 decimation filter input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25 28.3.1.1 input buffer overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25 28.3.2 decimation filter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-26 28.3.2.1 output buffer overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-26 28.3.3 bypass operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 28.3.4 filter prefill control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 28.3.5 timestamp data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29 28.3.5.1 timestamp data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29 28.3.5.2 timestamp management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29 28.3.6 flush command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29 28.3.7 soft reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-30 28.3.8 freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-30 28.3.9 filter implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-30 28.3.10rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31 28.3.11saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32 28.3.12interrupts and dma overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32 28.3.12.1 input buffer interrupt and dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33 28.3.12.2 output buffer interrupt and dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28.3.12.3 integrator interrupt and dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-35 28.3.13integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-35 28.3.13.1 integrator inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-35 28.3.13.2 integrator output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-36 28.3.13.3 integrator reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-37 28.3.13.4 integrator enabling and halting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-38 28.3.13.5 integrator exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-38 28.3.14cascade mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39 28.3.14.1 example configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41 28.3.14.2 cascade freeze, stop, and configuration change procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42 28.3.15enhanced debug monitor description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxiii 28.4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43 28.4.1 eqadc configuration for decimation filter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43 28.4.1.1 eqadc configuration / decimation filter input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43 28.4.1.2 eqadc configuration / decimator output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45 28.5 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46 28.5.1 iir filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46 28.5.2 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-49 28.5.2.1 use case 1 - normal mode, adc conversion and filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-50 28.5.2.2 use case 2 - input/output from/to the cpu/dma, stored data filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-52 chapter 29 enhanced time processing unit (etpu2) 29.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.1.1.1 etpu engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.1.2.1 etpu feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.1.2.2 etpu enhancements over tpu3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.1.2.3 etpu2 enhancements over etpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.1.3.1 etpu mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12 29.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13 29.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13 29.2.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13 29.2.2.1 etpu channel output signals [0-31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13 29.2.2.2 etpu channel input signals [0-31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13 29.2.2.3 time base clock signal ? tcrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14 29.2.2.4 etpu channel output disable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14 29.2.3 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15 29.2.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15 29.2.5 system configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19 29.2.5.1 etpumcr - etpu module configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19 29.2.5.2 etpucdcr - etpu coherent dual-parameter controller register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-22 29.2.5.3 etpumisccmpr - etpu misc compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-23 29.2.5.4 etpuscmoffdatar - etpu scm off-range data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-24 29.2.5.5 etpuecr - etpu engine configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-24 29.2.6 time base registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-27 29.2.6.1 etputbcr - etpu time base configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-28 29.2.6.2 etputb1r - etpu time base 1 (tcr1) visibility register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-31 29.2.6.3 etputb2r - etpu time base 2 (tcr2) visibility register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-31 29.2.6.4 etpuredcr - etpu stac configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-32 29.2.7 engine related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-33 29.2.7.1 etpuwdtr - etpu watchdog timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-33 29.2.7.2 etpuidler - etpu idle register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-34 29.2.8 channel registers layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-34 29.2.9 global channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-35 29.2.9.1 etpucisr - etpu channel interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-35 29.2.9.2 etpucdtrsr - etpu channel data transfer request status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36 29.2.9.3 etpuciosr - etpu channel interrupt overflow status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37 29.2.9.4 etpucdtrosr - etpu channel data transfer request overflow status register . . . . . . . . . . . . . . . . . . . . . . . 29-38 29.2.9.5 etpucier - etpu channel interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39 29.2.9.6 etpucdtrer - etpu channel data transfer request enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39 29.2.9.7 etpucpssr - etpu channel pending service status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40 29.2.9.8 etpucssr - etpu channel service status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-41 29.2.10channel configuration and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-42 29.2.10.1 etpucxcr - etpu channel x configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-43 29.2.10.2 etpucxscr - etpu channel x status control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45 29.2.10.3 etpucxhsrr - etpu channel x host service request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-47 29.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-47 29.3.1 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-47 29.3.2 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-48 29.3.2.1 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-48
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxiv 29.3.2.2 interrupts and data transfer requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-48 29.3.2.3 parameter access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-50 29.3.2.4 sdm organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-51 29.3.2.5 host service requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-53 29.3.2.6 scm access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-53 29.3.2.7 bus error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-55 29.3.3 scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-55 29.3.3.1 channel enabling and priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-55 29.3.3.2 channel priority schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-56 29.3.3.3 time slot latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-62 29.3.4 parameter sharing and coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-62 29.3.4.1 host side atomic access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-63 29.3.4.2 coherent dual-parameter controller - cdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-63 29.3.4.3 sdm arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-64 29.3.4.4 enhanced digital filter - edf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-65 29.3.5 time bases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-67 29.3.5.1 timer count register 1 - tcr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-67 29.3.5.2 timer count register 2 - tcr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-68 29.3.5.3 stac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-71 29.3.5.4 gtbe - global time base enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-73 29.3.5.5 tcrclk digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-73 29.3.6 safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-74 29.3.6.1 scm test - multiple input signature calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-74 29.3.7 performance monitoring features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-75 29.3.7.1 idle counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-75 29.4 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-76 29.4.1 multiple parameter coherency methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-76 29.4.2 estimating worst case latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-76 29.4.2.1 introduction to worst-case latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-77 29.4.2.2 using worst-case latency estimates to evaluate performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-78 29.4.2.3 priority scheme details used in wcl analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-79 29.4.2.4 first-pass worst-case latency analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-82 29.4.2.5 second-pass worst-case latency analys is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-88 29.4.3 misc algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-92 chapter 30 external bus interface (ebi) 30.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1.3 signal naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.1.4.1 single master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.1.4.2 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.1.4.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.1.4.4 slower-speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.1.4.5 16-bit data bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.1.4.6 multiplexed address on data bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.1.4.7 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.2 address/data bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.1 d_add [9:30] ? address lines 9-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.2 d_bdip ? burst data in progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.3 d_clkout ? clockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.4 cal_cs [0:3] ? calibration chip selects 0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.5 d_add_dat [0:31] ? data lines 0-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.2.3.6 d_oe ? output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.2.3.7 d_rd_wr ? read / write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.2.3.8 d_ta ? transfer acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.2.3.9 d_tea ? transfer error acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxv 30.2.3.10 d_ts ? transfer start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.2.3.11 d_we [0:3] ? write/byte enables 0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.2.4 signal output buffer enable logic by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10 30.3.1.1 ebi module configuration register (ebi_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10 30.3.1.2 ebi transfer error status register (ebi_tesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 30.3.1.3 ebi bus monitor control register (ebi_bmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12 30.3.1.4 ebi base registers (ebi_cal_br0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13 30.3.1.5 ebi option registers (ebi_cal_or0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15 30.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16 30.4.1 external bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16 30.4.1.1 address bus (up to 22 available on pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16 30.4.1.2 32-bit data bus (16-bit data bus mode also supported) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.4.1.3 multiplexed address on data pins (internal master only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.4.1.4 memory controller with support for various memory types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.4.1.5 burst support (wrapped only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.4.1.6 bus monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.4.1.7 port size configuration per chip select (16 or 32 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.4.1.8 configurable wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.4.1.9 configurable internal or external d_ta per chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.4.1.10 support for dynamic calibration with up to 4 chip-selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.4.1.11 four write/byte enable (d_we) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.4.1.12 slower-speed clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 30.4.1.13 stop and module disable modes for power savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 30.4.1.14 optional automatic d_clkout gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.4.1.15 misaligned access support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.4.1.16 compatible with mpc5xx external bus (with some limi tations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.4.2 external bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.4.2.1 external clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.4.2.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 30.4.2.3 basic transfer protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 30.4.2.4 single beat transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 30.4.2.5 burst transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-30 30.4.2.6 small accesses (small port size and short burst length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35 30.4.2.7 size, alignment and packaging on transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.4.2.8 termination signals protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41 30.4.2.9 non-chip-select burst in 16-bit data bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-43 30.4.2.10 calibration bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-44 30.4.2.11 misaligned access support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-45 30.4.2.12 address data multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-48 30.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-49 30.5.1 booting from external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-49 30.5.2 running with sdr (single data rate) burst memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-50 30.5.3 running with asynchronous memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-50 30.5.3.1 example wait state calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-50 30.5.3.2 timing and connections for asynchronous memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-51 30.5.4 connecting an mcu to multiple memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-52 30.5.5 summary of differences from mpc5xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-53 chapter 31 nexus development interface (ndi) 31.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.1.3.1 nexus reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.1.3.2 full-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.1.3.3 reduced-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.1.3.4 disabled-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.1.3.5 censored mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxvi 31.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.2.1.1 event out (evto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.2.1.2 event in (evti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.2.1.3 message data out (mdo[11:0] or [15:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.2.1.4 message start/end out (mseo [1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.2.1.5 ready (rdy ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.2.1.6 jtag compliancy (jcomp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.2.1.7 test data output (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.2.1.8 test clock input (tck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.2.1.9 test data input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.2.1.10 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.4 ndi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.4.1 enabling nexus clients for tap access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.4.2 configuring the ndi for nexus messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.4.3 programmable mcko frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13 31.4.4 nexus messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13 31.5 nexus port controller (npc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14 31.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14 31.5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14 31.6 npc memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15 31.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15 31.6.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.6.2.1 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.6.2.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.6.2.3 nexus device id register (did) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17 31.6.2.4 port configuration register (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17 31.7 npc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-19 31.7.1 npc reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-19 31.7.2 auxiliary output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-19 31.7.2.1 output message protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-19 31.7.2.2 output messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-20 31.7.2.3 ieee 1149.1-2001 (jtag) tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-21 31.7.2.4 nexus auxiliary port sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.7.2.5 nexus jtag port sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.7.2.6 mcko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.7.2.7 evto sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.7.2.8 nexus reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.8 npc initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.8.1 accessing npc tool-mapped regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.9 nexus dual etpu development interface (ndedi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.10 e200z7 class 3 nexus module (nz7c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.10.1introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.10.2block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-29 31.10.3overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-29 31.10.4features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-31 31.10.5enabling nexus3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-31 31.10.6tcodes supported by nz7c3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-32 31.11 nz7c3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-36 31.11.1 nz7c3 register access via jtag / once . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-37 31.12 ownership trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-38 31.12.1ownership trace messaging (otm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-38 31.12.2otm error messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-39 31.12.3 otm flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-39 31.13 program trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.13.1branch trace messaging (btm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.13.1.1 e200z7 indirect branch message instructions (power architecture book e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.13.1.2 e200z7 direct branch message instructions (power architecture book e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-41 31.13.1.3 btm using branch history messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-41 31.13.1.4 btm using traditional program trace messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-41 31.13.2btm message formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxvii 31.13.2.1 indirect branch messages (history) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.13.2.2 indirect branch messages (traditional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.13.2.3 direct branch messages (traditional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.13.2.4 resource full messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-43 31.13.2.5 debug status messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-43 31.13.2.6 program correlation messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.13.2.7 btm overflow error messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.13.3program trace synchronizati on messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-45 31.14 btm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.14.1enabling program trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.14.2 relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.14.3branch and predicate instruction history (hist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.14.4sequential instruction count (i-cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-48 31.14.5 program trace queueing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-48 31.14.5.1 program trace timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-48 31.14.6 data trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-49 31.14.6.1 data trace messaging (dtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-49 31.14.6.2 dtm message formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-50 31.14.6.3 dtm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-52 31.14.6.4 data trace timing diagrams (eight mdo configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-54 31.14.7 watchpoint support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-55 31.14.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-55 31.14.7.2 watchpoint messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-55 31.14.7.3 watchpoint error message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-56 31.14.7.4 watchpoint timing diagram (two mdo and one mseo configur ation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-57 31.14.8 nz7c3 read/write access to memory-mapped resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-57 31.14.8.1 single write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-57 31.14.8.2 block write access (non-burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-58 31.14.8.3 block write access (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-58 31.14.8.4 single read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-59 31.14.8.5 block read access (non-burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-60 31.14.8.6 block read access (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-60 31.14.8.7 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-61 31.14.8.8 read/write access error message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-61 31.14.9examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-61 31.14.10 ieee 1149.1 (jtag) rd/wr sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-63 31.14.10.1 jtag sequence for accessing internal nexus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-63 31.14.10.2 jtag sequence for read access of memory-mapped resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-63 31.14.10.3 jtag sequence for write access of memory-mapped resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-64 31.15 nexus crossbar edma interface (nxdm) and nexus crossbar flexray inte rface (nxfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-64 31.15.1block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-65 31.15.2features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-65 31.16 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-65 31.16.1rules for output messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-66 31.16.2auxiliary port arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-66 31.17 nxdm and nxfr programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-66 31.17.1nxdm and nxfr nexus register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-66 31.17.2nxdm and nxfr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-67 31.17.2.1 development control registers (dc1 and dc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-67 31.17.2.2 watchpoint trigger register (wt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-70 31.17.2.3 data trace control register (dtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-70 31.17.2.4 data trace start address registers 1 and 2 (dtsa1 and dtsa2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-71 31.17.2.5 data trace end address registers 1 and 2 (dtea1 and dtea2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-72 31.17.2.6 breakpoint / watchpoint control regi ster 1 (bwc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-72 31.17.2.7 breakpoint / watchpoint control regi ster 2 (bwc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-73 31.17.2.8 breakpoint/watchpoint address registers 1 and 2 (bwa1 and bwa2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-74 31.17.2.9 unimplemented registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-74 31.17.2.10 programming considerations (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-74 31.17.2.11 ieee 1149.1 (jtag) test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-74 31.17.3functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-76 31.17.4enabling nxdm and nxfr operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-76 31.17.5tcodes supported by nxdm and nxfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-77 31.17.5.1 data trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-79
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxviii 31.17.5.2 data trace messaging (dtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-79 31.17.5.3 dtm message formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-79 31.17.5.4 dtm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-81 31.17.5.5 data trace timing diagrams (eight mdo configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-82 31.17.6 watchpoint support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-82 31.17.6.1 watchpoint messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-83 31.17.6.2 watchpoint error message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-83 chapter 32 ieee 1149.1 test access port controller (jtagc) 32.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.1.4.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.1.4.2 ieee 1149.1-2001 defined test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.1.4.3 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.1.4.4 tap sharing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3.1 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3.2 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5 32.3.3 device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5 32.3.4 censor_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5 32.3.5 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.4.1 jtagc reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.4.2 ieee 1149.1-2001 (jtag) test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.4.3 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.4.3.1 enabling the tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9 32.4.3.2 selecting an ieee 1149.1-2001 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9 32.4.4 jtagc instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9 32.4.4.1 bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10 32.4.4.2 access_aux_tap_ x instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10 32.4.4.3 clamp instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10 32.4.4.4 extest ? external test instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10 32.4.4.5 enable_censor_ctrl instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11 32.4.4.6 highz instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11 32.4.4.7 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11 32.4.4.8 sample instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11 32.4.4.9 sample/preload instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11 32.4.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 chapter 33 device performance optimization 33.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.3 configuring hardware features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.3.1 branch target buffer (btb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.3.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.3.1.2 recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.3.2 frequency modulated pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.3.2.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.3.2.2 recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.3.3 flash bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.3.3.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.3.3.2 recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.3.4 crossbar switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxix 33.3.4.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.3.4.2 recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.3.5 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 33.3.5.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 33.3.5.2 recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 33.3.6 memory management unit (mmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-9 33.3.6.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-9 33.4 application software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.4.1 compiler optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.4.2 signal processing extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.4.3 hardware single precision fl oating point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-13 33.4.4 variable length encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-13 33.5 peripherals and general application guidel ines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-14 33.6 performance optimization checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-14 chapter 34 temperature sensor 34.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.2 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.3 temperature formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.3.1 t low and t high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.3.2 t tsens_code (t low ) and t tsens_code (t high ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.3.3 v bg_code (t low ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.4 temperature sensor voltage (v tens (t)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.5 bandgap reference voltage (v bg_code (t)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.6.1 temperature calculation constants register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.6.2 temperature calculation constants register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 appendix a revision history of this document
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxx
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxxi about this book this reference manual describes the pxr40 processor for software and hardware developers. information regarding bus timing, signal behavior, and ac, dc, and thermal characterist ics are detailed in the device data sheet ( pxr40 microcontroller data sheet ). the information in this book is subjec t to change without notic e, as described in the disclaimers on the title page. as with any technical document ation, the reader needs to make su re to use the most recent version of the documentation. to locate any published errata or updates for th is document, refer to the world-wide web at http://www.frees cale.com/powerpc . audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the pxr40 processor. it is assumed that the reader understands operating systems, microprocessor syst em design, basic principles of software and hardware, and basic details of the power architecture ? architecture. organization this document includes chapters that describe: ? the microcontroller as a whole ? the functionality of the indivi dual modules on the microcontroller when the microcontroller is specified as ?pxr40,? the reader is instructed to apply th is information to all of the microcontrollers specified on the front cover of this manual, unl ess individual devi ce-specific details are provided in that chapter. the following summary provides a brief description of the majo r sections of this manual: ? chapter 1, introduction, includes general descrip tions of the modules and fe atures incorporated in the device while focusing on new features. ? chapter 2, memory map, provides a high-level listi ng of the pxr40 memory map. ? chapter 3, signal descriptions, summarizes the external signal f unctions, their static electrical characteristics, and pad confi guration settings for the pxr40. ? chapter 4, resets, describes the reset sour ces available on the pxr40, including details on status flags and default configurations. ? chapter 5, power management controller (pmc), describes the on-chip module that provides voltage regulation for the pxr40. ? chapter 6, frequency modulated phase-locked loop (fmpll), describes the features and function of the fmpll module.
pxr40 microcontroller reference manual, rev. 1 xxxii freescale semiconductor ? chapter 7, system integration unit (siu), describes the siu module, which controls mcu reset configuration, pad configuration, external in terrupt, general-purpose i/o (gpio), internal peripheral multiplexing, and th e system reset operation. ? chapter 8, system information module, describes the system information module (sim), which contains the temperature sensor calibration constants and a unique 128- bit device id number. ? chapter 9, boot assist module (bam), describes the bam, whic h contains the mcu boot program code supporting the differen t booting modes for this device. ? chapter 10, interrupts and in terrupt controller (intc), summarizes the software and hardware interrupts for the pxr40 device. ? chapter 11, general-purpos e static ram (sram), describes the on-chip static ram (sram) implementation, covers general ope rations, configuration, and in itialization. it also provides information and examples of how to minimi ze power consumption when using the sram. ? chapter 12, flash memory array and control, describes the flash memory block and the flash memory controller. ? chapter 13, core (e200z7) overview, describes the organization of the e200z7 power processor core and gives an overview of the programming m odels as they are implemented on the device. the e200z7 is the main processor core on the pxr40. ? chapter 14, amba crossbar switch (xbar), describes the multi-port ax bs crossbar switch that supports simultaneous connections between the master and slave ports. ? chapter 15, peripheral bridge (pbridge), describes the interface between the system bus and lower bandwidth peripherals via the aips bridge. ? chapter 16, memory protection unit (mpu), describes the block that provides hardware access control for all memory references generated in the pxr40. ? chapter 17, error correction status module (ecsm), describes the ecsm block, which provides monitoring and control functions to report memory errors and apply error-correcting code (ecc) implementations. ? chapter 18, software watchdog timer (swt), describes a hardware-bas ed timer that can be implemented to prevent software runaway. ? chapter 19, system timer module (stm), describes the timer control module. ? chapter 20, periodic interrupt timer (pit_rti), describes an array of timers that can be used to initiate interrupts and trigger dma channels. ? chapter 21, enhanced direct memory access controller (edma), describes the enhanced dma controller implemented on the pxr40. ? chapter 22, flexray communication controller (flexray), describes the flexray communication controller on th e pxr40 that implements the flexray communications system protocol specification, version 2.1 rev a . ? chapter 23, enhanced modular i nput/output subsystem (emios200), describes the emios module, which provides timed i/o channels for communications with off-chip devices. ? chapter 24, flexcan module, describes the flexcan module, a communication controller implementing the can protocol according to bosch sp ecification version 2.0b and iso standard 11898.
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxxiii ? chapter 25, deserial serial peripheral interface (dspi), describes the serial peripheral interface (spi) block, which provides a s ynchronous serial interface for co mmunication between the pxr40 and external devices. ? chapter 26, enhanced serial co mmunication interface (esci), describes the esci interface, which allows asynchronous serial communications with off-chip peripheral devices. ? chapter 27, enhanced queued analog-to-digital converter (eqadc), ? chapter 28, decimation filter, describes the 12 on-chip modules that contain a multiply-accumulate (mac) unit ca pable of implementing a 16-bit, 4th order iir or 8th order fir filter. ? chapter 29, enhanced time processing unit (etpu2), describes the co-processor designed for timing control. ? chapter 30, external bus interface (ebi), describes the module that handles the transfer of information between the internal buses and the me mories or peripherals in the external address space. ? chapter 31, nexus development interface (ndi), describes the nexus development interface (ndi) block, which provides real-time devel opment support capabilities for the pxr40 in compliance with the ieee-isto 5001-2003 standard. ? chapter 32, ieee 1149.1 test access port controller (jtagc), describes configuration and operation of the joint test action group (jtag) controller implementati on. it describes those items required by the ieee ? 1149.1 standard and provides additi onal information specific to the device. for internal details and sample applications, see the ieee 1149.1 document. ? chapter 33, device performance optimization, describes how to improve the overall level of performance provide d by the device. ? chapter 34, temperature sensor, describes the on-board sensor th at monitors device temperature. ? appendix a, revision history of this document, describes the revision hi story of this document. suggested reading this section lists additional reading that provides bac kground for the information in this manual as well as general information about powerpc architecture. general information useful information about the powerpc archit ecture and computer architecture in general: ? programming environments manual for 32-bit impl ementations of the powerpc? architecture (mpcfpe32b) ? using microprocessors and microcom puters: the motorola family, william c. wray, ross bannatyne, joseph d. greenfield ? computer architecture: a quantitative approach , second edition, by john l. hennessy and david a. patterson.
pxr40 microcontroller reference manual, rev. 1 xxxiv freescale semiconductor ? computer organization and design: th e hardware/software interface , second edition, david a. patterson and john l. hennessy. power architecture documentation power architecture documentation is available from the sources listed on the back cover of this manual, as well as our web site, http://www.freescale.com/powerpc . ? reference manuals (formerly called user?s manuals)?these books provide details about individual powerpc implementations and are in tended to be used in conjunction with the powerpc programmers reference manual. ? addenda/errata to reference manuals?because so me processors have follow-on parts, an addendum is provided that describe s the additional features and f unctionality changes. also, if mistakes are found within a reference manual, an errata document may be issued before the next published release of the referenc e manual. these adde nda/errata are intended for use with the corresponding reference manuals. ? data sheets?data sheets provide specific info rmation regarding pin-out diagrams, bus timing, signal behavior, and ac, dc, and th ermal characteristics, as well as other design considerations. ? product briefs?each device has a product brief that provides an overview of its features. this document is roughly equivalent to the overview (chapter 1) of a device?s reference manual. ? application notes?these short documents address specific design issues us eful to programmers and engineers working with free scale semiconductor processors. additional literature is published as new processors become available. for a current list of powerpc documentation, refer to http://www.freescale.com/powerpc . conventions this document uses the foll owing notational conventions: cleared/set when a bit takes the valu e zero, it is said to be clea red; when it ta kes a value of one, it is said to be set. reserved when a bit or address is reserved, it should not be wr itten. if read, its value cannot be not guaranteed. reading or writing to reserved bits or addresses may cause unexpected results. mnemonics in text, instruction mn emonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. italics italics indicate variable command parameters. book titles in text are set in italics. 0x0 prefix to denote hexadecimal number 0b0 prefix to denote binary number reg[field] abbreviations for regist ers are shown in uppercase. sp ecific bits, fields, or ranges appear in brackets. for example, rambar [ba] identifies the base address field in the ram base address register.
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxxv nibble a 4-bit data unit byte an 8-bit data unit halfword a 16-bit data unit 1 word a 32-bit data unit doubleword a 64-bit data unit x in some contexts, such as signal encodi ngs, x (without italics) indicates a ?don?t care? condition. x with italics, used to express an undefi ned alphanumeric value (e.g., a variable in an equation); or a variable alphabetic character in a bit, register, or module name (e.g., dspi_ x could refer to dspi_a or dspi_b). n used to express an undefined numerical valu e; or a variable numeric character in a bit, register, or module name (e.g., eif n could refer to eif1 or eif0). ~ not logical operator & and logical operator | or logical operator || field concatenation operator overbar an overbar indicates that a signal is active-low. register figure conventions this document uses the following convent ions for the register reset values: the following register fields are used: 1 the only exceptions to this appear in the discussion of serial communication mo dules that support variable-length data transmission units. to simplify the discussion these un its are referred to as words regardless of length. w1c write 1 to clear the bit to 0. ? undefined at reset or ?not applicable.? u bit value is uninitialized upon reset. u bit value is unchanged upon reset. [ signal_name ] reset value is determined by the polarity of the indicated signal. r 0 indicates a reserved bit field in a memory-mapped register. these bits are always read as zeros. w r 1 indicates a reserved bit field in a memory-mapped register. these bits are always read as ones. w r fieldname indicates a read/write bit. w
pxr40 microcontroller reference manual, rev. 1 xxxvi freescale semiconductor acronyms and abbreviations table i lists acronyms and abbreviati ons used in this document. r fieldname indicates a read-only bit field in a memory-mapped register. w r indicates a write-only bit field in a memory-mapped register. w fieldname r fieldname write 1 to clear: indicates that writing a 1 to this bit field clears it. ww1c r 0 indicates a self-clearing bit. w fieldname table i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion alu arithmetic logic unit bdm background debug mode bist built-in self test bsdl boundary-scan description language codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing ea effective address fifo first-in, first-out gpio general-purpose i/o ieee institute for electrical and electronics engineers ifp instruction fetch pipeline ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lifo last-in, first-out lru least recently used lsb least-significant byte lsb least-significant bit
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxxvii terminology conventions table ii shows terminology conventions used throughout this document. mac multiply accumulate unit, also media access controller msb most-significant byte msb most-significant bit mux multiplex nc no connection nop no operation oep operand execution pipeline pc program counter plic physical layer interface controller pll phase-locked loop pin referring to an external pin or ball (i.e. external signal) por power-on reset risc reduced instruction set computing rx receive sof start of frame stac shared time and counter tap test access port ttl transistor transistor logic tx transmit uart universal asynchronous/synch ronous receiver transmitter usb universal serial bus table ii. notational conventions instruction operand syntax opcode wildcard cc logical condition (example: ne for not equal) table i. acronyms and abbreviated terms (continued) term meaning
pxr40 microcontroller reference manual, rev. 1 xxxviii freescale semiconductor register specifications an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rc any control register (example vbr is the vector base register) rm mac registers (acc, mac, mask) rn any address or data register rw destination register w (us ed for mac instructions only) ry,rx any source and destination registers, respectively xi index register i (can be an address or data register: ai, di) miscellaneous operands # immediate data following the 16-bit operation word of the instruction effective address y,x source and destination effective addresses, respectively assembly language program label list of registers for mo vem instruction (example: d3?d0) shift operation: shift left (<<), shift right (>>) operand data size: byte (b), word (w), longword (l) bc instruction and data caches dc data cache ic instruction cache # identifies the 4-bit vect or number for trap instructions <> identifies an indirect data address referencing memory identifies an absolute address referencing memory d n signal displacement value, n bits wide (example: d16 is a 16-bit displacement) sf scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for mac operations) operations + arithmetic addition or postincrement indicator ? arithmetic subtraction or predecrement indicator x arithmetic multiplication table ii. notational conventions (continued) instruction operand syntax
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor xxxix / arithmetic division ~ invert; operand is logically complemented &logical and | logical or ^ logical exclusive or << shift left (example: d0 << 3 is shift d0 left 3 bits) >> shift right (example: d0 >> 3 is shift d0 right 3 bits) ? source operand is moved to destination operand ?? two operands are exchanged sign-extended all bits of the upper portion are made equal to the high-order bit of the lower portion if then else test the condition. if true, the operations after th en are performed. if the condition is false and the optional else clause is present, the operations afte r else are performed. if the condition is false and else is omitted, the instruction performs no operat ion. refer to the bcc instruction description as an example. subfields and qualifiers {} optional operation () identifies an indirect address d n displacement value, n-bits wide (example: d 16 is a 16-bit displacement) address calculated effective address (pointer) bit bit selection (example: bit 3 of d0) lsb least significant bit (example: lsb of d0) lsb least significant byte lsw least significant word msb most significant bit msb most significant byte msw most significant word table ii. notational conventions (continued) instruction operand syntax
pxr40 microcontroller reference manual, rev. 1 xl freescale semiconductor
freescale semiconductor 1-1 pxr40 microcontroller reference manual, rev. 1 chapter 1 introduction the pxr40 device targets real-time, high performa nce applications. it is built upon the 90 nm cmos technology node. this document describes the features of the pxr40 and highlight s important electrical and physical characteri stics of the device. the e200z7 core of the pxr40 is comp atible with the power architecture ? book e architecture. it is 100% user-mode compatible (with floating point library) with the classic po werpc instruction set. the book e architecture has enhancemen ts that improve the architecture?s fit in embedded applicati ons. in addition to the classic powerpc instruction set, this core also has additional instructi on support for digital signal processing (dsp) and simd operations. the pxr40 has two levels of memory hierarchy, a 32 kb harvard architecture cache and a 256 kb on-chip sram. 4 mb of internal flash memory is provided. the features of the final, production-targeted device version are listed below. 1.1 pxr40 features table 1-1 shows the pxr40 feature set. table 1-1. pxr40 feature set feature pxr40 core e200z7 simd yes vle yes cache 32 kb (16 kb instruction/16 kb data) non-maskable interrupt (nmi) n mi & critical interrupt mmu 64 entry mpu yes xbar 5 5 windowing software watchdog yes nexus 3+ sram 256 kb flash 4 mb flash fetch accelerator 4 256 bit (first 1 mb of memory is 4 128; last 3 mb are 4 256) external bus yes calibration bus 16 bit non-muxed 32 bit muxed dma 96 channel dma nexus class 3
introduction 1-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note: 3.3 v is required for certain io segments only du ring debug/development (e.g., nexus 3 trace and bus) serial 3 uart_a yes uart_b yes uart_c yes microsecond bus uplink yes can 4 can_a 64 message buffers can_b 64 message buffers can_c 64 message buffers can_d 64 message buffers can_e no spi 4 spi_a yes spi_b yes spi_c yes spi_d yes flexray yes ethernet no system timers 4 pit chan 4 swt 1 watchdog emios 32 channel etpu 64 channel etpu_a yes (etpu2) etpu_b yes (etpu2) code memory 24 kb data memory 6 kb interrupt controller 448 adc 64 channel eqadc_a yes eqadc_b yes temperature sensor yes variable gain amp. yes decimation filter yes (8 on eqadc_b) sensor diagnostics yes pll fm vrc yes supplies 5v low power modes stop mode slow mode table 1-1. pxr40 feature set (continued) feature pxr40
introduction freescale semiconductor 1-3 pxr40 microcontroller reference manual, rev. 1 1.1.1 block diagram figure 1-1 shows a top-level block diagram of the pxr40. figure 1-1. pxr40 block diagram crossbar switch (xbar) memory protection unit (mpu) data and instruction system pbridge a pxr40 block diagram system integration interrupt controller osc/pll spe2 debug nexus jtag ieee isto 5001?-2003 2 x edma 64- and 32-ch e200z7 superscalar cpu pbridge b 256 kb sram w/ecc (32 kb s/b) 4mb flash w/ecc main memory system siu timed i/o system boot assist module (bam) 6k data 24k code ram emios 32-ch etpu2 32-ch etpu2 32-ch 4 x can 3 x uart/ 4 x spi 4 x dec fil 64-ch quad adci communications flexray? controller adc ? analog-to-digital converter adci ? adc interface aips ? peripheral i/o bridge amux ? analog multiplexer can ? controller area network decfil ? decimation filter ebi ? external bus interface ecsm ? error correction status module edma2 ? enhanced direct memory access emios ? enhanced modular i/o system eqadc ? enhanced queued a/d converter module etpu2 ? enhanced time processing unit 2 mmu ? memory management unit mpu ? memory protection unit pbridge ? peripheral i/o bridge s/b ? stand-by siu ? system integration unit spe2 ? signal processing engine 2 spi ? serial peripheral interface controller sram ? general-purpose static ram uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network vle ? variable length instruction encoding lin
introduction 1-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 1.1.2 critical performance parameters the critical performance parameters of the pxr40 feature the following: ? maximum cpu frequency: 264 mhz ? platform and peripheral modules typically run at half of the cpu frequency ? some peripheral modules (incl uding the etpu modules) support a full frequency mode with a maximum operating frequency of 200 mhz ? temperature range: ?40 ? to 105 ? c ? nominal power dissipation is less than 1.4 w, while enhancements to allow reduced power operation using clock gating are included ? separate power supply available for stand-by operation of a portion of sram 1.1.3 low-power modes the pxr40 includes two special modes to allo w reduction of applicat ion power consumption: ? slow mode: allows the device to be run at very low speed (appr oximately 1 mhz), with modules (including the pll) selectiv ely disabled by software. ? stop mode: system clock stopped to most modules including the cpu. wake-up timer used to restart the system clock af ter a predetermined time. 1.2 packages the pxr40 is offered in a 416-ball pbga, 1 mm ball pitch, 27 mm ? 27 mm outline (no ebi) package type. 1.2.1 chip-level features on-chip modules available within the fa mily include the fo llowing features: ? dual issue, 32-bit cpu core complex (e200z7) ? compliant with the power architecture embedded category ? 16 kb i-cache and 16 kb d-cache ? includes an instruction set enhancement allo wing variable length encoding (vle), optional encoding of mixed 16-bit and 32-bit instruct ions, for code size footprint reduction ? includes signal processing extens ion (spe2) instruction support for digital signal processing (dsp) and single-precisi on floating point operations ? 4 mb on-chip flash ? supports read during program and erase operati ons, and multiple bloc ks allowing eeprom emulation ? 256 kb on-chip general-purpose sr am including 32 kb of standby ram ? two direct memory access controller (edma2) blocks ? one supporting 64 channels
introduction freescale semiconductor 1-5 pxr40 microcontroller reference manual, rev. 1 ? one supporting 32 channels ? interrupt controller (intc) ? phase-locked loop with fm modulation (fmpll) ? crossbar switch architecture for concurrent access to peripherals, flash, or ram from multiple bus masters ? external bus interface (ebi) for cal ibration and application development ? system integration unit (siu) ? error correction status module (ecsm) ? boot assist module (bam) supports serial bootload via can or sci ? two second-generation enhanced time processor units (etpu2) ? 32 standard channels per etpu2 ? 24 kb code ram ? 6 kb parameter ram ? enhanced modular input output sy stem supporting 32 unif ied channels (emios) with each channel capable of single action, double action, pulse width modulation (pwm) a nd modulus counter operation ? two enhanced queued analog-to-digital converters (eqadc) ? support for 64 analog channels ? includes one absolute reference adc channel ? includes eight decimation fi lters (connected to eqadc_b) ? four deserial serial peri pheral interface (dspi) modules ? three enhanced serial comm unication interface (esci) modules ? four controller area ne twork (flexcan) modules ? dual-channel flexray controller ? nexus development interface (n di) per ieee-isto 5001-2011 standard ? device and board test support per jo int test action group (jtag) (ieee 1149.1) ? on-chip voltage regulator cont roller regulates supply voltage down to 1.2 v for core logic ? on-chip voltage regulator down to 3.3 v fo r pll, flash, and i/ o pre-driver logic 1.2.2 module features the following sections provide more details of the modules implemented on the pxr40. 1.2.3 high-performance e200z7 core processor the e200z7 core includes the following features: ? dual-issue, 32-bit power architecture ? cpu ? supports the 32-bit power architec ture book e programmer?s model
introduction 1-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? 64-bit general-purpose registers (gprs) support vector instructions defined by the spe2 apu ? all arithmetic instructions that execute in the core operate on data in the gprs ? enhanced signal processing ex tension (spe2) apu supports real-time fixed point and single-precision embedded numeric s operations using the gprs ? variable length encoding (vle) enhancements ? allows optional encoding of mixe d 16-bit and 32- bit instructions ? results in smaller code size footprint ? minimizes impact on performance ? six read and three wr ite operations per clock ? integrates a pair of integer execution units, a branch control unit, in struction fetch unit and load/store unit, and a mu lti-ported register file ? branch target prefetchin g performed by the branch unit allows single-cycle branches in many cases ? 16 kb instruction cache and 16 kb data cache, both supporting error detection hardware. ? memory management unit (mmu) with 64-entry fu lly-associative translation look-aside buffer (tlb) ? nexus class 3+ module ? supports non-maskable interrupt (c ompletely un-maskable and not gua ranteed to be recoverable) and critical interrupt (an interrupt that can be masked and is guara nteed to be recoverable) sources ? routed from a single package pin, via edge detection logic in the siu, to the cpu ? an additional wait for interrupt instruction: ? used in conjunction with low power stop mode ? instruction stops the system clock ? an external interrupt source or the system wa ke-up timer restart the system clock, allowing the cpu to service the interrupt ? includes multiple input signature register (misr) hardware whic h can be accessed by software to implement cpu self test functionality 1.2.4 on-chip flash memory the pxr40 flash memory modu le provides the following: ? 4 mb of programmable, non- volatile, flash memory ? nonvolatile memory (nvm) can be used for instruction and/or data storage ? a fetch accelerator optimizes the performance of the flash me mory array to match the cpu architecture ? architected to optimize the performance of the flash memory with the cpu to provide single-cycle random access to the flash memory wh en in full clock mode, and two-cycle access when in double clock mode ? configurable read buffering and line prefetch support ? an interface between the system bus and a dedicated flash memo ry array controller
introduction freescale semiconductor 1-7 pxr40 microcontroller reference manual, rev. 1 ? supports a 64-bit data bus width at the system bus port for cpu loads, dma transfers and cpu instruction fetch ? byte, halfword, word, and doubleword reads are supported ? only aligned word and doubleword writes are supported ? hardware and software configur able read and write access prot ections on a per-master basis ? pipelined interface to the flash memory array controller allowing overlapped accesses to proceed in parallel for interleaved or pi pelined flash memory array designs ? configurable access timing allowing use in a wide range of system frequencies ? multiple-mapping support and mapping-based bl ock access timing (0?31 additional cycles) allowing use for emulati on of other memory types ? software programmable block progr am/erase restriction control ? ecc with single-bit corr ection, double-bit detection ? minimum program size is two consecutive 32-bi t words, aligned on a 0- modulo-8 byte address (due to ecc) ? embedded hardware program and erase algorithm ? erase suspend, program suspe nd and erase-suspended program ? shadow information stored in non-volatile shadow block ? independent program/erase of the shadow block 1.2.5 general-purpose static ram (sram) the pxr40 sram module provides an internal ge neral-purpose 256 kb memory block. the sram controller includes these features: ? supports read/write accesses mapped to the sram memory from any master ? 32 kb block powered by separate supply fo r standby operation (contents retained) ? byte, halfword, word, and doubleword addressable ? ecc performs single-bit correction, doubl e-bit detection on 64- bit data elements ? ecc single-bit error corrections are optionally visible to software 1.2.6 error correction status module (ecsm) the error correction status modul e (ecsm) provides the following: ? status information regarding plat form memory errors reported by error detection code (edc) and error correcting code (ecc) hardware ? single-bit correction reporting for sram and flash memory ? multi-bit error reporting ? includes facilities to allow cpu software to test the error ecc and edc operation for on-chip memories by supporting injection of arbitrary error patterns
introduction 1-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 1.2.7 enhanced modular input ou tput system (timer?emios) the emios module provides the functionality to genera te or measure time events . a unified channel (uc) module is employed that provides a superset of the functionality of all of th e mios channels used on mpc5500 family devices, while providing a consistent user interface. this allows mo re flexibility as each unified channel can be progr ammed for different functions in differ ent applications. to identify as many as two timed events, each uc contains two comparators, a time base sele ctor and registers. this structure is able to produce match-events, which can be c onfigured to measure or generate a waveform. alternatively, input events can be used to capture the time base, allo wing measurement of an input signal. the emios provides the following features: ? 32 unified channels, featuring: ? 24-bit registers for capture/match values ? 24-bit internal counter ? global prescaler ? pin for input/output (each cha nnel signal is routed to a pin, however, most pins are also multiplexed with other signals) ? selectable time base ? can generate its own time base ? five 24-bit wide counter buses ? counter bus a can be driven by unified channel 23 ? counter bus b, c, d and e are driven by uni fied channels 0, 8, 16, and 24, respectively ? counter bus a can be shared am ong all unified channels. ucs 0 to 7, 8 to 15, 16 to 23, and 24 to 31 can share counter buses b, c, d and e, respectively ? shared time bases with the etpu ? synchronization among internal and external time bases ? shadow flag register ? state of block can be frozen for debug purposes 1.2.8 enhanced timing processor unit (etpu2) two etpu2 modules are available on the pxr40. the etpu2 is the second generation of the enhanced timing co-processors (etpu) that were used on th e mpc5500 family. etpu2 is fully upward compatible with etpu, runs the same binary c ode image, and can be used with th e same tool suite. etpu2 includes many enhancements to improve efficiency of co mpilers, functionality, ease of programming and operability while maintaining the same overall architect ure. some of these enhancements may be accessed using the existing compiler tool chain, while other enhancements require updates to the compiler. the etpu2 includes these distinctive features: ? 32 standard channels, each channel is asso ciated with one input and one output signal ? two independent 24-bit time ba ses for channel synchronization: ? event-triggered microengine ? 24 kb of code memory (scm)
introduction freescale semiconductor 1-9 pxr40 microcontroller reference manual, rev. 1 ? 6 kb of shared parame ter (data) ram (spram) ? resource sharing features support channel use of common channel registers, memory and microengine time ? hardware scheduler works as a task management unit, dispatching event service routines by pre-defined, host-configured priority ? channel context switch time is six system cycles . each channel has its own context of static data memory and timer hardware resources c onsisting of programmable flags, timer control and status hardware ? spram shared between host cpu and etpu , supporting communication either between channels and host or inter-channel ? dual-parameter coherency hardware support allo ws atomic access to two parameters by host ? enhancements to dma and interr upt structure to allow any cha nnel to assert any interrupt source or dma trigger 1 ? test and development support features: ? ieee-isto 5001-2003 standard class 3 compliant for the etpu (nexus) ? data trace via data write messaging and data read messaging ? ownership trace via ownership trace messaging (otm) ? program trace via br anch trace messaging ? watchpoint messaging via the auxiliary port ? scm continuous signature-check built-in se lf test (misc ? multiple input signature calculator), runs concurrent ly with etpu normal operation 1.2.9 software watchdog timer (swt) the software watchdog timer (swt) is a second watchdog module to co mplement the standard power architecture watchdog integrated in the cpu core. when enabled, the swt requires periodic execution of a watchdog servicing sequence. writ ing the sequence resets the timer to a specified time-out period. if this servicing action does not occur before the timer expires the swt ge nerates an interrupt or hardware reset. the swt can be configured to generate a reset or interrupt on an initial time-out, a reset is always generated on a second consecutive time-out. the following features are implemented: ? 32-bit time-out register to set the time-out period ? programmable selection of system or oscillator clock for timer operation ? programmable selection of window mode or regular servicing ? programmable selection of reset or interrupt on an initial time-out ? master access protection ? hard and soft configuration lock bits ? reset configuration inputs allow timer to be enabled out of reset
introduction 1-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 1.2.10 periodic interrupt timer (pit) the periodic interrupt timer (p it) is an array of timers that can be used to gene rate interrupts and trigger dma channels. it also provides a dedicated real-time in terrupt timer (rti), which runs on a separate clock and can be used for system wake-up. the following features are implemented: ? four independent timer channels ? each channel includes 32-bit wide down counter with automatic reload ? three channels clocked from system clock ? one channel clocked from crystal clock (wake-up timer) ? wake-up timer remains active when system enters stop mode. used to rest art system clock after predefined time-out period ? each channel can optionally generate in terrupt request when timer reaches zero ? channels can optionally produce trigger event wh en timer reaches zero (used to trigger eqadc queues) 1.2.11 system timer module (stm) the system timer module (stm) is a 32-bit time r designed to support commonly required operating system and application so ftware timing functions. the stm include s a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the following features are implemented: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.2.12 enhanced queued analog to digital converter (eqadc) the enhanced queued analog to digi tal converter (eqadc) bl ock provides accurate and fast conversions for a wide range of applications. the two eqadcs on the pxr40 provide a parallel interface to four on-chip analog to digital co nverters (adc), and a single-master to single-slave serial interface to an off-chip external device. the adcs include features designed to allow the di rect connection of high im pedance acoustic sensors that might be used in a system for detecting engi ne knock. these features incl ude differential inputs; integrated variable gain amplifiers for increasi ng the dynamic range; program mable pullup and pulldown resistors for biasing and sensor diagnostics. eqadc_b also integrates four pr ogrammable decimation filters capabl e of taking in adc conversion results at a high rate, passing them through a hardware low-pass filter , then down-sampling the output of the filter and feeding the lower sample rate results to the result fifos. this allows the adcs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise , while providing a reduced sample
introduction freescale semiconductor 1-11 pxr40 microcontroller reference manual, rev. 1 rate output to minimize the amount of dsp processing bandwidth require d to fully process the digitized waveform. the eqadcs provide the following features: ? quad on-chip adcs ? 4 12-bit adc resolution ? programmable resolution for increased c onversion speed (12-b it, 10-bit, 8-bit) ? 12-bit conversion time as low as 1 s (as fast as 1 m sample/sec) ? 10-bit conversion time as low as 867 ns (as fast as 1.2 m sample/sec) ? 8-bit conversion time as low as 733 ns (as fast as 1.4 m sample/sec) ? accuracy as high as 10-bit accur acy at 500 k sample/sec and 8-bi t accuracy at 1 m sample/sec ? differential conversions ? single-ended signal range from 0 to 5 v ? variable gain amplifiers on di fferential inputs (1, 2, 4) ? sample times of 2 (default), 8, 64, or 128 adc clock cycles ? provides time stamp info rmation when requested ? supports both right-justified unsigned and signed formats for conversion results ? 64 input channels, including 16 channels which can each be converted simultaneously by each eqadc ? eight additional internal channels for measuri ng control and monitoring vol tages inside the device ? including core voltage, i/o voltage, a nd low-voltage interrupt (lvi) voltages ? as many as eight inputs can be configured as f our pairs of differenti al analog input channels ? programmable pull-up/pull-down resi stors on each differential input ? silicon die temperature sensor ? provides temperature of silicon as an analog value ? read using an internal adc analog channel ? four decimation filters ? programmable decimation factor (2 to 16) ? selectable iir or fir filter ? fully programmable 4th order iir or 8th order fir ? saturated or non-saturated modes ? programmable rounding (convergent; two?s complement; truncated) ? pre-fill mode to pre-c ondition the filter before the sample window opens ? full duplex synchronous serial in terface to an external device ? free-running clock for us e by an external device ? supports a 26-bit message length ? six priority-based queues per adc ? trigger sources include software , timer channels and input pins
introduction 1-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? etpu result interface ? allows any adc result to be exported to etpu for use with reaction channels ? support for an additional 6 4?8=56 channels via external multiplexing 1.2.13 serial peripheral interface module (spi) the pxr40 includes four serial pe ripheral interface (spi) blocks th at provide a synchronous serial interface for communication to external devices. the spi features the following: ? supports pin count reduction th rough serialization and deserial ization of etpu and emios channels and memory-mapped registers ? channels and register content ar e transmitted using a spi protocol ? the protocol is completely c onfigurable for baud rate , polarity, phase, frame length, chip select assertion, etc. ? each bit in the frame may be c onfigured to serialize either et pu channels, emios channels or gpio signals ? can be configured to serialize da ta to an external device that is compatible with the microsecond bus protocol ? spi pins support 5 v logic levels or low volta ge differential signalling (lvds) to improve high-speed operation on data and clock signals the spis have multiple configurations: ? serial peripheral interface (spi) configuration wher e the spi operates as an up-to-16-bit spi with support for queues ? deserial serial interface (dsi) configuration where the spi serial izes as many as 32 bits from etpu, emios, or gpio output channels and dese rializes the received data by placing it on the etpu, emios, or gpio input channels ? combined serial interface (csi) configurati on where the spi operates in both spi and dsi configurations interleaving ds i frames with spi frames, givi ng priority to spi frames ? enhanced deserial serial interface (dsi) configuration where spi seri alizes as many as 32 bits with three possible sources per bit ? etpu, emios, new vi rtual gpio registers as possible bit source ? programmable inter-frame gap in continuous mode ? bit source selection allows mi crosecond bus downlink with comma nd or data frames as large as 32 bits ? microsecond bus dual receiver mode for queued operations, the spi queues re side in system memory external to the spi. data transfers between the memory and the spi fifos are accomplished through the use of the edma2 controller or through host software.
introduction freescale semiconductor 1-13 pxr40 microcontroller reference manual, rev. 1 1.2.14 serial communication interface module (uart) the pxr40 includes three serial communications interface (uart) modules. each uart allows asynchronous serial communica tions with peripheral devices and ot her mcus. it includes special support to interface to local interconnect network (lin) slave devices. the serial communication interf ace module offers the following: ? uart features: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? 2 receiver wake-up methods ? lin features: ? autonomous lin frame handling ? message buffer to store identi fier and up to eight data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin resp onses using up to 16 id filters 1.2.15 controller area network (can) module the pxr40 contains four contro ller area network (can) blocks.
introduction 1-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 each can module provides the following features: ? 64 message buffers (mb) of zer o to eight bytes data length ? based on and including all existing fe atures of the freescale toucan module ? full implementation of the can pr otocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate as fast as 1 mb/sec ? content-related addressing ? each mb configurable as recei ve (rx) or transmit (tx), al l supporting standard and extended messages ? individual rx mask registers per message buffer ? includes 1056 bytes of ram used for message buffer storage ? includes 256 bytes of ram used fo r individual rx mask registers ? full featured rx fifo with storage capacity for six frames and internal pointer handling ? powerful rx fifo id filtering, capable of ma tching incoming ids agains t either eight extended, 16 standard, or 32 partial (8 bits) ids, with individual masking capability ? selectable backwards compatibil ity with previous can version ? programmable clock source to the can protocol interface, either bus clock or crystal oscillator ? unused message buffer and rx mask register space can be used as general-purpose ram space ? listen-only mode capability ? programmable loop-back mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buf fer number or local priority on individual tx message buffers. ? hardware cancellation on tx message buffers. ? time stamp based on 16- bit free-running timer ? global network time, synchr onized by a specific message ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed) ? short latency time due to an arbitration scheme for high-priority messages ? low-power modes, with program mable wake-up on bus activity 1.2.16 enhanced direct memo ry access controller (edma2) the following summarizes the pxr40?s im plementation of the edma2 controller: ? second-generation modules capabl e of performing complex data movements via 64 programmable channels (edma2-a) and 32 progr ammable channels (e dma2-b), without intervention from the host processor ? dma engine
introduction freescale semiconductor 1-15 pxr40 microcontroller reference manual, rev. 1 ? performs source and destin ation address calculations ? performs data movement operations ? includes sram-based memory cont aining the transfer co ntrol descriptors (tcd ) for the channels. ? all data movement via dual-address transfer s: read from source, write to destination ? programmable source and destina tion addresses, transfer size, plus support for enhanced addressing modes ? tcd organized to support two-de ep, nested transfer operations ? an inner data transfer loop defi ned by a ?minor? byte transfer count ? an outer data transfer loop defi ned by a ?major? iteration count ? channel activation via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel li nking mechanism for c ontinuous transfers ? peripheral-paced hardware requests (one per channel) ? support for fixed-priority and round-robin channel arbitration ? channel completion reported vi a optional interrupt requests ? one interrupt per channel, optionally asse rted at completion of major iteration count ? error termination interrupts are optionally enabled ? support for scatter/ga ther dma processing ? channel transfers can be suspended by a higher priority channel ? nexus data trace support on each dma 1.2.17 crossbar switch (xbar) the following summarizes the pxr40?s im plementation of the crossbar switch: ? supports simultaneous connections between master ports and slave ports (each mast er must access a different slave) ? supports a 32-bit address bus widt h and a 64-bit data bus width ? six master ports: ? e200z7 core complex (two ports) ? edma2 module a ? edma2 module b ?flexray ? nexus debug interface (ndi) ? four slave ports ? flash memory ?sram ? peripheral bridge a ? peripheral bridge b
introduction 1-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? arbitration logic for when a slave port is simu ltaneously requested by more than one master ? includes memory protection unit (mpu) hardwa re to guard against unintended sram or peripheral accesses by the cpu, ed ma2 modules, and flexray module. 1.2.18 power management unit (pmu) the pxr40?s power management unit includes the following features: ? internally the chip has four supply voltages, nominally 5 v, 3.3 v, 1.2 v and v stby ? externally 5 v is required with the 3.3 v being supplied by an internal regulator running off the 5 v supply ? can also supply 3.3 v externally ? on-chip regulator controller suppl ies the 1.2 v via external components ? option to externally supply v stby when the application requires standby ram ? all supply voltages have voltage monitors and both the vdd regul ator and all monitors except v stby are adjustable ? the chip uses a protected por strategy, that is, the chip is guaranteed to run at the voltage point that reset is released 1.2.19 interrupt controller (intc) the pxr40 implements an interrupt cont roller that features the following: ? priority-based preemptive schedul ing of interrupt service requests (isrs), suitable for statically scheduled hard real-time systems ? 448 software-configurable interrupt sources ? can be used to break the work involved in serv icing an interrupt request into a high priority portion and a low priority portion: high priority portion is initiated by a peripheral interrupt request, but then the isr asserts a software-configurable interrupt request to fini sh the servicing in a lower priority isr. therefore these software-configurable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. ? 16 priority levels so that lower priority isrs do not delay the execution of higher priority isrs ? software-configurable pr iorities of isr or tasks ? modifying the priority can be used to impl ement the priority ceiling protocol for accessing shared resources ? for high priority interrupt requests, minimized time from the a ssertion of the interrupt request from the peripheral to when the processor is ex ecuting the interrupt service routine (isr) ? a unique vector for each interr upt request source for quick dete rmination of which isr needs to be executed ? support for a critical or non maskable interrupt ? non-maskable interrupt (nmi) multiplexed on wkpcfg pin to allow connection to the critical or non maskable input of the cpu co re, bypassing the interrupt controller and all
introduction freescale semiconductor 1-17 pxr40 microcontroller reference manual, rev. 1 multiplexing and selection logic (pr ovides an interrupt request to the core that is higher priority than any other interrupting source in the device) 1.2.20 frequency-modulated pll (fmpll) the fmpll allows the user to generate high spee d system clocks using a 4 mhz to 40 mhz crystal oscillator or external clock gene rator. further, the fmpll supports programmable frequency modulation of the system clock to reduce elec tromagnetic emissions peaks. the p ll multiplication factor and output clock divider ratio are all soft ware configurable. the pll has the following major features: ? input clock frequency selectable in two ranges: ? from 4 mhz to 20 mhz ? from 8 mhz to 40 mhz (when pllcfg2 pulled high) ? voltage controlled oscillator (vco) range from 192 mhz to 680 mhz ? reduced frequency divider (rfd) for reduced frequency operation without requiring pll relock ? three modes of operation: ? bypass mode with pll off ? bypass mode with pll running (default mode out of reset) ? pll normal mode ? each of the three modes may be run with a crys tal oscillator or an external clock reference ? programmable frequency modulation 1 ? modulation enabled/disabled through software ? triangle wave modulation ? programmable modulation depth ? programmable modulation frequency dependent on reference frequency ? lock detect circuitry reports wh en the pll has achieved frequency lock and continuously monitors lock status to report loss of lock conditions ? clock quality module ? optionally causes an interrupt request or sy stem reset if the crys tal clock frequency falls outside a predefined range ? optionally causes a system reset, or switches th e system clock to the crystal clock and causes an interrupt request, if the pll output cloc k frequency falls outside a predefined range ? programmable interrupt request or system reset on loss of lock ? self-clocked mode (scm) operation allows cont inued operation after fail ure of crystal clock ? configuration registers defined as an upwardly compatible superset of mpc5500 fmpll registers 1. you must configure the fmpll to ensure that the maximu m specified system frequency is not exceeded when frequency modulation is enabled.
introduction 1-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 1.2.21 system integration unit (siu) the siu provides the following features: ? system configuration ? mcu reset configurat ion via external pins ? pad configuration control for each pad ? control of virtual i/o via spi serialization ? system reset monitoring and generation ? power-on reset support ? reset status register provide s last reset source to software ? glitch detection on reset input ? software controlled reset assertion ? external interrupt ? sixteen interrupt requests ? rising or falling edge event detection ? programmable digital filt er for glitch rejection ? critical interrupt request ? non maskable interrupt request ?gpio ? virtual gpio via spi serialization (re quires external deserialization device) ? dedicated input and output registers fo r setting each gpio and virtual-gpio pin ? parallel gpio enables access to as many as eight gpios in one write ? internal multiplexing ? allows serial and para llel chaining of spis ? allows flexible selection of eqadc trigger inputs ? allows selection of interrupt reque sts between external pins and spi 1.2.22 boot assist module (bam) the bam is a block of read-only memory containi ng code that is executed every time the mcu is powered-on or reset in normal mode. the bam supports multiple boot modes: ? booting from internal flash memory ? serial boot loading (a program is downloaded in to on-chip general-purpose sram via uart or the can and then executed) the bam also reads the reset conf iguration half word (rchw) from flash memory (which may be external to the device) and confi gures the pxr40 hardware accordingl y. the bam provide s the following features: ? sets up mmu to cover all resour ces and mapping all physic al addresses to logi cal addresses with minimum address translation
introduction freescale semiconductor 1-19 pxr40 microcontroller reference manual, rev. 1 ? sets up the mmu to allow application boot code to execute as either clas sic power architecture book e code (default) or as freescale vle code ? location and detection of application boot code ? automatic switch to serial boot mode if internal flash memory is blank or invalid ? supports software-programmable 64-bit pa ssword protection for serial boot mode ? autobaud function in sci and can download mode 1 ? supports censorship protection for internal flash memory ? provides an option to enable the software watchdog timer 1.2.23 dual-channel flexray controller the pxr40 contains one dual-channel flexray controll er. the controller fully implements the flexray protocol specification version 2.1 rev a. the flexray protocol is designed to faci litate implementation of fault tolerant, time-triggered, a nd highly dependable contro l systems by offering a fault tolerant clock synchronization mechanism. the flexray protocol ma intains the global time across the functional nodes of a network with a precision (j itter) of maximum 1 s at a data rate of 10 mbit/sec and redundant communication channels. the flexray controller provi des the following features: ? flexray communications system protocol specification, versi on 2.1 rev a compliant protocol implementation ? flexray communications system electrical physical layer specification, version 2.1 rev a compliant bus driver interface ? single channel support ? flexray port a can be configured to be conne cted either to physical flexray channel a or physical flexray channel b. ? flexray bus data rates of 10 mbit/sec, 8 m bit/sec, 5 mbit/sec, and 2.5 mbit/sec supported ? 128 configurable message buffers with ? individual frame id filtering ? individual channel id filtering ? individual cycle counter filtering ? message buffer header, status and payload data stored in dedicated flexray memory ? allows for flexible and effici ent message buffer implementation ? consistent data access ensured by means of buffer locking scheme ? application can lock multiple buffers at the same time ? size of message buffer payload data s ection configurable from 0 to 254 bytes ? two independent message buffer segments with configurable size of payload data section ? each segment can contain message buffers assign ed to the static segment and message buffers assigned to the dynamic segment at the same time 1. feature available only on revision 2 release of device.
introduction 1-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? zero padding for transmit messag e buffers in static segment ? applied when the frame payload length exceeds the size of the message buffer data section ? transmit message buffers configur able with state/event semantics ? message buffers can be configured as ? receive message buffer ? single-buffered transmit message buffer ? double-buffered transmit message buffer (com bines two single buffered message buffer) ? individual message buffer r econfiguration supported ? means provided to safely di sable individual message buffers ? disabled message buffers can be reconfigured ? two independent receive fifos ? one receive fifo per channel ? as many as 255 entries for each fifo ? global frame id filtering, based on both value/mask filters and range filters ? global channel id filtering ? global message id filter ing for the dynamic segment ? four configurable slot error counters ? four dedicated slot status indicators ? used to observe slots without using receive message buffers ? measured value indicators fo r the clock synchronization ? internal synchronizatio n frame id and synchronization fr ame measurement tables can be copied into the flexray memory ? fractional macroticks are supported for clock correction ? maskable interrupt sources provided via individual and combined interrupt lines ? one absolute timer ? one timer that can be config ured as absolute or relative ? nexus data trace support 1.2.24 jtag controller (jtagc) the jtag controller (jtagc) block pr ovides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. the jt agc block is compliant with the ieee 1149.1-2001 and ieee 1149.7 standards, and supports the following features: ? ieee 1149.1-2001 test access port (tap) interfa ce five pins (jcomp, tdi, tms, tck, and tdo) ? ieee 1149.7 serial jtag test access port interface three pins (jcomp, tms, tck) ? a 5-bit instruction register that supports th e following ieee 1149.1-2001 defined instructions:
introduction freescale semiconductor 1-21 pxr40 microcontroller reference manual, rev. 1 ? bypass, idcode, extest, sample , sample/preload, highz, clamp ? a 5-bit instruction register that supports the additional followi ng public instructions: ? access_aux_tap_npc, access_aux_t ap_once, access_aux_tap_etpu, access_aux_tap_dmaan3, access_aux_tap_dmabn3, access_aux_tap_flexray ? three test data registers: a bypa ss register, a boundary scan regist er, and a device identification register. the size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths. ? a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry. ? censorship inhibit register ? 64-bit censorship password register ? if the external tool writes a 64-bit password that matches the se rial boot password stored in the internal flash memory shadow row, censorship is disabled until the next jtag reset 1.2.25 nexus the nexus debug interface (ndi) bl ock provides real-time developmen t support capabilities for the pxr40 in compliance with the ieee-isto 5001-2003 st andard. this developmen t support is supplied for mcus without requiring external addr ess and data pins for internal visibility. the ndi block is an integration of several individual nexus blocks that are selected to provide the development support interface for the pxr40. the ndi bloc k interfaces to the host processor, the etpu, and internal buses to provide development support as per the ieee -isto 5001-2003 standard. the development support provided includes program trace, data trace, watchpoi nt trace, ownership trace , run-time access to the mcu?s internal memory map and access to the power architecture and etpu internal registers during halt. the nexus interface also supports a jtag-only mode using only the jt ag pins. nexus also provides data trace support for flexray and both edma2s. the following features are implemented: ? 23 or 27 full duplex pin interface fo r medium and high visibility throughput ? one of two modes selected by register configuration: ? reduced-port mode (rpm) comprise s 12 mdo (message data out) pins ? full-port mode (fpm) comprises 16 mdo pins ? auxiliary output port ? debug support pins ? one mcko (message clock out) pin ? 12 or 16 mdo (message data out) pins ?two mseo (message start/end out) pins ? one rdy (ready) pin ? one evto (event out) pin ? auxiliary input port ? one evti (event in) pin ? 5-pin jtag port (jcomp, tdi, tdo, tms, and tck) or 3-pin (j comp, tms, and tck)
introduction 1-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? reduced-pin jtag mode as per ieee 1149.7 ? host processor (e200z7) standard class 3 compliant ? etpu development support standard class 3 compliant ? supports data trace for the flexra y controller and bo th edma2 modules ? run-time access to the on-chip memory ma p via the nexus read/write access protocol ? all features are independen tly configurable and controllable via the ieee 1149.1 i/o port ? the ndi block reset is controlled with jcomp, power-on reset, and the tap state machine. all these sources are indepe ndent of system reset. ? power-on-reset status indicat ion during reset via mdo[0] in disabled and reset modes 1.3 developer environment the pxr40 supports several tools to enab le easier application development. the following development support will be available. ? tower system modules for evaluation and prototyping ? compilers ? debuggers ? jtag and nexus interfaces ? rappid? initialization tool
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 2-1 chapter 2 memory map 2.1 introduction all addresses in the device, including those that are re served, are identified in the following tables. the addresses represent the physical addresses assigned to each block. logical addre sses are translated by the mmu into physical addresses. under software control of the memory management un it (mmu), the logical addresses allocated to ip blocks may be changed on a minimum of a 4 kb boundary. table 2-1 shows this device?s memory map. table 2-1. pxr40 memory map block address flash (4 mb) 0x0000_0000?0x003f_ffff reserved 0x0040_0000?0x00ef_bfff flash b shadow block 0x00ef_c000?0x00ef_ffff reserved 0x00f0_0000?0x00ff_bfff flash a shadow block 0 x00ff_c000?0 x00ff_ffff emulation re-mapping of fl ash 0x0100_0000?0x1fff_ffff external development memo ry 0x2000_0000?0x3fff_ffff internal standby sram (32 kb) 0x4000_0000?0x4000_7fff internal sram (224 kb) 0x4000_8000?0x4003_ffff reserved 0x4004_0000?0xc3ef_ffff peripheral bridge a registers 0xc3f0_0000?0xc3f0_3fff reserved 0xc3f0_4000?0xc3f7_ffff fmpll 0xc3f8_0000?0xc3f8_3fff ebi configuration 0xc3f8_4000?0xc3f8_7fff flash a configuration 0xc3f8_8000?0xc3f8_bfff flash b configuration 0 xc3f8_c000?0xc3f8_ffff siu 0xc3f9_0000?0xc3f9_3fff reserved 0xc3f9_4000?0xc3f9_ffff emios 0xc3fa_0000?0xc3fa_3fff reserved 0xc3fa_4000?0xc3fb_bfff
memory map pxr40 microcontroller reference manual, rev. 1 2-2 freescale semiconductor pmc 0xc3fb_c000?0xc3fb_ffff etpu registers 0xc3fc_0000?0xc3fc_3fff reserved 0xc3fc_4000?0xc3fc_7fff etpu parameter ram 0xc3fc_8000?0xc3fc_97ff etpu parameter ram mirror 0xc3fc_c000?0xc3fc_d7ff etpu code ram 0xc3fd_0000?0xc3fd_5fff reserved 0xc3fd_6000?0xc3fe_ffff pit / rti 0xc3ff_0000?0xc3ff_3fff reserved 0xc3ff_4000?0xc3ff_bfff reserved 0xc3ff_c000?0xc3ff_ffff peripheral bridge b regi sters 0xfff0_0000? 0xfff0_3fff xbar (axbs) 0xfff0_4000?0xfff0_7fff reserved 0xfff0_80 00?0xfff0_ffff mpu 0xfff1_0000?0xfff1_3fff reserved 0xfff1_4000?0xfff3_7fff swt 0xfff3_8000?0xfff3_bfff stm 0xfff3_c000?0xfff3_ffff ecsm 0xfff4_0000?0xfff4_3fff edma_a 0xfff4_4000?0xfff4_7fff intc 0xfff4_8000?0xfff4_bfff reserved 0xfff4_c000?0xfff5_3fff edma_b 0xfff5_4000?0xfff5_7fff reserved 0xfff5_80 00?0xfff7_ffff eqadc_a 0xfff8_0000?0xfff8_3fff eqadc_b 0xfff8_4000?0xfff8_7fff decimation filter a 0xfff8_8000?0xfff8_87ff decimation filter b 0 xfff8_8800?0xfff8_8fff decimation filter c 0xfff8_9000?0xfff8_97ff decimation filter d 0 xfff8_9800?0xfff8_9fff decimation filter e 0xfff8_a000?0xfff8_a7ff decimation filter f 0xfff8_a800?0xfff8_afff decimation filter g 0xfff8_b000?0xfff8_b7ff table 2-1. pxr40 memory map (continued) block address
memory map pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 2-3 decimation filter h 0xf ff8_b800?0xfff8_bfff reserved 0xfff8_c000?0xfff8_ffff dspi_a 0xfff9_0000? 0xfff9_3fff dspi_b 0xfff9_4000?0xfff9_7fff dspi_c 0xfff9_8000? 0xfff9_bfff dspi_d 0xfff9_c000? 0xfff9_ffff reserved 0xfffa_0000?0xfffa_ffff esci_a 0xfffb_0000?0xfffb_3fff esci_b 0xfffb_4000?0xfffb_7fff esci_c 0xfffb_8000?0xfffb_bfff reserved 0xfffb_c0000?0xfffb_ffff flexcan_a 0xfffc_0000?0xfffc_3fff flexcan_b 0xfffc_4000?0xfffc_7fff flexcan_c 0xfffc_8000?0xfffc_bfff flexcan_d 0xfffc_c000?0xfffc_ffff reserved 0xfffd_0000?0xfffd_ffff flexray 0xfffe_0000?0xfffe_3fff reserved 0xfffe_4000?0xfffe_bfff system information module (temp. sensor and unique device id) 0xfffe_c000?0xfffe_ffff reserved 0xffff_0000?0xffff_bfff boot assist module (bam) 0xffff_c000?0xffff_ffff table 2-1. pxr40 memory map (continued) block address
memory map pxr40 microcontroller reference manual, rev. 1 2-4 freescale semiconductor
freescale semiconductor 3-1 pxr40 microcontroller reference manual, rev. 1 chapter 3 signal descriptions this chapter describes the external device signals , including a table of signa l properties, detailed descriptions of the available signals, and the i/o pin power/ground segmentation. 3.1 pin function selection 3.1.1 pad configuration re gister (pcr) pa definition most pins (balls) on the package support more than one function. unlike prior devices in this class, the required pin function on this device is selected by a fi xed size of the pa bit fi eld in each siu_pcr. the pa width is fixed at 3 bits. the pin function categories are: pins that do not require selecti on of a function by modifying the pa field have a hard-wired value corresponding to the appropriate f unction available at the pin. all pa values might not be used. a definition of which values are used is provided in the siu chapter?s pcr settings table. the ?primary function? name is retained from previous mpc5xxx designs and indicat es the name used on the ball map. the name ?gpio? is also retained for clarity. the remaining function na mes are new and have been chosen for simplicity and clarity. 3.1.2 lvds signal selection a pin (ball) that is driven by a signal from a 5v pa d or from an lvds pad has a single pcr controlling both signals. different values of pa select either the 5v signal or the lvds signal. note that a single lvds pad supplies two signals ? a ?true? and a ?complement ? output. this means that one lvds pad drives two balls, but each ball ha s a separate pcr (and pa field). the two lvds signa ls are enabled only when the pa values in both pcrs are set to select lvds operation. both lvds signals are deselected when either pa is set to a value that dese lects its lvds signal. the ball that ha s its pa field still set to lvds will go to an undriven state until its pa field is updated to a non-lvds value. table 3-1. siu_pcr pa definition pa function category 000 gpio 001 primary function 010 alternate function 1 (a1) 011 alternate function 2 (a2) 100 alternate function 3 (a3)
signal descriptions 3-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 3-2 is an example of the options for pa on two ba lls, where ?true? and ?complement? lvds outputs are multiplexed with sck_c and sinc. additionally, when lvds signals are enabled on balls, their pcr src[1:0] bits control the differential signal output swing increase a nd decrease, as defined in table 3-3 . table 3-2. lvds example pcr235 1 [pa] selection 1 sckc_sck_c_lvdsp_gpio235 pcr236 2 [pa] selection 2 sinc_sck_c_lvdsm_gpio236 sckc ball function sinc ball function sckc sinc sckc sinc lvds lvds sck_c_lvds+ sck_c_lvds- sckc lvds sckc undriven lvds sinc undriven sinc table 3-3. differential signal output when lvds is enabled src1 src0 current flowing in the driver differential voltage across ?true? and ?complement? 0 0 normal default 0 1 increased increased (20%) 1 0 decreased decreased (20%) 1 1 normal same as default
signal descriptions freescale semiconductor 3-3 pxr40 microcontroller reference manual, rev. 1 3.2 external signal descriptions, pin multiplexing, and attributes this section summarizes the external signa l functions, their static electrical charac teristics, and pad configuration settings for this device. the signal properties and their elec trical characteristics are set in the syst em integration unit (s iu) pad configurati on (pcr) registers. see the pxr40 microcontroller data sheet for ball-map figures. table 3-4. signal properties and muxing summary gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416) etpu_a 113 tcrclka_irq7_ gpio113 p tcrclka etpu a tcr clock i mh v ddeh1 ?/up ?/up l1 a1 irq7 external interrupt request i a2 ?? ? g gpio113 gpio i/o 114 etpua0_etpua12_ gpio114 p etpua0 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg l2 a1 etpua12 etpu a channel (output only) o a2 ?? ? g gpio114 gpio i/o 115 etpua1_etpua13_ gpio115 p etpua1 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg l3 a1 etpua13 etpu a channel (output only) o a2 ?? ? g gpio115 gpio i/o 116 etpua2_etpua14_ gpio116 p etpua2 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg l4 a1 etpua14 etpu a channel (output only) o a2 ?? ? g gpio116 gpio i/o
signal descriptions freescale semiconductor 3-4 pxr40 microcontroller reference manual, rev. 1 117 etpua3_etpua15_ gpio117 p etpua3 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k1 a1 etpua15 etpu a channel (output only) o a2 ?? ? g gpio117 gpio i/o 118 etpua4_etpua16_ gpio118 p etpua4 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k2 a1 etpua16 etpu a channel (output only) o a2 ?? ? g gpio118 gpio i/o 119 etpua5_etpua17_ gpio119 p etpua5 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k3 a1 etpua17 etpu a channel (output only) o a2 ?? ? g gpio119 gpio i/o 120 etpua6_etpua18_ gpio120 p etpua6 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k4 a1 etpua18 etpu a channel (output only) o a2 ?? ? g gpio120 gpio i/o 121 etpua7_etpua19_ gpio121 p etpua7 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j1 a1 etpua19 etpu a channel (output only) o a2 ?? ? g gpio121 gpio i/o 122 etpua8_etpua20_ gpio122 p etpua8 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j2 a1 etpua20 etpu a channel (output only) o a2 ?? ? g gpio122 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-5 pxr40 microcontroller reference manual, rev. 1 123 etpua9_etpua21_ gpio123 p etpua9 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j3 a1 etpua21 etpu a channel (output only) o a2 ?? ? g gpio123 gpio i/o 124 etpua10_etpua22_ gpio124 p etpua10 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j4 a1 etpua22 etpu a channel (output only) o a2 ?? ? g gpio124 gpio i/o 125 etpua11_etpua23_ gpio125 p etpua11 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h1 a1 etpua23 etpu a channel (output only) o a2 ?? ? g gpio125 gpio i/o 126 etpua12_pcsb1_ gpio126 p etpua12 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h2 a1 pcsb1 dspi b peripheral chip select o a2 ?? ? g gpio126 gpio i/o 127 etpua13_pcsb3_ gpio127 p etpua13 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h4 a1 pcsb3 dspi b peripheral chip select o a2 ?? ? g gpio127 gpio i/o 128 etpua14_pcsb4_ gpio128 p etpua14 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h3 a1 pcsb4 dspi b peripheral chip select o a2 ?? ? g gpio128 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-6 pxr40 microcontroller reference manual, rev. 1 129 etpua15_pcsb5_ gpio129 p etpua15 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g1 a1 pcsb5 dspi b peripheral chip select o a2 ?? ? g gpio129 gpio i/o 130 etpua16_pcsd1_ gpio130 p etpua16 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g2 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio130 gpio i/o 131 etpua17_pcsd2_ gpio131 p etpua17 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g3 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio131 gpio i/o 132 etpua18_pcsd3_ gpio132 p etpua18 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g4 a1 pcsd3 dspi d peripheral chip select o a2 ?? ? g gpio132 gpio i/o 133 etpua19_pcsd4_ gpio133 p etpua19 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f1 a1 pcsd4 dspi d peripheral chip select o a2 ?? ? g gpio133 gpio i/o 134 etpua20_irq8_ gpio134 p etpua20 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f2 a1 irq8 external interrupt request i a2 ?? ? g gpio134 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-7 pxr40 microcontroller reference manual, rev. 1 135 etpua21_irq9_ gpio135 p etpua21 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f3 a1 irq9 external interrupt request i a2 ?? ? g gpio135 gpio i/o 136 etpua22_irq10_ gpio136 p etpua22 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f4 a1 irq10 external interrupt request i a2 ?? ? g gpio136 gpio i/o 137 etpua23_irq11_ gpio137 p etpua23 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e1 a1 irq11 external interrupt request i a2 ?? ? g gpio137 gpio i/o 138 etpua24_irq12_ gpio138 p etpua24 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e2 a1 irq12 external interrupt request i a2 ?? ? g gpio138 gpio i/o 139 etpua25_irq13_ gpio139 p etpua25 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e3 a1 irq13 external interrupt request i a2 ?? ? g gpio139 gpio i/o 140 etpua26_irq14_ gpio140 p etpua26 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e4 a1 irq14 external interrupt request i a2 ?? ? g gpio140 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-8 pxr40 microcontroller reference manual, rev. 1 141 etpua27_irq15_ gpio141 p etpua27 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d1 a1 irq15 external interrupt request i a2 ?? ? g gpio141 gpio i/o 142 etpua28_pcsc1_ gpio142 p etpua28 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d2 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio142 gpio i/o 143 etpua29_pcsc2_ gpio143 p etpua29 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d3 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio143 gpio i/o 144 etpua30_pcsc3_ gpio144 p etpua30 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg c1 a1 pcsc3 dspi c peripheral chip select o a2 ?? ? g gpio144 gpio i/o 145 etpua31_pcsc4_ gpio145 p etpua31 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg c2 a1 pcsc4 dspi c peripheral chip select o a2 ?? ? g gpio145 gpio i/o etpu_b 146 tcrclkb_irq6_ gpio146 p tcrclkb etpu b tcr clock i mh v ddeh6 ?/up ?/up t23 a1 irq6 external interrupt request i a2 ?? ? g gpio146 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-9 pxr40 microcontroller reference manual, rev. 1 147 etpub0_etpub16_ gpio147 p etpub0 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t24 a1 etpub16 etpu b channel (output only) o a2 ?? ? g gpio147 gpio i/o 148 etpub1_etpub17_ gpio148 p etpub1 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t25 a1 etpub17 etpu b channel (output only) o a2 ?? ? g gpio148 gpio i/o 149 etpub2_etpub18_ gpio149 p etpub2 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t26 a1 etpub18 etpu b channel (output only) o a2 ?? ? g gpio149 gpio i/o 150 etpub3_etpub19_ gpio150 p etpub3 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r23 a1 etpub19 etpu b channel (output only) o a2 ?? ? g gpio150 gpio i/o 151 etpub4_etpub20_ gpio151 p etpub4 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r24 a1 etpub20 etpu b channel (output only) o a2 ?? ? g gpio151 gpio i/o 152 etpub5_etpub21_ gpio152 p etpub5 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r25 a1 etpub21 etpu b channel (output only) o a2 ?? ? g gpio152 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-10 pxr40 microcontroller reference manual, rev. 1 153 etpub6_etpub22_ gpio153 p etpub6 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r26 a1 etpub22 etpu b channel (output only) o a2 ?? ? g gpio153 gpio i/o 154 etpub7_etpub23_ gpio154 p etpub7 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p23 a1 etpub23 etpu b channel (output only) o a2 ?? ? g gpio154 gpio i/o 155 etpub8_etpub24_ gpio155 p etpub8 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p24 a1 etpub24 etpu b channel (output only) o a2 ?? ? g gpio155 gpio i/o 156 etpub9_etpub25_ gpio156 p etpub9 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p25 a1 etpub25 etpu b channel (output only) o a2 ?? ? g gpio156 gpio i/o 157 etpub10_etpub26_ gpio157 p etpub10 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p26 a1 etpub26 etpu b channel (output only) o a2 ?? ? g gpio157 gpio i/o 158 etpub11_etpub27_ gpio158 p etpub11 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n24 a1 etpub27 etpu b channel (output only) o a2 ?? ? g gpio158 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-11 pxr40 microcontroller reference manual, rev. 1 159 etpub12_etpub28_ gpio159 p etpub12 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n25 a1 etpub28 etpu b channel (output only) o a2 ?? ? g gpio159 gpio i/o 160 etpub13_etpub29_ gpio160 p etpub13 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n26 a1 etpub29 etpu b channel (output only) o a2 ?? ? g gpio160 gpio i/o 161 etpub14_etpub30_ gpio161 p etpub14 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m25 a1 etpub30 etpu b channel (output only) o a2 ?? ? g gpio161 gpio i/o 162 etpub15_etpub31_ gpio162 p etpub15 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m24 a1 etpub31 etpu b channel (output only) o a2 ?? ? g gpio162 gpio i/o 163 etpub16_pcsa1_ gpio163 p etpub16 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u26 a1 pcsa1 dspi a peripheral chip select o a2 ?? ? g gpio163 gpio i/o 164 etpub17_pcsa2_ gpio164 p etpub17 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u25 a1 pcsa2 dspi a peripheral chip select o a2 ?? ? g gpio164 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-12 pxr40 microcontroller reference manual, rev. 1 165 etpub18_pcsa3_ gpio165 p etpub18 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u24 a1 pcsa3 dspi a peripheral chip select o a2 ?? ? g gpio165 gpio i/o 166 etpub19_pcsa4_ gpio166 p etpub19 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u23 a1 pcsa4 dspi a peripheral chip select o a2 ?? ? g gpio166 gpio i/o 167 etpub20_ gpio167 p etpub20 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v26 a1 ?? ? a2 ?? ? g gpio167 gpio i/o 168 etpub21_ gpio168 p etpub21 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v25 a1 ?? ? a2 ?? ? g gpio168 gpio i/o 169 etpub22_ gpio169 p etpub22 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v24 a1 ?? ? a2 ?? ? g gpio169 gpio i/o 170 etpub23_ gpio170 p etpub23 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg w26 a1 ?? ? a2 ?? ? g gpio170 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-13 pxr40 microcontroller reference manual, rev. 1 171 etpub24_ gpio171 p etpub24 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg w25 a1 ?? ? a2 ?? ? g gpio171 gpio i/o 172 etpub25_ gpio172 p etpub25 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg w24 a1 ?? ? a2 ?? ? g gpio172 gpio i/o 173 etpub26_ gpio173 p etpub26 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v23 a1 ?? ? a2 ?? ? g gpio173 gpio i/o 174 etpub27_ gpio174 p etpub27 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg y25 a1 ?? ? a2 ?? ? g gpio174 gpio i/o 175 etpub28_ gpio175 p etpub28 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg y24 a1 ?? ? a2 ?? ? g gpio175 gpio i/o 176 etpub29_ gpio176 p etpub29 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg y23 a1 ?? ? a2 ?? ? g gpio176 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-14 pxr40 microcontroller reference manual, rev. 1 177 etpub30_ gpio177 p etpub30 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg aa24 a1 ?? ? a2 ?? ? g gpio177 gpio i/o 178 etpub31_ gpio178 p etpub31 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ab24 a1 ?? ? a2 ?? ? g gpio178 gpio i/o gpio, irq, flexray 440 tcrclkc _ gpio440 9 p ?? ?mhv ddeh7 ?/up ?/up b26 a1 ?? ? a2 ?? ? g gpio440 gpio i/o 441 etpuc0 _ gpio441 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg c25 a1 ?? ? a2 ?? ? g gpio441 gpio i/o 442 etpuc1 _ gpio442 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg c26 a1 ?? ? a2 ?? ? g gpio442 gpio i/o 443 etpuc2 _ gpio443 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg d25 a1 ?? ? a2 ?? ? g gpio443 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-15 pxr40 microcontroller reference manual, rev. 1 444 etpuc3 _ gpio444 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg d26 a1 ?? ? a2 ?? ? g gpio444 gpio i/o 445 etpuc4 _ gpio445 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg e24 a1 ?? ? a2 ?? ? g gpio445 gpio i/o 446 etpuc5 _ gpio446 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg e25 a1 ?? ? a2 ?? ? g gpio446 gpio i/o 447 etpuc6 _ gpio447 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg e26 a1 ?? ? a2 ?? ? g gpio447 gpio i/o 448 etpuc7 _ gpio448 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg f23 a1 ?? ? a2 ?? ? g gpio448 gpio i/o 449 etpuc8 _ gpio449 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg f24 a1 ? ? ? a2 ?? ? g gpio449 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-16 pxr40 microcontroller reference manual, rev. 1 450 etpuc9_ irq0_ gpio450 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f25 a1 irq0 external interrupt request i a2 ?? ? g gpio450 gpio i/o 451 etpuc10_ _irq1_ gpio451 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f26 a1 irq1 external interrupt request i a2 ?? ? g gpio451 gpio i/o 452 etpuc11_ irq2_ gpio452 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g23 a1 irq2 external interrupt request i a2 ?? ? g gpio452 gpio i/o 453 etpuc12_ irq3_ gpio453 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g24 a1 irq3 external interrupt request i a2 ?? ? g gpio453 gpio i/o 454 etpuc13_ 3_irq4_ gpio454 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g25 a1 irq4 external interrupt request i a2 ?? ? g gpio454 gpio i/o 455 etpuc14_ 4_irq5_ gpio455 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g26 a1 irq5 external interrupt request i a2 ?? ? g gpio455 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-17 pxr40 microcontroller reference manual, rev. 1 456 etpuc15_ _ gpio456 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h23 a1 ?? ? a2 ?? ? g gpio456 gpio i/o 457 etpuc16_ fr_a_tx_ gpio457 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h24 a1 fr_a_tx flexray a transfer o a2 ?? ? g gpio457 gpio i/o 458 etpuc17_ fr_a_rx_ gpio458 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h25 a1 fr_a_rx flexray a receive i a2 ?? ? g gpio458 gpio i/o 459 etpuc18_ fr_a_tx_en_ gpio459 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h26 a1 fr_a_tx_en flexray a transfer enable o a2 ?? ? g gpio459 gpio i/o 460 etpuc19_ txda_ gpio460 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j23 a1 txda esci a transmit o a2 ?? ? g gpio460 gpio i/o 461 etpuc20_ rxda _ gpio461 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j24 a1 rxda esci a receive i a2 ?? ? g gpio461 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-18 pxr40 microcontroller reference manual, rev. 1 462 etpuc21_ txdb_ gpio462 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j25 a1 txdb esci b transmit o a2 ?? ? g gpio462 gpio i/o 463 etpuc22_ rxdb_ gpio463 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j26 a1 rxdb esci b receive i a2 ?? ? g gpio463 gpio i/o 464 etpuc23_ pcsd5_ gpio464 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k23 a1 pcsd5 dspi d peripheral chip select o a2 maa0 adc a mux address 0 o a3 mab0 adc b mux address 0 o g gpio464 gpio i/o 465 etpuc24_ pcsd4_ gpio465 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k24 a1 pcsd4 dspi d peripheral chip select o a2 maa1 adc a mux address 1 o a4 mab1 adc b mux address 1 o g gpio465 gpio i/o 466 etpuc25_ pcsd3_ gpio466 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k25 a1 pcsd3 dspi d peripheral chip select o a2 maa2 adc a mux address 2 o a3 mab2 adc b mux address 2 o g gpio466 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-19 pxr40 microcontroller reference manual, rev. 1 467 etpuc26_ pcsd2_ gpio467 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k26 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio467 gpio i/o 468 etpuc27_ pcsd1_ gpio468 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l23 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio468 gpio i/o 469 etpuc28_ pcsd0_ gpio469 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l24 a1 pcsd0 dspi d peripheral chip select i/o a2 ?? ? g gpio469 gpio i/o 470 etpuc29_ sckd_ gpio470 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l25 a1 sckd dspi d clock i/o a2 ?? ? g gpio470 gpio i/o 471 etpuc30_ soutd_ gpio471 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l26 a1 soutd dspi d data output o a2 ?? ? g gpio471 gpio i/o 472 etpuc31_ sind_ gpio472 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg m23 a1 sind dspi d data input i a2 ?? ? g gpio472 gpio i/o emios table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-20 pxr40 microcontroller reference manual, rev. 1 179 emios0_etpua0_ gpio179 p emios0 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae10 a1 etpua0 etpu a channel o a2 ?? ? g gpio179 gpio i/o 180 emios1_etpua1_ gpio180 p emios1 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af10 a1 etpua1 etpu a channel o a2 ?? ? g gpio180 gpio i/o 181 emios2_etpua2_ gpio181 p emios2 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad11 a1 etpua2 etpu a channel o a2 ?? ? g gpio181 gpio i/o 182 emios3_etpua3_ gpio182 p emios3 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae11 a1 etpua3 etpu a channel o a2 ?? ? g gpio182 gpio i/o 183 emios4_etpua4_ gpio183 p emios4 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af11 a1 etpua4 etpu a channel o a2 ?? ? g gpio183 gpio i/o 184 emios5_etpua5_ gpio184 p emios5 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad12 a1 etpua5 etpu a channel o a2 ?? ? g gpio184 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-21 pxr40 microcontroller reference manual, rev. 1 185 emios6_etpua6_ gpio185 p emios6 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae12 a1 etpua6 etpu a channel o a2 ?? ? g gpio185 gpio i/o 186 emios7_etpua7_ gpio186 p emios7 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af12 a1 etpua7 etpu a channel o a2 ?? ? g gpio186 gpio i/o 187 emios8_etpua8_ gpio187 p emios8 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac13 a1 etpua8 etpu a channel o a2 ?? ? g gpio187 gpio i/o 188 emios9_etpua9_ gpio188 p emios9 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad13 a1 etpua9 etpu a channel o a2 ?? ? g gpio188 gpio i/o 189 emios10_sckd_ gpio189 p emios10 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae13 a1 sckd dspi d clock o a2 ?? ? g gpio189 gpio i/o 190 emios11_sind_ gpio190 p emios11 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af13 a1 sind dspi d data input i a2 ?? ? g gpio190 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-22 pxr40 microcontroller reference manual, rev. 1 191 emios12_soutc_ gpio191 p emios12 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg af14 a1 soutc dspi c data output o a2 ?? ? g gpio191 gpio i/o 192 emios13_soutd_ gpio192 p emios13 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae14 a1 soutd dspi d data output o a2 ?? ? g gpio192 gpio i/o 193 emios14_irq0_ gpio193 p emios14 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac14 a1 irq0 external interrupt request i a2 cntxd flexcan d transmit o g gpio193 gpio i/o 194 emios15_irq1_ gpio194 p emios15 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad14 a1 irq1 external interrupt request i a2 cnrxd flexcan d receive i g gpio194 gpio i/o 195 emios16_etpub0_ gpio195 p emios16 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af15 a1 etpub0 etpu b channel o a2 fr_dbg[3] flexray debug o g gpio195 gpio i/o 196 emios17_etpub1_ gpio196 p emios17 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae15 a1 etpub1 etpu b channel o a2 fr_dbg[2] flexray debug o g gpio196 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-23 pxr40 microcontroller reference manual, rev. 1 197 emios18_etpub2_ gpio197 p emios18 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac15 a1 etpub2 etpu b channel o a2 fr_dbg[1] flexray debug o g gpio197 gpio i/o 198 emios19_etpub3_ gpio198 p emios19 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad15 a1 etpub3 etpu b channel o a2 fr_dbg[0] flexray debug o g gpio198 gpio i/o 199 emios20_etpub4_ gpio199 p emios20 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af16 a1 etpub4 etpu b channel o a2 ?? ? g gpio199 gpio i/o 200 emios21_etpub5_ gpio200 p emios21 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae16 a1 etpub5 etpu b channel o a2 ?? ? g gpio200 gpio i/o 201 emios22_etpub6_ gpio201 p emios22 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac16 a1 etpub6 etpu b channel o a2 ?? ? g gpio201 gpio i/o 202 emios23_etpub7_ gpio202 p emios23 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad16 a1 etpub7 etpu b channel o a2 ?? ? g gpio202 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-24 pxr40 microcontroller reference manual, rev. 1 203 emios24_pcsb0_ gpio203 p emios24 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af17 a1 pcsb0 dspi b peripheral chip select i/o a2 ?? ? g gpio203 gpio i/o 204 emios25_pcsb1_ gpio204 p emios25 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae17 a1 pcsb1 dspi b peripheral chip select o a2 ?? ? g gpio204 gpio i/o 432 emios26_pcsb2_ gpio432 p emios26 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad17 a1 pcsb2 dspi b peripheral chip select o a2 ?? ? g gpio432 gpio i/o 433 emios27_pcsb3_ gpio433 p emios27 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac17 a1 pcsb3 dspi b peripheral chip select o a2 ?? ? g gpio433 gpio i/o 434 emios28_pcsc0_ gpio434 p emios28 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af18 a1 pcsc0 dspi c peripheral chip select i/o a2 ?? ? g gpio434 gpio i/o 435 emios29_pcsc1_ gpio435 p emios29 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae18 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio435 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-25 pxr40 microcontroller reference manual, rev. 1 436 emios30_pcsc2_ gpio436 p emios30 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad18 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio436 gpio i/o 437 emios31_pcsc5_ gpio437 p emios31 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac18 a1 pcsc5 dspi c peripheral chip select o a2 ?? ? g gpio437 gpio i/o eqadc ?ana0 p ana0 10 eqadc a analog input i ae/up- down v dda_a1 ana0 ana0 a4 ?ana1 p ana1 10 eqadc a analog input i ae/up- down v dda_a1 ana1 ana1 b5 ?ana2 p ana2 10 eqadc a analog input i ae/up- down v dda_a1 ana2 ana2 c5 ?ana3 p ana3 10 eqadc a analog input i ae/up- down v dda_a1 ana3 ana3 d6 ?ana4 p ana4 10 eqadc a analog input i ae/up- down v dda_a1 ana4 ana4 a5 ?ana5 p ana5 10 eqadc a analog input i ae/up- down v dda_a1 ana5 ana5 b6 ?ana6 p ana6 10 eqadc a analog input i ae/up- down v dda_a1 ana6 ana6 c6 ?ana7 p ana7 10 eqadc a analog input i ae/up- down v dda_a1 ana7 ana7 d7 ?ana8 p ana8 eqadc a analog input i ae v dda_a1 ana8 ana8 a6 ?ana9 p ana9 eqadc a analog input i ae v dda_a1 ana9 ana9 c7 ?ana10 p ana10 eqadc a analog input i ae v dda_a1 ana10 ana10 b7 table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-26 pxr40 microcontroller reference manual, rev. 1 ?ana11 p ana11 eqadc a analog input i ae v dda_a1 ana11 ana11 a7 ?ana12 p ana12 eqadc a analog input i ae v dda_a1 ana12 ana12 d8 ?ana13 p ana13 eqadc a analog input i ae v dda_a1 ana13 ana13 c8 ?ana14 p ana14 eqadc a analog input i ae v dda_a1 ana14 ana14 b8 ?ana15 p ana15 eqadc a analog input i ae v dda_a1 ana15 ana15 a8 ?ana16 p ana16 eqadc a analog input i ae v dda_a1 ana16 ana16 d9 ?ana17 p ana17 eqadc a analog input i ae v dda_a1 ana17 ana17 c9 ?ana18 p ana18 eqadc a analog input i ae v dda_a1 ana18 ana18 d10 ?ana19 p ana19 eqadc a analog input i ae v dda_a1 ana19 ana19 c10 ?ana20 p ana20 eqadc a analog input i ae v dda_a1 ana20 ana20 d11 ?ana21 p ana21 eqadc a analog input i ae v dda_a1 ana21 ana21 c11 ?ana22 p ana22 eqadc a analog input i ae v dda_a1 ana22 ana22 d12 ?ana23 p ana23 eqadc a analog input i ae v dda_a1 ana23 ana23 c12 ?an24 p an24 eqadc a and b shared analog input i ae v dda_a0 an24 an24 b12 ?an25 p an25 eqadc a and b shared analog input i ae v dda_a0 an25 an25 d13 ?an26 p an26 eqadc a and b shared analog input i ae v dda_a0 an26 an26 c13 ?an27 p an27 eqadc a and b shared analog input i ae v dda_a0 an27 an27 b13 ?an28 p an28 eqadc a and b shared analog input i ae v dda_a0 an28 an28 a13 ?an29 p an29 eqadc a and b shared analog input i ae v dda_a0 an29 an29 b14 ?an30 p an30 eqadc a and b shared analog input i ae v dda_b1 an30 an30 c14 ?an31 p an31 eqadc a and b shared analog input i ae v dda_b1 an31 an31 d14 ?an32 p an32 eqadc a and b shared analog input i ae v dda_b1 an32 an32 a14 ?an33 p an33 eqadc a and b shared analog input i ae v dda_b0 an33 an33 b15 ?an34 p an34 eqadc a and b shared analog input i ae v dda_b0 an34 an34 c15 ?an35 p an35 eqadc a and b shared analog input i ae v dda_b0 an35 an35 d15 table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-27 pxr40 microcontroller reference manual, rev. 1 ?an36 p an36 eqadc a and b shared analog input i ae v dda_b1 an36 an36 a15 ?an37 p an37 eqadc a and b shared analog input i ae v dda_b0 an37 an37 c16 ?an38 p an38 eqadc a and b shared analog input i ae v dda_b0 an38 an38 c17 ?an39 p an39 eqadc a and b shared analog input i ae v dda_b0 an39 an39 d16 ?anb0 p anb0 eqadc b analog input i ae/up- down v dda_b0 anb0 anb0 c18 ?anb1 p anb1 eqadc b analog input i ae/up- down v dda_b0 anb1 anb1 d17 ?anb2 p anb2 eqadc b analog input i ae/up- down v dda_b0 anb2 anb2 d18 ?anb3 p anb3 eqadc b analog input i ae/up- down v dda_b0 anb3 anb3 d19 ?anb4 p anb4 eqadc b analog input i ae/up- down v dda_b0 anb4 anb4 c19 ?anb5 p anb5 eqadc b analog input i ae/up- down v dda_b0 anb5 anb5 c20 ?anb6 p anb6 eqadc b analog input i ae/up- down v dda_b0 anb6 anb6 b19 ?anb7 p anb7 eqadc b analog input i ae/up- down v dda_b0 anb7 anb7 a20 ?anb8 p anb8 eqadc b analog input i ae v dda_b0 anb8 anb8 b20 ?anb9 p anb9 eqadc b analog input i ae v dda_b0 anb9 anb9 d20 ?anb10 p anb10 eqadc b analog input i ae v dda_b0 anb10 anb10 b21 ?anb11 p anb11 eqadc b analog input i ae v dda_b0 anb11 anb11 a21 ?anb12 p anb12 eqadc b analog input i ae v dda_b0 anb12 anb12 c21 ?anb13 p anb13 eqadc b analog input i ae v dda_b0 anb13 anb13 d21 ?anb14 p anb14 eqadc b analog input i ae v dda_b0 anb14 anb14 a22 ?anb15 p anb15 eqadc b analog input i ae v dda_b0 anb15 anb15 b22 table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-28 pxr40 microcontroller reference manual, rev. 1 ?anb16 p anb16 eqadc b analog input i ae v dda_b0 anb16 anb16 c22 ?anb17 p anb17 eqadc b analog input i ae v dda_b0 anb17 anb17 a23 ?anb18 p anb18 eqadc b analog input i ae v dda_b0 anb18 anb18 b23 ?anb19 p anb19 eqadc b analog input i ae v dda_b0 anb19 anb19 c23 ?anb20 p anb20 eqadc b analog input i ae v dda_b0 anb20 anb20 d22 ?anb21 p anb21 eqadc b analog input i ae v dda_b0 anb21 anb21 a24 ?anb22 p anb22 eqadc b analog input i ae v dda_b0 anb22 anb22 b24 ?anb23 p anb23 eqadc b analog input i ae v dda_b0 anb23 anb23 a25 ? vrh_a p vrh_a adc a voltage reference high i vddint v rh_a vrh_a vrh_a a12 ? vrl_a p vrl_a adc a voltage reference low i vssint v rl_a vrl_a vrl_a a11 ? vrh_b p vrh_b adc b voltage reference high i vddint v rh_b vrh_b vrh_b a19 ? vrl_b p vrl_b adc b voltage reference low i vssint v rl_b vrl_b vrl_b a18 ? refbypcb p refbypcb adc b reference bypass capacitor i ae v dda_b0 refbypcb refbypcb b18 ? refbypca p refbypca adc a reference bypass capacitor i ae v dda_a1 refbypca refbypca b11 ? vdda_a0 p vdda_a internal logic supply input i vdde v dda_a0 vdda_a0 vdda_a0 a9 ? vdda_a1 p vdda_a internal logic supply input i vdde v dda_a1 vdda_a1 vdda_a1 b9 ? refbypca1 p refbypca1 adc a reference bypass capacitor i ae v dda_a1 refbypca1 refbypca1 a10 ? vssa_a1 p vssa_a ground i vsse v ssa_a1 vssa_a1 vssa_a1 b10 ? vdda_b0 p vdda_b internal logic supply input i vdde v dda_b0 vdda_b0 vdda_b0 a16 ? vdda_b1 p vdda_b internal logic supply input i vdde v dda_b1 vdda_b1 vdda_b1 b16 ? vssa_b0 p vssa_b ground i vsse v ssa_b0 vssa_b0 vssa_b0 b17 ? refbypcb1 p refbypcb1 adc b reference bypass capacitor i ae v dda_b0 refbypcb1 refbypcb1 a17 table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-29 pxr40 microcontroller reference manual, rev. 1 flexray 248 fr_a_tx_ gpio248 p fr_a_tx flexray a transfer o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ad4 a1 ?? ? a2 ?? ? g gpio248 gpio i/o 249 fr_a_rx_ gpio249 p fr_a_rx flexray a receive i fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ae3 a1 ?? ? a2 ?? ? g gpio249 gpio i/o 250 fr_a_tx_en_ gpio250 p fr_a_tx_en flexray a transfer enable o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) af3 a1 ?? ? a2 ?? ? g gpio250 gpio i/o 251 fr_b_tx_ gpio251 p fr_b_tx flexray b transfer o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ad5 a1 ?? ? a2 ?? ? g gpio251 gpio i/o 252 fr_b_rx_ gpio252 p fr_b_rx flexray b receive i fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ae4 a1 ?? ? a2 ?? ? g gpio252 gpio i/o 253 fr_b_tx_en_ gpio253 p fr_b_tx_en flexray b transfer enable o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) af4 a1 ?? ? a2 ?? ? g gpio253 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-30 pxr40 microcontroller reference manual, rev. 1 flexcan 83 cntxa_txda_ gpio83 p cntxa flexcan a transmit o mh v ddeh4 ?/up ?/up af19 a1 txda esci a transmit o a2 ?? ? g gpio83 gpio i/o 84 cnrxa_rxda_ gpio84 p cnrxa flexcan a receive i mh v ddeh4 ?/up ?/up ae19 a1 rxda esci a receive i a2 ?? ? g gpio84 gpio i/o 85 cntxb_pcsc3_ gpio85 p cntxb flexcan b transmit o mh v ddeh4 ?/up ?/up ad19 a1 pcsc3 dspi c peripheral chip select o a2 ?? ? g gpio85 gpio i/o 86 cnrxb_pcsc4_ gpio86 p cnrxb flexcan b receive i mh v ddeh4 ?/up ?/up ac19 a1 pcsc4 dspi c peripheral chip select o a2 ?? ? g gpio86 gpio i/o 87 cntxc_pcsd3_ gpio87 p cntxc flexcan c transmit o mh v ddeh4 ?/up ?/up af20 a1 pcsd3 dspi d peripheral chip select o a2 ?? ? g gpio87 gpio i/o 88 cnrxc_pcsd4_ gpio88 p cnrxc flexcan c receive i mh v ddeh4 ?/up ?/up ae20 a1 pcsd4 dspi d peripheral chip select o a2 ?? ? g gpio88 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-31 pxr40 microcontroller reference manual, rev. 1 246 cntxd_ gpio246 p cntxd flexcan d transmit o mh v ddeh4 ?/up ?/up ad20 a1 ?? ? a2 ?? ? g gpio246 gpio i/o 247 cnrxd_ gpio247 p cnrxd flexcan d receive i mh v ddeh4 ?/up ?/up ac20 a1 ?? ? a2 ?? ? g gpio247 gpio i/o esci 89 txda_ gpio89 p txda esci a transmit o mh v ddeh1 ?/up ?/up m2 a1 ?? ? a2 ?? ? g gpio89 gpio i/o 90 rxda _ gpio90 p rxda esci a receive i mh v ddeh1 ?/up ?/up m3 a1 ?? ? a2 ?? ? g gpio90 gpio i 91 txdb_pcsd1_ gpio91 p txdb esci b transmit o mh v ddeh1 ?/up ?/up p1 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio91 gpio i/o 92 rxdb_pcsd5_ gpio92 p rxdb esci b receive i mh v ddeh1 ?/up ?/up n1 a1 pcsd5 dspi d peripheral chip select o a2 ?? ? g gpio92 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-32 pxr40 microcontroller reference manual, rev. 1 244 txdc_etrig0_ gpio244 p txdc esci c transmit o mh v ddeh4 ?/up ?/up af23 a1 etrig0 eqadc trigger input i a2 ?? ? g gpio244 gpio i/o 245 rxdc_ gpio245 p rxdc esci c receive i mh v ddeh5 ?/up ?/up ad22 a1 ?? ? a2 ?? ? g gpio245 gpio i/o dspi 93 scka_pcsc1_ gpio93 p scka dspi a clock i/o mh v ddeh3 ?/up ?/up ad8 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio93 gpio i/o 94 sina_pcsc2_ gpio94 p sina dspi a data input i mh v ddeh3 ?/up ?/up af7 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio94 gpio i/o 95 souta_pcsc5_ gpio95 p souta dspi a data output o mh v ddeh3 ?/up ?/up ad7 a1 pcsc5 dspi c peripheral chip select o a2 ?? ? g gpio95 gpio i/o 96 pcsa0_pcsd2_ gpio96 p pcsa0 dspi a peripheral chip select i/o mh v ddeh3 ?/up ?/up ae6 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio96 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-33 pxr40 microcontroller reference manual, rev. 1 97 pcsa1_ gpio97 p pcsa1 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ac6 a1 ?? ? a2 ?? ? g gpio97 gpio i/o 98 pcsa2_ gpio98 p pcsa2 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ac7 a1 ?? ? a2 ?? ? g gpio98 gpio i/o 99 pcsa3_ gpio99 p pcsa3 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ae7 a1 ?? ? a2 ?? ? g gpio99 gpio i/o 100 pcsa4_ gpio100 p pcsa4 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ae5 a1 ?? ? a2 ?? ? g gpio100 gpio i/o 101 pcsa5_etrig1_ gpio101 p pcsa5 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ad6 a1 etrig1 eqadc trigger input i a2 ?? ? g gpio101 gpio i/o 102 sckb_ gpio102 p sckb dspi b clock i/o mh v ddeh3 ?/up ?/up ae8 a1 ?? ? a2 ?? ? g gpio102 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-34 pxr40 microcontroller reference manual, rev. 1 103 sinb_ gpio103 p sinb dspi b data input i mh v ddeh3 ?/up ?/up ae9 a1 ?? ? a2 ?? ? g gpio103 gpio i/o 104 soutb_ gpio104 p soutb dspi b data output o mh v ddeh3 ?/up ?/up af9 a1 ?? ? a2 ?? ? g gpio104 gpio i/o 105 pcsb0_pcsd2_ gpio105 p pcsb0 dspi b peripheral chip select i/o mh v ddeh3 ?/up ?/up ad9 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio105 gpio i/o 106 pcsb1_pcsd0_ gpio106 p pcsb1 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ac9 a1 pcsd0 dspi d peripheral chip select i/o a2 ?? ? g gpio106 gpio i/o 107 pcsb2_soutc_ gpio107 p pcsb2 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up af8 a1 soutc dspi c data output o a2 ?? ? g gpio107 gpio i/o 108 pcsb3_sinc_ gpio108 p pcsb3 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ad10 a1 sinc dspi c data input i a2 ?? ? g gpio108 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-35 pxr40 microcontroller reference manual, rev. 1 109 pcsb4_sckc_ gpio109 p pcsb4 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ac8 a1 sckc dspi c clock i/o a2 ?? ? g gpio109 gpio i/o 110 pcsb5_pcsc0_ gpio110 p pcsb5 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up af6 a1 pcsc0 dspi c peripheral chip select i/o a2 ?? ? g gpio110 gpio i/o 235 sckc_sck_c_lvdsp_ gpio235 p sckc dspi c clock i/o mh+ lvd s v ddeh4 ?/up ?/up ad21 a1 sck_c_lvdsp lvds+ downstream signal positive output clock o a2 ?? ? g gpio235 gpio i/o 236 sinc_sck_c_lvdsm_ gpio236 p sinc dspi c data input i mh+ lvd s v ddeh4 ?/up ?/up ae22 a1 sck_c_lvdsm lvds? downstream signal negative output clock o a2 ?? ? g gpio236 gpio i/o 237 soutc_sout_c_lvdsp_ gpio237 p soutc dspi c data output o mh+ lvd s v ddeh4 ?/up ?/up af21 a1 sout_c_lvdsp lvds+ downstream signal positive output data o a2 ?? ? g gpio237 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-36 pxr40 microcontroller reference manual, rev. 1 238 pcsc0_sout_c_lvdsm_ gpio238 p pcsc0 dspi c peripheral chip select i/o mh+ lvd s v ddeh4 ?/up ?/up ae21 a1 sout_c_lvdsm lvds? downstream signal negative output data o a2 ?? ? g gpio238 gpio i/o 239 pcsc1_ gpio239 p pcsc1 dspi c peripheral chip select o mh v ddeh4 ?/up ?/up ac22 a1 ?? ? a2 ?? ? g gpio239 gpio i/o 240 pcsc2_gpio240 p pcsc2 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ae23 a1 ?? ? a2 ?? ? g gpio240 gpio i/o 241 pcsc3_gpio241 p pcsc3 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ad23 a1 ?? ? a2 ?? ? g gpio241 gpio i/o 242 pcsc4_gpio242 p pcsc4 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up af24 a1 ?? ? a2 ?? ? g gpio242 gpio i/o 243 pcsc5_gpio243 p pcsc5 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ae24 a1 ?? ? a2 ?? ? g gpio243 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-37 pxr40 microcontroller reference manual, rev. 1 reset and clocks ? reset p reset external reset input i mh v ddeh1 reset/up reset/up r2 230 rstout p rstout external reset output o mh v ddeh1 rstout/low rstout/ high a3 212 bootcfg1_irq3_ gpio212 p bootcfg1 boot configuration i mh v ddeh1 bootcfg/ down input/down n2 a1 irq3 external interrupt request i a2 ?? ? g gpio212 gpio i/o 213 wkpcfg_nmi_ gpio213 p wkpcfg weak pull configuration input i mh v ddeh1 wkpcfg/up input/up n3 a1 nmi critical interrupt to core 11 i a2 ?? ? g gpio213 gpio i 208 pllcfg0_irq4_ gpio208 p pllcfg0 fmpll mode configuration input i mh v ddeh1 pllcfg/up input/up r3 a1 irq4 external interrupt request i a2 ?? ? g gpio208 gpio i/o 209 pllcfg1_irq5_ gpio209 p pllcfg1 fmpll mode configuration input i mh v ddeh1 pllcfg/up input/up (for rev2 of the device: ?/up) p2 a1 irq5 external interrupt request i a2 soutd dspi d data output o g gpio209 gpio i/o ? pllcfg2 p pllcfg2 fmpll mode configuration input i mh v ddeh1 pllcfg/ down pllcfg/ down p3 ?xtal p xtal crystal oscillator output o ae v dd33 xtal xtal ac26 ?extal p extal crystal oscillator input i ae v dd33 extal extal ab26 table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-38 pxr40 microcontroller reference manual, rev. 1 214 engclk p engclk ebi engineering clock output note: extclk (external clock input) selected through siu register) of v dde2 engclk/ enabled engclk/ enabled ad1 jtag and nexus (see footnote 12 about resets) ?evti ? 13 evti nexus event in i f v dde2 ?/up evti/up t4 227 evto (the bam uses this pin to select if auto baud rate is on or off) ? 13 evto nexus event out o f v dde2 abs/up evto/hi u1 219 mcko ? 13 mcko nexus message clock out o f v dde2 o/low disabled 14 t2 220 mdo0_gpio220 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo0 15 nexus message data out o f v dde2 o/low mdo0/low u3 a1 ?? ? a2 ?? ? g gpio220 gpio i/o 221 mdo1_gpio221 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo1 15 nexus message data out o f v dde2 o/low ?/down u4 a1 ?? ? a2 ?? ? g gpio221 gpio i/o 222 mdo2_gpio222 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo2 15 nexus message data out o f v dde2 o/low ?/down v1 a1 ?? ? a2 ?? ? g gpio222 gpio i/o 223 mdo3_gpio223 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo3 15 nexus message data out o f v dde2 o/low ?/down v2 a1 ?? ? a2 ?? ? g gpio223 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-39 pxr40 microcontroller reference manual, rev. 1 75 mdo4_gpio75 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo4 15 nexus message data out o f v dde2 o/low ?/down v3 a1 ?? ? a2 ?? ? g gpio75 gpio i/o 76 mdo5_gpio76 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo5 15 nexus message data out o f v dde2 o/low ?/down v4 a1 ?? ? a2 ?? ? g gpio76 gpio i/o 77 mdo6_gpio77 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo6 15 nexus message data out o f v dde2 o/low ?/down w1 a1 ?? ? a2 ?? ? g gpio77 gpio i/o 78 mdo7_gpio78 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo7 15 nexus message data out o f v dde2 o/low ?/down w2 a1 ?? ? a2 ?? ? g gpio78 gpio i/o 79 mdo8_gpio79 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo8 15 nexus message data out o f v dde2 o/low ?/down w3 a1 ?? ? a2 ?? ? g gpio79 gpio i/o 80 mdo9_gpio80 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo9 15 nexus message data out o f v dde2 o/low ?/down y1 a1 ?? ? a2 ?? ? g gpio80 gpio i/o table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-40 pxr40 microcontroller reference manual, rev. 1 81 mdo10_gpio81 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo10 15 nexus message data out o f v dde2 o/low ?/down y2 a1 ?? ? a2 ?? ? g gpio81 gpio i/o 82 mdo11_gpio82 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo11 15 nexus message data out o f v dde2 o/low ?/down y3 a1 ?? ? a2 ?? ? g gpio82 gpio i/o 231 mdo12_gpio231 ? 13 mdo12 15 nexus message data out o f v dde2 o/low ?/down aa1 a1 ?? ? a2 ?? ? g gpio231 gpio i/o 232 mdo13_gpio232 ? 13 mdo13 15 nexus message data out o f v dde2 o/low ?/down aa2 a1 ?? ? a2 ?? ? g gpio232 gpio i/o 233 mdo14_gpio233 ? 13 mdo14 15 nexus message data out o f v dde2 o/low ?/down aa3 a1 ?? ? a2 ?? ? g gpio233 gpio i/o 234 mdo15_gpio234 ? 13 mdo15 15 nexus message data out o f v dde2 o/low ?/down y4 a1 ?? ? a2 ?? ? g gpio234 gpio i/o 224 mseo0 ? 13 mseo0 15 nexus message start/end out o f v dde2 o/low mseo/hi u2 table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
signal descriptions freescale semiconductor 3-41 pxr40 microcontroller reference manual, rev. 1 225 mseo1 ? 13 mseo1 15 nexus message start/end out o f v dde2 o/low mseo/hi t3 226 rdy ? 13 rdy nexus ready output o f v dde2 o/low rdy/hi r4 ?tck ? 13 tck jtag test clock input i f v dde2 tck/down tck/down ab2 ?tdi ? 13 tdi jtag test data input i f v dde2 tdi/up tdi/up ac2 228 tdo ? 13 tdo jtag test data output o f v dde2 tdo/up tdo/up ab1 ?tms ? 13 tms jtag test mode select input i f v dde2 tms/up tms/up ab3 ?jcomp ? 13 jcomp jtag tap controller enable i f v dde2 jcomp/down jcomp/down r1 ? test ? test test mode select (not for customer use) ifv ddeh1 test/down test/down b4 ? vddsyn ? vddsyn clock synthesizer power input i vdde v ddsyn vddsyn vddsyn ad26 ? vsssyn ? vsssyn clock synthesizer ground input i vsse v ddsyn vsssyn vsssyn aa26 ?vstby ? vstby sram standby power input i vhv v ddeh1 vstby vstby m4 ? regsel ? regsel selects regulator mode (linear/switch mode) iaev ddreg regsel regsel w23 ?regctl ? regctl regulator controller output to base/gate of power transistor o ae v ddreg regctl regctl y26 ?vssfl ? vssfl tie to v ss i vss v ddreg vssfl vssfl ab25 ? vddreg ? vddreg source voltage for on-chip regulators and low voltage detect circuits i vddint v ddreg vddreg vddreg aa25 1 the gpio number is the same as the corresp onding pad configuration register (siu_pcr n ) number in pins that have gpio functionality. for pins that do not have gpio functionality, this number is the pcr number. 2 the primary signal name is used as the pin label on the bga map for identification purposes. however, the primary signal functi on is not available on all devices and is indicated by a dash in the following table columns: signal functions, p/f/g, and i/o type. 3 p/a/g stands for primary/alternate/gpio. this column indicates wh ich function on a pin is primar y, alternate 1, alternate 2, (a lternate n ) and gpio. 4 each line in the function column corresponds to a separate signal function on the pin. for all device i/o pins, the primary, al ternate, or gpio signal functions are designated in the pa field of the siu_pcr n registers except where explicitly noted. table 3-4. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
3-42 freescale semiconductor signal descriptions pxr40 microcontroller reference manual, rev. 1 refer to the pxr40 microcontroller data sheet for ball-map figures. 5 mh = high voltage, medium speed f = fast speed fs = fast speed with slew ae = analog with esd protection circuitry (up/down = pul l up and pull down circuits included in the pad) vhv = very high voltage 6 vdde (fast i/o) and vddeh (slow i/o) power supply inputs are gro uped into segments. each segment of vddeh pins can connect to a separate 3.3?5.0 v (+5%/?10%) power supply input. each segment of vdde pi ns can connect to a separate 1.8?3.3 v (10%) power supply. 7 the status during reset pin is sampled after the internal por is negated. prior to exiting por, the signal has a high impedance . the terminology used in this column is: o ? output, i ? input, up ? weak pull up enabl ed, down ? weak pulldown enabled, low ? output driven low, high ? output driven high, abs ? auto baud select (during reset or until jcomp assertion). a dash on the left side of the slash denotes that both the input and output buffers for the pin are off. a dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. the signal name to th e left or right of the slash indicates the pin is enabled. 8 the function after reset of a gpi function is general purpose in put. a dash on the left side of the slash denotes that both the input and output buffers for the pin are off. a dash on the right side of the slash denote s that there is no weak pull up/down enabled on the pin. 9 this signal name includes etpu_c functionality that this device does not have. this is for forward compatibility with devices t hat have an etpu_c. 10 during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pu ll resistors are disabled when the system clock propagates through the device. 11 nmi does not have a pcr pa configuration; it is enabled when nmi is enabled through the siu_ireer and siu_ifeer registers. 12 nexus reset is different than system reset; mdo 1-11 are enabled when trace (rpm or fpm) is enabled, and mdo 12-15 when fpm tra ce is enabled. mseo and mcko are also dependent on trace (rpm or fpm) being enabled. 13 the nexus pins don?t have a ?primary? function as they are not co nfigured by the siu. the pins are selected by asserting jcomp and configuring the npc. siu values have no effect on the f unction of these pins once enabled. 14 mcko is disabled from reset; it can be enabled from the tool (controlled by nexus npc_pcr register).
signal descriptions freescale semiconductor 3-43 pxr40 microcontroller reference manual, rev. 1 3.3 detailed signal description this section provides detailed descriptions of the signal functions available for the device. 3.3.1 etpu signals table 3-5. etpu signals signal name description tcrclka_irq7 _gpio113 tcrclka_irq [7]_gpio[113] is the tcr clock input for the etpu a module. the first alternate function is an external inte rrupt request input for the siu module. etpua[0:11]_etpua[12:23]_ gpio[114:125] etpua[0:11]_etpua[12:23]_gpio[ 114:125] is an input/output channel pin for the etpu a module. etpua[n] is the primary function and is an input/output channel for the etpu a module. the alternate function, etpua[m], is an output channel for the etpu a module. when configured as etpua[m], th e pin functions as output only. etpua12_pcsb1_gpio126 input/out put channel pin for the etpu a module. the first alternate function is a peripheral chip select for the dspi b module. etpua13_pcsb3_gpio127 etpua14_pcsb4_gpio128 etpua15_pcsb5_gpio129 etpua16_pcsd1_gpio130 input/output channel pin for the etpu a module. the first alternate function is a peripheral chip select for the dspi d module. etpua17_pcsd2_gpio131 etpua18_pcsd3_gpio132 etpua19_pcsd4_gpio133 etpua20_irq8 _gpio134 input/output channel pin for the etpu a mo dule. the first alternate function is an external interrupt request input for the siu module. etpua21_irq9 _gpio135 etpua22_irq10 _gpio136 etpua23_irq11 _gpio137 etpua24_irq12 _gpio138 etpua25_irq13 _gpio139 etpua26_irq14 _gpio140 etpua27_irq15 _gpio141 etpua28_pcsc1_gpio142 input/output channel pin for the etpu a module. the first alternate function is a peripheral chip select for the dspi c module. etpua29_pcsc2_gpio143 etpua30_pcsc3_gpio144 etpua31_pcsc4_gpio145 tcrclkb_irq6 _gpio146 tcrclkb_irq [6]_gpio[146] is the tcr b clock input for the etpu module. the alternate function is an external inte rrupt request input for the siu module. etpub[0:15]_etpub[16:31]_ gpio[147:162] etpub[0:15]_etpub[16: 31]_gpio[147:162] are 16 input/ output channel pins for the etpu b module. the alternate functions are ou tput channels for the etpu b module; that is, when configured as etpub[16:31], the pins function as outputs only.
signal descriptions 3-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 3.3.2 irq and gpio signals etpub[16:19]_p csa[1:4]_ gpio[163:166] etpub[16:19]_pcsa[1:4] _gpio[163:166] are in put/output channel pins for the etpu b module. the alternate functions are perip heral chip select signals for dspi a. etpub[20:31]_gpio[167: 178] etpub[20:31]_gpio[167:178] are input/output channel pins for the etpu b module. table 3-6. irq and gpio signals 1 signal name description tcrclkc_ gpio440 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc0_ gpio441 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc1_ gpio442 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc2_ gpio443 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc3_ gpio444 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc4_ gpio445 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc5_ gpio446 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc6_ gpio447 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc7_ gpio448 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc8_ gpio449 this pin does not have a primary function assigned to it. the primary function is reserved for etpu_c for compatibil ity with future devices. etpuc9_ irq0 _gpio450 this pin does not have a primary function assigned to it. the alternate function is an external interrupt request input for the siu module. etpuc10_ irq1 _gpio451 this pin does not have a primary function assigned to it. the alternate function is an external interrupt request input for the siu module. etpuc11_ irq2 _gpio452 this pin does not have a primary function assigned to it. the alternate function is an external interrupt request input for the siu module. etpuc12_ irq3 _gpio453 this pin does not have a primary function assigned to it. the alternate function is an external interrupt request input for the siu module. etpuc13_ irq4 _gpio454 this pin does not have a primary function assigned to it. the alternate function is an external interrupt request input for the siu module. etpuc14_ irq5 _gpio455 this pin does not have a primary function assigned to it. the alternate function is an external interrupt request input for the siu module. etpuc15_ gpio456 this pin does not have a primary function assigned to it. table 3-5. etpu signals (continued) signal name description
signal descriptions freescale semiconductor 3-45 pxr40 microcontroller reference manual, rev. 1 3.3.3 emios signals 1 these signal names include etpu_c functionality that this devi ce does not have. this is for forward compatibility with devices that have an etpu_c. table 3-7. emios signals signal name description emios[0:9]_etpua[0:9]_ gpio[179:188] emios[0:9]_etpua[0:9]_gpio[1 79:188] is an input/output channel pin for the emios module. the alternate functions are output chan nels for the etpu a module; that is, when configured as etpua[0:9], the pins function as outputs only. emios10_sckd_gpio189 emios10_sckd_g pio189 is an input/output channel pin for the emios module. the alternate function is a dspi clock pin for the dspi d module. emios11_sind_gpio190 emios1 1_sind_gpio190 is an input/output channel pin for the emios module. the alternate function is a data input pin for the dspi d module emios12_soutc_gpio191 emios [12]_soutc_gpio[191] is an output channel pin fo r the emios module. the alternate function is the data out put signal for the dspi c module. emios13_soutd_gpio192 emios [13]_soutd_gpio[192] is an output channel pin fo r the emios module. the alternate function is the data out put signal for the dspi d module. emios14_irq0 _gpio193 emios[14]_irq [0]_gpio[193] is an output channel pin for the emios module. the alternate function is an external interrupt request input. emios15_irq1 _gpio194 emios[15]_irq [1]_gpio[194] is an output channel pin for the emios module. the alternate function is an external interrupt request input. emios[16:23]_e tpub[0:7]_ gpio[195:202] output channel pins for the emios module. alternate function is an etpu b output channel emios24_pcsb0_gpio203 output c hannel pins for the emios module. alternat e function peripheral chip select for the dspi b module. emios25_pcsb1_gpio204 output c hannel pins for the emios module. alternat e function peripheral chip select for the dspi b module. emios26_pcsb2_gpio432 output c hannel pins for the emios module. alternat e function peripheral chip select for the dspi b module. emios27_pcsb3_gpio433 output c hannel pins for the emios module. alternat e function peripheral chip select for the dspi b module. emios28_pcsc0_gpio434 output channel pi ns for the emios module. alternate f unction peripheral chip select for the dspi c module. emios29_pcsc1_gpio435 output channel pi ns for the emios module. alternate f unction peripheral chip select for the dspi c module. emios30_pcsc2_gpio436 output channel pi ns for the emios module. alternate f unction peripheral chip select for the dspi c module. emios31_pcsc5_gpio437 output channel pi ns for the emios module. alternate f unction peripheral chip select for the dspi c module.
signal descriptions 3-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 3.3.4 eqadc signals 3.3.5 flexray signals table 3-8. eqadc signals signal name description ana0?ana23 ana[n] is an analog input to eqadc_a?s converter pair. an24?an39 an[n] is an analog input that goes to both eqadc?s converter pairs. anb0?anb23 anb[n] is an analog input to eqadc_b?s converter pair. vrh_a v rha is the voltage reference high input pin for the eqadc_a. vrl_a v rla is the voltage reference low input pin for the eqadc_a. vrh_b v rhb is the voltage reference high input pin for the eqadc_b. vrl_b v rlb is the voltage reference low input pin for the eqadc_b. refbypcb refbypcb is a bypass capacitor input for the eqadc_b. the refbypcb pin is used to connect an external bias capacitor between the refbypcb pin and v rlb . the value of this capacitor must be 100nf. this bypass capac itor is used to provide a stable reference voltage for the adc. refbypca refbypca is a bypass capacitor input fo r the eqadc_a. the refbypca pin is used to connect an external bias capacitor between the refbypca pin and v rla . the value of this capacitor must be 100nf. this bypass capac itor is used to provide a stable reference voltage for the adc. vdda_a0 v dda n is the analog supply input pin for the eqadc_a. vdda_a1 v dda n is the analog supply input pin for the eqadc_a. refbypca1 refbypca1 is a bypass c apacitor input for t he eqadc_a. the refbypca1 pin is used to connect an external bias capacitor prov iding a stable reference voltage for the adc. vssa_a1 v ssa n is the analog ground reference input pin for the eqadc_a. vdda_b0 v dda n is the analog supply input pin for the eqadc_b. vdda_b1 v dda n is the analog supply input pin for the eqadc_b. vssa_b0 v ssa n is the analog ground reference input pin for the eqadc_b. refbypcb1 refbypcb1 is a bypass capacitor input for the eqadc_b. the refbypcb1 pin is used to connect an external bias capacitor prov iding a stable reference voltage for the adc. table 3-9. flexray signals signal name description fr_a_tx_gpio248 flexray channel a transmit pin. fr_a_rx_gpio249 flexray channel a receive pin. fr_a_tx_en_gpio250 flexray channel a transmit enable pin. fr_b_tx_gpio251 flexray channel b transmit pin. fr_b_rx_gpio252 flexray channel b receive pin. fr_b_tx_en_gpio253 flexray channel b transmit enable pin.
signal descriptions freescale semiconductor 3-47 pxr40 microcontroller reference manual, rev. 1 3.3.6 flexcan signals 3.3.7 esci signals etpuc16_ fr_a_tx_ gpio45 1 this pin does not have a primary function assigned to it. the alternate function is flexray channel a transmit. etpuc17_ fr_a_rx_ gpio458 1 this pin does not have a primary function assigned to it. the alternate function is flexray channel a receive. etpuc18_ fr_a_tx_en_ gpio459 1 this pin does not have a primary function assigned to it. the alternate function is flexray channel a transmit enable. 1 this signal name includes etpu_c functionality that this device does not have. this is for forward compatibility with devices that have an etpu_c. table 3-10. flexcan signals signal name description cntxa_txda_gpio83 transmit pin for the flexcan a module. al ternate function is the transmit pin for the esci a module cnrxa_rxda_gpio84 receive pin for the flexcan a module. alternate function is the receive pin for the esci a module cntxb_pcsc3_gpio85 transmit pin for the flexcan b module. alternate function is a peripheral chip select output for the dspi c module. cnrxb_pcsc4_gpio86 receive pin for the flexcan b module. alternate function is a peripheral chip select output for the dspi c module. cntxc_pcsd3_gpio87 transmit pin for the flexcan c modul e. alternate function is a peripheral chip select output for the dspi c module. cnrxc_pcsd4_gpio88 receive pin for the flexcan c modul e. alternate function is a peripheral chip select output for the dspi c module. cntxd_gpio246 transmit pin for the flexcan d module. cnrxd_gpio247 receive pin for the flexcan d module. table 3-11. esci signals signal name description txda_gpio89 transmit data pin for the esci a module. rxda _gpio90 receive pin for the esci a module. txdb_pcsd1_gpio91 transmit data pin for the esci b module. the alternate function is a peripheral chip select output for the dspi d module. rxdb_pcsd5_gpio92 receive pin for the esci b module. t he alternate function is a peripheral chip select output for the dspi d module. table 3-9. flexray signals (continued) signal name description
signal descriptions 3-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 3.3.8 dspi signals txdc_etrig0_gpio244 transmit data pin fo r the esci c module. the alternate fu nction is external trigger signal to trigger a software or hardware event. the eqadc can detect rising edge, falling edge, high level, and low level on each of the external trigger signals. the eqadc also supports configurable digital filters for these external trigger signals. the eqadc external trigger input pins can be connected to the etpu, the emios, or an external signal. the source is selected by configuring the eqadc trigger source in the siu_isel4-7 registers. etrig[0] is the external trigger for cfifo0, cfifo2, and cfifo4 rxdc_gpio245 receive pin for the esci c module. etpuc19_ txda_gpio460 1 this pin does not have a primary function as signed to it. the alternate function is the transmit pin for the esci a module etpuc20_ rxda _gpio461 1 this pin does not have a primary function as signed to it. the alternate function is the receive pin for the esci a module etpuc21_ txdb_gpio462 1 this pin does not have a primary function as signed to it. the alternate function is the transmit pin for the esci b module etpuc22_ rxdb_gpio463 1 this pin does not have a primary function as signed to it. the alternate function is the receive pin for the esci b module 1 this signal name includes etpu_c functionality that this device does not have. this is for forward compatibility with devices that have an etpu_c. table 3-12. dspi signals signal name description scka_pcsc1_gpio93 spi clock pin for the dspi a module. the alternate signal function is a peripheral chip select for the dspi c module sina_pcsc2_gpio94 data input pin for the dspi a module. the alternate signal function is a peripheral chip select for the dspi c module souta_pcsc5_gpio95 data output pin for the dspi a module. the alternate signal function is a peripheral chip select for the dspi c module pcsa0_pcsd2_gpio96 peripheral chip select for the dspi a module. the alternate signal function is a peripheral chip select for the dspi d module pcsa1_gpio97 peripheral chip selects for the dspi a module. pcsa2_gpio98 pcsa3_gpio99 pcsa4_gpio100 pcsa5_etrig1_gpio101 peripheral chip select for the dspi a module. alternate function is external trigger signal to trigger a software or hardware event. the eqadc can detect rising edge, falling edge, high level, and low level on each of the external trigger signals. the eqadc also supports configurable digital filters for these external trigger signals. the eqadc external trigger input pins can be connected to the etpu, the emios, or an external signal. the source is selected by configuring the eqadc trigger source in the siu_isel4-7 registers. etrig[1] serves as the external tr igger for cfifo1, cfifo3, and cfifo5. table 3-11. esci signals (continued) signal name description
signal descriptions freescale semiconductor 3-49 pxr40 microcontroller reference manual, rev. 1 sckb_gpio102 spi clock pin for the dspi b module. sinb_gpio103 data input pi n for the dspi b module. soutb_gpio104 data output pin for the dspi b module. pcsb0_pcsd2_gpio105 peripheral chip select for the dspi b module. the alternate function is peripheral chip select for the dspi d module. pcsb1_pcsd0_gpio106 peripheral chip select for the dspi b module.the alternate function is peripheral chip select for the dspi d module. pcsb2_soutc_gpio107 peripheral chip sele ct for the dspi b module. the alte rnate function is data output pin for the dspi c module pcsb3_sinc_gpio108 peripheral chip select for the dspi b module. the alternate function is data input pin for the dspi c module. pcsb4_sckc_gpio109 peripheral chip select for the dspi b module. the alternate function is spi clock pin for the dspi c module. pcsb5_pcsc0_gpio110 peripheral chip select for the dspi b module. the alternate function is peripheral chip select for the dspi c module. sckc_sck_c_lvdsp_ gpio235 spi clock pin for the dspi c module. the alte rnate function is the lvds+ version of sckc. sinc_sck_c_lvdsm_ gpio236 data input pin for the dspi c module. the alternate function is the lvds- version of sckc. soutc_sout_c_lvdsp_ gpio237 data output pin for the dspi c module. the alternate function is the lvds+ version of soutc. pcsc0_sout_c_lvdsm_ gpio238 peripheral chip select for the dspi c module. the alternate function is the lvds- version of soutc pcsc1_gpio239 peripheral chip select for the dspi b module. pcsc2_gpio240 peripheral chip select for the dspi b module. pcsc3_gpio241 peripheral chip select for the dspi b module. pcsc4_gpio242 peripheral chip select for the dspi b module. pcsc5_gpio243 peripheral chip select for the dspi b module. etpuc23_ pcsd5_gpio464 1 this pin does not have a primary function assigned to it. the alternate function is a peripheral chip select for the dspi d module. etpuc24_ pcsd4_gpio465 1 this pin does not have a primary function assigned to it. the alternate function is a peripheral chip select for the dspi d module. etpuc25_ pcsd3_gpio466 1 this pin does not have a primary function assigned to it. the alternate function is a peripheral chip select for the dspi d module. etpuc26_ pcsd2_gpio467 1 this pin does not have a primary function assigned to it. the alternate function is a peripheral chip select for the dspi d module. etpuc27_ pcsd1_gpio468 1 this pin does not have a primary function assigned to it. the alternate function is a peripheral chip select for the dspi d module. etpuc28_ pcsd0_gpio469 1 this pin does not have a primary function assigned to it. the alternate function is a peripheral chip select for the dspi d module. table 3-12. dspi si gnals (continued) signal name description
signal descriptions 3-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 3.3.9 ebi signals etpuc29_ sckd_gpio470 1 this pin does not have a primary function assi gned to it. the alternate function is a dspi clock pin for the dspi d module. etpuc30_ soutd_gpio471 1 this pin does not have a primary function assi gned to it. the alternate function is a data output pin for the dspi d module. etpuc31_ sind_gpio472 1 this pin does not have a primary function assi gned to it. the alternate function is a data input pin for the dspi d module. 1 this signal name includes etpu_c functionality that this device does not have. this is for forward compatibility with devices that have an etpu_c. table 3-13. ebi signals (development bus only) signal name description d_cs0 _gpio256 ebi chip sele ct output signal. d_cs2 _d_dat31_gpio257 ebi chip select output signal. the alternate function is data signal 31. d_cs3 _d_tea _gpio258 ebi chip select output signal. the altern ate function is tea which indicates that an error occurred in the current external bus transfer. d_add12_gpio259 ebi address signals. d_add13_gpio260 d_add14_gpio261 d_add15_gpio262 d_add16_d_dat16_gpio263 ebi address signals with alternate functions of ebi data signals. d_add17_d_dat17_gpio264 d_add18_d_dat18_gpio265 d_add19_d_dat19_gpio266 d_add20_d_dat20_gpio267 d_add21_d_dat21_gpio268 d_add22_d_dat22_gpio269 d_add23_d_dat23_gpio270 d_add24_d_dat24_gpio271 d_add25_d_dat25_gpio272 d_add26_d_dat26_gpio273 d_add27_d_dat27_gpio274 d_add28_d_dat28_gpio275 d_add29_d_dat29_gpio276 d_add30_d_dat30_gpio277 d_dat[0:15]_gpio[278: 293] ebi data signals. table 3-12. dspi si gnals (continued) signal name description
signal descriptions freescale semiconductor 3-51 pxr40 microcontroller reference manual, rev. 1 3.3.10 reset and clock signals d_rd_wr _gpio294 indicates whether an external bus transfer is a read or write operation. d_we0 _gpio295 write/byte enable specify which data pins contain valid data for an external bus transfer. d_we1 _gpio296 d_oe _gpio297 output enable indicates that the ebi is ready to accept read data. d_ts _gpio298 transfer start is asserted by the ebi owner to indicate the start of a transfer. d_ale_gpio299 address latch enable is used to demultipl ex the address from data bus. it is asserted while the least significant 16 bits of the address ar e present in the multiplexed address/data bus. d_ta _gpio300 transfer acknowledge is asserted by th e ebi owner to acknowledge that the slave has completed the cu rrent transfer. d_cs1 _gpio301 ebi chip sele ct output signal. d_bdip _gpio302 burst data in progress indicates th at an ebi burst transfer is in progress. d_we2 _gpio303 write/byte enable specify which data pins contain valid data for an external bus transfer. d_we3 _gpio304 d_add9_gpio305 ebi address signals. d_add10_gpio306 d_add11_gpio307 table 3-14. reset and clock signals signal name description reset the reset input is asserted by an external device to reset the all modules of the device mcu. the reset pin must be asserted during a power-on reset. rstout the rstout output is a push/pull output that is a sserted during an internal device reset. the pin can also be asserted by software without causing an internal reset of the device mcu. note: during a power-on-reset (por), rstout is tri-stated. bootcfg[0:1]_irq [2:3]_ gpio[211:212] bootcfg[0:1] signals are samp led on every reset. the values are used by the boot assist module (bam) program to determine the boot configuration of the device. the alternate functions are the external interrupt request inputs (irqs). wkpcfg_nmi_gpio213 wkpcfg (sampled at every reset) determines whether specific etpu and emios pins are connected to a weak pullup or weak pulldown during and immediately after reset. the alternate function (nmi) is a critical interrupt to the core. pllcfg0_irq4 _gpio208 pllcfg n are sampled at every reset. these values are used to configure the fmpll mode of operation. the alternate functi on is an external interrupt request input. pllcfg1_irq5 _gpio209 pllcfg n are sampled at every reset. these values are used to configure the fmpll operation mode. the alternate functions are an external interrupt request input and data output for the dspi module d. pllcfg2 pllcfg n are sampled at every reset. these values are used to configure the fmpll operation mode. pllcfg2 configures the crystal oscillator range. table 3-13. ebi signals (development bus only) (continued) signal name description
signal descriptions 3-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 3.3.11 jtag and nexus signals xtal xtal is the output pin for an external crystal oscillator. extal extal is the input pin for an external crystal oscillator or an external clock source. d_clkout clkout is the device system cl ock output (for the development ebi). engclk engclk is a 50% duty cycle output clock with a maximum frequency of the device system clock divided by two. engclk is not synchronous to clkout. table 3-15. jtag and nexus signals signal name description evti evti is an input that is read during a debug port reset to enable or disable the nexus auxiliary port for data trace. after reset, the evti pin is used to initiate program and data trace synchronization messages or generate a breakpoint. evto evto is an output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. the bam uses this pin to select if auto baud rate is on or off ( section 9.3.4, serial boot mode ). mcko mcko is a free running clock output to the development tools which is used for timing of the mdo and mseo signals. mdo0_gpio220 1 1 gpio function for mdo[11:0] is only available on rev.2 of t he device. do not connect pin directly to a power supply or ground. mdo[0] is a trace message output to the deve lopment tools. in addition, mdo[0] indicates the lock status of the system clock following a power-on reset. there is an internal pullup on mdo[0]. this pin functions as gpio when nexus messaging is disabled. mdo[3:1]_gpio[223:221] 1 mdo[3:1] are the trace message outputs to t he development tools for reduced port mode. these pins function as gpio when nexus messaging is disabled. mdo[11:4]_gpio[82:75] 1 mdo[11:4] are the trace message outputs to the development tools for reduced port mode. these pins function as gpio when nexus messaging is disabled mdo[15:12]_gpio[234:231] trace message outputs to the deve lopment tools for full port mode. these pins function as gpio when the nexus development interface (ndi) functions in reduced port mode or when nexus messaging is disabled mseo [1:0] mseo [1:0] are output signals that indicate when messages start and end on the mdo pins. rdy rdy is an output signal that indicates to the de velopment tools the data is ready to be read from or written to the nexus read/write access registers. tck tck provides the clock input for the on-chip test logic. tdi tdi provides the serial test instructi on and data input for the on-chip test logic. tdo tdo provides the serial test da ta output for the on-chip test logic. tms tms controls test mode operations for the on-chip test logic. jcomp jcomp enables the jtag tap controller. test test places the chip into test mode. you must tie this pin to vss. table 3-14. reset and clock signals (continued) signal name description
signal descriptions freescale semiconductor 3-53 pxr40 microcontroller reference manual, rev. 1 3.3.12 pmc and power/voltage signals table 3-16. pmc and power/voltage signals signal name description regsel selects pmc regulator mode (linear/switch mode). regctl core voltage regulator output control pin to the external bipolar/mos transistor. vddsyn v ddsyn is the power supply input for the fmpll. it is also the 3.3v regulator output, when enabled (see the pmc chapter). vsssyn v sssyn is the ground reference input for the fmpll. vdd33 io pre-drivers and flash power supply. vstby v stby is the power supply input that is used to maintain a portion of the contents of internal sram during powe r down. if not used, tie v stby to v ss . vssfl vssfl must be tied to v ss . vddreg source voltage for on-chip regulators and low voltage detect (lvd) circuits. vddeh n , vdde n i/o supply input. vrh_a v rha is the voltage reference high input pin for the eqadc_a. vrl_a v rla is the voltage reference low input pin for the eqadc_a. vrh_b v rhb is the voltage reference high input pin for the eqadc_b. vrl_b v rlb is the voltage reference low input pin for the eqadc_b. vdda_a0 v dda n is the analog supply input pin for the eqadc_a. vdda_a1 v dda n is the analog supply input pin for the eqadc_a. vssa_a1 v ssa n is the analog ground reference input pin for the eqadc_a. vdda_b0 v dda n is the analog supply input pin for the eqadc_b. vdda_b1 v dda n is the analog supply input pin for the eqadc_b. vssa_b0 v ssa n is the analog ground reference input pin for the eqadc_b.
signal descriptions 3-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 4-1 chapter 4 resets note throughout this text the phrase ?reset conf iguration pins? is used to refer to wkpcfg, bootcfg, and pllcfg pins. not all packages have bootcfg[0] . in this case, bootcfg[0] is sampled as 0b0. 4.1 reset sources this device supports the foll owing system reset sources: ? power-on reset ? external reset ? loss of lock reset ? loss of clock reset ? watchdog timer/debug reset ? jtag reset ? software system reset all reset sources are processed by the reset controller, which monito rs the reset input sources, and upon detection of a reset ev ent, resets internal logic and c ontrols the assertion of the rstout pin. the software external reset only causes the rstout pin to be asserted for a number of clock cycles determined by the pll mode (refer to section 4.3.2, rstout ), and does not reset the device. for all reset sources, the bootcfg[0: 1] and pllcfg[0:2] signals are us ed to determine the boot mode and configuration of the fmpll, respectively. table 4-1 shows the options for bootcfg[0:1] and table 4-2 for pllcfg[0:2]. refer to chapter 6, frequency modulated phase-locked loop (fmpll) , for information on the fmpll during reset. table 4-1. bootcfg options bootcfg[0] bootcfg[1] meaning 0 0 boot from internal flash memory 0 1 flexcan / esci boot 1 0 boot from external memory 1 1 this mode is only available in packages that have an ebi. 1 1 boot from external memory 1
resets pxr40 microcontroller reference manual, rev. 1 4-2 freescale semiconductor the reset status register (siu_rsr) gives the source, or sources, of the last re set and indicates whether a glitch has occurred on the reset pin. the siu_rsr is updated for all reset sources except jtag reset. all reset sources initiate execution of the boot assi st module (bam) program with the exception of the software external reset. the reset configuration ha lf word (rchw) determines the mcu configuration after reset. the rchw is stored in internal flash, or a de fault configuration is used. during rese t, the rchw is read from internal flash memory. the bootcfg[0:1] 1 pins are defined in chapter 7, system integration unit (siu) . the bam program reads the value of the bootcfg[0:1] pins from the bootcfg field of the siu_rsr, then reads the rchw from the specified location, and then uses the rchw value to determine and execute the specified boot procedure. note: the reset controller latches the value on the bootcfg input to the siu 4 clock cycles prior to the negation of rstout . 4.2 reset vector the reset vector for this device is 0xffff_fffc. this is a fixed loca tion in the bam. the bam program executes after every internal reset. the bam program determines where to branch after its execution completes based on the value on the bootcfg[0:1] pins. see the bam chapter?s functional description for details on the bam program operation and branch location to application software. 4.3 reset pins 4.3.1 reset the reset pin is an active low input. the reset pin must be asserted by an external device during a power-on or whenever an external reset is required. the internal reset signal asserts only if the reset pin asserts for 10 clock cycles . assertion of the reset pin while the reset state m achine is already processing a reset causes the reset cycle to start over. the reset pin has a glitch detector which detects spikes greater than 2 clocks in duration that fa ll below the switch point of the inpu t buffer logic of the vddeh input table 4-2. pllcfg options package pins 1 clock mode pllcfg[0] pllcfg[1] 0 0 pll off mode 0 1 normal mode with external reference 1 0 normal mode with crystal reference 11 reserved 1 the pllcfg[2] pin configures the crystal oscillator range: pllcfg[2] = 0, for 8 mhz to 20 mhz pllcfg[2] = 1, for 40 mhz 1. bootcfg[0] is not available on all packages.
resets pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 4-3 pins. the switch point lies betw een the maximum vil and minimum vi h specifications for the vddeh input pins. figure 4-1 and figure 4-2 show logic flows of the reset st ate machine on assertion of reset . 4.3.2 rstout the rstout pin is an active low output that uses a push/pull configuration. the rstout pin is driven to the low state by the mcu for all internal and external reset sources. if the pll is configured for normal mode, the rstout pin is asserted for 2400 cl ock cycles, plus 4 cycles for sampling of the configuration pins. see table 4-3 for other source values. the rstout pin can also be asserted by a write to the ser bit of the system reset control register (siu_srcr); however no system rese t occurs under this circumstance. 4.4 fmpll lock gating signal the fmpll loss of lock reset request is connected to both a reset request and a reset gating signal in the siu. the fmpll asserts the loss of lock re set request until the pll has achieved lock. 4.5 reset source descriptions for the following reset source descriptions refer to the reset flow diagrams in figure 4-1 and figure 4-2 . figure 4-1 shows the reset flow for assertion of the reset pin. figure 4-2 shows the internal processing of reset for all reset sources. table 4-3. clock cycles for different reset sources source description number of clock cycles (short count) 1 1 used in the xosc and xref modes. number of clock cycles (long count) 2 2 used in the bypass and 1:1 modes. siu_por power on reset 2400 16000 siu_er external rese t (reset pin) 2410 16100 siu_llr loss of lock reset 2420 16200 siu_wtr watchdog timer reset 2430 16300 siu_cr core reset 2440 16400 siu_swtr software watchdog timer reset 2450 16500 siu_lcr loss of clock reset 2460 16600 siu_ssr software system reset 2470 16700 siu_ser software external reset 2480 16800
resets pxr40 microcontroller reference manual, rev. 1 4-4 freescale semiconductor figure 4-1. external reset flow diagram asserted? f t reset f t asserted? reset asserted? reset a wait 2 clock cycles set latch, wait 8 clock set rgf bit to entry point in internal reset flow f t cycles
resets pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 4-5 figure 4-2. internal reset flow diagram f t rstout assert negated? software asserted? external reset update reset status register negated? asserted? software system reset f t f t clock cycles clock cycles f t latch wkpcfg pin latch pllref, bootcfg reset request rstout negate internal resets and wait 24001 wait 4 clock cycles wait n1 apply wkpcfg pin rstout assert internal resets and a entry point from apply bootcfg and pllref pins values asserted? internal reset f t loss of lock external reset flow and por notes: 1. the clock count is dependent on the configuration of the pll (refer to section 4.3.2, rstout ).
resets pxr40 microcontroller reference manual, rev. 1 4-6 freescale semiconductor 4.5.1 power-on reset (por) the internal power-on reset signal is asserted when either the supply voltages, nominally 3.3v (vdd33) and 1.2v (vdd) or the reset supply (vddeh1) fa ll below defined threshold voltages. see the device data sheet for the specifi cations of these threshol ds. the pmc provides additi onal software-configurable registers for masking of por asser tions based on these and additional supplies. see the pmc chapter for details. although assertion of the power- on reset signal causes reset, the reset pin must be asserted during a power-on reset to guarant ee proper operation of the mcu. the system clock source is dete rmined during rese t as shown in table 6-13 (fmpll chapter). the value of the pllcfg[0:1] pins are latche d during reset. if pllcfg[0:1] are changed during a reset other than power-on reset, the internal clocks may glitch as the clock source is changed between pll off mode and pll clock mode or from one pll clock mode to a nother. whenever pllcfg[0:1] are changed in reset to a value other than what it was before the reset, an immediate loss of lock condition is de clared. this only applies if the pll was running in a locked stat e prior to the assertion of reset and change of pllcfg[0:1]. the signal on the wkpcfg pin determ ines whether weak pull up or pul l down devices are enabled after reset on the etpu and emios pins. the wkpcfg pin is applied on the assertion of the internal reset signal (assertion of rstout ). see section 4.7.3, reset weak pu ll up/down configuration , for more information. once the reset input pin is negated the reset controller ch ecks the fmpll loss of lock reset request signal. the internal reset signal and rstout are kept asserted until the fm pll negates the loss of lock reset request signal. after the loss of lock reset reque st signal is negated, the re set controller waits for a predetermined number of cl ock cycles (refer to section 4.3.2, rstout ) before negating the rstout pin. the reset configuration pins are sampled 4 clock cycles before the negation of rstout , and the associated bits/fields are updated in the siu_rsr. in addition, the pors and ers b its are set, and all other reset status bits are cleared in the reset status register. 4.5.2 external reset when the reset controller det ects assertion of the reset pin, the internal reset signal and rstout pin are asserted. the values on the wkpcfg pin and pllcfg pins are applied at the assertion of the internal reset signal (assertion of rstout ). once the reset pin is negated and the fmpll loss of lock reset request signal is negated, the reset c ontroller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes, the reset configuration pins are latched. the reset controller then waits 4 clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, the ers bit is set, and al l other reset status bits in the siu_rsr are cleared. 4.5.3 loss of lock a loss of lock reset occurs when the fmpll loses lock and the loss of lock reset enable (lolre) bit in the fmpll synthesizer control register (esy ncr2) is set. the internal reset signal and rstout pin are asserted. the values on the wkpcfg and pllcfg pins are applied at the as sertion of the internal reset signal (assertion of rstout ). once the fmpll loss of lock reset request signal is negated, the reset controller waits for a predetermine d number of clock cycles (refer to section 4.3.2, rstout ). once
resets pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 4-7 the clock count finishes, the reset c onfiguration pins are sampled. the re set controller then waits 4 clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, the llrs bit is set, and all ot her reset status bits in the siu_rsr are cleared. refer to section 6.4.3.1, pll lock detection , in the fmpll chapter for more information on loss of lock. 4.5.4 loss of clock a loss of clock reset occurs when a failure in either the referen ce signal or fmpll output, and the loss of clock reset enable (locre) bit in the esyncr2 is set. the internal reset signal and rstout pin are asserted. the value on the wkpcfg and pllcfg pins are applied at the asserti on of the internal reset signal (assertion of rstout ). once the loss of clock and loss of lo ck reset request si gnals are negated, the reset controller waits for a predeter mined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes, the re set configuration pins are sampled. the reset controller then waits 4 clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, the lcrs bit is set, and all other reset status bits in the siu_ rsr are cleared. refer to section 6.4.3.2, loss-of-clock detection , in the fmpll chapter for more information on loss of clock. 4.5.5 core watchdog timer/debug reset there are two watchdog timer resets: a core watchdog and a platform watchdog. a core watchdog timer reset occurs when the e200z7 core watchdog timer is enab led (the e200z7 core watchdog is counting core clocks, which is different th an the peripheral/platform clocks), and a time-out occurs with the enable next wa tchdog timer (ewt) and watchdog timer interrupt status (wis) bits set in the timer status register, and with the watc hdog reset control (wrc) field in the timer control register configured for a reset. the wdrs bit in the siu_rsr is also set when a debug reset command is issued from a debug tool. to determine whethe r the wdrs bit was set due to a watchdog timer or debug reset, see the wrs field in the e200z7 core timer status register. the effect of a watchdog timer or debug reset request is the same for the reset controller. the internal reset signal and rstout pin are asserted. the value on the wkpcfg pin is applied at the assertion of the internal reset sign al (assertion of rstout ), as is the pllref value. once the watchdog timer/debug reset request is negated and the fmpll loss of lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes the reset configuration pins are sampled. the reset controller then waits 4 clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, the wtrs bit is set, and all other reset status bits in the siu_rsr are cleared. refer to the e200z7 core reference manual for more information on the core watchdog timer and debug operation. refer to chapter 18, software watchdog timer (swt) , for more information on the platform watchdog. 4.5.6 jtag reset a system reset occurs when jtag is enabled and ei ther the extest, clamp, or highz instructions are executed by the jtag controller. the internal re set signal is asserted. the state of the rstout pin is determined by the jtag instruction. the values on the wkpcfg and pllcfg pins are applied at the
resets pxr40 microcontroller reference manual, rev. 1 4-8 freescale semiconductor assertion of the internal reset signal. once the jtag reset request is negated an d the fmpll loss of lock reset request signal is negated, the reset controller wa its for a predetermined numbe r of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes the re set configuration pins are sampled, and the associated bits/fields are updated in the siu_rsr. the reset status bits in the siu_rsr are unaffected. refer to chapter 32, ieee 1149.1 test acce ss port controller (jtagc) , for more information. 4.5.7 software system reset a software system reset is caused by a write to the ssr bit in th e system reset control register (siu_srcr), section 7.3.1.3, system reset c ontrol register (siu_srcr) . a write of one to the ssr bit causes an internal reset of the mcu. the internal reset signal and rstout pin are asserted. the value on the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), as is the pllref value. the ssr bit is automatically clear ed and once the fmpll loss of lock reset request signal is negated, the reset contro ller waits for a predetermined num ber of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes the reset configuration pins are sampled. the reset controller then waits 4 clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, the ssrs bit is set, and all other reset status bits in the siu_rsr are cleared. 4.5.8 software external reset a write of one to the ser bit in the siu_srcr causes the external rstout pin to be asserted for a predetermined number of cl ock cycles (refer to section 4.3.2, rstout ). the ser bit automatically clears after the clock counting expi res. a software external reset does not cause a reset of the mcu, the bam program is not executed, the reset co nfiguration pins are not sampled. the serf bit in the siu_rsr is set, but no other status bi ts are affected. the serf bit in the si u_rsr is not automatically cleared after the 6000 clock cycles expire, and remains set until cleared by software or another reset besides the software external reset occurs. for a software external reset, the e200z7 core will continue to execute instructions, timers that are enabled will continue to operate, and interrupt requests will contin ue to be processed. it is the responsibility of the application to ensure devices connected to rstout are not accessed during a software external reset, and to determine how to manage mcu resources when using the software external reset. 4.6 reset registers in the siu the system integration unit (siu) on this device in cludes two register s, siu_rsr and siu_srcr, that affect the reset behavior of this device. see chapter 7, system integration unit (siu) ,for descriptions of these registers.
resets pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 4-9 4.7 reset configuration 4.7.1 reset configuration half word (rchw) 4.7.1.1 rchw overview the reset configuration half word (rchw) defines boot options and must be programmed in a choice of predefined locations in internal flash. the word at the word address boundary after the rchw must be programmed with the user a pplication?s starting address. the bam pa sses control to the user application at this starting address. on every reset except the software external reset (ser ), in internal or external boot modes, the bam attempts to read the rchw from in ternal or external memory respec tively. the locations for the rchw are given in table 4-4 . for internal boot, the predefined locations are searched in the order given in the table. if a valid rchw is not found in internal boot mode or in external boot mode, the bam initiates the serial boot mode. note that in serial boot mode, a user define d start address must still be supplied as part of the download protocol. refer to the bam chapter for complete details. 4.7.1.2 rchw structure when booting from the external flash device, the rc hw must reside in the first 16 bits of memory. table 4-4. rchw location boot mode address external 0x0000_0000 internal 0x0000_0000 0x0000_4000 0x0001_0000 0x0001_c000 0x0002_0000 0x0003_0000 boot_block_address + 0x0000_0000 0123456789101112131415 swtwteps0vle01011010 boot identifier = 0x5a figure 4-3. reset configuration half word
resets pxr40 microcontroller reference manual, rev. 1 4-10 freescale semiconductor the following table describes the fields in the reset configuration halfword: when enabled by rchw[swt, wte] bits, the watchdog timeout periods are as shown in table 4-6 . note the following: ? the core wd timeout for 20 and 40 mhz crystal is the same because the pllcfg[2] pin should be set for 40 mhz crystal, which has the effect of doubling the pll input divider. ? the swt clock source is direct ly from the crystal oscillator. th e core wd is clocked by the pll. ? the core wd timeouts reported here correspond to the pll settings after reset. core wd timeouts will change as soon as the pll is programmed with different multipliers. table 4-5. field description 0?3 reserved. these bit values are ignored when the halfw ord is read. program to 0 for future compatibility. 4 swt software watchdog timer enable. this bit determines if the software watchdog timer is enabled after passing control to the user application code. 0 disable software watchdog timer 1 enable software watchdog timer after reset. the timeout period is 261600 system clocks. 5 wte mcu core watchdog timer enable. this bit determines if the core software watchdog timer is enabled.after passing control to the user application code. 0 disable core software watchdog timer 1 enable core watchdog timer after reset. the timeout period is 2.5*2 17 system clocks. 6 ps0 port size. defines the width of the data bus connected to the memory on d_cs0. after system reset, the bam changes d_cs0 to a 16-bit port to fetch the rchw from either 16- or 32-bit exte rnal memories. then the bam reconfigures the ebi as a 16- or 32-bit port, depending on this bit. 0 32-bit d_cs0 port size 1 16-bit d_cs0 port size note: used in development bus boot modes only (not availa ble on all packages). do not clear this bit if the device only has a 16-bit data bus. 7 vle vle code indicator. this bit configures the mmu entr ies 1-3 coded as classic book e instructions or as freescale vle instructions. 0 user code executes as classic book e code 1 user code executes as freescale vle code 8?15 bootid boot identifier. this field serves two functions: ? indicates which block in flash memory contains the boot program ? indicates if the flash memory is programmed (bootid=0x5a) or invalid table 4-6. watchdog timeout periods crystal frequency (mhz) core wd timeout (ms) swt timeout (ms) 827.349 12 18.3 32.7 16 13.7 24.5 20 11 19.6 40 9.8
resets pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 4-11 4.7.2 reset configuration timing the timing diagram in figure 4-4 shows the relationship between reset signals and the configuration pins for a power-on reset. the timing diagram is valid for internal and external rese ts assuming that vdd and vdd33 are within valid operating range s. the wkpcfg and pllcfg signals are applied at the assertion of the internal reset si gnal (assertion of rstout ). the values of the configur ation pins are latched 4 clock cycles before the ne gation of the rstout pin and stored in the reset stat us register and synsr register. figure 4-4. reset configuration timing 4.7.3 reset weak pull up/down configuration the signal on the wkpcfg pin determines whether sp ecified etpu and emios pins are connected to weak pull up or weak pull down de vices at reset (see the signal desc ription chapter for the etpu and emios pins that are affected by wkpcfg). for all rese t sources except the software external reset, the wkpcfg pin is applied at the assertion of the internal re set signal (assertion of rstout ). if the wkpcfg signal is logic high at this time, pull up de vices will be enabled on the etpu and emios pins. if the wkpcfg signal is logic low at the assertion of the internal reset signal, pull down devices will be enabled on those pins. the value on wk pcfg must be held constant duri ng reset to avoid oscillations on rstout reset internal reset vdd por pll xtal clock ready crystal powering up or acquiring lock wkpcfg, bootcfg are user drives config pins relative to rstout pllref is (4 clock cycles) pll locked 2400 1 clocks ?don?t care? and wkpcfg is treated as ?1? during por assertion. pllref and wkpcfg are applied, but not latched. note: 1. the clock count is dependent on th e configuration of the pll (refer to section 4.3.2, rstout ). if the pll is configured in bypass mode, this clock count is 16000. latched. pins start to drive/sample when por negates
resets pxr40 microcontroller reference manual, rev. 1 4-12 freescale semiconductor the etpu and emios pins caused by switching pul l up/down states. the final value of wkpcfg is latched 4 clock cycles befo re the negation of rstout . after reset, software may modify the weak pull up/down selection for all i/o pins th rough the pcr registers in the siu.
freescale semiconductor 5-1 pxr40 microcontroller reference manual, rev. 1 chapter 5 power management controller (pmc) 5.1 introduction the power management controller (pmc) is compatib le with 3.3v or 5v opera tion. it provides voltage regulation to the microcontroller and includes advanced power on rese t (por) and precision low voltage detector (lvd) monitors that guarantee safe device operation. 5.1.1 features the pmc contains the fo llowing features (see section 5.1.1.1, analog pmc_smps features and section 5.1.1.2, digital pmc_smps features for detailed analog and digital features of this device): ? compatible for both 5v and 3.3v operations. ? a switched mode power supply (smps) buck regulator and a low drop out (ldo) linear regulator, sharing the same control pin (regsel). ? smps regulator is selected when the regsel pin is connected to vdd reg. a 5v nominal suppy voltage is recommended to operate and defines the lvd level to 5v. ? ldo regulator is selected when the regsel pin is connected to vss. a 3v nominal suppy voltage is recommended to operate and defines the vddreg lvd level to 3v. ? high precision low voltage de tector (lvd) monitor for pmc supply voltage vddreg, vdd core voltage supply, and vddsyn. ? a low voltage band gap generate s the reference voltages and curr ents for voltage regulators and lvds. ? a power on reset (por) monitor is used to check main regulator supply vddreg and core supply vdd and guarantees proper system functio n even at very low voltage supply levels. ? no power sequencing c onstraint required. ? an independent internal regulator generates 1.2v supply voltage for the low voltage digital portion of the pmc. ? a 5v to 3.3v ldo regula tor is enabled when th e pmc is in smps5v mode and when the pmc is in ldo mode with nominal supply voltage of 5v (ldo5v mode). th e ldo 5v to 3v is disabled when vddreg is 3.3v nominal and in this case vddreg and vddsyn must be connected together (ldo3v mode). ? a loose precision temperature sens or detects over-temperature condi tions in the pmc and adjacent area. its low accuracy requires that temperature is checked with th e included precision temperature sensor before taking any corrective action. ? direct measurement of pmc in ternal voltages is available at predefined adc channels.
power management controller (pmc) 5-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.1.1.1 analog pmc_smps features ? embedded voltage regulator (2.7 v up to 5.5 v regulator supply (vddr eg)) controller for generating core vdd voltage. for the co rrect allowed voltage range refer to pxr40 microcontroller data sheet . ? the pmc supports two regulation modes (linear and switch mode ), which are controlled by regsel pin. ? when vddreg is above 4.0 v roughly, the 3.3 v internal linear regul ator is enabled and regulates the vddsyn ball to a nominal 3.3 v, sense point is taken on vd d33. vddsyn and vdd33 must be connected/shorted together with minimum im pedance (no resistors or inductors allowed). ? monitors the following supplies: ? core voltage pin that connects in the package to core voltage ? 3.3v via the vdd33 pin (input to the 3.3v network) ? 5v on vddreg ? disabling 3.3 v internal regulator ?see section 5.5.4, 3.3v internal voltage regulator . if vddreg is 5 v, you need to drive vdd33/vddsyn at 3.5 v +/- 3% and program th e pmc to regulate the 3.3 v at minimum voltage by programming the corr espondent control nibble to el iminate contention between the two regulators. 5.1.1.2 digital pmc_smps features software interfaces for: ? low voltage detects and por circuits from the pmc analog blocks plus lvd from vddsyn segment as 3.3v lvd ? low voltage detects for reset segment lvd (vddeh1) ? por level of reset pin segement (vddeh1) ? low voltage detects for ot her io segement lvd (vdd eh3, vddeh4, vddeh5, vddeh6, vddeh7) ? low voltage detect on vdda (from adc band gap reference) ? standby regulator brownout circuit
power management controller (pmc) freescale semiconductor 5-3 pxr40 microcontroller reference manual, rev. 1 5.1.2 block diagram the figure 5-1 is the block diagram for the pmc . figure 5-1. power management controller block diagram 5.1.3 pmc operation modes there are three modes of operation and relative c onfiguration used at board level to choose which regulators are active from start up on and which levels for lvd s hould be enforced during operation. pmc operation modes are resumed in table 5-1 . table 5-1. pmc operation modes short mode full name description ldo3v 3.3v voltage supply, ldo regulator enabled when external pin regsel is connected to vss -it has a weak internal resistive pull down- and regulator supply voltage is 3.3v nominal, the linear 1.2v vrc is enabled and the internal 3.3v regulator is disabled with tri-stated output. vddsyn must be connected to vddreg. an external ballast transistor is expected on regctl as described in 1.2v ldo regulator section. vddreg lvd selected to 3v nominal. por vddreg vdd33 lv i vddreg lv i vdd3.3 ldo 3.3v regulator por vdd lv i vdd band gap reference digital interface pmc to adc interface 0.62v pmc logic/registers adc regctl vss regsel vdd vddreg pmc power architecture? ldo 1.2v regulator control buck 1.2v regulator control vddsyn vss
power management controller (pmc) 5-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.2 external signals description 5.2.1 signals information the following table describes the pmc signals and thei r properties (also refer to the signals chapter). 5.3 signals details the following sections detail the signals used by the pmc . 5.3.1 vddreg positive analog power supply for pmc and voltage regul ators. it can be nominal 5v or nominal 3.3v. it supplies internal regulators and lvds. voltage range vddr for 5v operation and vd d33 for 3v operation can be found in the pxr40 microcontroller data sheet . ldo5v 5v voltage supply, ldo regulator enabled when external pin regselis connected to vss -it has a weak internal resistive pull down- and regulator supply voltage is 5v nominal, the linear 1.2v vrc is enabled, as the internal 3.3v regulator. an external ballast transistor is expected on regctl as described in 1.2v ldo regulator section. an external decoupling capacitor is expected on vddsyn (details in the 3.3v regulator section). vddreg lvd selected to 3v nominal. smps5v 5v voltage supply, smps regulator enabled when external pin regsel is connected to vddreg and regulator supply voltage is 5v nominal, the switched mode vrc is e nabled, and the internal 3.3v regulator is enabled. an external mos - schottky device is expected on regctl as described in smps regulator section. a decoupling capacitor must be used on vddsyn (details in the 3.3v regulator section). vddreg lvd selected to 5v nominal. table 5-2. pmc signals pin name type nominal voltage (v) vddreg supply 3.3 or 5 vss supply ground vdd supply 1.2 vddsyn supply 3.3 regsel input ground or vddreg regctl output 0v ? 5v pwm signal in smps mode about vdd+0.7v in ldo mode. vss supply ground vdd33 input 3.3 table 5-1. pmc operation modes (continued) short mode full name description
power management controller (pmc) freescale semiconductor 5-5 pxr40 microcontroller reference manual, rev. 1 requires a decoupling cap of 5 ? 20 uf between vddreg and vss as close as possible to the pins to minimize board parasitcs. 5.3.2 vdd positive digital power supply fo r core voltage. nominal value is 1.2v, voltage range is vdd12. decoupling capacitance configurati on depends on selected regulator (ldo or smps). more details available in the correspondent regulator description and in section 5.7.2, hardware design recommendations . 5.3.3 vddsyn positive 3.3v regulator out put - power supply, voltage range vdd33, usua lly tied flash. internal regulator is on in smps5v mode or in ldo5v mode. the 3.3v regulator is off in ld o3v mode with vddreg in the 3.3v range. when enabled, the vddsyn regulat or can source up to 80 ma keeping the regulation in the 3.3v range. see the pxr40 microcontroller data sheet for more details. sense voltage is taken at vdd33, hence it is recommended to short vddsy n and vdd33 with low impedance short track. when the internal regulator is disabled the pin has a weak 35 k ? pull down resistor and vddsyn must be connected to vddreg. re quires an external capacitor of 200 nf - 4 uf (depending on the application), on the pad or as closest as possible with negative connection to vss. 5.3.4 vss negative digital power supply. pmc substrate connection. 5.3.5 regctl vrc 1.2v output that connects to the base of ballast npn in ldo3v or ldo5v mode, or to the gate of the n-mos in smps5v mode. 5.3.6 regsel analog input that selects 1.2 vrc operation. it can be connected only to vddreg or vss. when connected to vddreg it enables the smps regulator , and requires a nominal supply voltage of 5v. else the ldo regulator is enabled and both 3.3v and 5v operation are allowed. a weak 200k ? pull down resistor keeps the default level at 0v when pin is floating. 5.3.7 vdd33 sense point for lvd and regulator fee dback of the 3.3v vddsyn analog supply. input that produces 3.3v regulator reference and lvd 3.3v reference. must be shorted to vddsyn w ith low impedance connection.
power management controller (pmc) 5-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.4 memory map/register definition table 5-3 shows the pmc memory map. th e pmc memory maps 3 register s for configuring, monitoring, and trimming the lvd monitors. 5.4.1 configuration register (pmc_mcr ) the configuration register contai ns configuration and interrupt en able bits for the lvd monitors. refer to section 5.1.1, features , for a listing of which vddeh powers are monitored. table 5-3. power management controller memory map address register bits access reset value section/page pmc_base + 0x0000 pmc_mcr ? configuration register 32 r/w 0x9800_0000 5.4.1/5-6 pmc_base + 0x0004 pmc_trimr ? trimming register 32 r/w 0x0000_0006 5.4.2/5-8 pmc_base + 0x0008 pmc_sr ? status register 32 r/w 0x0200_0000 or 0x0600_0000 1 1 reset value depends on whether ram standby r egulator switch reported a brownout condition. 5.4.3/5-12 offset: pmc_base + 0x0000 access: user read/write 0 1 2 3 4 56789101112131415 r lv r e r lv r e h lv r e 5 0 lv r e 3 3 lv r e c lv r e a 00 lv i e r lv i e h lv i e 5 0 lv i e 3 3 lv i e c lv i e a 0 tlk w reset100 1100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0000000000000 w reset000 0000000000000 figure 5-2. configuration and status register (pmc_mcr) table 5-4. pmc_mcr field descriptions field description 0 lv r e r reset-pin-supply low-voltage reset enable. this bit defines whether an lvd assertion on the supply of the i/o segment that cont ains the reset pin will gene rate system reset or not. 0 disabled. lvd assertion on the supply of the i/o segment that contains the re set pin does not c ause system reset. 1 enabled. lvd assertion on the supply of the i/o segmen t that contains the reset pin causes system reset. 1 lv r e h vddeh low-voltage reset enable. this bit defines whet her an lvd assertion on any monitored vddeh supply will generate system reset or not. 0 disabled. lvd assertion on any monitore d vddeh supply does not cause system reset. 1 enabled. lvd assertion on any monitore d vddeh supply c auses system reset. 2 lv r e 5 0 vddreg low-voltage reset enable. this bit defines whether an lvd assertion on the vddreg supply of the voltage regulator will generate system reset or not. 0 disabled. lvd assertion on the vddreg supply of the voltage regulator does not cause system reset. 1 enabled. lvd assertion on the vddreg supply of the voltage regulator causes system reset.
power management controller (pmc) freescale semiconductor 5-7 pxr40 microcontroller reference manual, rev. 1 3 lv r e 3 3 vddsyn low-voltage reset enable. this bit defines whether an lvd assertion on the vddsyn supply will generate system reset or not. 0 disabled. lvd assertion on the vddsyn supply does not cause system reset. 1 enabled. lvd assertion on the v ddsyn supply causes system reset. 4 lv r e c core-voltage-supply vdd low-voltage reset enable. this bi t defines whether an lvd assertion on the core voltage vdd supply will generate system reset or not. 0 disabled. lvd assertion on the core voltage supply does not cause system reset. 1 enabled. lvd assertion on the core voltage supply caus es system reset. 5 lv r e a vdda low-voltage reset enable. this bit defines whether an lvd assertion on the analog power input vdda1 will generate system reset or not. 0 disabled. lvd assertion on the analog powe r input vdda1 does not cause system reset. 1 enabled. lvd assertion on the analog power input vdda1 causes system reset. 6?7 reserved 8 lv i e r reset-pin-supply low-voltage interrupt enable. this bit ena bles the generation of the low-voltage interrupt request when the supply of the i/o segment that contains the re set pin falls below the corresponding lvd threshold. the low-voltage interrupt is independent from low-voltage reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled. low-voltage interrupt request is disabled. 1 enabled. low-voltage interrupt request is enabled. 9 lv i e h vddeh low-voltage interrupt enable. this bit enables the generation of the low-voltage interrupt request when any monitored vddeh supply falls below the corresponding lvd threshold. the low-voltage interrupt is independent from low-voltage reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled. low-voltage interrupt request is disabled. 1 enabled. low-voltage interrupt request is enabled. 10 lv i e 5 0 vddreg low-voltage interrupt enable. this bit enables the generation of the low-voltage interrupt request when the vddreg supply of the voltage regulator falls below the corre sponding lvd threshold. the low-voltage interrupt is independent from low-voltage reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled. low-voltage interrupt request is disabled. 1 enabled. low-voltage interrupt request is enabled. 11 lv i e 3 3 vddsyn low-voltage interrupt enable. this bit enables t he generation of the low-voltage interrupt request when the vddsyn power supply gets below the corresponding lvd th reshold. the low-voltage interrupt is independent from low-voltage reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled. low-voltage interrupt request is disabled. 1 enabled. low-voltage interrupt request is enabled. 12 lv i e c core-voltage-supply low-voltage vdd interrupt enable. this bit enables the generation of the low-voltage interrupt request when the core voltage supply gets below the corresponding lvd threshold. the low-voltage interrupt is independent from low-voltage reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled. low-voltage interrupt request is disabled. 1 enabled. low-voltage interrupt request is enabled. table 5-4. pmc_mcr field descriptions (continued) field description
power management controller (pmc) 5-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.4.2 trimming register (pmc_trimr) the trimming register allows the user to fine tune the voltage of the regulators and the lvd thresholds. it can only be written when the tlk bit of the pmc_mc r is negated. once tlk has been asserted, this register becomes read-only unt il the next system reset. 13 lv i e a vdda low-voltage interrupt enable. this bit enables the generation of the low-voltage interrupt request when the analog power input vdda1 falls below the corresponding lv d threshold. the low-volt age interrupt is independent from low-voltage reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled. low-voltage interrupt request is disabled. 1 enabled. low-voltage interrupt request is enabled. 14 reserved 15 tlk trimming lock. this is a set-only bit that comes out of rese t negated, and can be asserted one time after reset to lock the trimming register. once asserted, it cannot be negated anymore. when tlk is asserted, the trimming register becomes read-only and cannot be changed until the next reset. 0 trimming register can be written. 1 trimming register is read-only. 16?31 reserved offset: pmc_base + 0x0004 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 0 lvdatrim lvdregtrim w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vdd33trim lvd33trim vddctrim lvdctrim w reset0000000000000110 figure 5-3. trimming register (pmc_trimr) table 5-5. pmc_trimr field descriptions field description 0?7 reserved table 5-4. pmc_mcr field descriptions (continued) field description
power management controller (pmc) freescale semiconductor 5-9 pxr40 microcontroller reference manual, rev. 1 8?11 lv dat r i m lvd vdda trimming. this field is used to fine tune the voltage threshold of the vdda1 rising lvd, used to monitor the analog power input vdda1. see the pxr40 microcontroller data sheet for details. 0111 lvda+160 mv 0110 lvda+140 mv 0101 lvda+120 mv 0100 lvda+100 mv 0011 lvda+80 mv 0010 lvda+60 mv 0001 lvda+40 mv 0000 lvda+20 mv 1111 nominal, start-up and default value lvda 1110 lvda-20 mv 1101 lvda-40 mv 1100 lvda-60 mv 1011 lvda-80 mv 1010 lvda-100 mv 1001 lvda-120 mv 1000 lvda-140 mv 12?15 lvdregtrim description: this field is used to fine tune the voltage thre shold of lvdreg the rising lvd, used to monitor the vddreg supply - rising edge. see the pxr40 microcontroller data sheet for details. 0111 lvdreg?8 * lvdstepreg 0110 lvdreg?7 * lvdstepreg 0101 lvdreg?6 * lvdstepreg 0100 lvdreg?5 * lvdstepreg 0011 lvdreg?4 * lvdstepreg 0010 lvdreg?3 * lvdstepreg 0001 lvdreg?2 * lvdstepreg 0000 lvdreg?1 * lvdstepreg 1111 nominal, start-up and default value lvdreg 1110 lvdreg + 1 * lvdstepreg 1101 lvdreg + 2 * lvdstepreg 1100 lvdreg + 3 * lvdstepreg 1011 lvdreg + 4 * lvdstepreg 1010 lvdreg + 5 * lvdstepreg 1001 lvdreg + 6 * lvdstepreg 1000 lvdreg + 7 * lvdstepreg table 5-5. pmc_trimr field descriptions (continued) field description
power management controller (pmc) 5-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16?19 vdd33trim description: this field is used to fine tune vdd33 the output voltage of the 3.3v regulator, the vddsyn supply. see the pxr40 microcontroller data sheet for details. 0111vdd33?8 * stepv33 0110 vdd33?7 * stepv33 0101 vdd33?6* stepv33 0100 vdd33?5* stepv33 0011 vdd33?4* stepv33 0010 vdd33?3* stepv33 0001 vdd33?2* stepv33 0000 vdd33?1* stepv33 1111 nominal, start-up and default value vdd33 1110 vdd33+1* stepv33 1101 vdd33+2* stepv33 1100 vdd33+3* stepv33 1011 vdd33+4* stepv33 1010 vdd33+5* stepv33 1001 vdd33+6* stepv33 1000 vdd33+7* stepv33 20?23 lvd33trim description: lvd 3.3v trimming. this field is used to fine tune the rising voltage threshold of the vddsyn supply, which can be internally regulated by the 3.3v regulator in ldo5v and smps5v modes or can be provided externally in ldo3v mode. see the pxr40 microcontroller data sheet for details. 0111 lvd33?8 * lvdstep33 0110 lvd33?7 * lvdstep33 0101 lvd33?6 * lvdstep33 0100 lvd33?5 * lvdstep33 0011 lvd33?4 * lvdstep33 0010 lvd33?3 * lvdstep33 0001 lvd33?2 * lvdstep33 0000 lvd33?1 * lvdstep33 1111 nominal, start-up and default value of lvd33 1101 lvd33+1 * lvdstep33 1110 lvd33+2 * lvdstep33 1100 lvd33+3 * lvdstep33 1011 lvd33+4 * lvdstep33 1001 lvd33+5 * lvdstep33 1010 lvd33+6 * lvdstep33 1000 lvd33+7 * lvdstep33 table 5-5. pmc_trimr field descriptions (continued) field description
power management controller (pmc) freescale semiconductor 5-11 pxr40 microcontroller reference manual, rev. 1 24?27 vddctrim description: this field is used to fine tune vdd12out the output voltage of the 1.2v regulator, correspondent to the vdd supply. see the pxr40 microcontroller data sheet for details. 0111 vdd12out?8 * stepv12 0110 vdd12out?7 * stepv12 0101 vdd12out? 6 * stepv12 0100 vdd12out?5 * stepv12 0011 vdd12out?4 * stepv12 0010 vdd12out?3 * stepv12 0001 vdd12out? 2 * stepv12 0000 vdd12out?1 * stepv12 1111 nominal, start-up and default value of vdd12out 1110 vdd12out+1* stepv12 1101 vdd12out+2* stepv12 1100 vdd12out+3* stepv12 1011 vdd12out+4* stepv12 1010 vdd12out+5* stepv12 1001 vdd12out+6* stepv12 1000 vdd12out+7* stepv12 28?31 lvdctrim description: lvd 1.2v trimming. this field is used to fine tune the rising voltage threshold of the vdd supply. see the pxr40 microcontroller data sheet for details. 0111 lvd12?11 * lvdstep12 0110 lvd12?10 * lvdstep12 ? start up value 0101 lvd12?9 * lvdstep12 0100 lvd12?8 * lvdstep12 0011 lvd12?7 * lvdstep12 0010 lvd12?6 * lvdstep12 0001 lvd12?5 * lvdstep12 0000 lvd12?4 * lvdstep12 1111 lvd12?3 * lvdstep12 1101 lvd12?2 * lvdstep12 1110 lvd12?1 * lvdstep12 1100 default lvd12 value to be programmed immediately after reset if core voltage internal regulator is used 1011 lvd12+ 1* lvdstep12 1001 lvd12+ 2* lvdstep12 1010 lvd12+ 3* lvdstep12 1000 lvd12+ 4* lvdstep12 table 5-5. pmc_trimr field descriptions (continued) field description
power management controller (pmc) 5-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.4.3 status register (pmc_sr) the status register contains interr upt flag bits for the lvd monitors. offset: pmc_base + 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 00000 lv f stby bgrdy bgts 0 0 0 0 0 lv f c stby 00 w w1c reset 0 0 0 0 0 u 1 1 reset value depends on whether ram standby regulator switch reported a brownout condition. 0 0 0000 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lv f c r lv f c h lv f c 50 lv f c 33 lv f c c lv f c a 0 0 lv f r lv f h lv f 50 lv f 33 lv f c lv fa 0 0 w w1c w1c w1c w1c w1c w1c reset0 0 0 0 0 0 0 0 0 0000 000 figure 5-4. status register (pmc_sr) table 5-6. pmc_sr field descriptions field description 0?4 reserved 5 lvfstby standby-ram-supply low-voltage flag. this read-only bi t indicates that a brownout condition was reported by the ram standby regulator switch. software can clear this bit by writing ?1? to the lvfcstby bit. 0 no occurrence. 1 lvd occurrence, or brownout, reported by the ram standby regulator switch. 6 bgrdy bandgap ready. this read-only bit gets asserted wh en the pmc bandgap circuit has finished its startup procedure during power-up. the pmc lvds are di sabled (output negated) wh ile bgrdy is negated. 0 bandgap not ready. pmc lvds disabled. 1 bandgap ready. pmc lvds enabled. 7 bgts bandgap temperature status. this read-onl y bit stores bandgap temperature status. 0 temperature out of range. above 160 c. 1 temperature in range. below 160 c. 8?12 reserved 13 lvfcstby standby-ram-supply lvf clear. this write-only bit is used to clear the low-voltage flag reported by the ram standby regulator switch. writing 1 to this bit inform s the ram standby regulator switch to clear lvfstby. writing 0 has no effect. reading this bit always returns 0. 0 no effect. 1 clears lvfstby. 14?15 reserved 16 lv f c r reset-pin-supply lvf clear. this write-only bit is used to clear the low-voltage flag associated with the supply of the i/o segment that contains the reset pin. writin g 1 to this bit clears lvfr. writing 0 has no effect. reading this bit always returns 0. 0 no effect. 1 clears lvfr.
power management controller (pmc) freescale semiconductor 5-13 pxr40 microcontroller reference manual, rev. 1 17 lv f c h vddeh lvf clear. this write-only bit is used to cl ear the low-voltage flag as sociated with the monitored vddeh supplies. writing 1 to this bit clears lvfh. writing 0 has no effect. reading this bit always return 0. 0 no effect. 1 clears lvfh. 18 lv f c 5 0 vddreg lvf clear. this write-only bit is used to clear the low-voltage flag associated with the vddreg voltage regulator supply. writing 1 to this bit clears lvf50. writing 0 has no effect. reading this bit always returns 0. 0 no effect. 1 clears lvf50. 19 lv f c 3 3 vddsyn lvf clear. this write-only bit is used to clear the low-voltage flag associated with the vddsyn 3.3 v supply. writing 1 to this bit clears lvf33. writin g 0 has no effect. reading this bit always returns 0. 0 no effect. 1 clears lvf33. 20 lv f c c core-voltage-supply lvf clear. this write-only bit is used to clear the low-voltage flag associated with the core voltage supply. writing 1 to this bit clears lvfc. writing 0 has no effect. reading this bit always returns 0. 0 no effect. 1 clears lvfc. 21 lv f c a vdda lvf clear. this write-only bit is used to clear the low-voltage flag associated with the analog power input vdda1. writing 1 to this bit clears lvfa. writing 0 has no effect. reading this bit always return 0. 0 no effect. 1 clears lvfa. 22?23 reserved 24 lv f r reset-pin-supply low-voltage flag. this read-only bit is the low-voltage flag associat ed with the supply of the i/o segment that contains the reset pin. it is asserted when the supply falls below the corresponding lvd threshold, and can be cleared by the cpu by writing 1 to the lvfcr bit. if the lvie r bit is also asserted, a low-voltage interrupt is sent to the cpu. if lvrer is also asserted, a system reset will be generated, which will clear lvfr and negate the interrupt request. 0 no occurrence. 1 lvd occurrence detected on the supply of the i/o segment that contains the reset pin. 25 lv f h vddeh low-voltage flag. this read-only bit is the low-voltage flag associated with the monitored vddeh supplies. it is asserted when any monitored vddeh supply falls below its corresponding lvd threshold, and can be cleared by the cpu by writing 1 to the lvfch bi t. if the lvieh bit is also asserted, a low-voltage interrupt is sent to the cpu. if lvreh is also asse rted, a system reset will be generated, which will clear lvfh and negate the interrupt request. 0 no occurrence. 1 lvd occurrence detected on a monitored vddeh supply. 26 lv f 5 0 vddreg low-voltage flag. this read-only bit is the lo w-voltage flag associated with the vddreg supply of the voltage regulator. it can be cleared by the cpu by wr iting 1 to the lvfc50 bit. if the lvie5 bit is also asserted, a low-voltage interrupt is sent to the cpu. if lvre50 is al so asserted, a system reset will be generated, which will clear lvf50 and negate the interrupt request. 0 no occurrence. 1 lvd occurrence detected on the vddr eg supply of the voltage regulator. table 5-6. pmc_sr field descriptions (continued) field description
power management controller (pmc) 5-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.5 functional description see figure 5-1 for a block diagram of the pmc bl ock. its main building blocks are ? a precision bandgap voltage ? power on reset and low voltage de tector on vddreg regulator supply ? a voltage regulator controller with a linear low drop out and a switched mode power supply options selectable vi a the regsel control ? por and lvd on vdd digital core supply ? a 3.3v ldo regulator, w ith its relative 3.3v lvd ? a digital interface to core logic ? an interface between measurable pm c internal signals to the adc a start-up sequence has been implem ented aiming at improved predictabi lity of pmc behavior. a loose tolerance por keeps the device in reset until the vddreg rises above the minimum required voltage for the internal bandgap to come up. when por clears a nd the band gap reference is stable, the lvds are enabled. a dedicated circuit is used to keep lvds set until current and voltage references are stable and the real lvds? values are valid. when the references are stable, the voltage regulator (selected by the pin regsel) enters in soft start mode and rises in a controlled fashion the 1.2v regul ated voltage supply vdd. as both target regulated voltage vdd12out and lvd level lv d12 rely on bandgap voltage, an eq uivalent variation is to be 27 lv f 3 3 vddsyn low-voltage flag. this read-only bit is th e low-voltage flag associated with the vddsyn 3.3 v supply. it is asserted when the 3.3 v supply falls below the corresponding lvd threshold, and can be cleared by the cpu by writing 1 to the lvfc33 bit. if the lvie33 bit is also asserted, a low-voltage interrupt is sent to the cpu. if lvre33 is also asserted, a system re set will be generated, which will clear lvf3 3 and negate the interrupt request. 0 no occurrence. 1 lvd occurrence detected on the 3.3v supply. 28 lv f c core-voltage-supply low-voltage flag. this read-only bi t is the low-voltage flag associated with the core voltage supply. it is asserted when the core voltage supply falls below the corresponding lvd threshold, and can be cleared by the cpu by writing 1 to the lvfcc bi t. if the lviec bit is also asserted, a low-voltage interrupt is sent to the cpu. if lvrec is also asse rted, a system reset will be generated, which will clear lvfc and negate the interrupt request. 0 no occurrence. 1 lvd occurrence detected on the core voltage supply. 29 lv fa vdda low-voltage flag. this read-only bit is the low-voltage flag associated with the analog power input vdda1. it is asserted when the vdda1 supply falls below its corresponding lvd threshold, and can be cleared by the cpu by writing 1 to the lvfca bit. if th e lviea bit is also asserted, a low-voltage interrupt is sent to the cpu. if lvrea is also asserted, a s ystem reset will be generated, which will clear lvfa and negate the interrupt request. 0 no occurrence. 1 lvd occurrence detected on the vdda1 supply. 30?31 reserved table 5-6. pmc_sr field descriptions (continued) field description
power management controller (pmc) freescale semiconductor 5-15 pxr40 microcontroller reference manual, rev. 1 expected in absolute lvd trip points and voltage re gulator output, so the system shall come up correctly in any condition. if an external regulator is used to generate th e supply voltage, the allowed nominal range is vdd12, but the start up value must be higher than the maximu m lvd threshold lvd12 to clear por and lvd flags and exit the reset state. all lvds force reset at start-up. as soon as all of th em are cleared, the trimming register can be loaded from flash into the band ga p. the low variation of band gap referen ce voltage after trim, reported in the pxr40 microcontroller data sheet , allows the system to achieve hi gh precision regulator target voltage output (not considering transient effects on regulator loads) and lvd trip points. figure 5-5. pmc internal regulators nominal start-up sequence, rising slope may vary 5.5.1 pmc internal 1.2v voltage regulator selection the pmc features two main regulator s for core supply voltage vdd. the selection is done at board level by connecting the regsel to vddreg or vss. a linear low drop out regulator controller is se lected when the pin regsel is connected to vss, otherwise an asynchronous buc k switched mode regulator controller is selected wh en the pin is connected to vddreg. do not change regsel pin voltage when the device is powered by any supply. the allowed voltage range of the pm c supply vddreg is reported in the pxr40 microcontroller data sheet under the vddr symbol. specific ally, when the switched mode supply is chosen (smps5v mode) the nominal supply voltage ex pected is 5 v. nominal voltage values of 3v and 5v are allowed in ldo3v and ldo5v, respectively. this is because in the ldo3v mode, vddsyn/vdd33 are supplied to the soc from external source; whereas in the ldo5 v mode, vddsyn is connected back to vdd33. when the ldo regulator is selected in ldo3v or ldo5v mode both nominal 5.0 v and 3.3 v are allowed. time voltage vddreg 4 (v) 2 vdd vddsyn
power management controller (pmc) 5-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 a weak pull down of about 100 k ? is added to ensure the selection of the ldo regulator even when the signal regsel is not connected at board level. 5.5.2 pmc bandgap an accurate band gap voltage is used in the pmc as reference for regulators and lvds. target band gap voltage vbg is 0.62v with variation defined in pxr40 microcontroller data sheet . during factory test, the bandgap is calibrated in curv ature and absolute value, in order to achieve a good accuracy over temperature range and supply voltage variation. 5.5.3 vddreg lvd a user programmable low voltage detector (lvd) monitors the pm c main supply voltage vddreg. when ldo regulator is se lected, with respective selection pin regsel, the lvd threshold is for a nominal 3.3v supply (both ldo3v and ldo5v modes), el se when the smps regul ator is selected the lvd threshold is nominal 5.0v (smps5v mode). rising lvd threshold voltage is docum ented under lvdreg symbol in the pxr40 microcontroller data sheet . the assertion and negation voltages are adjustable via software by wr iting to the lvdregtrim field of the pmc_trimr register, wh ich selects one of the 16 voltages av ailable through the appropriate tapped output. the reset and default value of the 4-bit register is ?1111?, corresponding to the nominal lvdreg voltage. lvd scaled voltage can be measured via adc by selecting the respective channel reported in table 5-8 . during this measurement, the output of the lvd is tem porarily forced to low leve l so that false events, which may be caused by adc reading, are discarded. 5.5.4 3.3v internal voltage regulator a 3.3v internal voltage regulator is available and it can supply a total dc current of idd33 with a maximum load frequency of 10 khz. the board s hould be designed to dump all current overshoots and undershoots, by having the vddsyn pin connected to de coupling capacitors. the recommended external capacitor range may vary between 220 nf and 2.2 f with esr < 100 m ? . this regulator is always enabled when supply voltage vddreg is in the vddr 5v nominal range. when the supply voltage is in the vddr 3v nominal range the regulator is automatically turned off, so that an external supply can be applied. in this case vdd reg and vddsyn must be connected to the same supply voltage with a maximum voltage difference of 200mv. the regulator can be disabled, so that an external 3.3 v supply can be used (see section 5.1.1, features ). in this case it is recommended that the supplied 3.3v is nominal 3.5v +/- 3% during start up when both regulators may be enabled. for the correct operation of the device the external ly supplied vdd33 voltage must be higher than the maximum co rrespondent lvd rising voltage lvd33.
power management controller (pmc) freescale semiconductor 5-17 pxr40 microcontroller reference manual, rev. 1 the bond diagram and over volta ge protection is shown in figure 5-6 . core lvd and flash supply are provided by pad vdd33, which is also the default feedback signal for the 3.3v regulator loop. a high voltage detect comparator switches the feedback point from vdd33 to the regulator output vddsyn in the event that this node raises above its maximum rating value, forcing th e regulator to correct its dc point. this feature protects the circuitry connected to th e internal 3.3v supply in any event which disconnects vdd33 and vddsyn (e.g. a board fa ilure or a bond wire failure). figure 5-6. 3.3v regulator power connection tolerance of the 3.3v regulator, reported in the pxr40 microcontroller data sheet , assumes appropriate decoupling capacitance on vddsyn pi n, maximum current load less than or equal to idd33, and a correct board layout with reduced parasitics. it excludes line a nd load variation above 10 khz. the regulator output voltage, vdd33o ut, is adjustable via software by writing to the field vdd33trim of the correspondent trimming regist er pmc_trimr, which selects one of the 16 voltages spaced at stepv33 step and available through the relative resist or chain. the reset value of the 4-bit register is ?1111?. 5.5.5 3.3v vddsyn lvd a user programmable low voltage detector (lvd) monitors th e voltage vddsyn. rising lvd threshold voltage is doc umented under lvd33 symbol in the pxr40 microcontroller data sheet . flash internal 3.3v supply vddreg vreg 3.3 vbg vddreg vreg 1.2 vddsyn vdd33 r r r r vbg r lvd core + -
power management controller (pmc) 5-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the assertion and negation voltages are adjustable via software by writing to the lvd33trim field of the pmc_trimr register, which select s one of the 16 voltages availabl e through the appropriate tapped output. the reset and defau lt value of the 4-bit register is ? 1111?, corresponding to the nominal lvd33 voltage. lvd scaled voltage can be measured via adc by selecting the respective channel reported in table 5-8 . during this measurement, the output of the lvd is tem porarily forced to low leve l so that false events, which may be caused by adc reading, are discarded. 5.5.6 1.2v voltage regulator controller a double voltage regulator controller (vrc) is implemented in this power management system. it is composed of a linear ldo vrc, and an sm ps vrc. a soft startu p block slews the out put voltage of the regulator output smoothly in order to avoid ringing or over voltage condition and steep voltage and current slopes. a block diagram of the regulator is shown in figure 5-7 . the ldo voltage regulator controller is designed to drive an external bipolar transistor and relative decoupling capacitance at bipolar emitter. a smaller compensatio n capacitor might be required on regctl, depending on the external bipolar selected. the switched controller is a full analog asynchronous regulator, with ramp compensation and equalized error integration. it is used to drive an external high side n-mos driver / sc hottky diode.the regulator output voltage is adjustable using software, to pe rmit the device to center the supply for maximum transient margin. the feedback of the regulation loop comes from th e vdd core voltage through a trimmable resistive divider. by adjusting the trimming control 4-bit word vddctrim it is possible to adjust the regulator target dc output voltage vdd12o ut during device operation, with 16 voltage steps of size stepv12, around the typical regulator target voltage. the reset value, start up and default condition of the 4-bit register is ?1111?. tolerance of the 1.2v regu lators, reported in the pxr40 microcontroller data sheet , assumes appropriate external active and passive devices as reported in bill of materials section 5.7.2, hardware design recommendations , maximum current load less than or equal to idd12 , and a correct board layout with reduced parasitics. it excludes line and load variation above 10 khz. the 1.2v supply is internally connected to an adc chan nel so that the actual voltage may be read by the microcontroller. the suitable external driver has an automotive range temperature profile and ? in case of npn device a minimum beta of 50, maximum current rating >1.5a; ? in case of high side driver maximum threshold voltage of 1.5v, gate capacitance less than 5nf, maximum current rating >2a.
power management controller (pmc) freescale semiconductor 5-19 pxr40 microcontroller reference manual, rev. 1 figure 5-7. internal regulator 1.2v ldo and smps diagram 5.5.7 1.2v vdd lvd a user programmable low voltage detector (lvd) monitors the core supply voltage vdd. rising lvd threshold voltage is doc umented under lvd12 symbol in the pxr40 microcontroller data sheet . the assertion and negation vol tages are adjustable via software by wr iting to the lvdctrim field of the pmc_trimr register, which select s one of the 16 voltages availabl e through the appropriate tapped output. the reset value of the 4-bi t register is ?0110?, corresponding to the nominal lvd12 voltage. when an internal regulator (smps or ldo) is used to generate the core voltage supply, it is required to change the field of the register to ?1100? before increasing core logic clock frequency. lvd scaled voltage can be measured via adc by selecting the respective channel reported in table 5-8 . during this measurement, the output of the lvd is tem porarily forced to low leve l so that false events, which may be caused by adc reading, are discarded. pwm controller vddreg regulator select decoupling regsel vref band gap vddreg vddreg vrc1p2 vddreg max 1.2a@1.2v njd 2873 vrctrl = trimmed external components pmc 1.2v regulator vdd si3460 50kohm smps mode ldo mode
power management controller (pmc) 5-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.5.8 trimming during power up and reset, the bandgap is untrimm ed. this allows the mcu to come out of reset. at the end of the reset sequence, the bandgap is trimmed by the pmc. this trimming controls the bandgap voltage, which is used as the refe rence for the internal regulators and lvd. the bandgap trim values are not visible and they cannot be altered or overwritten by the user. the levels of the internal regulators and lvd, though, can be adjusted by the user by programming the trim registers. this allows the user to control the internal regulator or lvd level within a range of +/- 8 steps from the default valu e. this is described in section 5.4.2, trimming re gister (pmc_trimr) . 5.5.9 interrupts the pmc generates one interrupt request signal for each lvd source: vddreg lvd, vddsyn lvd, vdd lvd, and vdda1 lvd. the module also genera tes combined interrupt request signal which is asserted whenever any of the individual interrupt request signa ls becomes asserted. 5.5.10 pmc power-on reset a power-on reset (por) circuit monitors its supply voltage, providing a logic re set in a guaranteed low voltage range. power-on reset will assert as soon as possible after the voltage levels of the por power supplies begin to rise. each por will negate before its power supply rises into the spec ified range. the behavior for each por during power supply ramping is shown in figure 5-8 . power-on reset (por) circuits are pres ent at the following power supplies: ? 5v supply of the pmc block and bandgap (vddreg) ? 1.2v core supply vdd the por can be used to prevent cr itical circuit-like band gap refere nce or lvds to operate when the supply voltage is too low (output signa ls are out of specification). por trip voltage tracks with technology variations and it should be such that all circuits, that are disabled by its output, can at least work with supplies down to por level. the dependence between por and lv d on vddreg is summarized in figure 5-9 . as shown, the lvd will reach a consistent state before the por actually releases the reset, avoi ding false startup condition.
power management controller (pmc) freescale semiconductor 5-21 pxr40 microcontroller reference manual, rev. 1 figure 5-8. por rising and falling edges figure 5-9. por and lvd rising and falling edges por_b por_b asserts por_b negates por_b asserts por_b indeterminate indeterminate (ramp up) (ramp down) power supply specified power supply range por_b asserts por_b negates por_b indeterminate v supply specified v supply range lvi_b negates lvi_b asserts por_b & lvi_b overlap lvi_b asserts por_b asserts lvi_b indeterminate por_b & lvi_b overlap
power management controller (pmc) 5-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 5.5.11 adc test mux during pmc functional mode it is possible to pe rform direct measurements through the adc. pmc internal voltages are routed to the adc. each si gnal can be measured with adc running at full speed. regulator feedback and lvd threshold signals propa gated to adc are a scaled down version of the correspondent supply, by means of a resistive divider with program mable steps. the scaled signal read by the adc vscaled will be approximate ly equal to the supply voltage vsuppl y divided by the target voltage (lvd or regulator output) vtarget and mu ltiplied by the band gap reference vbg: vscaled=vsupply*vbg/vtarget. eqn. 5-1 by measuring with adc scaled supply voltage, suppl y voltage and bandgap voltage, it is possible to calculate the approximate target lv d or regulator value. vtarget is equal to: vtarget=vsupply*vbg/vadc. during lvd measurement, the continuous time monito ring is temporarily disabl ed as the multiplexer toggling could induce a false detection. table 5-7. por and lvds that gate mcu reset type supply description por vddreg 5v supply of the pmc block and bandgap (vddreg) por vdd 1.2v core supply vdd lvd vdd lvd core-voltage-supply vdd low-voltage lvd vddsyn lvd vddsyn low voltage lvd reset lvd reset-pin-supply low-voltage table 5-8. adc test mux channel for internal pmc signals eqadc_a channel number signal propagated to adc typical value (approximated) adc0 ch145 band gap 0.62v 0.62v (trimmed) adc0 ch146 analog supply 1.2v 1.22v adc0 ch147 vdd12out equal to vdd12out / 2.045 adc0 ch180 lvd 1.2v equal to vlvd12 / 1.774 adc0 ch181 vdd33out equal to vdd33out / 5.460 adc0 ch182 lvd 3.3v equal to vlvd33 / 4.758 adc0 ch183 lvd 5.0v equal to vlvdreg / 4.758 in ldo mode; (vlvdreg / 7.032 in smps mode) adc1 ch196 lvd vdda equal to vdda lvd / 3.8934
power management controller (pmc) freescale semiconductor 5-23 pxr40 microcontroller reference manual, rev. 1 5.6 initialization the pmc module requires that its ma in supply voltage, vddreg, rises a bove the por level, so that the band gap reference voltage can be enabled. after the band gap has come up and stabilized, th e 1.2v regulator soft star t and optionally the 3.3v regulator soft start begin. when the internal regulator is used to generate 1.2v core supply, it is required to write ?1100? to the lvdctrim field before clock fr equency is increased. 5.7 application information 5.7.1 regulator example figure 5-10. vrc 1.2v ldo confi guration with external bipolar mcu the resistor may or may not be required. this depends on the allowable power dissipation of the npn bypass transistor device. the bypass transistor must be operated out of saturation region. mandatory decoupling capacitor network vddreg vrcctl vdd12 vss *vrcctl capacitor: may or may not be required * regsel
power management controller (pmc) 5-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 5-11. vrc 1.2v buck smps ldo configuration with external mos - schottky diode 5.7.2 hardware design recommendations table 5-10. vrc ldo recommended external devices part name part type nominal description bcp68t1 npn on semiconductor? njd2874 npn on semiconductor? 3bcp68 npn nxp semiconductors? capacitor 6 x 4.7f?20v ceramic low esr -one for each vdd pin capacitor 6 x 0.1f?20v ceramic -one capacitor for each vdd pin capacitor 20f supply decoupling cap (close to bipolar collector) capacitor 2.2uf snubber cap, required with njd2874 (on bipolar base) resistor 12 ohm esr for snubber cap mcu mandatory decoupling capacitor network vddreg vrcctl vdd12 vss no vrcctl capacitor is allowed regsel
power management controller (pmc) freescale semiconductor 5-25 pxr40 microcontroller reference manual, rev. 1 table 5-11. vrc smps recommended external devices part name part type nominal description ir7353 hs nmos + schottky low threshold n-mos / low vf schottky diode ss8p3l schottky low vf schottky diode si3460f nmos low threshold n-mos lqh66sn2r2m03 inductor 2.2 h?3.2a murata? unshielded or shielded coil c3225x7r1e106m capacitor 2x10uf - 25v tdk hi gh capacitance ceramic smd (on vdd close to coil) c3225x7r1e225k capacitor 2x2.2uf - 25v tdk ceramic smd (on vdd close to mcu) capacitor 6 x 0.1uf - 20v ceramic -one capacitor for each vdd pin c3225x7r1e106m capacitor 2x10uf - 25v supply decoupling cap - close to n-mos drain resistor 20 kohm pull down for power n-mos gate
power management controller (pmc) 5-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 6-1 pxr40 microcontroller reference manual, rev. 1 chapter 6 frequency modulated phase-locked loop (fmpll) 6.1 introduction the frequency modulated phase-loc ked loop (fmpll) module is a fr equency modulated phase-locked loop that has been optimized to generate voltage controlled oscillator (vco) frequencies from 192 mhz ? 600 mhz based on an input clock range of 8 mhz to 40 mhz. the frequency multiplication, output dividers and the frequency modulation waveform are regi ster-programmable through a peripheral bus interface. figure 6-1 shows the operating frequency domains of the various blocks on this device. figure 6-1. pxr40 block operating frequency domain diagram pll core platform / etpu / ebi cal bus extal d_clkout f platf note: t cycsys = 1 / f sys t cyc =1 / f platf ?? 2 = divide-by-2 ? x = divide-by-x, depending on siu_sysdiv[bypass] and siu_sysdiv[sysclkdiv]. blocks / (d_clkout is not available on all packages and cannot be programmed for faster than fsys/2.) ? 2 pllcfg[0:1] siu_sysdiv[ sysclkdiv [0:1]] ipg div sel etpu div sel siu_sysdiv[ ipclkdiv [0:1]] f etpu sysdiv ? x flash ndedi div f ebi_cal siu_sysdiv[ bypass ] x = 2, 4, 8, or 16 x=1 f sys siu_eccr[ ebdf [0:1]] f periph
frequency modulated phase-locked loop (fmpll) 6-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 for register and bit descriptions, see: ? section 7.3.1.27, system clock register (siu_sysdiv) ? section 7.3.1.24, external clock control register (siu_eccr) 6.1.1 block diagram a simplified block diagram of the fmpll illustrate s the functionality and interdependence of major blocks (see figure 6-2 ). shaded blocks represent analog circuit components th at make up the core analog portion of the fmpll. the complete fmpll closed-loop system contains the feedback divider (emfd) and output divider (erfd). refer to section 6.4.3.3, pll normal mode without fm, for details on each sub-block. figure 6-2. fmpll block diagram 6.1.2 features the fmpll has these major features (refer to pxr40 microcontroller data sheet for performance data and restrictions): ? input clock frequency range: 8 mhz to 40 mhz (extal) ? programmable frequency multipl ication factor setti ngs which specify vco frequencies of 192 mhz ? 600 mhz ? pll off mode (low-power mode) ? register programmable output clock divider (erfd) ? programmable frequency modulation ? modulation applied as a triangle waveform ? peak-to-peak register pr ogrammable modulation depths fmdac_ctl[0:4] d2afm fmdac extal eprediv pfd filter vco erfd loc_pll loc_ref emfd pll clock out used to create the loss of clock reset request and decide which pll mode to switch to when a loss of clock condition occurs
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-3 pxr40 microcontroller reference manual, rev. 1 ? register programmable modulation rates of f extal /80, f extal /40, and f extal /20 (modulation rate must be between 400 khz and 1 mhz). ? lock detect circuitry provides a signal indicating the fmpll ha s acquired lock and continuously monitors the fmpll output for any loss of lock ? loss-of-clock circuitry monitors input refere nce and fmpll output cloc ks with programmable ability to select a backup cl ock source as well as generate a reset or interr upt in the event of a failure 6.1.3 modes of operation there are two main modes of fm pll: pll off mode and normal mode. these modes are briefly described in this section. when pll off mode is sel ected, the fmpll is turned off; the cl ock source must come from somewhere else or the device will not function. the lock detect or is not functional and does not indicate that the fmpll is in a locked state. frequency modulation is not available and the fmpll is put into a low-power, idle state. a full swing square wave clock input fo r the entire system must be supplied on the extal pin (refer to pxr40 microcontroller data sheet for external clock input requi rements). this operating mode is described in section 6.4.2, pll off mode . when normal mode is selected, the fmpll is full y programmable. the fmp ll reference clock source can be a crystal oscillator or an external clock generator. the lock de tector indicates the lock status of the fmpll, and frequency modulation of the output clock can be enabled. this operating mode is described in section 6.4.3, normal mode. 6.2 external signal description refer to chapter 3, signal descriptions , for detailed sign al descriptions. 6.3 memory map and registers this section provides a detailed de scription of the fmpll registers. 6.3.1 module memory map table 6-1 shows the fmpll memory map. the address of each register is gi ven as an offset to the fmpll base address. the table lists registers in the order of their addresses, identi fied by complete name and mnemonic, and the type of their accesses. table 6-1. fmpll memory map offset from fmpll_base_addr (0xc3f8_0000) register bits access reset value section/page 0x0000 reserved 0x0004 synsr?fmpll synthesize r status register 32 r/w ? 1 6.3.2.1/6-4
frequency modulated phase-locked loop (fmpll) 6-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 6.3.2 register descriptions this section lists the fmpll registers in address or der and describes the regist ers and their bit fields. 6.3.2.1 fmpll synthesizer status register (synsr) 0x0008 esyncr1?fmpll enhanced synthesizer control register 1 32 r/w 0x8001_0053 6.3.2.2/6-7 0x000c esyncr2?fmpll enhanced synthesizer control register 2 32 r/w 0x0000_0005 6.3.2.3/6-9 0x0010?0x001c reserved 0x20 synfmcr?fmpll synthesizer fm control register 32 r/w ? 1 6.3.2.4/6-12 1 see specific register description. offset: fmpll_base_addr + 0x0004 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000000 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0lolflocmode pll sel pll ref locks lock locf u 1 1 these bits may read 0 or 1, depending on current state of the pll, however they do not provide any useful user information. u 1 w w1c w1c reset0000000 0 0 0 0 0 0 0 0 0 figure 6-3. fmpll synthesizer status register (synsr) table 6-2. synsr bit field descriptions field description 0?21 reserved table 6-1. fmpll memory map (continued) offset from fmpll_base_addr (0xc3f8_0000) register bits access reset value section/page
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-5 pxr40 microcontroller reference manual, rev. 1 22 lolf loss- of-lock flag. this bit provides the interrupt request fl ag. to clear the flag, write a 1 to the bit. writing 0 has no effect. the lolf is not set in response to the following conditions: ? loss of lock due to a system reset, or ? loss of lock due to changing any of the follo wing: multiplication factor divider (esyncr1_emfd), pre-divider (esyncr1_eprediv), or modulation depth (eysncr2_edepth) prior to the lolf being set and cleared (for example, in response to an unexpected loss of lock condition). the lolf will be set in response to the following conditions: ? changing any of the following: emfd, eprediv, or edepth subsequent to the lolf being set and cleared (for example, in response to an unexpected loss of lock condition), or ? changing the modulation rate (esyncr2_e rate), regardless of previous conditions. if the lolirq bit is set, these conditions will trigger an interrupt request. to avoid unintentional interrupt requests, the following steps are recommended: ? clear the lolirq bit ? change emfd, eprediv, edepth, and/or erate ? ensure the pll is locked ? clear the lolf bit ? set the lolirq bit, if desired if the flag is set due to a system failure, writing the esyncr1[emfd] bits or enabling fm does not clear the flag. assert reset to clear the flag. if lock is reacquired, the bit remains set until either a write 1 or reset is asserted. 0 interrupt service not requested. 1 interrupt service requested. 23 loc loss-of-clock status. the loc bit is an indication of whether a loss-of-clock condition is present when operating in normal pll mode. if loc = 0, the system clocks ar e operating normally. if loc = 1, the system clocks have failed due to a reference failure or a pll failure. if the read of the loc bit and the loss-of-clock condition occur simultaneously, the bit does not reflect the current loss-of-c lock condition. if a loss-of-c lock condition occurs that sets this bit and the clocks later return to normal, this bit is cleared. loc is always zero in pll off mode. 0 clocks are operating normally. 1 clocks are not operating normally. 24 mode clock mode. the state of this bit, along with pllsel and pllref, indicates which clock mode the pll is operating in (see ta bl e 6 - 1 3 ). the value of esyncr1[clkcfg2] is reflected in this location. 0 pll off mode. 1 pll clock mode. 25 pllsel pll mode select. the state of this bit, along with mode and pllref, i ndicates which mode the pll operates in. this bit is cleared in pll off mode. the value of esyncr1[clkcfg1] is reflected in this location. 0 pll off mode. 1 normal pll mode. 26 pllref pll clock reference source. the state of this bit, along with mode and pllsel, indicates which reference source has been chosen for normal pll mode. this bit is cleared in pll off mode. the value of esyncr1[clkcfg0] is reflec ted in this location. 0 external clock reference chosen 1 crystal clock reference chosen note: the pll controls the oscillator.. table 6-2. synsr bit field descriptions (continued) field description
frequency modulated phase-locked loop (fmpll) 6-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27 locks sticky pll lock status bit. the locks bit is a sticky indi cation of pll lock status. locks is set by the lock detect circuitry when the pll acquires lock after: 1) a sy stem reset, or 2) a write to the esyncr1 which modifies the esyncr1[emfd] bits, or 3) freque ncy modulation is enabled. whenever the pll loses lock, locks is cleared. locks remains cleared after the pll re-locks, un til one of the three conditions occurs. furthermore, if the locks bit is read when the pll simultaneously loses lock, the bit does not reflect the current loss-of-lock condition. if operating in pll off mode, locks re mains cleared after reset. 0 pll has lost lock since last system reset, a write to esyncr1 to modify the esyncr1[emfd] and esyncr1[eprediv] bit fields, or frequency modulation enabled 1 pll has not lost lock since last system reset, a write to esyncr1 to modi fy the esyncr1[emfd] and esyncr1[eprediv] bit fields, or frequency modulation enabled 28 lock pll lock status bit. the lock bit indicates whether the pll has acquired lock. refer to pxr40 microcontroller data sheet for tolerances. if the lock bit is read when the pll simultaneously loses lock or acquires lock, the bit does not reflect the current condition of the pll. if operating in pll off mode, lock remains cleared after reset. 0 pll is unlocked 1 pll is locked 29 locf loss-of-clock flag. this bit provides the interrupt request flag. to clear the flag, writ e a 1 to the bit. writing 0 has no effect. asserting reset clears th e flag. if clocks return to normal after the flag has been set, the bit remains set until cleared by either writing 1 or asserting re set. a loss-of-clock conditi on can only be detected if locen = 1. 0 interrupt service not requested. 1 interrupt service requested. 30?31 reserved table 6-2. synsr bit field descriptions (continued) field description
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-7 pxr40 microcontroller reference manual, rev. 1 6.3.2.2 fmpll enhanced synthesize r control register 1 (esyncr1) this is one of two fmpll synthesizer control register s that are used to access enhanced features in the fmpll. the bit fields in the esyncr1 behave as described in figure 6-4 . offset: fmpll_base_addr + 0x0008 access: user read/write 0 123456789101112131415 r 1 clkcfg[2:0] 0 0 0 0 0 0 0 0 eprediv w reset 1 ? 1 ? 1 ? 1 00000000 00? 2 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 emfd w 0 3 reset0 00000000010 0000 1 reset value determined by pllcfg pins during reset. 2 resets to value of pllcfg[2] (0 if pllcfg[2]=0; 1 if pllcfg[2]= 1) 3 do not set this bit to 1. figure 6-4. fmpll enhanc ed synthesizer contro l register 1 (esyncr1) table 6-3. esyncr1 bit field descriptions field description 0 reserved. note: this bit is set to 1 on reset and always reads as 1. writes to this bit have no effect. 1?3 clkcfg[2:0] clock configuration. the clkcfg[2:0] bits are writab le versions of the mode, pllsel, and pllref bits in the synsr. these change the clock mode, after reset has negated, via software. clkcfg[2:0] map directly to mode, pllsel, and pllref to control the system clock mode. note: clkcfg = 0b101 (or any reserved/invalid value) can produce an unpredictable clock output. note: the esyncr2[lolre] and esyncr2[locre] should be set to 0 before changing the pll mode, so that a reset is not immediately generated when clkcfg is written. 4?11 reserved 12?15 eprediv enhanced pre-divider. the eprediv bits control the value of the divider on the inpu t clock. the output of the pre-divider circuit generates the reference clock to the pll analog loop. the decimal equivalent of the eprediv binary number is substituted into the equation from ta bl e 6 - 8 . note: setting eprediv to any of the invalid states in ta bl e 6 - 4 causes the pll to produce an unpredictable output clock. the outp ut frequency of the divider must equal f pllref (see the pxr40 microcontroller data sheet ). when the eprediv bits are changed, the pll immedi ately loses lock. do not change the eprediv bits during fm operation. before changing eprediv, fm mu st be disabled and then reconfigured after the pll re-locks to the new eprediv value. to prevent an immediate reset, clear the lolre bit before writing the eprediv bits. in pll off mode, the eprediv bits have no effect.
frequency modulated phase-locked loop (fmpll) 6-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16?23 reserved. note: do not set this bit to 1. 24?31 emfd enhanced multiplication factor divider. the emfd bits control the value of the divider in the pll feedback loop. the value specified by the emfd bits establis h the multiplication factor applied to the reference frequency. the decimal equivalent of the emfd binar y number is substituted into the equation from ta b l e 6 - 1 0 for f sys to determine the equivalent multiplicatio n factor. the range of settings is 32 ? emfd ? 132. note: emfd values less than 32 and greater than 13 2 are invalid and cause the pll to produce an unpredictable clock output. the vc o frequency must be within the f vco specification (see the pxr40 microcontroller data sheet ). when the emfd bits are changed, the pll loses lock. do not change the emfd bits during fm operation. before changing emfd, fm must be disabled and then reconfigured after the pll re-locks to the new emfd value.to prevent an immediate reset, clear t he lolre bit before writing the emfd bits. in pll off mode, the emfd bits have no effect. ta b l e 6 - 5 shows the available divide ratios. table 6-4. pre-divider ratios eprediv input divide ratio (eprediv+1) 0000 1 0001 2 (default if pllcfg[2]=0) 0010 3 0011 4 (default if pllcfg[2]=1) 0100 5 0101 6 0110 invalid 0111 8 1000 invalid 1001 10 1010?1111 invalid table 6-5. feedback divide ratios emfd feedback divide ratio (emfd+16) 0000_0000?0001_1111 invalid 0010_0000 48 (default for pxr40) 0010_0001 49 0010_0010 50 0010_0011 51 0010_0100 52 table 6-3. esyncr1 bit field descriptions (continued) field description
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-9 pxr40 microcontroller reference manual, rev. 1 6.3.2.3 fmpll enhanced synthesize r control register 2 (esyncr2) this is the second of two enhanced versions of the fmpll synthesizer control register used to access enhanced features in the fmpll. the bit fiel ds in the esyncr2 behave as described in figure 6-5 . 0010_0101 53 . . 0101_0011 . . . . 99 . . 1000_0100 132 1000_0101?1111_1111 invalid offset: fmpll_base_addr + 0x000c access: user read/write 01234567 8 9 10 1112131415 r 0 0 0 0 0 0 0 0 locen lolre locre lol irq loc irq 0 erate w reset00000000 0 0 0 00000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r clk cfg _dis 0 0 0 0 edepth 0 0 erfd w reset00000000 0 0 0 0 0 1 1 1 figure 6-5. fmpll enhanc ed synthesizer contro l register 2 (esyncr2) table 6-6. esyncr2 bit field descriptions field description 0?7 reserved 8 locen loss-of-clock enable. the locen bit determines whet her the loss-of-clock function is operational along with backup clock modes, and interrupt and reset functions. see section 6.4.3.2, loss- of-clock detection, for more information. in pll off mode, this bit has no effect. locen does not affect the loss-of-lock circuitry. 0 loss-of-clock disabled. 1 loss-of-clock enabled. 9 lolre loss-of-lock reset enable. the lolre bit determines how the integration module handles a loss-of-lock indication. see section 6.4.3.1, pl l lock detection, for more information. when operating in normal pll mode, the pll must be locked before setting the lolre bit. otherwise reset is immediately asserted. the lolre bit has no effect in pll off mode. 0 assert reset on loss of lock is disabled. 1 assert reset on loss of lock. table 6-5. feedback divide ratios emfd feedback divide ratio (emfd+16)
frequency modulated phase-locked loop (fmpll) 6-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 10 locre loss-of-clock reset enable. the locre bit determines how the integration module handles a loss-of-clock condition when locen is equal to 1. locre has no effect when locen is equal to 0. if the locf bit in the synsr indicates a loss-of-cloc k condition, setting the locre bit causes an immediate reset. the locre bit has no effect in pll off mode. 0 assert reset on loss of clock is disabled. 1 assert reset on loss of clock. 11 lolirq loss-of-lock interrupt request. the lolirq bit de termines how the integration module handles a loss-of-lock indication. see section 6.6.1, loss-of-lock interrupt request, for more information. when operating in normal mode, the pll must be lo cked before setting the lolirq bit. otherwise an interrupt is immediately requested. the lolirq bit has no effect in pll off mode. 0 request interrupt is disabled. 1 request interrupt. 12 locirq loss- of-clock interrupt request. the locirq bit deter mines how the integration module handles a loss- of-clock condition when locen = 1. lo cirq has no effect when locen = 0. if the locf bit in the synsr indi cates a loss-of-clock condition, sett ing (or having previously set) the locirq bit causes an interrupt request. the locirq bit has no effect in pll off mode. 0 request interrupt on loss of clock is disabled. 1 request interrupt on loss of clock. 13 reserved 14?15 erate 1 enhanced modulation rate. the erate bits control the rate of frequency modulation appli ed to the system frequency. ta b l e 6 - 7 shows the allowabl e modulation rates. 16 clkcfg_dis the clkcfg_dis bit is used to disable the ability to change the pll mode using the clkcfg bits. this protects the system from errant soft ware writes and/or bit flips on th e clkcfg[2:0] bits that could change the pll clock mode. note: if the pll is configured for pll off mode when the clkcfg_dis bit is set, the pll will automatically enter normal mode. for this reason, it is advisable to set the pll for the desired mode (normal mode with crystal reference or normal mode with external reference) before setting the clkcfg_dis bit to protect from inadvertent mode changes. 0 writes to clkcfg[2:0] enabled. 1 writes to clkcfg[2:0] disabled. 17?20 reserved 21?23 edepth 2 enhanced modulation depth. the edepth bit field controls the frequency modulation depth 2 , and in conjunction with the synfmcr[fmdac_en] bit enable s frequency modulation. the edepth bit must be set to a non-zero value for fm operation. the sequence for enabling and configuring fm operation is described in section 6.4.3.4.2, programming system clock frequency with frequency modulation . this program sequence must be followed exactly to insure proper operation of the fm. 24?25 reserved table 6-6. esyncr2 bit field descriptions (continued) field description
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-11 pxr40 microcontroller reference manual, rev. 1 26?31 erfd enhanced reduced frequency divider. the erfd bits cont rol a divider at the outpu t of the pll. the value specified by the erfd bits establish the divisor appl ied to the pll frequency. the erfd divides the output clock by the quantity (erfd + 1). even-numbered erfd se ttings, which would result in odd divide ratios, are not allowed. the decimal equivalent of the erfd binary nu mber is substituted into the equation from ta b l e 6 - 1 0 . note: the erfd divides the output clock by the quantity (erfd + 1). even numbered erfd settings, which would result in odd divide ratios, are invalid and cause the pll to produce an unpredictable output clock. the pll output clock must be within the f pll specification (see the pxr40 microcontroller data sheet ). changing the erfd bits does not affect the pll, hen ce, no re-lock delay is incurred. resulting changes in clock frequency are synchronized to th e next falling edge of the current syst em clock. these bits should be written only when the lock bit (lock) is set, to av oid surpassing the allowable system operating frequency. in pll off mode, the erfd bits have no effect. the available output divider ratios are given in ta b l e 6 - 8 . 1 erate and edepth must be enabled simultaneously to avoid un intentional assertion of the lolf. program the desired modulation rate and depth to the erate and edepth bit fields simultaneously with a single 32 bit write to the esyncr2 register. 2 auto-calibration is not available on the pxr40 device. edepth does not set modulation depth and is used only in conjunction with the synfmcr[fmdac_en] to enable fm. see section 6.4.3.4, pll normal mode with frequency modulation ?. table 6-7. programmable modulation rates erate modulation rate (hz) 00 f mod = f extal /80 01 f mod = f extal /40 10 f mod = f extal /20 11 invalid table 6-8. output divide ratios erfd output divide ratio (erfd+1) 00_0000 divide-by-1 00_0001 divide-by-2 00_0010 invalid 00_0011 divide-by-4 00_0100 invalid 00_0101 divide-by-6 00_0110 invalid 00_0111 divide-by-8 (default value for pxr40) table 6-6. esyncr2 bit field descriptions (continued) field description
frequency modulated phase-locked loop (fmpll) 6-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 6.3.2.4 fmpll synthesizer fm control register (synfmcr) the synthesizer fm cont rol register (synfmcr) contains bi ts for enabling and configuring pll frequency modulation. . . . . . . 11_1100 invalid 11_1101 divide-by-62 11_1110 invalid 11_1111 divide-by-64 offset: fmpll_base_addr + 0x0020 access: user read/write 0 123456789101112131415 r fmd ac_e n fmdac_ctl w reset0 000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w reset0 000000000000000 figure 6-6. fmpll synthesizer fm control register (synfmcr) table 6-9. esynfmcr bit field descriptions field description 0 reserved 1 fmdac_en frequency modulation register enable. when this bit is set, the fmdac_ctl field is enabled and the fm depth can be controlled directly by the value in fm dac_ctl. the esyncr2[edepth] field must also be set to a non-zero value to enable fm. 0 fmdac_ctl disabled. 1 fmdac_ctl enabled. dac is controlled by the value in fmdac_ctl. 2?10 reserved table 6-8. output divide ratios erfd output divide ratio (erfd+1)
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-13 pxr40 microcontroller reference manual, rev. 1 11?15 fmdac_ctl digital-to-analog converter control. this bitfield value is written to the dac to control the fm depth by percentage during fm operation. 00100 ? 1% 01000 ? 2% 01100 ? 3% 10000 ? 4% these values have been shown in characterization da ta to produce the specifie d fm percentage within the device specification. however, the user may program intermediate values to trim the fm percentage for a specific application if de sired. do not program fmdac_ctl to any value that will cause the system frequency to exceed the maximum specification. 16?0 reserved table 6-9. esynfmcr bit field descriptions field description
frequency modulated phase-locked loop (fmpll) 6-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 6.4 functional description the fmpll module contains the frequency modulated phase lock loop (fmpll), enhanced frequency divider (erfd), enhanced synthesi zer control registers (esyncr1 an d esyncr2), synthesizer status register (synsr), synthesizer fm control register (synfmcr) and cl ock/pll control logic. the block also contains a reference frequenc y pre-divider controlled by the ep rediv bits in the esyncr1. this enables the user to use a high frequency crystal or external clock generator and obtain finer frequency synthesis resolution than would be av ailable if the raw input clock were used dir ectly by the analog loop. for the remainder of this chapter, the te rm ?reference frequenc y? and the symbol f ref indicate the output of the pre-divider circuit. this is the cloc k on which frequency multiplication is performed. 6.4.1 general the system clock source is dete rmined during reset as shown in table 6-13 . the value of the pllcfg[0:1] pins are latched during reset. if pllcfg[0:1] are changed during a rese t other than power-on reset, the internal clocks may glitch as the clock source is changed between pll off mode and pll clock mode or from one pll clock mode to anothe r. whenever pllcfg[0:1] are change d in reset to a value other than what it was before the reset, an immediate loss of lo ck condition is declared. this only applies if the pll was running in a locked state prior to the a ssertion of reset and ch ange of pllcfg[0:1]. table 6-10 shows the pll clock to input clock frequenc y relationships for the available clock modes. 6.4.2 pll off mode when pll off mode is selected, the pll is turned off. the user must supply an external clock on the extal pin and select that clock sour ce before entering pll off mode. the selected clock is directly used to produce the various sy stem clocks. refer to pxr40 microcontroller data sheet for external clock input requirements. in pll off mode, th e analog portion of the pll is di sabled, the frequency modulation capability is not available, and no clocks are generated at the pll output. the pre-divider is bypassed and has no effect on the system cloc k frequency in pll off mode. 6.4.3 normal mode when normal pll mode is selected, the pll is full y programmable. the pll can synthesize frequencies ranging from 48x to 148x the reference frequency of the output of the predivider, with or without table 6-10. clock-out vs. clock-in relationships clock mode frequency equation pll off mode f pll = f extal normal pll mode 1 1 equation to be used when programming enhanced control registers (esyncr1 and esyncr2). see eprediv, emfd, and erfd bitfield descriptions for valid ranges for these fields. f pll f extal emfd 16 + ?? ? eprediv 1 + ?? erfd 1 + ?? --------------------------------------------------------------------------- =
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-15 pxr40 microcontroller reference manual, rev. 1 frequency modulation enabled. the post-divider is cap able of reducing the pll clock frequency without forcing a re-lock. the pll reference can be a crystal os cillator reference or an external clock reference. this clock is divided by the pre-divider ci rcuit to create the pll reference clock. 6.4.3.1 pll lock detection the lock detect logic monitors th e reference frequency and the pll fee dback frequency to determine when frequency lock has been achieve d. phase lock is inferred by the frequency relationship, but is not guaranteed. the pll lock status is re flected in the lock status bit in the synsr. a sticky lock status indication, locks, is also provided. the lock detect function uses two counters, whic h are clocked by the reference and pll feedback respectively. when the reference counter has counted n cycles, the feedback counter?s count is compared. if the feedback counter has also counted n cycles, th e process is repeated for n + k counts. then if the two counters? counts match, the lock criteria is relaxed by one count a nd the system is notified that the pll has achieved frequency lock. after three successful compares, the tolerance is relaxed. after lock has been detected, the lock circuitry continues to monitor the reference and feedback frequencies using the alternate count and compare process. if the coun ters do not match at any comparison time, then the lock status bit is cleared to indicate that the pll has lost lock. at this point, the lock criteria is tightened and the lo ck detect process is repeated. the alternate count sequences prevent false lock dete cts due to frequency aliasing while the pll tries to lock. alternating between a tight and relaxed lock crit eria prevents the lock detect function from randomly toggling between locked a nd not locked status due to phase sensitivities. figure 6-7 illustrates the sequence for detecting locked and not-locked conditions. when the frequency modulation is enab led, the loss of lock continues to function as described but with the lock and loss of lock criteria reduced to ensure that false loss of lock c onditions are not detected. in pll off mode, the pll cannot lo ck because the pll is disabled.
frequency modulated phase-locked loop (fmpll) 6-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 6-7. lock detect sequence after the pll acquires lock after reset, the lock and locks status bits are set. if the eprediv or emfd are changed, or if an unexpect ed loss-of-lock condition occurs, the lock and locks status bits are negated. while the pll is in an unlocked condition, the syst em clocks continue to be sourced from the pll as the pll attempts to re-lock. consequently, during the re-locking process, the system clock frequency is not well defi ned and may exceed the ma ximum system frequency vi olating the system clock timing specifications. because of this condition, use of the loss-of-lock reset function is recommended. after the pll has re-locked, the lock bit is set. the locks bit remain s cleared if the loss of lock was unexpected. the locks bit is set to one when the lo ss of lock was caused by changing the eprediv or emfd fields. 6.4.3.2 loss-of-clock detection when enabled by the locen bit in the esyncr2, the loss-of-clock (loc ) detection circuit monitors the input clocks to the phase/fre quency detector (pfd) (see figure 6-2 ). when the referenc e or feedback clock frequency falls below a min imum frequency, the loc circuitry consid ers the clock to have failed and a loss-of-clock status is reflected by the sticky lo cf bit, and non-sticky loc bit in the synsr. see pxr40 microcontroller data sheet for the minimum clock frequency. in pll off mode, the loss-of-clock circuitry is disabled. depending which clock source has fail ed, the loc circuitry switches th e pll output clock?s source to the remaining operational clock if enab led by locen. the pll output clocks are derived from the alternate clock source until reset is asserte d. the alternate clock source used is dependent on whether the loc is count n + k reference cycles, and compare number of feed- lock detected back cycles relax lock criteria. reference count equals n and feed- back count equals n in same count and compare sequence. reference count equals n + k and feed- back count equals n + k in same count and compare sequence. alert system that pll has locked. feedback count does not equal reference count of n or n+k. alert system that pll is not locked. tighten lock criteria. continue monitoring pll with alternate n and n+k count and compare sequences. count n reference cycles, and compare number of feedback cycles elapsed. elapsed.
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-17 pxr40 microcontroller reference manual, rev. 1 caused by a reference clock failure or a pll failure. if the reference fails, the pll goes out of lock and into self-clocked mode (scm) (see table 6-11 ). the pll remains in scm until the next reset. when the pll is operating in scm, the pll runs open loop at a default vco frequency. the rfd will set to divide-by-6 to ensure the clock pr esented to the system is well be low the maximum allowable frequency for the device. if the loss-of-clock condition is due to a pll failure (i.e., loss of feedback clock), the pll reference becomes the system clock sour ce until the next reset, even if the pll regains itself and re-locks. a special loss-of-clock condition occurs when both th e reference and the pll fa il. the failures may be simultaneous or the pll may fail first. in either case , the reference clock failure takes priority and the pll attempts to operate in scm. if successful, the pll remains in scm until the next reset. during scm, modulation is always disabl ed. if the pll cannot operate in scm, th e system remains static until the next reset. both the reference and the pll mu st be functioning properly to exit reset. 6.4.3.3 pll normal mode without fm in pll mode, the system clocks are synthesized by the fmpll by multiplying up the reference clock frequency. it is critical that th e system clock frequenc y remain within the ra nge for the device (see pxr40 microcontroller data sheet ). the output of the fmpll can be divi ded down in powers of 2 up to 64 to reduce the system frequency with th e erfd. the erfd is no t contained in the fee dback loop of the pll, so changing the erfd bits does not affect fmpll ope ration. finally, the pll can be frequency modulated to reduce electromagnetic in terference often associated with clock circuitry. figure 6-2 shows the overall block diagram for the pll. each of the major blocks is discussed briefly in the following sections. 6.4.3.3.1 phase/fr equency detector the phase/frequency detector (pfd) is a dual-latch phase-frequency det ector. it compares both the phase and frequency of the refere nce clock and the feedback clock. the reference clock comes from the crystal oscillator or an external clock source. the feedback clock comes from the vco output divided down by the emfd in normal pll mode. when the frequency of the feedback clock equals the frequency of the reference clock (i.e., the pll is frequency locked), the pfd pulses the up or down signals depending on the relative phase of the two clocks. if the falling edge of the reference clock lead s the falling edge of the feedback clock, then the up signal is pulsed. if the falling edge of the feedback clock leads the falli ng edge of the reference clock, then the down signal is pulsed. th e width of these pulses relative to th e reference clock is dependent on how much the two clocks lead or lag each other. after pha se lock is achieved, the pfd continues to pulse the up and down signals for a very short duration duri ng each reference clock cycle. these short pulses table 6-11. loss-of-clock summary clock mode system clock source before failure reference failure alternate cloc k selected by loc circuitry until reset pll failure alternate clock selected by loc circuitry until reset pll pll pll self-clocked mode pll reference pll off ext. clock(s) none na note: the loc circuit monitors the inputs to th e pfd: reference and feedback clocks (see figure 6-2 ).
frequency modulated phase-locked loop (fmpll) 6-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 force the pll to continually update and preven t a frequency drift phenomena referred to as ?dead-banding.? dead-b and describes the minimum amount of pha se error between the reference and feedback clocks that a phase detector cannot correct. 6.4.3.3.2 charge pump/loop filter operation of the charge pump is controlled by the up and down signals from the pfd. they control whether the charge pumps apply or remove charge, respectively, from the loop filter. 6.4.3.3.3 vco the voltage into the vco controls the frequency of its output. the frequency- to-voltage relationship (vco gain) is positive. 6.4.3.3.4 emfd the mfd divides down the output of the vco and feeds it back to th e pfd. the pfd c ontrols the vco frequency (via the charge pump and loop filter) such th at the reference and feedback clocks have the same frequency and phase. thus, the input to the mfd, whic h is also the output of the vco, is at a frequency that is the reference frequency multiplied by the sa me amount the mfd divides by. for example, if the mfd divides the vco frequency by 48, then the pll is frequency locked when the vco frequency is 48 times the reference frequency. the presence of the mfd in the loop a llows the pll to perform frequency multiplication, or synthesis. 6.4.3.3.5 programming system clock frequency in normal pll clock mode, the default system frequency is dete rmined by the default eprediv, emfd, and erfd values. when programming the pll, do not violate the ma ximum system clock frequency or max/min vco frequency specifications. based on the desired syst em clock frequency, ep rediv, emfd, and erfd must be calculated for the given crysta l or external refere nce frequency. see pxr40 microcontroller data sheet for the max/min vco frequency range and the maximum allowable system frequency. frequency modulation should be disabled prior to changing the eprediv, emfd, or erate bit fields. a change to eprediv, emfd, edep th, or erate while modul ation is enabled inva lidates the previous fm depth configuration. use these directions to accommodate the frequency overshoot that occurs when the eprediv or emfd bits are changed. if frequency m odulation is going to be enabled th e maximum allowable frequency must be reduced by the programmed ? f m . 1. determine the appropriate value for the epredi v, emfd, and erfd fiel ds in the synthesizer control register(s), remember to include the ? f m if frequency modulation is to be enabled. the amount of jitter in the system clocks can be minimized by selecting the maximum emfd factor that can be paired with an erfd factor to provide the desired frequency. the maximum emfd value that can be used is dete rmined by the vco and emfd range.
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-19 pxr40 microcontroller reference manual, rev. 1 2. write a value of erfd = erfd (from step 1) + 2 to the erfd field of the esyncr2. not increasing the erfd when changing the eprediv or emfd could subject the device to clock frequencies beyond the range specified for the de vice due to the pll?s unlocked state. 3. if frequency modulation is curr ently enabled, disable it by writi ng 00 to the edepth field of the esyncr2. 4. if programming the eprediv and/or emfd, write the value(s) determined in step 1 to the appropriate field(s) in the esyncr1. 5. monitor the synthesizer lock bit (lock) in th e synthesizer status register (synsr). when the pll achieves lock, write the erfd value determined in step 1 to the erfd field of the esyncr2. this changes the system clocks frequency to th e desired frequency. if frequency modulation is desired, leave erfd programmed to erfd + 2 until after completing the steps in section 6.4.3.4.2, programming system clock fr equency with frequency modulation . 6. if frequency modulation was enable d initially, it can be re-enabl ed following the steps listed in section 6.4.3.4.2, programming system clock fr equency with frequency modulation . during startup, current transients on the vdd supply are related to the system frequenc y. a technique can be used to reduce these current transients when the system frequency is changed from its default value to your desired frequency. follow the above procedure for step 1. in step 2, rather than set erfd to erfd (from step 1) + 2, set this to a value which will produce a low system frequenc y (close to the default system frequency), e.g. erfd = erfd (from step 1) + 4. once set, follow steps 3 and 4 as above. in step 5, wait for the lock bit to set, then set the efrd bit to erfd (from step 2) ? 2. wait for a small duration of time for the current to stabilize, then repeat this procedure until the erfd value is equal to the value determined in step 1. using this technique you should obser ve the system frequency increasing in steps to the desired system frequency. this results in the vdd current increasing to its equivalent final valu e in smaller current steps which, therefore, produce smaller cu rrent transients, making it easie r for the power supply to handle. 6.4.3.4 pll normal mode with frequency modulation in normal pll clock mode, frequency modulation is not enabled in the default synthesis mode. when frequency modulation is enabled several parameters must be set to generate the desired level of modulation. the parameters to be programmed are th e erate and edepth bit fields of the esyncr2 register and the fmdac_en and fmdac_ctl bits in the synfmcr register. the erate bit controls the frequency of modulation, f mod . the edepth bits work in conjunc tion with the fmdac_ctl bits in the synfmcr to enable and c ontrol the modulation depth, f m . the available modula tion rates and depths are given in table 6-7 and table 6-8 , respectively. the modulation wave form is always a triangle wave and its shape is not programmable. an example of one period of the modulation waveform is shown in figure 6-8 .
frequency modulated phase-locked loop (fmpll) 6-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 6-8. frequency modulation waveform 6.4.3.4.1 frequency modulation control the frequency modulation control co nsists of programming a reference current into the modulation d/a so that the m odulation depth (f max and f min ) remains within specificati on. disable freque ncy modulation prior to changing the eprediv, emfd, or erate bit fi elds. upon enabling freque ncy modulation a new configuration sequence is required. do not change eprediv, emfd or er ate while modulation is active or unpredictable results may occur. 6.4.3.4.2 programming system clock frequency with frequency modulation the following steps illustrate pr oper programming of the frequency mo dulation mode. these steps ensure proper operation of the fm configur ation routine and prevent freque ncy overshoot from the programming sequence. the pll should be programm ed and allowed to lock in non-fm mode at the desired frequency as outlined in section 6.4.3.3.5, programming sy stem clock frequency . 1. write a value of erfd = erfd + 2 to the erfd field of the esyncr2 to ensure the maximum system frequency is not exceeded during the fm configuration. th is is done when allowing the pll to lock in non-fm mode. note even numbered erfd settings, which w ould result in odd divide ratios, are invalid and cause the pll to produ ce an unpredictable output clock. the pll output clock must be within the f pll specification f max f min ? t 1 f mod --------------- - = t f f max = f sys + {0.5%, 1%, 1.5%, 2%} f min = f sys ? {0.5%, 1%,1.5%, 2%} f mod = f extal /q where q = {20, 40, 80} ? fm ? fm
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-21 pxr40 microcontroller reference manual, rev. 1 2. write the synfmcr[fmdac_en] bit to l ogical 1 (to enable fmdac_ctl) and the synfmcr[fmdac_ctl] bit field to the appropriate value shown in table 6-12 . 3. program the desired modulation ra te into the erate field of th e esyncr2 register and set the edepth field to a non-zero value. the absolute va lue in the edepth field is non-critical as this value is not used for actual fm depth, however edepth must be non-zero to enable fm. make sure not to change erfd from step 2 when se tting erate and edepth as they share the same register space. 4. wait for the pll to lock. when the pll achieves lock, write the desired erfd value. make sure not to modify erate/edepth as th ey share the same register space. the frequency modulation system is dependent on several factors, including the accuracies of the v ddsyn /v sssyn voltage, of the crystal oscillator fre quency, and of the manufacturing variation. for example, if a 5% accurate su pply voltage is used, then a 5% m odulation depth error results. if the crystal oscillator frequency is skewed from the nominal operating frequency, the resulting modulation frequency is proportionally skewed. fi nally, the error due to the manuf acturing and environment variation alone can cause the frequency modulation depth error to be greater than 20%. table 6-12. fmdac_ctl settings for fm configuration peak-to-peak fm depth (edepth) fmdac_ctl 1% (center frequency 0.5%) 0x04 2% (center frequency 1.0%) 0x08 3% (center frequency 1.5%) 0x0c 4% (center frequency 2.0%) 0x10
frequency modulated phase-locked loop (fmpll) 6-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 6.5 resets this section describes the reset operation of the pll, including power-on reset and normal resets. the reset values of registers and sign als are provided in other sections. 6.5.1 clock mode selection the initial clock mode is reflected in the mode, p llsel, and pllref bits of the synthesizer status register (synsr) as well as the esyncr1[clkcfg[2:0]] bit field. the clock mode can be modified by writing to the clkcfg[2:0] bit field. the synthesizer status register then reflects the newly-selected pll clock mode. table 6-13 summarizes clock mode selection. 6.5.1.1 power-on reset (por) the pll will not operate until th e por state has ended. refer to pxr40 microcontroller data sheet for these thresholds. at this point, the pll operates in self-clocked mode (scm) until a vali d reference clock is detected by the internal clock monitor circuit. internal to the pll, the vco is he ld in reset until the ne gation of the por signal. this prevents the pll from attempting to lock before its supplies are within specif ication, which can caus e vco/loop gain to be lower than what the analog loop is designed for. 6.5.1.2 external reset after por has negated, the pll will begin its lock detect al gorithm if normal mode is selected. however, if a valid reference is not present, the pll will cont inue to operate in self clocked mode until one is present. pll configuration at por ma y be selected by external pins p llcfg[0:1] or reset state values of configuration registers. after the initial lock with the default divider sett ings (assuming normal mo de was selected), you may write to the syncr/esyncr(s) to modify the divide rs for the desired operati ng frequency. the pll may table 6-13. clock mode selection package pins 1 1 the pllcfg[2] pin configures the crystal oscillator range: pllcfg[2] = 0, for 8 mhz to 20 mhz pllcfg[2] = 1, for 40 mhz clock mode synthesizer status register (synsr) mode, pllsel, and pllref bits pllcfg[0] pllcfg[1] mode/ clkcfg[2] pllsel/ clkcfg[1] pllref/ clkcfg[0] 0 0 pll off mode 0 x x 0 1 normal mode with external reference 1 1 0 1 0 normal mode with crystal reference 1 1 1 11 reserved 100
frequency modulated phase-locked loop (fmpll) freescale semiconductor 6-23 pxr40 microcontroller reference manual, rev. 1 not be able to lock due to an (e)mfd and crystal frequency combination that attempts to force the vco outside of its operating range caution when running in an unlocked state, th e clocks generated by the pll are not guaranteed stable and may exceed the maximum specified operating frequency of the device. the rfd shoul d always be used as described in section 6.4.3.3.5, programming system clock frequency, to insulate the system from any potential freque ncy overshoot of the pll clocks. 6.5.2 pll loss-of-lock reset by programming the lolre bit in the esyncr2, the p ll can assert reset when a loss-of-lock condition occurs. because the lock and locks bi ts in the synsr are re-initialized after reset, the siu reset status register described in section 3.2.1.2, reset status register (siu_rsr), must be read to determine a loss-of-lock condition occurred. in pll off mode, the pll cannot lock; therefore a loss-of-lock condition cannot occur and lolre has no effect. 6.5.3 pll loss-of-clock reset when a loss-of-clock condi tion is recognized, reset is asserted if the locre bit in the syncr is set. the locf and loc bits in the synsr are cleared after reset, therefore, the loc bit must be read in the siu_rsr to determine that a loss- of-clock condition occurred. locre has no effect in pll off mode. 6.6 interrupts this section describes the interrupt requests that the pll can generate. 6.6.1 loss-of-lock interrupt request by setting the lolirq bit in the esyncr2, the p ll can request an interrupt when a loss-of-lock condition occurs. in pll off mode, the pll cannot lock; therefore a loss-of-lock condition cannot occur and the lolirq has no effect. 6.6.2 loss-of-clock interrupt request when a loss-of-clock condition is recognized, the pll requests an interrupt if the locirq bit in the syncr is set. the locirq bit has no effect in pll off mode or if locen is equal to 0.
frequency modulated phase-locked loop (fmpll) 6-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 7-1 pxr40 microcontroller reference manual, rev. 1 chapter 7 system integration unit (siu) 7.1 introduction this chapter describes the device system integration uni t (siu) that configures a nd initializes the following controls: ? mcu reset configuration ? system reset operation ? pad configuration ? external interrupts ? general-purpose i/o (gpio) ? internal peripheral multiplexing ? gpdi and gpdo i/os of the dspi modules
system integration unit (siu) 7-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.1.1 block diagram figure 7-1 is a block diagram of the siu. the siu regi sters are accessed using the crossbar switch. figure 7-1. siu block diagram note the power-on reset detection module, pad interface/pad ring module, and peripheral i/o channels shown shaded in figure 7-1 are external to the siu. reset reset configuration siu registers reset controller pad interface/ pad ring pad configuration rstout power-on reset detection external irq/ edge detects gpio peripheral i/o channels imux irq inputs, dspi signals irq [0] irq [15] bootcfg[0] wkpcfg d_cs [0] pllcfg[1] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bootcfg[1] ? ? ? pllcfg[0] pllcfg[2] d_cs [2] d_cs [3] gpio[n]
system integration unit (siu) freescale semiconductor 7-3 pxr40 microcontroller reference manual, rev. 1 7.1.2 overview the system integration unit (siu) is accessed by the core th rough the system bus crossbar switch (xbar) and the peripheral bridge a (pbridge_a). table 7-1 lists the features the siu configures: : 7.1.3 modes of operation there are several operating modes for configuring and testing the chip: table 7-1. siu features feature description mcu reset operations controls the external pin boot logic system reset operations monitors internal and external reset sources, and drives the rstout signal ? power-on reset support ? reset status register providi ng last reset source to software ? glitch detection on reset input ? software controlled reset assertion pad configuration registers enables the configuration and init ialization of the i/o pin electrical characteristics using software to select the following: ? active function from the set of multiplexed functions ? pullup and pulldown characteristics of the pin ? slew rate for slow and medium pads ? open drain mode for output pins ? hysteresis for input pins ? drive strength of bus signals for fast pads external interrupt operations ? 16 interrupt requests ? rising- or falling-edge event detection ? programmable digital filter for glitch rejection ? nmi and critical interrupt control general-purpose i/o (gpio) provides uniform and discrete i/o control of mcu general-purpose i/o pins, where each gpio signal has an input register and an output register. internal peripheral multiplexing provides flexibility to cust omize signal/pin assignments fo r application development that allows: ? serial and parallel chaining of dspis ? flexible selection of eqadc trigger inputs ? assignment of interrupt requests (i rqs) between external pins and dspi table 7-2. siu modes of operation operating mode description normal in normal mode, the siu provides the register interface and logic that controls the device and system configuration, the reset controller, and gpio. the siu continues operation with no changes in stop mode. debug siu operation in debug mode is identical to operation in normal mode.
system integration unit (siu) 7-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.2 external signal description table 7-3 lists the external pins used by the siu. 7.2.1 detailed signal descriptions 7.2.1.1 reset input (reset ) reset is an active-low input signal asserted by an external device during a power-on reset (por) or external reset. reset assertion for ten clock cycles or more will cause the intern al reset. there will be an additional two clock delay from the reset pin change to the event actually taking place. asserting the reset signal while the device is pr ocessing a reset restarts the reset process at the beginning. reset has a glitch detector logic that se nses electrical fluctuations on the v ddeh input pins that drop below the switch point value for more than two cl ock cycles. the switch point value is between the maximum v il and minimum v ih specifications for the v ddeh input pins. table 7-3. siu signal properties name function i/o type resets reset reset input input rstout reset output output system configuration gpio n general-purpose i/o i/o bootcfg[0:1]_ irq [2:3]_ gpio[211:212] boot configuration input interrupt request general-purpose i/o input input i/o wkpcfg_ nmi_ gpio[213] weak-pull configuration non-maskable interrupt to core general-purpose i/o input input i/o external interrupt irq [0:15] 1 1 the gpio and irq signals are multiplex ed with other functions on the device. external interrupt request input input
system integration unit (siu) freescale semiconductor 7-5 pxr40 microcontroller reference manual, rev. 1 7.2.1.2 reset output (rstout ) rstout is an active-low output signal th at uses a push/pull conf iguration. it is driven to the low state by the mcu for all internal and external reset sources. after the reset input signal negates, rstout asserts for: ? 16000 clock cycles for devices configured in bypass mode ? 2400 clock cycles for all other fmpll modes to invoke an external software reset, write a 1 to the system external reset (ser) bit in the system reset control register (siu_srcr). this asserts rstout for 2400 clock cycles. an external software reset does not execute the bam module or sample bootcfg[0:1]. 7.2.1.3 general-purpose i/o (gpio n ) the gpio signals provide general-purpose input a nd output functions. gpio signals are generally multiplexed with other i/o pin func tions. each gpio input and output is separately controlled by an eight-bit general-purpose data input (siu_gpdi n ) and a general-purpose data output (siu_gpdo n ) register. the siu also implements several pa rallel gpio registers (siu_pgpdo x_x and siu_pgpdi x_x ) that can be used to access up to 32 gpio bits in a single- and word-sized accesses. the values read/written to these parallel registers are cohe rent with the data read /written to the siu_gpdo x _ x and siu_gpdi x_x registers refer to the following sections for more information: section 7.3.1.14, gpio pin data out put registers 0?512 (siu_gpdon) section 7.3.1.15, gpio pin data i nput registers 0?255 (siu_gpdin) 7.2.1.4 boot configuration (bootcfg[0:1]) the bootcfg value specifies the location and boot mode used by the boot assist module (bam). all reset sources can read the boot configuration fi eld, bootcfg[0:1], except a debug port reset and a software external reset. bootcfg[0:1] is sampled while pr ocessing a reset. the bootcfg values are used only while rstout is asserted. otherwise, the default value for bootcf g (0b00) in the reset status register (siu_rsr) is used, as shown in table 7-4 . table 7-4. bootcfg configuration bootcfg[0] bootcft[1] meaning 0 0 boot from internal flash memory (default) 0 1 flexcan / esci boot 1 0 boot from external memory (no arbitration) 1 1 boot from external memory (external arbitration) ?ebi not available on all packages
system integration unit (siu) 7-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.2.1.5 i/o weak pullup reset configuration (wkpcfg) the wkpcfg signal is applied when the inte rnal reset signal asserts (indicated by rstout asserting), and is sampled four clock cycles before rstout negates. the wkpcfg value configures the internal weak pullup or weak pulldown pin characteristics af ter a reset occurs in th e emios or etpu modules. the value of wkpcfg is latched at reset, stored in the reset status register (siu_rsr), and updated for all reset sources except the debug port reset and softwa re external reset. the wk pcfg value must be valid and not change until rstout negates. 7.2.1.6 external interrupt request input (irq) irq [0:15] the external interrupt re quest (irq) inputs connect to the siu irq inputs. the external irq input select register (siu _eiisr) specifies the irq [0:15] signals that are input to the siu irqs.
system integration unit (siu) freescale semiconductor 7-7 pxr40 microcontroller reference manual, rev. 1 7.3 memory map and register definition table 7-5 is the address map for the siu registers. all re gister addresses shown are an offset of the siu base address. table 7-5. siu memory map address register bits access reset value section/page siu_base = 0xc3f9_0000 reserved siu_base + 0x0004 siu_midr?mcu id register 32 r 0x5674_6000 0r 0x5674_e000 7.3.1.1/7-10 siu_base + 0x0008 reserved siu_base + 0x000c siu_rsr?reset status register 32 r/w 0x8000_u 7.3.1.2/7-11 siu_base + 0x0010 siu_srcr?s ystem reset control register 32 r/w 0x0000_8000 7.3.1.3/7-15 siu_base + 0x0014 siu_eisr?siu external interrupt status register 32 r/w1c 0x0000_0000 7.3.1.4/7-15 siu_base + 0x0018 siu_direr?d ma/interrupt request enable register 32 r/w 0x0000_0000 7.3.1.5/7-16 siu_base + 0x001c siu_dirsr?d ma/interrupt request select register 32 r/w 0x0000_0000 7.3.1.6/7-17 siu_base + 0x0020 siu_osr?overrun status register 32 r/w 0x0000_0000 7.3.1.7/7-18 siu_base + 0x0024 siu_orer?ov errun request enable register 32 r/w 0x0000_0000 7.3.1.8/7-19 siu_base + 0x0028 siu_ireer?irq rising-edge event enable register 32 r/w 0x0000_0000 7.3.1.9/7-20 siu_base + 0x002c siu_ifeer ?irq falling-edge event enable register 32 r/w 0x0000_0000 7.3.1.10/7-21 siu_base + 0x0030 siu_idfr?irq digital filter register 32 r/w 0x0000_0000 7.3.1.11/7-22 siu_base + 0x0034 siu_ifir?irq filter ed input register 32 r/w 0x0000_0000 7.3.1.12/7-22 siu_base + (0x0038?0x003f) reserved siu_base + (0x0040?0x043e) siu_pcr0 ? siu_pcr511? pad configuration registers 0?511 16 r/w see siu_pcr n settings table for reset values 7.3.1.13/7-24 siu_base + (0x0440?0x05ff) reserved siu_base + (0x0600?0x07ff) siu_gpdo0 ? siu_gpdo511? gpio pin data output registers 0?511 8r/w 0x00 7.3.1.14/7-40 siu_base + (0x0800?0x08ff) siu_gpdi0 ? siu_gpdi255? gpio input data registers 0?255 (legacy support only, new implementation at siu_base + 0x0e00) 8r 0x00 7.3.1.15/7-40 siu_base + (0x0900?0x0903) reserved
system integration unit (siu) 7-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 siu_base + (0x0904?0x0907) siu_eiisr (sometimes referred to as isel1) ? external irq input select register 32 r/w 0x0000_0000 7.3.1.16/7-41 siu_base + (0x0908?0x090b) siu_disr (sometimes referred to as isel2) ? dspi input select register 32 r/w 0x0000_0000 7.3.1.17/7-43 siu_base + (0x090c?0x090f) reserved siu_base + (0x0910?0x091f) siu_isel4?7?eqadc command fifo trigger sour ce select?imux select registers 32 r/w 0x0000_0000 7.3.1.18/7-46 siu_base + 0x0920 siu_isel8? etpu input select register 32 r/w 0x0000_0000 7.3.1.19/7-60 siu_base + 0x0924 siu_isel9? eqadc advance trigger selection 32 r/w 0x0000_0000 7.3.1.20/7-61 siu_base + 0x0928 siu_decfi l1?decimation filter register 1 32 r/w 0x0000_0000 7.3.1.21/7-62 siu_base + 0x092c siu_decfi l2?decimation filter register 2 32 r/w 0x0000_0000 7.3.1.22/7-64 siu_base + (0x0930?0x097f) reserved siu_base + 0x0980 siu_ccr ?chip configuration register 32 r/w 0x000x_0000 7.3.1.23/7-66 siu_base + 0x0984 siu_eccr?e xternal cloc k control register 32 r/w 0x0000_1001 7.3.1.24/7-67 siu_base + (0x0988?0x098c) reserved siu_base + 0x0990 siu_cbrh?compare b high register 32 r/w 0x0000_0000 7.3.1.25/7-68 siu_base + 0x0994 siu_cbrl?compare b low register 32 r/w 0x0000_0000 7.3.1.26/7-69 siu_base + (0x0998?0x099f) reserved siu_base + 0x9a0 siu_sysdiv?system clock register 32 r/w 0x0000_0010 7.3.1.27/7-69 siu_base + 0x9a4 siu_hlt?halt register 32 r/w 0x0000_0000 7.3.1.28/7-70 siu_base + 0x9a8 siu_hltack?halt acknowledge register 32 r/w 0x0000_0000 7.3.1.29/7-71 siu_base + (0x09ac?0x0bff) reserved siu_base + (0x0c00?0x0c3c) siu_pgpdo0?s iu_pgpdo15? parallel gpio pin data output register 0?15 32 r/w 0x0000_0000 7.3.1.30/7-73 siu_base + (0x0c40?0x0c7c) siu_pgpdi0 ? siu_pgpdi15? parallel gpio pin data input register 0?15 32 r 0x0000_0000 7.3.1.31/7-74 siu_base + (0x0c80?0x0cfc) siu_mpgpdo0 ? siu_mpgpdo31? masked parallel gpio pin data output register 0?31 32 w 0x0000_0000 7.3.1.32/7-75 table 7-5. siu memory map (continued) address register bits access reset value section/page
system integration unit (siu) freescale semiconductor 7-9 pxr40 microcontroller reference manual, rev. 1 siu_base+0x0d00 siu_dspiah?dspia gp mask-output high register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d04 siu_dspial?dspia gp mask-output low register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d08 siu_dspibh?dspib gp mask-output high register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d0c siu_dspibl?dspib gp mask-output low register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d10 siu_dspich?dspic gp mask-output high register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d14 siu_dspicl?dspic gp mask-output low register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d18 siu_dspidh?dspid gp mask-output high register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d1c siu_dspidl?dspid gp mask-output low register 32 r/w 0x0000_0000 7.3.1.33.1/7-78 siu_base+0x0d20? siu_base+0x0d3f reserved siu_base+0x0d40 siu_etpuba? dspia etpub select register 32 r/w 0x0000_0000 7.3.1.33.2/7-79 siu_base+0x0d44 siu_emiosa? dspia emios select register 32 r/w 0x0000_0000 7.3.1.33.2/7-79 siu_base+0x0d48 siu_dspiahla?dspia siu_dspiah/l select register 32 r/w 0x0000_0000 7.3.1.33.2/7-79 siu_base+0x0d4c? reserved siu_base+0x0d50 siu_etpuab?dspib etpua select register 32 r/w 0x0000_0000 7.3.1.33.3/7-81 siu_base+0x0d54 siu_emiosb? dspib emios select register 32 r/w 0x0000_0000 7.3.1.33.3/7-81 siu_base+0x0d58 siu_dspibhlb?dspib siu_dspibh/l select register 32 r/w 0x0000_0000 7.3.1.33.3/7-81 siu_base+0x0d5c reserved siu_base+0x0d60 siu_etpuac?dspic etpua select register 32 r/w 0x0000_0000 7.3.1.33.4/7-82 siu_base+0x0d64 siu_emiosc ?dspic emios select register 32 r/w 0x0000_0000 7.3.1.33.4/7-82 siu_base+0x0d68 siu_dspichlc?dspic siu_dspich/l select register 32 r/w 0x0000_0000 7.3.1.33.4/7-82 siu_base+0x0d6c siu_etpubc ?dspic etpub select register 32 r/w 0x0000_0000 7.3.1.33.4/7-82 siu_base+0x0d70 siu_etpubd ?dspid etpub select register 32 r/w 0x0000_0000 7.3.1.34/7-84 table 7-5. siu memory map (continued) address register bits access reset value section/page
system integration unit (siu) 7-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1 register descriptions 7.3.1.1 mcu id register (siu_midr) the siu_midr contains the part identification number and mask revision number specific to the device. the part number is a read-only field that is mask programmed with the pa rt number of the device. the part number changes depending on the module versions c ontained in a device. the part number does not change for bug fixes or process changes. the mask number is a read-only field that is mask programmed with the specific mask revision level of the device. the current value applies to revi sion 0 and is updated for each mask revision. the mcu id register is 32 bits. figure 7-2 shows the mcu id register values. siu_base+0x0d74 siu_emiosd ?dspid emios select register 32 r/w 0x0000_0000 7.3.1.34/7-84 siu_base+0x0d78 siu_dspidhld?dspic siu_dspich/l select register 32 r/w 0x0000_0000 7.3.1.34/7-84 siu_base+0x0d7c? siu_base+0x0dff reserved siu_base+0x0e00? siu_base+0x0fdc siu_gpdi0?siu_gpdi511?gpio pin data input register 0?511 8 r 0x0u 7.3.1.35/7-86 table 7-5. siu memory map (continued) address register bits access reset value section/page
system integration unit (siu) freescale semiconductor 7-11 pxr40 microcontroller reference manual, rev. 1 the following table desc ribes the midr fields: 7.3.1.2 reset status register (siu_rsr) the siu_rsr contains the sources of th e most recent reset, and the state of the configuration pins at reset. except for a por request or a software external reset, all reset requests, regard less of priority, are not serviced until the current reset completes. this register contains one reset st atus bit for each reset source (see table 7-7 ). a reset status bit set to 1 indicates a reset request by that source. af ter the reset status bits are set, they remain set until another re set occurs. simultaneous reset requests ar e prioritized. when reset requests with different priorities occur on the same clock cycle, the reset request with th e highest priority is serviced and the status bit of only that reset request is set. address: siu_base + 0x0004 access: read only 0123456789101112131415 r partnum w pxr40 part number 0 1 0 1 0 1 1 0 0 1 1 1 0 1 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pkg 0 0 0 0 masknum_major masknum_minor w default reset values 416= 0b0110 516=0b1110 0 0 0 0 0b0000 0b0000 figure 7-2. pxr40 mcu id register (siu_midr) table 7-6. siu_midr bi t field descriptions field description 0?15 partnum mcu part number. read-only, mask-programmed part identification number of the mcu. pxr40 reads 0x5674 16?19 pkg package settings. pkg selects the pin package for the device. 0110 select the 416 package 1110 select the 516 package all other settings are reserved. 20?23 reserved 24?27 masknum_major major revision number of mcu mask. read-only, mask programmed mask number of the mcu. reads 0x0 for the initial mask set of the device, and changes sequentially for each mask set. 28?31 masknum_minor minor revision number of mcu mask. read-only, mask programmed mask number of the mcu. reads 0x0 for the initial mask set of the device, and changes sequentially for each mask set.
system integration unit (siu) 7-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the following table lists the reset sources and arbitration priorities: the wkpcfg bit retains the latest value of the wkpc fg signal before reset. the bootcfg field retains the latest values of the boot cfg[0:1] signals before reset. figure 7-3. reset status register (siu_rsr) table 7-7. reset source priorities reset source priority group ? power on reset (por) ? external reset highest 0 ? software system reset higher 1 ? loss-of-clock ? loss-of-lock ? core watchdog or debug ? platform watchdog lower 2 ? software external reset lowest 3 address: siu_base + 0x000c access: r/w 0 1 2 3 4 5 6 7 8 9 101112131415 r pors ers llrs lcrs wdrs 0 swt rs 0000000ssrs serf w reset 1 1 the reset status register receives the reset values during power-on reset. 1000 0 00000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rwkp cfg 2 2 the reset value of the wkpcfg bit is the value on the wkpcfg pin at the time of the last reset. 0 0 0 0 0 0 0 0 0 0 0 abr bootcfg rgf w reset 1 u 2 00000000000u u 3 3 the reset value of the bootcfg bits is the value on t he bootcfg[0:1] pins at th e time of the last reset. 0
system integration unit (siu) freescale semiconductor 7-13 pxr40 microcontroller reference manual, rev. 1 the following table lists and describes th e fields of the reset status register: table 7-8. siu_rsr bit field descriptions field description 0 pors power-on reset status. 0 another reset source was acknowledged by the reset co ntroller since the last assertion of the power-on reset input. 1 the power-on reset input to the reset controller was asserted and no other reset source was acknowledged since the assertion of the power-on reset input except an external reset. 1 ers external reset status. 0 the last reset source acknowledged by the reset controller was not a valid assertion of the reset pin. 1 the last reset source acknowledged by the rese t controller was a valid assertion of the reset pin. 2 llrs loss-of-lock reset status. 0 the last reset source acknowledged by the reset controller was not a loss-of-pll lock reset. 1 the last reset source acknowledged by the re set controller was a lo ss-of-pll lock reset. 3 lcrs loss-of-clock reset status. 0 the last reset source acknowledged by the reset controller was not a loss-of-clock reset. 1 the last reset source acknowledged by the reset controller was a loss-of-clock reset. 4 wdrs core watchdog timer/debug reset status. 0 the last reset source acknowledged by the reset controller was not a watchdog timer or debug reset. 1 the last reset source acknowledged by the reset controller was a watchdog timer or debug reset. 6 swtrs platform software watch dog reset status. 0 the last reset source acknowledged by the reset controller was not a platform software watchdog timer or debug reset. 1 the last reset source acknowledged by the reset controller was a platform software watchdog timer or debug reset. 7?13 reserved 14 ssrs software system reset status. 0 the last reset source acknowledged by the reset controller was not a software system reset. 1 the last reset source acknowledged by the re set controller was a software system reset. 15 serf software external reset flag. 0 the software external reset input to the reset controller was not asserted, or this bit has been cleared by writing a 1 to it. 1 the software external reset input to the reset controller was asserted while this bit was 0. 16 wkpcfg weak pull configuration pin status 0 the wkpcfg pin value latched during the last reset was a logical 0 and weak pulldown is the default setting. 1 the wkpcfg pin value latched during the last reset was a logical 1 and weak pullup is the default setting. 17?27 reserved 28 abr auto baud rate 0 auto baud rate disabled 1 auto baud rate enabled
system integration unit (siu) 7-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 except for a por request or writing a 1 to the software external reset flag (serf) bit, all reset requests, regardless of priority are not servi ced until the current reset completes. in the following cases, more than one reset bit is set in the reset stat us register (siu_rsr): 29?30 bootcfg reset configuration pin status. bootcfg[0:1] identif ies the address of the reset configuration ha lfword (rchw) and whether arbitration is used by the boot assist module (bam). 00 internal boot mode ? lowest address (0x0000_0000) from one of the six las fields in internal flash memory. 01 serial boot mode ? lower halfword of the censorship control word. 10 external boot mode ? lowest address (0x0000_0000) of external memory as defined by the chip select 0 (d_cs [0]) signal with no external arbitration. 11 external boot mode with external arbitration. 31 rgf reset glitch flag. set by the reset controller when a glitch is detected on the reset pin. this bit is cleared by the assertion of the power-on reset input to the reset controller, or a write of 1 to the rgf bit. refer to section 7.4.2.2, reset pin glitch detect , for more information on glitch detection. 0 no glitch has been detected on the reset pin. 1 a glitch has been detected on the reset pin. table 7-9. causes that set multiple reset status bits case 1 condition ? por request negates and the device remains in the reset ? external reset requested ? por and external reset status bits are set reason por request started the reset sequence, but an ex ternal reset request was received before the por reset sequence ended. case 2 condition ? software external reset requested ? serf flag bit set but no previously set bits in the siu_rsr are cleared reason the serf flag bit is cleared by writing a 1 (write 1 to clear) to the bit location or when another reset source is asserted. case 3 condition ? loss-of-clock reset requested ? loss-of-lock reset requested ? watchdog reset requested reason more than one reset request o ccurred on the same clock cycle with no reset request by a higher-priority reset source, therefore the status bits for all the requesting resets are set. refer to ta b l e 7 - 7 . table 7-8. siu_rsr bit fiel d descriptions (continued) field description
system integration unit (siu) freescale semiconductor 7-15 pxr40 microcontroller reference manual, rev. 1 7.3.1.3 system reset control register (siu_srcr) the system reset control register c onfigures whether a software system reset or a software external reset is generated. an software system rese t uses an internal system reset. an software external reset asserts rstout . figure 7-4. system reset control register (siu_srcr) the following table describes the fields in the system reset control register: 7.3.1.4 external interrupt status register (siu_eisr) the external interrupt status register is us ed to record edge-tri ggered events on the irq [0]?irq [15] inputs to the siu and record the critical interrupts nmi and swt. when an edge -detect enable bit is set in the address: siu_base + 0x0010 access: r/w 0123456789101112131415 r0ser 00000000000000 w ssr 1 1 the ssr bit always reads 0. a write of 0 to this bit has no effect. see note 2 2 write 1 to the ser bit to generate a software external reset. a write of 0 to this bit has no effect. when the reset completes, the ser bit is cleared to 0. reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset1000000000000000 table 7-10. siu_srcr bit field descriptions field description 0 ssr software system reset. the software system reset is processed as a synchronous reset. except for a software external reset, the bit automatically clears if any other reset source asserts. 0 no software system reset. 1 generate an software internal system reset. 1 ser software external reset. used to generate a software external reset. writing a 1 to this bit asserts rstout for 2400 clocks, and the internal reset is not asserted. the bit automatically clears when the software external reset completes or any other reset source is asserted. after a software external reset has been initiated, rstout negates if this bit is cleared before the 2400 clock period expires. 0 do not generate a software external reset. 1 generate a software external reset. 2?31 reserved
system integration unit (siu) 7-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 siu_ireer or siu_ifeer registers for an irq and an irq edge-event occurs and is detected, the irq flag bit is set in the siu_eisr. the irq flag bits are cleare d by writing a 1 to the bi t. a write of 0 has no effect. the irq flag bit is set regardless of the state of th e dma or interrupt request enable bit in siu_direr. the irq flag bit remains set until cleared by softwa re or through the servicing of a dma or interrupt request. the following table describes the fields in the external interr upt status register: 7.3.1.5 dma/interrupt request enable register (siu_direr) the siu_direr asserts a dma transfer or external interrupt request if the irq flag bit is set in the siu_eisr. the dma transfer or external interrupt requ est enable bits (eire flags) enable an external interrupt request or dma transfer re quest. the siu uses one interrupt re quest to the interrupt controller. the eire bits determine the external interrupt requests that a ssert the siu interrupt request to the interrupt controller. address: siu_base + 0x0014 access: r/w1c 0123456789101112131415 rnmi000000000000000 w w1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reif15eif14eif13eif12eif11eif10eif9eif8eif7eif6eif5eif4eif3eif2eif1eif0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 7-5. external interrupt status register (siu_eisr) table 7-11. siu_eisr bit field descriptions field description 0 nmi non-maskable interrupt flag. this bit is set when a nmi interrupt occurs on the nmi input pin. cleared by writing a 1. 0 no nmi event has occurred on the nmi input 1 an nmi event has occurred on the nmi input 1?15 reserved 16?31 eif n external interrupt request flag n. this bit is set when an edge-triggered event occurs on the corresponding irq[ n ] input. cleared by writing a 1. 0 no edge-triggered event has occurred on the corresponding irq[ n ] input. 1 an edge-triggered event has occurred on the corresponding irq[ n ] input.
system integration unit (siu) freescale semiconductor 7-17 pxr40 microcontroller reference manual, rev. 1 the following table describes the fields in the dma interrupt requ est enable register: 7.3.1.6 dma/interrupt request select register (siu_dirsr) the siu_dirsr selects between a dma or interrupt request for events on the irq [0]?irq [3] inputs. if the irq flag bits are set in the ex ternal irq status register (siu_e isr) and the dma/interrupt request enable register (siu_direr), then the select bi t in the dma interrupt request select register (siu_dirsr) determines whether a dma or interrupt request is asserted. address: siu_base + 0x0018 access: r/w 0123456789101112131415 r nmi sel8 0000000 nmi sel0 0000000 w reset000000000 0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reire 15 eire 14 eire 13 eire 12 eire 11 eire 10 eire 9 eire 8 eire 7 eire 6 eire 5 eire 4 eire 3 eire 2 eire 1 eire 0 w reset000000000 0000000 figure 7-6. dma/interrupt request enable register (siu_direr) table 7-12. siu_direr bit field descriptions field description 0 nmisel 8 non maskable interrupt / critical in terrupt selection (nmi comes from external pin). siu generates two specific sources of interrupt to the core, one of them is defined as critical interrupt and the other is defined as non maskable interrupt (nmi). the nmisel bit sele cts which signal receives the irq from the pin. 0 nmi is enabled (ivor1 core exception) 1 critical interrupt is enabled (ivor0 core exception) note: nmisel8 is a write once bit. 1?7 reserved 8 nmisel 0 non maskable interrupt / critical interrupt selection (n mi comes from watchdog timer, swt). siu generates two specific sources of interrupt to th e core, one of them is defined as crit ical interrupt and the other is defined as non maskable interrupt (nmi). 0 nmi is enabled (ivor1 core exception) 1 critical interrupt is enabled (ivor0 core exception) note: nmisel0 is a write once bit. 9?15 reserved 16?31 eire n external interrupt request enable n. enables the assertion of the interrupt request from the siu to the interrupt controller when an edge-triggered event occurs on the irq[ n ] pin. 0 external interrupt request is disabled. 1 external interrupt request is enabled. note: eire[0:3] can optionally enable dma requests instead of irqs.
system integration unit (siu) 7-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the following table describes the fiel ds of the request select register: 7.3.1.7 overrun status register (siu_osr) the siu_osr flag bits indicate that an overrun has occurred. address: siu_base + 0x001c access: r/w 0123456789101112131415 r0000000000000000 w reset0 000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 dirs 3 dirs 2 dirs 1 dirs 0 w reset0000000000000000 figure 7-7. dma/interrupt request select register (siu_dirsr) table 7-13. siu_dirsr bit field descriptions field description 0?27 reserved 28?31 dirs n dma interrupt request select n. selects between a dma transfer or external interrupt request when an edge-triggered event occurs on the corresponding irq[ n ] pin. 0 interrupt request is selected. 1 dma request is selected. address: siu_base + 0x0020 access: r/w 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovf 15 ovf 14 ovf 13 ovf 12 ovf 11 ovf 10 ovf 9 ovf 8 ovf 7 ovf 6 ovf 5 ovf 4 ovf 3 ovf 2 ovf 1 ovf 0 w reset0000000000000000 figure 7-8. overrun status register (siu_osr)
system integration unit (siu) freescale semiconductor 7-19 pxr40 microcontroller reference manual, rev. 1 the following table describes the fiel ds in the overrun status register: 7.3.1.8 overrun request enable register (siu_orer) the siu_orer contains bits to enable an overrun if the corresponding flag bit is set in the siu_osr. if the overrun request enable bit and the flag bit are se t, the single combined ove rrun request from the siu to the interrupt cont roller is asserted. the following table describes the fields in the overrun request enable register: table 7-14. siu_osr bit field descriptions field description 0?15 reserved 16?31 ovf n overrun flag n. this bit is set when an overrun occurs on irq[ n ]. bit 31 (ovf0) is the overrun flag for irq [0]; bit 16 (ovf15) is overrun flag for irq [15]. 0 no overrun occurred. 1 an overrun occurred. address: siu_base + 0x0024 access: r/w 0 1 2 3 4 5 6789101112131415 r0 0 0 0 0 0 0000000000 w reset0 0 0 0 0 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ore 15 ore 14 ore 13 ore 12 ore 11 ore 10 ore 9 ore 8 ore 7 ore 6 ore 5 ore 4 ore 3 ore 2 ore 1 ore 0 w reset0 0 0 0 0 0 0000000000 figure 7-9. overrun request enable register (siu_orer) table 7-15. siu_orer bit field descriptions field function 0?15 reserved 16?31 ore n overrun request enable n. e nables the overrun request when an overrun occurs on the irq[ n ] pin. bit 31 (ore0) is the enable overrun flag for irq [0]; bit 16 (ore15) is overrun flag for irq [15]. 0 overrun request is disabled. 1 overrun request is enabled.
system integration unit (siu) 7-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.9 irq rising-edge event enable register (siu_ireer) the siu_ireer enables rising edge-triggered events on irq [ n ]. rising- and falling-edge events are enabled by setting the bits in siu_ireer and siu_ifeer. siu_ireer bits used for nmi events are write once and another write will be allowed after a reset. the following table describes the fields in the irq rising-edge event enable register: address: siu_base + 0x0028 access: r/w 0123456789101112131415 r iree_ nmi8 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r iree 15 iree 14 iree 13 iree 12 iree 11 iree 10 iree9 iree8 iree7 iree6 iree5 iree4 iree3 iree2 iree1 iree0 w reset0000000000000000 figure 7-10. irq rising-edge event enable register (siu_ireer) table 7-16. siu_ireer bit field descriptions field function 0 iree_ nmi8 irq rising-edge event enable for nmi from external nmi pin . 0 rising-edge event is disabled. 1 rising-edge event is enabled. 1?15 reserved 16?0 iree n irq rising-edge event enable n. enables rising-edge-triggered events on the corresponding irq[ n ] pin. 0 rising-edge event is disabled. 1 rising-edge event is enabled.
system integration unit (siu) freescale semiconductor 7-21 pxr40 microcontroller reference manual, rev. 1 7.3.1.10 irq falling-edge event enable register (siu_ifeer) the siu_ifeer enables falling edge-triggered events on irq [ n ]. rising- and falling-edge events are enabled by setting the bits in both siu_ireer and siu_ifeer. siu_ifeer bits used for nmi events are write once and another write will be allowed after a reset. the following table describes the fields in the irq falling-edge ev ent enable register: address: siu_base + 0x002c access: r/w 0123456789101112131415 r ifee_ nmi8 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ifee 15 ifee 14 ifee 13 ifee 12 ifee 11 ifee 10 ifee 9 ifee 8 ifee 7 ifee 6 ifee 5 ifee 4 ifee 3 ifee 2 ifee 1 ifee 0 w reset0000000000000000 figure 7-11. irq falling-edge event enable register (siu_ifeer) table 7-17. siu_ifeer bit field descriptions field function 0 ifee_ nmi8 irq rising-edge event enable for nmi from external nmi pin . 0 rising-edge event is disabled. 1 rising-edge event is enabled. 1?15 reserved 16?0 ifee n irq falling-edge event enable n. enables falling-edge-triggered events on the corresponding irq[ n ] pin. 0 falling-edge event is disabled. 1 falling-edge event is enabled.
system integration unit (siu) 7-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.11 irq digital filter register (siu_idfr) the siu_idfr specifies the amoun t of digital filtering on irq [0]?irq [15]. the digital fi lter length field specifies the number of system clocks that define the period of the digi tal filter and the minimum time an irq signal must hold the active state to qualify as an edge-triggered event. the following table describes the field in the irq digital filter register: 7.3.1.12 irq filtered input register (siu_ifir) the siu_ifir is a read only register wher e the filtered values of the nmi and irq [0]?irq [15] pins are captured. address: siu_base + 0x0030 access: r/w 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 dfl w reset0000000000000000 figure 7-12. irq digital filter register (siu_idfr) table 7-18. siu_idfr bit field descriptions field function 0?27 reserved 28?31 dfl digital filter length. defines the digital filter period on the irq [ n] inputs according to the following equation: for a 100 mhz system clock, this gives a range of 20 ns to 328 s. the minimum time of three clocks accounts for synchronization of the irq input pins with the system clock. filter period systemclockperiod 2 dfl ? ?? 1s ? ystemclockperiod ? + =
system integration unit (siu) freescale semiconductor 7-23 pxr40 microcontroller reference manual, rev. 1 address: siu_base + 0x0034 access: read only 0123456789101112131415 r ifi_ nmi 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ifi15 ifi14 ifi13 ifi12 ifi11 ifi10 ifi9 ifi8 ifi7 ifi6 ifi5 ifi4 ifi3 ifi2 ifi1 ifi0 w reset0000000000000000 figure 7-13. irq filtered input register (siu_ifir) table 7-19. siu_ifir bit field descriptions field function 0?31 ifi n filtered input n?set/cleared for the corresponding filtered irq pin. 0 a logic zero has passed through the irq digital filter for the corresponding irq pin. 1 a logic one has passed through the irq digital filter for the corresponding irq pin.
system integration unit (siu) 7-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.13 pad configuration registers (siu_pcr) the following subsections define pad configuration registers (pcr) in the siu_pcr segment. these registers define the pad configuratio n for all configurable device pins that specify that active function, direction, and electr ical attributes for the pin. th e information presented pertains to which bits and fields are active for a given pin or group of pi ns, and the reset state of the register. the reset state of siu_pcrs given in this section is the value before the bam program executes. the bam program can change some pad c onfiguration registers ba sed on the reset configur ation. refer to the bam chapter for more detailed information. the siu_pcrs are 16-bit registers that are read from or written to as: ? 16-bit values aligned on 16-bit boundaries, or ? 32-bit values aligned on 32-bit address boundaries. note the fields available in a siu_pcr de pend on the type of pad it controls. refer to the siu_pcr definition. all device pin names begi n with the primary function, followed by the alternate function, and then gpio. in some cases, the third function can be a secondary alternate, wh ich supersedes the gpio. those exceptions are noted in the documentation. for example, siu_pcr85 configures the cntxb_pcsc[3]_gpio[85] muxed signal, where cntxb is the pr imary function, pcsc[3] is the alternate function. for iden tification of the source module for primary and alternate functions, and the description of these signals, refer to chapter 3, signal descriptions , of this manual. refer to the chapter for the specific module that uses the si gnal for an additional signal description. address: siu_base + offset (see siu_pcrn settings tabl e) access: user read/write 0123456789101112131415 r 0 0 0 pa obe ibe dsc ode hys src wpe wps w reset see siu_pcrn settings table for reset values figure 7-14. pad configuration register (siu_pcr n )
system integration unit (siu) freescale semiconductor 7-25 pxr40 microcontroller reference manual, rev. 1 the following table describes the fields in the pad configuration control registers: table 7-20. siu_pcr bit field descriptions field description 0?2 reserved 3?5 pa [ pin assignment. selects the function of a multiplexe d pad. a separate port enable output signal from the siu is asserted for each value of this register. the size of the field can be from 1 to 3 bits, depending on the amount of multiplexing on the pad. 6 obe output buffer enable. enables the pad as an out put and drives the output buffer enable signal. 0 disable output buffer for the pad. 1 enable output buffer for the pad is enabled. 7 ibe input buffer enable. enables the pad as an input and drives the input buffer enable signal. 0 disable input buffer for the pad. 1 enable input buffer for the pad is enabled. 8?9 dsc[ drive strength control. controls the pad drive strength. drive strength control pertains to pins with the fast i/o pad type. 00 10 pf drive strength 01 20 pf drive strength 10 30 pf drive strength 11 50 pf drive strength 10 ode open drain output enable. controls output driver configuration for the pads. either open drain or push/pull driver configurations can be selected. this feature applies to output pins only. 0 disable open drain for the pad (push/pull driver enabled). 1 enable open drain for the pad. 11 hys input hysteresis. controls whether hysteresis is enabled for the pad. 0 disable hysteresis for the pad. 1 enable hysteresis for the pad. pa pin function 1 1 for any siu_pcr that does not comply with these rules, the pa definition is given explicitly with the siu_pcr definition. 000 gpio 0 0 1 primary function 0 1 0 alternate 1 0 1 1 alternate 2 1 0 0 alternate 3 1 0 1 invalid value 1 1 0 invalid value 1 1 1 invalid value
system integration unit (siu) 7-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12?13 src[ slew rate control. controls slew rate for the pad. sl ew rate control pertains to pins with slow or medium i/o pad types, and the output signals are driven according to the value of this field. actual slew rate depends on the pad type and load. refer to the el ectrical specifications for this information. 00 minimum slew rate 01 medium slew rate 10 invalid value 11 maximum slew rate 14 wpe weak pullup/down enable. controls whether the weak pullup/down devices are enabled/disabled for the pad. pullup/down devices are enabled by default. 0 disable weak pull device for the pad. 1 enable weak pull device for the pad. 15 wps weak pullup/down select. controls whether weak pullup or weak pulldown devices are used for the pad when weak pullup/down devices are enabled. the wkpcfg pin determines whether pullup or pulldown devices are enabled during reset. the wps bit determines whether weak pullup or pulldown devices are used after reset, or for pads in which the wkpcfg pin does not determine the reset weak pullup/down state. 0 pulldown is enabled for the pad. 1 pullup is enabled for the pad. table 7-20. siu_pcr bit field descriptions (continued) field description
system integration unit (siu) freescale semiconductor 7-27 pxr40 microcontroller reference manual, rev. 1 there are a number of input signals on the device that have multiple extern al pins as input sources. only one input source can be active at any time for these pins. to achieve th is, there is a pre-defined priority for the pcr registers controlling these pi ns, which is used to mux the input sources and allo w only one active input. the multiple source inputs wi th pcr priority is given in table 7-21 . table 7-21. pcr priority for multiple source inputs function pcr number highest priority ? lowest priority irq0 193 450 ? irq1 194 451 ? irq2 211 452 ? irq3 212 453 ? irq4 208 454 ? irq5 209 455 ? pcsb0 105 203 ? sckc 235 109 ? sinc 236 108 ? pcsc0 238 110 434 sckd 189 470 ? sind 190 472 ? pcsd0 106 469 ? canrxd 247 194 ? txda 89 83 460 rxda 90 84 461 txdb 91 462 ? rxdb 92 463 ? fr_rx_a 249 458 ?
system integration unit (siu) freescale semiconductor 7-28 pxr40 microcontroller reference manual, rev. 1 table 7-22. siu_ pcrn settings pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps 75 2 0x00d6 gpio75 3 mdo4 ? ? ? ??? 0 0 11 ?????? 76 2 0x00d8 gpio76 3 mdo5 ? ? ? ??? 0 0 11 ?????? 77 2 0x00da gpio77 3 mdo6 ? ? ? ??? 0 0 11 ?????? 78 2 0x00dc gpio78 3 mdo7 ? ? ? ??? 0 0 11 ?????? 79 2 0x00de gpio79 3 mdo8 ? ? ? ??? 0 0 11 ?????? 80 2 0x00e0 gpio80 3 mdo9 ? ? ? ??? 0 0 11 ?????? 81 2 0x00e2 gpio81 3 mdo10 ? ? ? ??? 0 0 11 ?????? 82 2 0x00e4 gpio82 3 mdo11 ? ? ? ??? 0 0 11 ?????? 83 0x00e6 gpio83 cntxa txda 4 ? ? ?0000??000011 84 0x00e8 gpio84 cnrxa rxda 4 ? ? ?0000??000011 85 0x00ea gpio85 cntxb pcsc3 ? ? ?0000??000011 86 0x00ec gpio86 cnrxb pcsc4 ? ? ?0000??000011 87 0x00ee gpio87 cntxc pcsd3 ? ? ?0000??000011 88 0x00f0 gpio88 cnrxc pcsd4 ? ? ?0000??000011 89 0x00f2 gpio89 txda ? ? ? ??000??000011 90 0x00f4 gpio90 rxda ? ? ? ??000??000011 91 0x00f6 gpio91 txdb pcsd1 ? ? ?0000??000011 92 0x00f8 gpio92 rxdb pcsd5 ? ? ?0000??000011 93 0x00fa gpio93 scka pcsc1 ? ? ?0000??000011 94 0x00fc gpio94 sina pcsc2 ? ? ?0000??000011 95 0x00fe gpio95 souta pcsc5 ? ? ?0000??000011 96 0x0100 gpio96 pcsa0 pcsd2 ? ? ?0000??000011
system integration unit (siu) freescale semiconductor 7-29 pxr40 microcontroller reference manual, rev. 1 97 0x0102 gpio97 pcsa1 ? ? ? ??000??000011 98 0x0104 gpio98 pcsa2 ? ? ? ??000??000011 99 0x0106 gpio99 pcsa3 ? ? ? ??000??000011 100 0x0108 gpio100 pcsa4 ? ? ? ??000??000011 101 0x010a gpio101 pcsa5 etrig1 ? ? ?0000??000011 102 0x010c gpio102 sckb ? ? ? ??000??000011 103 0x010e gpio103 sinb ? ? ? ??000??000011 104 0x0110 gpio104 soutb ? ? ? ??000??000011 105 0x0112 gpio105 pcsb0 pcsd2 ? ? ?0000??000011 106 0x0114 gpio106 pcsb1 pcsd0 ? ? ?0000??000011 107 0x0116 gpio107 pcsb2 soutc ? ? ?0000??000011 108 0x0118 gpio108 pcsb3 sinc 4 ? ? ?0000??000011 109 0x011a gpio109 pcsb4 sckc 4 ? ? ?0000??000011 110 0x011c gpio110 pcsb5 pcsc0 4 ? ? ?0000??000011 113 0x0122 gpio113 tcrclka irq7 ? ? ?0000??000011 114 0x0124 gpio114 etpua0 etpua12 ? ? ?0000??00001u 115 0x0126 gpio115 etpua1 etpua13 ? ? ?0000??00001u 116 0x0128 gpio116 etpua2 etpua14 ? ? ?0000??00001u 117 0x012a gpio117 etpua3 etpua15 ? ? ?0000??00001u 118 0x012c gpio118 etpua4 etpua16 ? ? ?0000??00001u 119 0x012e gpio119 etpua5 etpua17 ? ? ?0000??00001u 120 0x0130 gpio120 etpua6 etpua18 ? ? ?0000??00001u 121 0x0132 gpio121 etpua7 etpua19 ? ? ?0000??00001u table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-30 pxr40 microcontroller reference manual, rev. 1 122 0x0134 gpio122 etpua8 etpua20 ? ? ?0000??00001u 123 0x0136 gpio123 etpua9 etpua21 ? ? ?0000??00001u 124 0x0138 gpio124 etpua10 etpua22 ? ? ?0000??00001u 125 0x013a gpio125 etpua11 etpua23 ? ? ?0000??00001u 126 0x013c gpio126 etpua12 pcsb1 ? ? ?0000??00001u 127 0x013e gpio127 etpua13 pcsb3 ? ? ?0000??00001u 128 0x0140 gpio128 etpua14 pcsb4 ? ? ?0000??00001u 129 0x0142 gpio129 etpua15 pcsb5 ? ? ?0000??00001u 130 0x0144 gpio130 etpua16 pcsd1 ? ? ?0000??00001u 131 0x0146 gpio131 etpua17 pcsd2 ? ? ?0000??00001u 132 0x0148 gpio132 etpua18 pcsd3 ? ? ?0000??00001u 133 0x014a gpio133 etpua19 pcsd4 ? ? ?0000??00001u 134 0x014c gpio134 etpua20 irq8 ? ? ?0000??00001u 135 0x014e gpio135 etpua21 irq9 ? ? ?0000??00001u 136 0x0150 gpio136 etpua22 irq10 ? ? ?0000??00001u 137 0x0152 gpio137 etpua23 irq11 ? ? ?0000??00001u 138 0x0154 gpio138 etpua24 5 irq12 ? ? ?0000??00001u 139 0x0156 gpio139 etpua25 5 irq13 ? ? ?0000??00001u 140 0x0158 gpio140 etpua26 5 irq14 ? ? ?0000??00001u 141 0x015a gpio141 etpua27 5 irq15 ? ? ?0000??00001u 142 0x015c gpio142 etpua28 5 pcsc1 ? ? ?0000??00001u 143 0x015e gpio143 etpua29 5 pcsc2 ? ? ?0000??00001u 144 0x0160 gpio144 etpua30 pcsc3 ? ? ?0000??00001u table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-31 pxr40 microcontroller reference manual, rev. 1 145 0x0162 gpio145 etpua31 pcsc4 ? ? ?0000??00001u 146 0x0164 gpio146 tcrclkb irq6 ? ? ?0000??000011 147 0x0166 gpio147 etpub0 etpub16 ? ? ?0000??00001u 148 0x0168 gpio148 etpub1 etpub17 ? ? ?0000??00001u 149 0x016a gpio149 etpub2 etpub18 ? ? ?0000??00001u 150 0x016c gpio150 etpub3 etpub19 ? ? ?0000??00001u 151 0x016e gpio151 etpub4 etpub20 ? ? ?0000??00001u 152 0x0170 gpio152 etpub5 etpub21 ? ? ?0000??00001u 153 0x0172 gpio153 etpub6 etpub22 ? ? ?0000??00001u 154 0x0174 gpio154 etpub7 etpub23 ? ? ?0000??00001u 155 0x0176 gpio155 etpub8 etpub24 ? ? ?0000??00001u 156 0x0178 gpio156 etpub9 etpub25 ? ? ?0000??00001u 157 0x017a gpio157 etpub10 etpub26 ? ? ?0000??00001u 158 0x017c gpio158 etpub11 etpub27 ? ? ?0000??00001u 159 0x017e gpio159 etpub12 etpub28 ? ? ?0000??00001u 160 0x0180 gpio160 etpub13 etpub29 ? ? ?0000??00001u 161 0x0182 gpio161 etpub14 etpub30 ? ? ?0000??00001u 162 0x0184 gpio162 etpub15 etpub31 ? ? ?0000??00001u 163 0x0186 gpio163 etpub16 pcsa1 ? ? ?0000??00001u 164 0x0188 gpio164 etpub17 pcsa2 ? ? ?0000??00001u 165 0x018a gpio165 etpub18 pcsa3 ? ? ?0000??00001u 166 0x018c gpio166 etpub19 pcsa4 ? ? ?0000??00001u 167 0x018e gpio167 etpub20 ? ? ? ??000??00001u table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-32 pxr40 microcontroller reference manual, rev. 1 168 0x0190 gpio168 etpub21 ? ? ? ??000??00001u 169 0x0192 gpio169 etpub22 ? ? ? ??000??00001u 170 0x0194 gpio170 etpub23 ? ? ? ??000??00001u 171 0x0196 gpio171 etpub24 ? ? ? ??000??00001u 172 0x0198 gpio172 etpub25 ? ? ? ??000??00001u 173 0x019a gpio173 etpub26 ? ? ? ??000??00001u 174 0x019c gpio174 etpub27 ? ? ? ??000??00001u 175 0x019e gpio175 etpub28 ? ? ? ??000??00001u 176 0x01a0 gpio176 etpub29 ? ? ? ??000??00001u 177 0x01a2 gpio177 etpub30 ? ? ? ??000??00001u 178 0x01a4 gpio178 etpub31 ? ? ? ??000??00001u 179 0x01a6 gpio179 emios0 etpua0 ? ? ?0000??00001u 180 0x01a8 gpio180 emios1 etpua1 ? ? ?0000??00001u 181 0x01aa gpio181 emios2 etpua2 ? ? ?0000??00001u 182 0x01ac gpio182 emios3 etpua3 ? ? ?0000??00001u 183 0x01ae gpio183 emios4 etpua4 ? ? ?0000??00001u 184 0x01b0 gpio184 emios5 etpua5 ? ? ?0000??00001u 185 0x01b2 gpio185 emios6 etpua6 ? ? ?0000??00001u 186 0x01b4 gpio186 emios7 etpua7 ? ? ?0000??00001u 187 0x01b6 gpio187 emios8 etpua8 ? ? ?0000??00001u 188 0x01b8 gpio188 emios9 etpua9 ? ? ?0000??00001u 189 0x01ba gpio189 emios10 sckd ? ? ?0000??00001u 190 0x01bc gpio190 emios11 sind ? ? ?0000??00001u table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-33 pxr40 microcontroller reference manual, rev. 1 191 0x01be gpio191 emios12 soutc ? ? ?0000??00001u 192 0x01c0 gpio192 emios13 soutd ? ? ?0000??00001u 193 0x01c2 gpio193 emios14 irq0 cntxd ? ?0000??00001u 194 0x01c4 gpio194 emios15 irq1 cnrxd 4 ? ?0000??00001u 195 0x01c6 gpio195 emios16 etpub0 fr_dbg[3] ? ?0000??00001u 196 0x01c8 gpio196 emios17 etpub1 fr_dbg[2] ? ?0000??00001u 197 0x01ca gpio197 emios18 etpub2 fr_dbg[1] ? ?0000??00001u 198 0x01cc gpio198 emios19 etpub3 fr_dbg[0] ? ?0000??00001u 199 0x01ce gpio199 emios20 etpub4 ? ? ?0000??00001u 200 0x01d0 gpio200 emios21 etpub5 ? ? ?0000??00001u 201 0x01d2 gpio201 emios22 etpub6 ? ? ?0000??00001u 202 0x01d4 gpio202 emios23 etpub7 ? ? ?0000??00001u 203 0x01d6 gpio203 emios24 pcsb0 4 ? ? ?0000??00001u 204 0x01d8 gpio204 emios25 pcsb1 ? ? ?0000??00001u 208 0x01e0 gpio208 pllcfg0 irq4 ? ? ?0100??010011 209 0x01e2 gpio209 pllcfg1 irq5 soutd ? ?0100??010011 211 0x01e6 gpio211 bootcfg0 irq2 ? ? ?0100??010010 212 0x01e8 gpio212 bootcfg1 irq3 ? ? ?0100??010010 213 0x01ea gpio213 wkpcfg nmi ? ? ??100???10011 214 0x01ec ? engclk ? ? ? ??? 1 ? 1 1 ?????? 219 0x01f6 ? mcko ? ? ? ????? 1 1 ?????? 220 0x01f8 gpio220 3 mdo0 ? ? ? ???00110000?? 221 0x01fa gpio221 3 mdo1 ? ? ? ???0011000000 table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-34 pxr40 microcontroller reference manual, rev. 1 222 0x01fc gpio222 3 mdo2 ? ? ? ???0011000000 223 0x01fe gpio223 3 mdo3 ? ? ? ???0011000000 224 0x0200 ? mseo0 ? ? ? ????? 1 1 ?????? 225 0x0202 ? mseo1 ? ? ? ????? 1 1 ?????? 226 0x0204 ? rdy ? ? ? ????? 1 1 ?????? 227 0x0206 ? evto ? ? ? ????? 1 1 ?????? 228 0x0208 ? tdo ? ? ? ????? 1 1 ?????? 229 0x020a ? d_clkout ? ? ? ??? 1 ? 1 1 ?????? 230 0x020c ? rstout ? ? ? ????????? 1 1 ?? 231 6 0x020e gpio231 mdo12 ? ? ? ???001100??00 232 6 0x0210 gpio232 mdo13 ? ? ? ???001100??00 233 6 0x0212 gpio233 mdo14 ? ? ? ???001100??00 234 6 0x0214 gpio234 mdo15 ? ? ? ???001100??00 235 0x0216 gpio235 sckc sck_c_lvds+ ? ? ?0000??000011 236 0x0218 gpio236 sinc sck_c_lvds- ? ? ?0000??000011 237 0x021a gpio237 soutc sout_c_lvds+ ? ? ?0000??000011 238 0x021c gpio238 pcsc0 sout_c_lvds- ? ? ?0000??000011 239 0x021e gpio239 pcsc1 ? ? ? ??000??000011 240 0x0220 gpio240 pcsc2 ? ? ? ?0000??000011 241 0x0222 gpio241 pcsc3 ? ? ? ?0000??000011 242 0x0224 gpio242 pcsc4 ? ? ? ?0000??000011 243 0x0226 gpio243 pcsc5 ? ? ? ?0000??000011 244 0x0228 gpio244 txdc etrig0 ? ? ?0000??000011 table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-35 pxr40 microcontroller reference manual, rev. 1 245 0x022a gpio245 rxdc ? ? ? ??000??000011 246 0x022c gpio246 cntxd ? ? ? ??000??000011 247 0x022e gpio247 cnrxd ? ? ? ??000??000011 248 0x0230 gpio248 fr_a_tx ? ? ? ??000??00001 7 1 7 249 0x0232 gpio249 fr_a_rx ? ? ? ??000??00001 7 1 7 0 250 0x0234 gpio250 fr_a_tx_en ? ? ? ??000??00001 7 1 7 0 251 0x0236 gpio251 fr_b_tx ? ? ? ??000??00001 7 1 7 0 252 0x0238 gpio252 fr_b_rx ? ? ? ??000??00001 7 1 7 0 253 0x023a gpio253 fr_b_tx_en ? ? ? ??000??00001 7 1 7 256 0x0240 gpio256 d_cs0 ? ? ? ??0000000??11 257 0x0242 gpio257 d_cs2 d_add_dat31 ? ? ?00000000??11 258 0x0244 gpio258 d_cs3 d_tea ? ? ?00000000??11 259 0x0246 gpio259 d_add12 ? ? ? ??0000000??11 260 0x0248 gpio260 d_add13 ? ? ? ??0000000??11 261 0x024a gpio261 d_add14 ? ? ? ??0000000??11 262 0x024c gpio262 d_add15 ? ? ? ??0000000??11 263 0x024e gpio263 d_add16 d_add_dat16 ? ? ?00000000??11 264 0x0250 gpio264 d_add17 d_add_dat17 ? ? ?00000000??11 265 0x0252 gpio265 d_add18 d_add_dat18 ? ? ?00000000??11 266 0x0254 gpio266 d_add19 d_add_dat19 ? ? ?00000000??11 267 0x0256 gpio267 d_add20 d_add_dat20 ? ? ?00000000??11 268 0x0258 gpio268 d_add21 d_add_dat21 ? ? ?00000000??11 269 0x025a gpio269 d_add22 d_add_dat22 ? ? ?00000000??11 table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-36 pxr40 microcontroller reference manual, rev. 1 270 0x025c gpio270 d_add23 d_add_dat23 ? ? ?00000000??11 271 0x025e gpio271 d_add24 d_add_dat24 ? ? ?00000000??11 272 0x0260 gpio272 d_add25 d_add_dat25 ? ? ?00000000??11 273 0x0262 gpio273 d_add26 d_add_dat26 ? ? ?00000000??11 274 0x0264 gpio274 d_add27 d_add_dat27 ? ? ?00000000??11 275 0x0266 gpio275 d_add28 d_add_dat28 ? ? ?00000000??11 276 0x0268 gpio276 d_add29 d_add_dat29 ? ? ?00000000??11 277 0x026a gpio277 d_add30 d_add_dat30 ? ? ?00000000??11 278 0x026c gpio278 d_add_dat0 ? ? ? ??0000000??11 279 0x026e gpio279 d_add_dat1 ? ? ? ??0000000??11 280 0x0270 gpio280 d_add_dat2 ? ? ? ??0000000??11 281 0x0272 gpio281 d_add_dat3 ? ? ? ??0000000??11 282 0x0274 gpio282 d_add_dat4 ? ? ? ??0000000??11 283 0x0276 gpio283 d_add_dat5 ? ? ? ??0000000??11 284 0x0278 gpio284 d_add_dat6 ? ? ? ??0000000??11 285 0x027a gpio285 d_add_dat7 ? ? ? ??0000000??11 286 0x027c gpio286 d_add_dat8 ? ? ? ??0000000??11 287 0x027e gpio287 d_add_dat9 ? ? ? ??0000000??11 288 0x0280 gpio288 d_add_dat10 ? ? ? ??0000000??11 289 0x0282 gpio289 d_add_dat11 ? ? ? ??0000000??11 290 0x0284 gpio290 d_add_dat12 ? ? ? ??0000000??11 291 0x0286 gpio291 d_add_dat13 ? ? ? ??0000000??11 292 0x0288 gpio292 d_add_dat14 ? ? ? ??0000000??11 table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-37 pxr40 microcontroller reference manual, rev. 1 293 0x028a gpio293 d_add_dat15 ? ? ? ??0000000??11 294 0x028c gpio294 d_rd_wr ? ? ? ??0000000??11 295 0x028e gpio295 d_we0 ? ? ? ??0000000??11 296 0x0290 gpio296 d_we1 ? ? ? ??0000000??11 297 0x0292 gpio297 d_oe ? ? ? ??0000000??11 298 0x0294 gpio298 d_ts ? ? ? ??0000000??11 299 0x0296 gpio299 d_ale ? ? ? ??0000000??10 300 0x0298 gpio300 d_ta ? ? ? ??0000000??11 301 0x029a gpio301 d_cs1 ? ? ? ??0000000??11 302 0x029c gpio302 d_bdip ? ? ? ??0000000??11 303 0x029e gpio303 d_we2 ? ? ? ??0000000??11 304 0x02a0 gpio304 d_we3 ? ? ? ??0000000??11 305 0x02a2 gpio305 d_add9 ? ? ? ??0000000??11 306 0x02a4 gpio306 d_add10 ? ? ? ??0000000??11 307 0x02a6 gpio307 d_add11 ? ? ? ??0000000??11 432 0x03a0 gpio432 emios26 pcsb2 ? ? ?0000??00001u 433 0x03a2 gpio433 emios27 pcsb3 ? ? ?0000??00001u 434 0x03a4 gpio434 emios28 pcsc0 4 ? ? ?0000??00001u 435 0x03a6 gpio435 emios29 pcsc1 ? ? ?0000??00001u 436 0x03a8 gpio436 emios30 pcsc2 ? ? ?0000??00001u 437 0x03aa gpio437 emios31 pcsc5 ? ? ?0000??00001u 440 0x03b0 gpio440 tcrclkc ? ? ? ??000??000011 441 0x03b2 gpio441 ? ? ? ? ??000??00001u table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-38 pxr40 microcontroller reference manual, rev. 1 442 0x03b4 gpio442 ? ? ? ? ??000??00001u 443 0x03b6 gpio443 ? ? ? ? ??000??00001u 444 0x03b8 gpio444 ? ? ? ? ??000??00001u 445 0x03ba gpio445 ? ? ? ? ??000??00001u 446 0x03bc gpio446 ? ? ? ? ??000??00001u 447 0x03be gpio447 ? ? ? ? ??000??00001u 448 0x03c0 gpio448 ? ? ? ? ??000??00001u 449 0x03c2 gpio449 ? ? ? ? ??000??00001u 450 0x03c4 gpio450 ? irq0 4 ? ?0000??00001u 451 0x03c6 gpio451 ? irq1 4 ? ?0000??00001u 452 0x03c8 gpio452 ? irq2 4 ? ?0000??00001u 453 0x03ca gpio453 ? irq3 4 ? ?0000??00001u 454 0x03cc gpio454 ? irq4 4 ? ?0000??00001u 455 0x03ce gpio455 ? irq5 4 ? ?0000??00001u 456 0x03d0 gpio456 ? ? ? ? ??000??00001u 457 0x03d2 gpio457 ? fr_a_tx ? ? ?0000??00001u 458 0x03d4 gpio458 ? fr_a_rx 4 ? ? ?0000??00001u 459 0x03d6 gpio459 ? fr_a_tx_en ? ? ?0000??00001u 460 0x03d8 gpio460 ? txda 4 ? ? ?0000??00001u 461 0x03da gpio461 ? rxda 4 ? ? ?0000??00001u 462 0x03dc gpio462 ? txdb 4 ? ? ?0000??00001u 463 0x03de gpio463 ? rxdb 4 ? ? ?0000??00001u 464 0x03e0 gpio464 ? pcsd5 maa0 mab0 00000??00001u table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) freescale semiconductor 7-39 pxr40 microcontroller reference manual, rev. 1 465 0x03e2 gpio465 ? pcsd4 maa1 mab1 00000??00001u 466 0x03e4 gpio466 ? pcsd3 maa2 mab2 00000??00001u 467 0x03e6 gpio467 ? pcsd2 ? ? ?0000??00001u 468 0x03e8 gpio468 ? pcsd1 ? ? ?0000??00001u 469 0x03ea gpio469 ? pcsd0 4 ? ? ?0000??00001u 470 0x03ec gpio470 ? sckd 4 ? ? ?0000??00001u 471 0x03ee gpio471 ? soutd ? ? ?0000??00001u 472 0x03f0 gpio472 ? sind 4 ? ? ?0000??00001u 1 ??? means the field is not impl emented in the pcr (and a defaul t value of 0 should be written) ?u? means the field is defined by the wkpcfg pin at reset 2 pcr75?pcr82: reduced port mode mdo pins, only dsc bits should be driven by pcr (also ibe and obe for gpio). 3 gpio functionality available on rev.2 of the device. 4 selection of this function may be affected by a higher priority pcr. see ta bl e 7 - 2 1 . 5 when the siu_isel8 register is in its defa ult state, this etpu pin will not be enabl ed as an input, irrespective of the siu_pcr [pa] field. 6 pcr231?pcr234: pa are controlled by nexus port controller (npc). the full port mode (fpm) bit in the npc pad configuration regi ster controls whether the pins function as mdo or gpio. the pad interface port enable is driven by th e npc block. when the fpm bit is set, th e npc enables the mdo port enable, and disables gpio. when the fpm bit is cleared, the npc disables the mdo port enable, and enables gpio. ? the obe bit applies only to gpio operation ? clear the ode bit to 0 for mdo operation ? the hys bit has no effect on mdo operation ? clear the wpe bit to 0 for mdo operation 7 bit = 1 only for rev.2 of the device. table 7-22. siu_pcrn settings (continued) pcrn address offset gpio primary function a2 a3 a4 siu_pcrn[3:15] 1 (siu_pcrn[0:2] = reserved, should be cleared) 3456789101112131415 pa 2 pa 1 pa 0 obe ibe dsc1 dsc0 ode hys src1 src0 wpe wps
system integration unit (siu) 7-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.14 gpio pin data output registers 0?512 (siu_gpdo n ) the 8-bit siu_gpdo n registers defined in figure 7-15 each specify the output data for the function assigned to the gpio[ n ] pin. the n notation in the siu_gpdo n register name relate to the [ n ] in gpio[ n ] signal name. for example, siu_gpdo246 contains the pdo246 bit for cnt xd_gpio246. the address for a gpdo pin is the gpio number plus an offset of siu_base + 0x0600. software writes to the siu_gpdo n registers to drive data out on the external pin. each register drives one external pin, which allows independent control of the pin. writes to the siu_gpdo n registers have no effect if an input function is assigned to the pin by the pad configuration register. if the direction of a gpio signal cha nges from input to output, the siu_gpdo n register value is automatically driven out to the exte rnal pin without a software update. writes to the siu_gpdo n registers have no effect wh en a primary or al ternate function is assigned (except you can read the value back that was just written). 7.3.1.15 gpio pin data input registers 0?255 (siu_gpdi n ) note this register is implemented for le gacy purposes and is limited to 256 general purpose input registers. fo r full access to all 512 general purpose input registers, the siu_gpdi n registers in section 7.3.1.35, gpio pin data input registers (siu_gpd i0_3 - siu_gpdi508_511) - standard , should be used. the 8-bit read-only siu_gpdi n registers defined in figure 7-16 each specify the input state for the function assigned to the gpdi[ n ] pin. the n notation in the siu_gpdi n register name relates to the [ n ] in gpio[ n ] signal name. for example, siu_gpdi246 c ontains the pdi246 bit for cntxd_gpio246. the address: siu_base + 0x0600 + n r/w 01234567 r0000000 pdo n w reset00000000 figure 7-15. general purpose data output (gpdo) registers 0?512 (siu_gpdo n ) table 7-23. siu_gpdo bit field descriptions field description 0?6 reserved 7 pdo n pin data out. stores the data to drive out the external gpio. if the register is read, it returns the value written. 0 a logic 0 is driven on the external gpio pin when the pin is configured as an output. 1 a logic 1 is driven on the external gpio pin when the pin is configured as an output.
system integration unit (siu) freescale semiconductor 7-41 pxr40 microcontroller reference manual, rev. 1 gpdi address for a particular pin is the gpio number plus an offs et of siu_base + 0x0800. gaps exist in the memory where gpio pins are not implemented in the package. software reads the siu_gpdi n registers to get the input state of the external gpio pin. each gpdi register contains the input state of one external gpio pin. if a gpdi register is configured as output, and the input buffer enable bi t is set to one in the pcr register, the siu_gpdi n register reflects the state of the output pin. 7.3.1.16 external irq input se lect register (siu_eiisr) the siu_eiisr selects the source fo r the external interrupt/dma inputs. address: siu_base + 0x0800 + n read only 01234567 r0000000pdi n w reset00000000 figure 7-16. general purpose data input (gpdi) registers 0?255 (siu_gpdi n ) table 7-24. siu_gpdi bit field descriptions field description 0?6 reserved 7 pdi n pin data in. this bit reflects the input state on the external gpio pin for the register. if pcr n [ibe] = 1, then: 0 signal on pin is a logic 0. 1 signal on pin is a logic 1. address: siu_base + 0x0904 access: r/w 0123456789101112131415 r esel15 esel14 esel13 esel12 esel11 esel10 esel9 esel8 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r esel7 esel6 esel5 esel4 esel3 esel2 esel1 esel0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 7-17. external irq input select register (siu_eiisr)
system integration unit (siu) 7-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the following table describes the ex ternal irq input select fields: table 7-25. siu_eiisr bit field descriptions field description 0?1 esel15 external irq input select 15. specifies the input for irq [15]. 00 irq [15] pin 01 dspi_b[15] deserialized input 10 dspi_c[0] deserialized input 11 dspi_d[1] deserialized input 2?3 esel14 external irq input select 14. specifies the input for irq [14]. 00 irq [14] pin 01 dspi_b[14] deserialized input 10 dspi_c[15] deserialized input 11 dspi_d[0] deserialized input 4?5 esel13 external irq input select 13. specifies the input for irq [13]. 00 irq [13] pin 01 dspi_b[13] deserialized input 10 dspi_c[14] deserialized input 11 dspi_d[15] deserialized input 6?7 esel12 external irq input select 12. specifies the input for irq [12]. 00 irq [12] pin 01 dspi_b[12] deserialized input 10 dspi_c[13] deserialized input 11 dspi_d[14] deserialized input 8?9 esel11 external irq input select 11. specifies the input for irq [11]. 00 irq [11] pin 01 dspi_b[11] deserialized input 10 dspi_c[12] deserialized input 11 dspi_d[13] deserialized input 10?11 esel10 external irq input select 10. specifies the input for irq 10]. 00 irq [10] pin 01 dspi_b[10] deserialized input 10 dspi_c[11] deserialized input 11 dspi_d[12] deserialized input 12?13 esel9 external irq input select 9. specifies the input for irq [9]. 00 irq [9] pin 01 dspi_b[9] deserialized input 10 dspi_c[10] deserialized input 11 dspi_d[11] deserialized input 14?15 esel8 external irq input select 8. specifies the input for irq [8]. 00 irq [8] pin 01 dspi_b[8] deserialized input 10 dspi_c[9] deserialized input 11 dspi_d[10] deserialized input 16?17 esel7 external irq input select 7. specifies the input for irq [7]. 00 irq [7] pin 01 dspi_b[7] deserialized input 10 dspi_c[8] deserialized input 11 dspi_d[9] deserialized input
system integration unit (siu) freescale semiconductor 7-43 pxr40 microcontroller reference manual, rev. 1 7.3.1.17 dspi input select register (siu_disr) the siu_disr specifies the foll owing operations for each dspi: ? data input source ? slave select ? clock input trigger input to allow serial and pa rallel chaining of the dspi modules. 18?19 esel6 external irq input select 6. specifies the input for irq [6]. 00 irq [6] pin 01 dspi_b[6] deserialized input 10 dspi_c[7] deserialized input 11 dspi_d[8] deserialized input 20?21 esel5 external irq input select 5. specifies the input for irq [5]. 00 irq [5] pin 01 dspi_b[5] deserialized input 10 dspi_c[6] deserialized input 11 dspi_d[7] deserialized input 22?23 esel4 external irq input select 4. specifies the input for irq [4]. 00 irq [4] pin 01 dspi_b[5] deserialized input 10 dspi_c[6] deserialized input 11 dspi_d[1] deserialized input 24?25 esel3 external irq input select 3. specifies the input for irq [3]. 00 irq [3] pin 01 dspi_b[3] deserialized input 10 dspi_c[4] deserialized input 11 dspi_d[5] deserialized input 26?27 esel2 external irq input select 2. specifies the input for irq [2]. 00 irq [2] pin 01 dspi_b[2] deserialized input 10 dspi_c[3] deserialized input 11 dspi_d[4] deserialized input 28?29 esel1 external irq input select 1. specifies the input for irq [1]. 00 irq [1] pin 01 dspi_b[1] deserialized input 10 dspi_c[2] deserialized input 11 emios channel 15 output 30?31 esel0 external irq input select 0. specifies the input for irq [0]. 00 irq [0] pin 01 dspi_b[0] deserialized input 10 dspi_c[1] deserialized input 11 emios channel 14 output table 7-25. siu_eiisr bit field descriptions (continued) field description
system integration unit (siu) 7-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the following table describes th e dspi input select fields: address: siu_base + 0x0908 access: r/w 0123456789101112131415 r sinsela sssela scksela trigsela s inselb ssselb sckselb trigselb w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sinselc ssselc sckselc trigselc s inseld ssseld sckseld trigseld w reset0000000000000000 figure 7-18. dspi input select register (siu_disr) table 7-26. siu_disr bit field descriptions field description 0?1 sinsela dspi a data input select. specifies the source of the dspi a data input. 00 sina_pcsc[2]_gpio[94] pin 01 soutb 10 soutc 11 soutd 2?3 sssela dspi a slave select input select. specifies the source of the dspi a slave select input. 00 pcsa[0]_pcsd[2]_gpio[96] pin 01 pcsb[0] (master) 10 pcsc[0] (master) 11 pcsd[0] (master) 4?5 scksela dspi a clock input select. specifies t he source of the dspi a clock input. 00 scka_pcsc[1]_gpio[93] pin 01 sckb (master) 10 sckc (master) 11 sckd (master) 6?7 trigsela dspi a trigger input select. specifies the source of the dspi a trigger input. 00 no trigger 01 pcsb[4] 10 pcsc[4] 11 pcsd[4] 8?9 sinselb dspi b data input select. specifies the source of dspi b data input. 00 sinb_gpio[103] pin 01 souta 10 soutc 11 soutd
system integration unit (siu) freescale semiconductor 7-45 pxr40 microcontroller reference manual, rev. 1 10?11 ssselb dspi b slave select input select. specifies the source of the dspi b slave select input. 00 pcsb[0]_pcsd[2]_gpio[105] pin 01 pcsa[0] (master) 10 pcsc[0] (master) 11 pcsd[0] (master) 12?13 sckselb dspi b clock input select. specifies t he source of the dspi b clock input. 00 sckb_gpio[102] pin 01 scka (master) 10 sckc (master) 11 sckd (master) 14?15 trigselb dspi b trigger input select. specifies the source of the dspi b trigger input for master or slave mode. 00 invalid value 01 pcsa[4] 10 pcsc[4] 11 pcsd[4] 16?17 sinselc dspi c data input select. specifies the source of the dspi c data input. 00 pcsb[3]_sinc_gpio[108] pin 01 souta 10 soutb 11 soutd 18?19 ssselc dspi c slave select input select. specifie s the source of the dspi c slave select input. 00 pcsb[5]_pcsc[0]_gpio[110] pin 01 pcsa[0] (master) 10 pcsb[0] (master) 11 pcsd[0] (master) 20?21 sckselc dspi c clock input select. specifies the source of the dspi c clock input when in slave mode. 00 pcsb[4]_sckc_gpio[109] pin 01 scka (master) 10 sckb (master) 11 sckd (master) 22?23 trigselc dspi c trigger input select. specifies the source of the dspi c trigger input for master or slave mode. 00 invalid value 01 pcsa[4] 10 pcsb[4] 11 pcsd[4] 24?25 sinseld dspi d data input select. specifies the source of the dspi d data input. 00 pcsa[3]_gpio[99] pin 01 souta 10 soutb 11 soutc table 7-26. siu_disr bit fi eld descriptions (continued) field description
system integration unit (siu) 7-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.18 eqadc command fifo trigger sour ce select - imux select registers (siu_isel[4-7]) the imux select registers (siu_isel[4 -7]) are used to select a trigger s ource for a command fifo. siu_isel select registers [4:5] are used to select a trigger source for co mmand fifos in one eqadc. siu_isel select registers [6:7] are used to sele ct a trigger source for command fifos in a second eqadc. the ctsel (combined trigge r select) field is used to conf igure one of many possible trigger sources for each command fifo. to trigger the eqadc, the trigger s ource must change to the state that the input to the command fifo has been programmed to recognize. a command fifo tri gger input can be program med to recognize either rising or falling edges, and lo w or high gated trigger types. 26?27 ssseld dspi d slave select input select. specifie s the source of the dspi d slave select input. 00 pcsb[1]_pcsd[0]_gpio[106] pin 01 pcsa0 (master) 10 pcsb0 (master) 11 pcsc0 (master) 28?29 sckseld dspi d clock input select. specifies the so urce of the dspi d clock input in slave mode. 00 pcsa[2]_sckd_gpio[98] pin 01 invalid value 10 sckb (master) 11 sckc (master) 30?31 trigseld dspi d trigger input select. specifies the source of the dspi d trigger input for master or slave mode. 00 invalid value 01 pcsa4 10 pcsb4 11 pcsc4 siu_isel4: etrig_a[5:2] address: siu_base + 0x0910 access: r/ w 0123456789101112131415 r 0 ctsel5_0 0 ctsel4_0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 ctsel3_0 0 ctsel2_0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-26. siu_disr bit fi eld descriptions (continued) field description
system integration unit (siu) freescale semiconductor 7-47 pxr40 microcontroller reference manual, rev. 1 siu_isel5: etrig_a[1:0] address: siu_base + 0x0914 access: r/ w 0123456789101112131415 r 0 ctsel1_0 0 ctsel0_0 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset 0000000000000000 siu_isel6: etrig_b[5:2] address: siu_base + 0x0918 access: r/ w 0123456789101112131415 r 0 ctsel5_1 0 ctsel4_1 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 ctsel3_1 0 ctsel2_1 w reset 0000000000000000 siu_isel7: etrig_b[1:0] address: siu_ base + 0x091c access: r/ w 0123456789101112131415 r 0 ctsel1_1 0 ctsel0_1 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset 0000000000000000
system integration unit (siu) 7-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 7-27. eqadc_a command fifo 0 trigger sources ctsel0_0 eqadc_a trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 etrig1 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 xxxxx etpua30 emios 10 xxxxx emios10 etrig 11 x x x x x etrig0 pin
system integration unit (siu) freescale semiconductor 7-49 pxr40 microcontroller reference manual, rev. 1 table 7-28. eqadc_a command fifo 1 trigger sources ctsel1_0 eqadc_a trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua7 0 0 1 1 1 etrig0 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua31 emios 1 0 x x x x x emios11 etrig 1 1 x x x x x etrig1 pin
system integration unit (siu) 7-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 7-29. eqadc_a command fifo 2 trigger sources ctsel2_0 eqadc_a trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua14 0 0 1 1 1 etrig1 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua29 emios 10 x x x xx emios15 etrig 1 1 x x x x x etrig0 pin
system integration unit (siu) freescale semiconductor 7-51 pxr40 microcontroller reference manual, rev. 1 table 7-30. eqadc_a command fifo 3 trigger sources ctsel3_0 eqadc_a trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua22 0 0 1 1 1 etrig0 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua28 emios 10 x x x xx emios14 etrig 1 1 x x x x x etrig1 pin
system integration unit (siu) 7-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 7-31. eqadc_a command fifo 4 trigger sources ctsel4_0 eqadc_a trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua30 0 0 1 1 1 etrig1 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua27 emios 10 x x x xx emios13 etrig 1 1 x x x x x etrig0 pin
system integration unit (siu) freescale semiconductor 7-53 pxr40 microcontroller reference manual, rev. 1 table 7-32. eqadc_a command fifo 5 trigger sources ctsel5_0 eqadc_a trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 etrig0 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua26 emios 10 x x x xx emios12 etrig 1 1 x x x x x etrig1 pin
system integration unit (siu) 7-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 7-33. eqadc_b command fifo 0 trigger sources ctsel0_1 eqadc_b trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 etrig1 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua30 emios 10 x x x xx emios10 etrig 1 1 x x x x x etrig0 pin
system integration unit (siu) freescale semiconductor 7-55 pxr40 microcontroller reference manual, rev. 1 table 7-34. eqadc_b command fifo 1 trigger sources ctsel1_1 eqadc_b trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua7 0 0 1 1 1 etrig0 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua31 emios 1 0 x x x x x emios11 etrig 1 1 x x x x x etrig1 pin
system integration unit (siu) 7-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 7-35. eqadc_b command fifo 2 trigger sources ctsel2_1 eqadc_b trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua14 0 0 1 1 1 etrig1 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua29 emios 10 x x x xx emios15 etrig 1 1 x x x x x etrig0 pin
system integration unit (siu) freescale semiconductor 7-57 pxr40 microcontroller reference manual, rev. 1 table 7-36. eqadc_b command fifo 3 trigger sources ctsel3_1 eqadc_b trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua22 0 0 1 1 1 etrig0 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua28 emios 10 x x x xx emios14 etrig 1 1 x x x x x etrig1 pin
system integration unit (siu) 7-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 7-37. eqadc_b command fifo 4 trigger sources ctsel4_1 eqadc_b trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 00110 etpua30 0 0 1 1 1 etrig1 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua27 emios 10 x x x xx emios13 etrig 1 1 x x x x x etrig0 pin
system integration unit (siu) freescale semiconductor 7-59 pxr40 microcontroller reference manual, rev. 1 table 7-38. eqadc_b command fifo 5 trigger sources ctsel5_1 eqadc_b trigger inputs etsel 0 0 0 0 0 0 0 not connected (default) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 etrig0 pin 0 1 0 x x reserved 01100 etpua28 01101 etpua29 01110 etpua30 01111 etpua31 10000 etpub28 10001 etpub29 10010 etpub30 10011 etpub31 1 0 1 0 0 reserved 1 0 1 0 1 reversed 1 0 1 1 0 reserved 1 0 1 1 1 reserved 11000 emios16 11001 emios17 11010 emios18 11011 emios19 11100 emios20 11101 emios21 11110 emios22 11111 emios23 etpu 01 x x x xx etpua26 emios 10 x x x xx emios12 etrig 1 1 x x x x x etrig1 pin
system integration unit (siu) 7-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.19 etpu input select register (siu_isel 8) the siu_isel 8 register is used to multiplex th e etpu[24:29] inputs. these 6 etpu channels can come from the output of the dspi or co rresponding pad. when siu_isel8 is in its default state, the etpu pins listed in figure 7-19 will not be enabled as input, irresp ective of the siu_pcr[pa] field (pcr138-143). address: siu_base + 0x0920 access: r/w 0123456789101112131415 r00000000000 etpu 29 000 etpu 28 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 etpu 27 000 etpu 26 000 etpu 25 000 etpu 24 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 7-19. etpu input select register (siu_isel8) table 7-39. siu_isel8 bit field descriptions field description 0?11 reserved 11 etpu29 etpu29 input select. specifies the source of the etpu29 channel input. 0 dspi_b serialized input 8 1 etpu29 channel input pad 12?14 reserved 15 etpu28 etpu28 input select. specifies the source of the etpu28 channel input. 0 dspi_b serialized input 9 1 etpu28 channel input pad 16?18 reserved 19 etpu27 etpu27 input select. specifies the source of the etpu27 channel input. 0 dspi_b serialized input 10 1 etpu27 channel input pad 20?22 reserved 23 etpu26 etpu26 input select. specifies the source of the etpu26 channel input. 0 dspi_b serialized input 11 1 etpu26 channel input pad 24?26 reserved 27 etpu25 etpu25 input select. specifies the source of the etpu25 channel input. 0 dspi_b serialized input 12 1 etpu25 channel input pad
system integration unit (siu) freescale semiconductor 7-61 pxr40 microcontroller reference manual, rev. 1 7.3.1.20 eqadc advance trigge r selection (siu_isel9) the eqadc?s streaming mode requires a second trigger for queue 0. th e source for this trigger can come from etpu, emios or pit channels. this mux select register selects the source of the queue 0 trigger. 28?30 reserved 31 etpu24 etpu24 input select. specifies the source of the etpu24 channel input. 0 dspi_b serialized input 13 1 etpu24 channel input pad address: siu_base + 0x0924 access: r/w 0123456789101112131415 r0000000000000000 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000 etsel0a w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 7-20. eqadc advance trigger selection (siu_isel9) table 7-40. etsel0a bit field descriptions etsel0a eqadc trigger input 0 0 0 0 0 reserved 00001 rti trigger 00010 pit0 trigger 00011 pit1 trigger 00100 pit2 trigger 00101 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 reserved 01000 etpua30 and pit0 01001 etpua30 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpua28 01101 etpua29 table 7-39. siu_isel8 bit field descriptions field description
system integration unit (siu) 7-62 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.21 decimation filter register 1 (siu_decfil1) the siu_decfil1 register contains four zsel x and hsel x fields that route se lected etpu outputs to the zir (zero/integrate/read) and halt input s for decimation filter s a through d. see chapter 28, decimation filter , for more information on the zir and ha lt operations in th e decimation filter. 01110 etpua30 01111 etpua31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 10100 emios10 and pit2 10101 emios10 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 address: siu_base + 0x0928 access: r/w 0123456789101112131415 r zsela hsela zselb hselb w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r zselc hselc zseld hseld w reset0000000000000000 table 7-40. etsel0a bit field descriptions (continued) etsel0a eqadc trigger input
system integration unit (siu) freescale semiconductor 7-63 pxr40 microcontroller reference manual, rev. 1 table 7-41. siu_decfil1 bit field descriptions field description 0?3 zsela zir input select for decimation filter a 0000 unused 0001 etpua channel 22 0010 etpua channel 23 0011 etpua channel 24 0100 etpua channel 25 4?7 hsela halt input select for decimation filter a 0000 unused 0001 etpua channel 22 0010 etpua channel 23 0011 etpua channel 24 0100 etpua channel 25 8?11 zselb zir input select for decimation filter b 0000 unused 0001 etpua channel 22 0010 etpua channel 23 0011 etpua channel 24 0100 etpua channel 25 12?15 hselb halt input select for decimation filter b 0000 unused 0001 etpua channel 22 0010 etpua channel 23 0011 etpua channel 24 0100 etpua channel 25 16?19 zselc zir input select for decimation filter c 0000 unused 0001 etpub channel 22 0010 etpub channel 23 0011 etpub channel 24 0100 etpub channel 25 20?23 hselc halt input select for decimation filter c 0000 unused 0001 etpub channel 22 0010 etpub channel 23 0011 etpub channel 24 0100 etpub channel 25 24?27 zseld zir input select for decimation filter d 0000 unused 0001 etpub channel 22 0010 etpub channel 23 0011 etpub channel 24 0100 etpub channel 25 28?31 hseld halt input select for decimation filter d 0000 unused 0001 etpub channel 22 0010 etpub channel 23 0011 etpub channel 24 0100 etpub channel 25
system integration unit (siu) 7-64 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.22 decimation filter register 2 (siu_decfil2) the siu_decfil2 register contains four zsel x and hsel x fields that route se lected etpu outputs to the zir (zero/integrate/read) and halt i nputs for decimation filt ers e through h. see chapter 28, decimation filter , for more information on the zir and ha lt operations in th e decimation filter. address: siu_base + 0x092c access: r/w 0123456789101112131415 r zsele hsele zself hself w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r zselg hselg zselh hselh w reset0000000000000000 table 7-42. siu_decfil2 bit field descriptions field description 0?3 zsele zir input select for decimation filter e 0000 unused 0001 etpua channel 18 0010 etpua channel 19 0011 etpua channel 20 0100 etpua channel 21 4?7 hsele halt input select for decimation filter e 0000 unused 0001 etpua channel 18 0010 etpua channel 19 0011 etpua channel 20 0100 etpua channel 21 8?11 zself zir input select for decimation filter f 0000 unused 0001 etpua channel 18 0010 etpua channel 19 0011 etpua channel 20 0100 etpua channel 21 12?15 hself halt input select for decimation filter f 0000 unused 0001 etpua channel 18 0010 etpua channel 19 0011 etpua channel 20 0100 etpua channel 21
system integration unit (siu) freescale semiconductor 7-65 pxr40 microcontroller reference manual, rev. 1 16?19 zselg zir input select for decimation filter g 0000 unused 0001 etpub channel 18 0010 etpub channel 19 0011 etpub channel 20 0100 etpub channel 21 20?23 hselg halt input select for decimation filter g 0000 unused 0001 etpub channel 18 0010 etpub channel 19 0011 etpub channel 20 0100 etpub channel 21 24?27 zselh zir input select for decimation filter h 0000 unused 0001 etpub channel 18 0010 etpub channel 19 0011 etpub channel 20 0100 etpub channel 21 28?31 hselh halt input select for decimation filter h 0000 unused 0001 etpub channel 18 0010 etpub channel 19 0011 etpub channel 20 0100 etpub channel 21 table 7-42. siu_decfil2 bit fi eld descriptions (continued) field description
system integration unit (siu) 7-66 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.23 chip configuration register (siu_ccr) the siu_ccr controls the chip configuration for enabling and disabling nexus on the external bus interface. figure 7-21. chip configuration register (siu_ccr) the following table describes th e chip configuration fields: address: siu_base + 0x0980 access: r/w 012345678910111213 14 15 r00000000000000matchdisnex w reset00000000000000 0 x 1 1 when system reset negates, the value in this bit depends on the censorship control word and the boot configuration bits. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000000 0 test w reset00000000000000 0 0 table 7-43. siu_ccr bit field descriptions field description 0?13 reserved 14 match compare register match. holds the value of the match input signal to the siu. the match input is asserted if the values in siu_cbrh and siu_cbrl are the same as the public password stored in flash, 0x feed_face_cafe_beef. the match bit is reset by the intern al reset condition. 0 match input signal is negated 1 match input signal is asserted 15 disnex disable nexus. holds the value of the ne xus disable input signal to the siu. when system reset negates, the value in this bi t depends on the censorship control word and the boot configuration bits. 0 nexus disable input signal is negated. 1 nexus disable input signal is asserted. 16?30 reserved 31 test test mode enable. allows reads or writes to undocumented registers used only for production tests. since these production te st registers are undocumented, estimating the impact of errant accesses to them is impossible. do not change this bit from its negated state at reset. 0 undocumented production test regist ers cannot be read or written. 1 undocumented production test regi sters can be read or written.
system integration unit (siu) freescale semiconductor 7-67 pxr40 microcontroller reference manual, rev. 1 7.3.1.24 external clock co ntrol register (siu_eccr) the siu_eccr controls the timing relationship betw een the system clock and the external clocks engclk and clkout. all bits and fi elds in the siu_eccr ar e read/write and are reset by the internal reset condition. the following table describes the external clock control fields: address: siu_base + 0x0984 access: r/w 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r engdiv ecss 000 ebts 0 ebdf w reset0001000000000001 figure 7-22. external clock control register (siu_eccr) table 7-44. siu_eccr bit field descriptions field description 0?15 reserved 16?23 engdiv engineering clock division factor. specifies the frequency ratio between f periph (also referred to as f platf on this device) and engclk. the engclk frequency is divided from f platf according to the following equation: the maximum engclk frequency is 66 mhz (132 mhz ? 2) note: setting engdiv to 0 makes the engclk frequency equal to the f periph . 24 ecss engineering clock (engclk) source select. 0 the system clock is the source of the engclk. 1 the external clock (the extal frequency of the oscillator) is the source of the engclk. 25?27 reserved 28 ebts external bus tap select. changes the phase relationship between the system clock and clkout. changing the phase relationship so that clkout is advanced in relation to the system clock increases the out put hold time of the external bus signals to a non-zero value. it also increases the output delay times, increases the input hold times to non-zero values, and decreases the input setup times. refer to the electrical specifications for how the ebts bit affects the external bus timing. 0 external bus signals have zero output hold times. 1 external bus signals have non-zero output hold times. note: do not change ebts while an external bus transaction is in process. engineering clock frequency f periph engdiv 2 ? -------------------------------- =
system integration unit (siu) 7-68 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.25 compare b register high (siu_cbrh) the siu_cbrh holds the 32-bit value that is co mpared against the pub lic password in flash (0xfeed_face_cafe_beef). the cmpbh field is r ead/write and is reset by the internal reset condition. 29 reserved 30?31 ebdf external bus division factor. specifies the frequency ratio between the system clock and the external clock, clkout. do not change ebdf during an external bus access or while an access is pending. the clkout frequency is divided from the system clock frequency according to the descriptions below. when operating in full mode (1:1), set the divider to 0b01 (divide-by-2). 00 divide by 1 01 divide by 2 10 divide by 3 11 divide by 4 address: siu_base + 0x0990 access: r/w 0123456789101112131415 r cmpbh w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cmpbh w reset0000000000000000 figure 7-23. compare b register high (siu_cbrh) table 7-44. siu_eccr bit field descriptions field description
system integration unit (siu) freescale semiconductor 7-69 pxr40 microcontroller reference manual, rev. 1 7.3.1.26 compare b register low (siu_cbrl) the siu_cbrl holds the 32-bit value that is co mpared against the public password in flash (0xfeed_face_cafe_beef). the cmpbl field is re ad/write and is reset by the internal reset condition. 7.3.1.27 system clock register (siu_sysdiv) the siu_sysdiv field is read/write and is reset by the internal reset condition. figure 7-25. system clock register (siu_sysdiv) address: siu_base + 0x0994 access: r/w 0123456789101112131415 r cmpbl w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cmpbl w reset0000000000000000 figure 7-24. compare b register low (siu_cbrl) address: siu_base + 0x9a0 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ip- clkdiv[0:1] by- pass sys- clkdi[v0:1] w reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 table 7-45. siu_sysdiv bit field descriptions field description 0-21 reserved 22?23 ipclkdiv ip clock divider. the ipclkdiv bits select the divider value for the platform, peripheral and etpu clocks with respect to the system clock. 00 cpu frequency is doubled (max 264mhz). platform, peripheral and etpu clocks are 1/2 of cpu frequency 01 cpu and etpu frequency is doubled (max 200mhz). platform and peripheral clocks are 1/2 of cpu frequency 10 reserved 11 cpu, etpu, platform, and peripheral?s clocks all run at same speed (max 132mhz) note: refer to the pxr40 microcontroller data sheet for the latest frequency specifications.
system integration unit (siu) 7-70 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.28 halt register (siu_hlt) the siu_hlt register is used to di sable the clocks to various modules. each bit will driv e a separate stop output of the siu. these outputs wi ll be connected as shown in table 7-46 . note some peripherals have an mdis (modul e disable) bit in the module control register that can be set to disa ble the module clock, reducing power consumption. in most cases the periphe ral registers are still readable and writeable. however, using the siu_hlt re gister also disables the read/write functions on the disabled peripheral's registers for additional power saving. see section chapter 20, periodic in terrupt timer (pit_rti) , for more information on how to use the siu_hlt and siu_hltack registers. figure 7-26. halt register (siu_hlt) 24?26 reserved 27 bypass bypass bit. 0 system clock divider is not bypassed 1 system clock divider is bypassed 28?29 sysclkdiv system clock divider. the sysclkdi v bits select the divider value for the system clock. note that the sysclkdiv divider is required in addition to the rfd to allow the other source for the system clock (osc) to be divided down to slowest frequencies to improve power. the output of the clock divider is nominally a 50% duty cycle. 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 30?31 reserved address: siu_base + 0x9a4 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r hlt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hlt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-45. siu_sysdiv bit field descriptions field description
system integration unit (siu) freescale semiconductor 7-71 pxr40 microcontroller reference manual, rev. 1 7.3.1.29 halt acknowledge register (siu_hltack) the siu_hltack bits indicate that the module requested to halt via the hlt bit has completed the halt process and has entered a halted state with the modul e clocks disabled. the hl tack bits are read-only and writes have no effect, it is reset by the intern al reset condition. the input signals from each module will be connected as shown in table 7-47., halt acknowledge re gister field descriptions . table 7-46. siu_hlt regi ster field descriptions field description 0-31 hlt halt selects the hlt bits halt specific modules. each bit corresponds to a separate module as mapped below: 0 cpu and platform 1 1 rsvd 2 rsvd 3 rsvd 4 rsvd 5 etpu_a and etpu_b 6 npc 7 ebi 8 eqadcs: eqadc_a and eqadc_b 9 rsvd 10 emios_a 11 decfilts (decimation filters) 12 rsvd 13 pit 14 rsvd 15 rsvd 16flexcan_d 17 flexcan_c 18 flexcan_b 19 flexcan_a 20 dspi_d 21 dspi_c 22 dspi_b 23 dspi_a 24 rsvd 25 rsvd 26 rsvd 27 rsvd 28 rsvd 29 esci_c 30 esci_b 31 esci_a 1 stops all cpu clocks; stops the platform, exclud ing interrupt controller and watchdogs. note: these are only halted when the cpu execut es a wait instruction to request the halt.
system integration unit (siu) 7-72 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 7-27. halt acknowledge register (siu_hltack) address: siu_base + 0x9a8 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r hltack w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hltack w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-47. halt acknowledge register field descriptions field description 0-31 hltack halt acknowledge the hltack bits acknowledge halt for specific modules. each bit corresponds to a separate module as mapped below: 0 cpu and platform 1 1 rsvd 2 rsvd 3 rsvd 4 rsvd 5 etpu_a, etpu_b 6 npc 7 ebi 8 eqadcs: eqadc_a and eqadc_b 9 rsvd 10 emios_a 11 decfilts (decimation filters) 12 rsvd 13 pit 14 rsvd 15 rsvd 16 flexcan_d 17 flexcan_c 18flexcan_b 19 flexcan_a 20 dspi_d 21 dspi_c 22 dspi_b 23 dspi_a 24 rsvd 25 rsvd 26 rsvd 27 rsvd 28 rsvd 29 esci_c 30 esci_b 31 esci_a 1 stops all cpu clocks, stops the platform, e xcluding interrupt controller and watchdogs.
system integration unit (siu) freescale semiconductor 7-73 pxr40 microcontroller reference manual, rev. 1 7.3.1.30 parallel gpio pin data output register (siu_pgpdo0 - siu_pgpdo15) the pgpdo x registers are written to by so ftware to drive data out on the external gpio pin. these registers access the same gpio pins accessed by siu_gpdo0?siu_gpdo511 bit registers. the siu_gpdo registers should map directly to these registers. for example, siu_pgpdo0 bit 31 is siu_gp do31 bit 7, siu_pgpdo0 bit 30 is si u_gpdo30 bit 7,...., siu_ pgpd07 bit 0 is siu_gpdo224 bit 7. table 7-48 is a lookup table correlating the siu_gpdo x and siu_pgpdo n registers. the parallel gpio read/write should be deco de the logical addresses to the same physi cal address of the normal gpio. this way b oth gpdo and corresponding pgpdo registers will be upda ted by a single write to a either register. table 7-48. correlation between siu_gpdo x and siu_pgpdo n pgpdon pgpdo n bit number 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 0 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 1 3233343536373839404142434445464748495051525354555657585960616263 2 6465666768697071727374757677787980818283848586878889909192939495 3 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 4 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 5 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 6 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 7 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 8 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 9 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 10 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 11 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 12 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 13 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 14 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 15 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511
system integration unit (siu) 7-74 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 7-28. parallel gpio pin data output register (siu_pgpdo0 - siu_pgpdo15) 7.3.1.31 parallel gpio pin data input register (s iu_pgpdi0 - siu_pgpdi15) the gpdi x registers are read-only registers that allow read ing of the input state of an external gpio pin. these registers access the same gpio pins accessed by siu_gpdi0 - siu_gpdi511 bit registers. the siu_gpdi registers should map dir ectly to these registers. see section 7.3.1.30, parallel gpio pin data output register (siu_pgpdo0 - siu_pgpdo15) , for a lookup table and examples. the gpio read/write should decode logical addresses to the same physi cal address of the normal gpio. this way both the gpdi and corresponding pgpdi regist er should be updated on a pin state change when the ibe is asserted in the corresponding pcr. figure 7-29. parallel gpio pin data input register (siu_pgpdi0 - siu_pgpdi15) siu_base + 0xc00 - siu_base + 0xc3c (16) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r pgpdo 0 pgpdo 1 pgpdo 2 pgpdo 3 pgpdo 4 pgpdo 5 pgpdo 6 pgpdo 7 pgpdo 8 pgpdo 9 pgpdo 10 pgpdo 11 pgpdo 12 pgpdo 13 pgpdo 14 pgpdo 15 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pgpdo 16 pgpdo 17 pgpdo 18 pgpdo 19 pgpdo 20 pgpdo 21 pgpdo 22 pgpdo 23 pgpdo 24 pgpdo 25 pgpdo 26 pgpdo 27 pgpdo 28 pgpdo 29 pgpdo 30 pgpdo 31 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-49. siu_pgpdo0 - si u_pgpdo15 field descriptions field description 0?31 pgpdo x pin data out. stores the data to be driven out on t he external gpio pin controlled by this register. 0 logic low value is driven on the data out signal for th e corresponding gpio pin when the pin is configured as an output. 1 logic high value is driven on the data out signal for the corresponding gpio pin when the pin is configured as an output. siu_base + 0xc40 - siu_base + 0xc7c (16) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r pgpdi 0 pgpdi 1 pgpdi 2 pgpdi 3 pgpdi 4 pgpdi 5 pgpdi 6 pgpdi 7 pgpdi 8 pgpdi 9 pgpdi 10 pgpdi 11 pgpdi 12 pgpdi 13 pgpdi 14 pgpdi 15 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pgpdi 16 pgpdi 17 pgpdi 18 pgpdi 19 pgpdi 20 pgpdi 21 pgpdi 22 pgpdi 23 pgpdi 24 pgpdi 25 pgpdi 26 pgpdi 27 pgpdi 28 pgpdi 29 pgpdi 30 pgpdi 31 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
system integration unit (siu) freescale semiconductor 7-75 pxr40 microcontroller reference manual, rev. 1 7.3.1.32 masked parallel gp io pin data output re gister (siu_mpgpdo0 - siu_mpgpdo31) the mpgpdox registers are written to by software to drive data out on the external gpio pin (they are write-only registers and reading them will return 0; reading must be done by accessing the corresponding siu_gpdo register). these registers access the same gpio pins accessed by siu_gpdo0? siu_gpdo511 bit registers. the most significant 16 bits in the siu_mpgpdo registers should map directly to these registers. for example, si u_mpgpdo0 bit 31 is siu_gpdo15 bit 7, siu_mpgpdo0 bit 30 is siu_gpdo17 bit 7,...., siu_mpgpd15 bit 16 is siu_gpdo240 bit 7. the least significant sixteen bits are the corresponding valu es to be written at gpio pins defined by mask field. the masked parallel gpio read/write should be decode the logical addre sses to the same physical address of the normal gpio. figure 7-30. masked parallel gpio pin data output register (siu_mpgpdo0 - siu_mpgpdo31) table 7-50. siu_pgpdi0 - siu_pgpdi1 5 - siu_pgpdo15 field descriptions field description 0?31 pgpdi x pin data in. stores the value of the pad-interface signals (data in) corresponding to the external gpio pin associated with the register. 0 the value of the pad-interface signals (data in ) for the corresponding gpio pin is logic low. 1 the value of the pad-interface signals (data in ) for the corresponding gpio pin is logic high. siu_base + 0xc80 - siu_base + 0xcfc (32) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r w mask 0 mask 1 mask 2 mask 3 mask 4 mask 5 mask 6 mask 7 mask 8 mask 9 mask 10 mask 11 mask 12 mask 13 mask 14 mask 15 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 data 10 data 11 data 12 data 13 data 14 data 15 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-51. siu_mpgpdo0 - siu_mpgpdo31 field descriptions field description 0?15 mask x pin data out. controls the write access to the corresponding gpdo. 0 previous value defined by gpdo is maintain. 1 corresponding gpdo is written with value defined by data field. 16?31 datax pin data out. stores the data to be driven out on t he external gpio pin controlled by this register. 0 logic low value is driven on the pad interface data out signal for the corresponding gpio pin when the pin is configured as an output. 1 logic high value is driven on the pad interface data out signal for the corresponding gpio pin when the pin is configured as an output.
system integration unit (siu) 7-76 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.33 siu dspi serialization registers each bit in the dspi serialized out put frame can contain a signal routed from the output of one of three on-chip sources. the sources on th is device are the etpu module, em ios module, or a software-updated gpo data register. the mapping betw een module or data register and the output frame for a single dspi channel is performed by independent 32-bit registers, one fo r each module that is mapped plus one for the data register. an example of how th ese registers are used to create th e dspi serialized output is shown below.
system integration unit (siu) freescale semiconductor 7-77 pxr40 microcontroller reference manual, rev. 1 emios 0 1 2 3 4 15 30 31 example of pin multiplexing etpub 0 1 2 3 4 15 30 31 etpub select regist er (for dspi_a) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 chan# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 enable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 emios select register (for dspi_a) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 chan# 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 enable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 dspia output register frame bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 function & channel selection etpub channel 30 dspiah/l select register (for dspi_a) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 serial gpo a siu_dspial[mask17] siu_dspial[data17] enable
system integration unit (siu) 7-78 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.33.1 masked serial gpo registers for dspi (siu_dspi ah, siu_dspial, siu_dspibh, siu_dspibl, siu_d spich, siu_dspicl , siu_dspidh, siu_dspidl) these registers are written by softwa re to drive data out on the seri alization module described in the figure 7-35 , figure 7-38 , figure 7-41 , figure 7-45 . the purpose of these registers is to allow any combination of bits in each half of the 32 bit serializ ed data frame to be update d with a single 32-bit write operation, while allowing other bits to maintain their pr evious state. this is ac complished by writing a 16 bit masked value coherently with an update value contained in a 16 bit out put field, and only updating those bits in the output register for which the corresponding mask bit is set. table 7-52. siu address map for masked serial output and serial selection registers address use siu_base + 0x0d00 -siu_base + 0x0d03 d spia gp mask-output high register siu_base + 0x0d04 -siu_base + 0x0d07 dspia gp mask-output low register siu_base + 0x0d08 -siu_base + 0x0d0b dspib gp mask-output high register siu_base + 0x0d0c -siu_base + 0x0d0f dspib gp mask-output low register siu_base + 0x0d10 -siu_base + 0x0d13 ds pic gp mask-outp ut high register siu_base + 0x0d14 -siu_base + 0x0d17 d spic gp mask-output low register siu_base + 0x0d18 -siu_base + 0x0d1b dspid gp mask-output high register siu_base + 0x0d1c -siu_base + 0x0d1f d spid gp mask-output low register siu_base + 0x0d20 -siu_base + 0x0d3f reserved siu_base + 0x0d40 -siu_base + 0x0d 43 dspia etpub select register siu_base + 0x0d44 -siu_base + 0x0d 47 dspia emios select register siu_base + 0x0d48 -siu_base + 0x 0d4b dspia gpo select register siu_base + 0x0d4c -siu_base + 0x0d4f reserved siu_base + 0x0d50 -siu_base + 0x0d 53 dspib etpua select register siu_base + 0x0d54 -siu_base + 0x0d 57 dspib emios select register siu_base + 0x0d58 -siu_base + 0x 0d5b dspib gpo select register siu_base + 0x0d5c -siu_base + 0x0d5f reserved siu_base + 0x0d60 -siu_base + 0x0d 63 dspic etpua select register siu_base + 0x0d64 -siu_base + 0x0d67 dspic emios select register siu_base + 0x0d68 -siu_base + 0x 0d6b dspic gpo select register siu_base + 0x0d6c -siu_base + 0x0d6f reserved siu_base + 0x0d70 -siu_base + 0x0d 73 dspid etpub select register siu_base + 0x0d74 -siu_base + 0x0d77 dspid emios select register siu_base + 0x0d78 -siu_base + 0x 0d7b dspid gpo select register siu_base + 0x0d7c -siu_base + 0x0d7f reserved siu_base + 0x0d80 -siu_ base + 0x0dc0 reserved
system integration unit (siu) freescale semiconductor 7-79 pxr40 microcontroller reference manual, rev. 1 figure 7-31. masked serial gpo register for dspi - dspi_a/b/c/d gpo mask output high register (siu_dspiah/siu_dspibh/siu_dspich/siu_dspidh) figure 7-32. masked serial gpo register for dspi - dspi_a/b/c/d gpo mask output low register (siu_dspial/siu_dspibl/siu_dspicl/siu_dspidl) 7.3.1.33.2 serialized ou tput signal selectio n registers for dspi_a the following three registers are used by dspi_a to select the sources of the serialized output when running in dsi or csi configuration. each register bit enables a path from the etpu_b channel, emios channel and data register bit siu_dspiah/siu_dspial to the equi valent bit position in the dspi_a serialized output frame. the user must ensure that bit select ions from each of these registers do not overlap. multiple sources are siu_base + 0xd00, siu_base + 0xd08, siu_base + 0xd10, siu_base + 0xd18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r w mask 0 mask 1 mask 2 mask 3 mask 4 mask 5 mask 6 mask 7 mask 8 mask 9 mask 10 mask 11 mask 12 mask 13 mask 14 mask 15 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 data 10 data 11 data 12 data 13 data 14 data 15 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 siu_base + 0xd04, siu_base + 0xd0c, siu_base + 0xd14, siu_base + 0xd1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r w mask 16 mask 17 mask 18 mask 19 mask 20 mask 21 mask 22 mask 23 mask 24 mask 25 mask 26 mask 27 mask 28 mask 29 mask 30 mask 31 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data 16 data 17 data 18 data 19 data 20 data 21 data 22 data 23 data 24 data 25 data 26 data 27 data 28 data 29 data 30 data 31 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-53. siu_dspial/siu_dspibl/siu _dspicl/siu_dspidl field descriptions field description 0?15 mask x pin data out. controls the write a ccess to the corresponding gpo for dspi. these bits are write-only and read as 0. 0 previous value defined by gpdo is maintained. 1 corresponding gpo is written with value defined by data field. note: the mask bits have to be written at the same time (s ame access cycle) as the data bits, for the mask to work (the mask information is not stored). 16?31 data x pin data out. stores the data to be driven out on t he external gpio pin controlled by this register. 0 logic low value is driven on the pad interface data out signal for the corresponding gpo for dspi when this output is selected in the dspi serialization module. 1 logic high value is driven on the pad interface data out signal for the corresponding gpo for dspi when this output is selected in the dspi serialization module.
system integration unit (siu) 7-80 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 logically ored, which provides the potential for co mbining outputs from multiple timer channels and data registers to produce more complex bit behavior. figure 7-33. etpu_b select register for dspi_a (siu_etpuba) figure 7-34. emios select register for dspi_a (siu_emiosa) siu_base + 0xd40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r etpub 15 etpub 14 etpub 13 etpub 12 etpub 11 etpub 10 etpub 9 etpub 8 etpub 7 etpub 6 etpub 5 etpub 4 etpub 3 etpub 2 etpub 1 etpub 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpub 31 etpub 30 etpub 29 etpub 28 etpub 27 etpub 26 etpub 25 etpub 24 etpub 23 etpub 22 etpub 21 etpub 20 etpub 19 etpub 18 etpub 17 etpub 16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-54. siu_etpuba field descriptions field description 0?31 etpub x etpub channel select 0 this bit in the dspi_a serialized output frame will not use the respective etpub channel 1 this bit in the dspi_a serialized output frame will use the respective etpub channel siu_base + 0xd44 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r emios 7 emios 6 emios 5 emios 4 emios 3 emios 2 emios 1 emios 0 emios 8 emios 9 emios 10 emios 11 emios 12 emios 13 emios 14 emios 15 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r emios 16 emios 17 emios 18 emios 19 emios 20 emios 21 emios 22 emios 23 emios 0 emios 1 emios 2 emios 3 emios 4 emios 5 emios 6 emios 7 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-55. siu_emiosa field descriptions field description 0?31 emios x emios channel select 0 this bit in the dspi_a serialized output fr ame will not use the respective emios channel 1 this bit in the dspi_a serialized output frame will use the respective emios channel
system integration unit (siu) freescale semiconductor 7-81 pxr40 microcontroller reference manual, rev. 1 figure 7-35. siu_dspiah/l select re gister for dspi_a (siu_dspiahla) 7.3.1.33.3 serialized ou tput signal selectio n registers for dspi_b the following three registers are used by dspi_b to select the sources of the serialized output when running in dsi or csi configuration. each register bit enables a path from the etpu_a channel, emios channel and data register bit siu_dspibh/siu_dspibl to the equiva lent bit position in the dspi_b se rialized output fr ame. the user must ensure that bit selections fr om each of these registers do not overl ap. multiple sources are logically ored, which provides the potential fo r combining outputs from multiple timer channels and data registers to produce more complex bit behavior. figure 7-36. etpu_a select register for dspi_b (siu_etpuab) siu_base + 0xd48 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dspi ah 0 dspi ah 1 dspi ah 2 dspi ah 3 dspi ah 4 dspi ah 5 dspi ah 6 dspi ah 7 dspi ah 8 dspi ah 9 dspi ah 10 dspi ah 11 dspi ah 12 dspi ah 13 dspi ah 14 dspi ah 15 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dspi al 16 dspi al 17 dspi al 18 dspi al 19 dspi al 20 dspi al 21 dspi al 22 dspi al 23 dspi al 24 dspi al 25 dspi al 26 dspi al 27 dspi al 28 dspi al 29 dspi al 30 dspi al 31 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-56. siu_dspiahla field descriptions field description 0?31 dspiah/l x dspi_a data register bit 0 the corresponding serial gpo a output (from the siu_dspiah/l register) is disabled 1 the corresponding serial gpo a output (fro m the siu_dspiah/l register) is enabled siu_base + 0xd50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r etpua 23 etpua 22 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 29 etpua 28 etpua 27 etpua 26 etpua 25 etpua 24 etpua 31 etpua 30 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpua 12 etpua 13 etpua 14 etpua 15 etpua 0 etpua 1 etpua 2 etpua 3 etpua 4 etpua 5 etpua 6 etpua 7 etpua 8 etpua 9 etpua 10 etpua 11 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-57. siu_etpuab field descriptions field description 0?31 etpua x etpua channel select 0 this bit in the dspi_b serialized output frame will not use the respective etpua channel 1 this bit in the dspi_b serialized output frame will use the respective etpua channel
system integration unit (siu) 7-82 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 7-37. emios select register for dspi_b (siu_emiosb) figure 7-38. siu_dspibh/l select re gister for dspi_b (siu_dspibhlb) 7.3.1.33.4 serialized ou tput signal selectio n registers for dspi_c the following three registers are used by dspi_c to select the sources of the serialized output when running in dsi or csi configuration. each register bit enables a path from the etpu_a channel, emios channel and data register bit siu_dspich/siu_dspicl to the equiva lent bit position in the dspi_c se rialized output fr ame. the user must ensure that bit selections fr om each of these registers do not overl ap. multiple sources are logically ored, which provides the potential fo r combining outputs from multiple timer channels and data registers to produce more complex bit behavior. siu_base + 0xd54 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r emios 11 emios 10 emios 9 emios 8 emios 6 emios 5 emios 4 emios 3 emios 2 emios 1 emios 0 emios 23 emios 15 emios 14 emios 13 emios 12 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r emios 23 emios 15 emios 14 emios 13 emios 12 emios 11 emios 10 emios 9 emios 8 emios 6 emios 5 emios 4 emios 3 emios 2 emios 1 emios 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-58. siu_emiosb field descriptions field description 0?31 emios x emios channel select 0 this bit in the dspi_b serialized output fr ame will not use the respective emios channel 1 this bit in the dspi_b serialized output frame will use the respective emios channel siu_base + 0xd58 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dspi bh 0 dspi bh 1 dspi bh 2 dspi bh 3 dspi bh 4 dspi bh 5 dspi bh 6 dspi bh 7 dspi bh 8 dspi bh 9 dspi bh 10 dspi bh 11 dspi bh 12 dspi bh 13 dspi bh 14 dspi bh 15 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dspi bl 16 dspi bl 17 dspi bl 18 dspi bl 19 dspi bl 20 dspi bl 21 dspi bl 22 dspi bl 23 dspi bl 24 dspi bl 25 dspi bl 26 dspi bl 27 dspi bl 28 dspi bl 29 dspi bl 30 dspi bl 31 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-59. siu_dspibhlb field descriptions field description 0?31 dspibh/l x dspi_b data register bit 0 the corresponding serial gpo b output (from the siu_dspibh/l register) is disabled 1 the corresponding serial gpo b output (fro m the siu_dspibh/l register) is enabled
system integration unit (siu) freescale semiconductor 7-83 pxr40 microcontroller reference manual, rev. 1 figure 7-39. etpu_a select register for dspi_c (siu_etpuac) figure 7-40. emios select register for dspi_c (siu_emiosc) siu_base + 0xd60 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r etpua 12 etpua 13 etpua 14 etpua 15 etpua 0 etpua 1 etpua 2 etpua 3 etpua 4 etpua 5 etpua 6 etpua 7 etpua 8 etpua 9 etpua 10 etpua 11 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpua 23 etpua 22 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 29 etpua 28 etpua 27 etpua 26 etpua 25 etpua 24 etpua 31 etpua 30 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-60. siu_etpuac field descriptions field description 0?31 etpua x etpua channel select 0 this bit in the dspi_c serialized output frame will not use the respective etpua channel 1 this bit in the dspi_c serialized output frame will use the respective etpua channel siu_base + 0xd64 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r emios 12 emios 13 emios 14 emios 15 emios 23 emios 0 emios 1 emios 2 emios 3 emios 4 emios 5 emios 6 emios 8 emios 9 emios 10 emios 11 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r emios 23 emios 22 emios 21 emios 20 emios 19 emios 18 emios 17 emios 16 emios 29 emios 28 emios 27 emios 26 emios 25 emios 24 emios 31 emios 30 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-61. siu_emiosc field descriptions field description 0?31 emios x emios channel select 0 this bit in the dspi_c serialized output frame will not use the respective emios channel 1 this bit in the dspi_c serialized output frame will use the respective emios channel
system integration unit (siu) 7-84 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 7-41. siu_dspich/l select re gister for dspi_c (siu_dspichlc) figure 7-42. etpu_b select register for dspi_c (siu_etpubc) 7.3.1.34 serialized output signal selection registers for dspi_d the following registers are used by dspi_d to select the sources of the serialized output when running in dsi or csi configuration. the register bit enables a path from the etpu_b cha nnel or emios channel to the equivalent bit position in the dspi_d serialized output frame. the user must ensure that bit sel ections from each of these registers do not overlap. multiple sources are logically ored, which provides the potential for combining outputs from multiple timer channels and data regi sters to produce more complex bit behavior. siu_base + 0xd68 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dspi ch 0 dspi ch 1 dspi ch 2 dspi ch 3 dspi ch 4 dspi ch 5 dspi ch 6 dspi ch 7 dspi ch 8 dspi ch 9 dspi ch 10 dspi ch 11 dspi ch 12 dspi ch 13 dspi ch 14 dspi ch 15 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dspi cl 16 dspi cl 17 dspi cl 18 dspi cl 19 dspi cl 20 dspi cl 21 dspi cl 22 dspi cl 23 dspi cl 24 dspi cl 25 dspi cl 26 dspi cl 27 dspi cl 28 dspi cl 29 dspi cl 30 dspi cl 31 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-62. siu_dspichlc field descriptions field description 0?31 dspich/l x dspi_c data register bit 0 the corresponding serial gpo c output (fro m the siu_dspich/l register) is disabled 1 the corresponding serial gpo c output (fro m the siu_dspich/l register) is enabled siu_base + 0xd6c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r etpub 12 etpub 13 etpub 14 etpub 15 etpub 0 etpub 1 etpub 2 etpub 3 etpub 4 etpub 5 etpub 6 etpub 7 etpub 8 etpub 9 etpub 10 etpub 11 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpub 23 etpub 22 etpub 21 etpub 20 etpub 19 etpub 18 etpub 17 etpub 16 etpub 29 etpub 28 etpub 27 etpub 26 etpub 25 etpub 24 etpub 31 etpub 30 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-63. siu_etpuac field descriptions field description 0?31 etpua x etpua channel select 0 this bit in the dspi_c serialized output frame will not use the respective etpua channel 1 this bit in the dspi_c serialized output frame will use the respective etpua channel
system integration unit (siu) freescale semiconductor 7-85 pxr40 microcontroller reference manual, rev. 1 figure 7-43. etpu_b select register for dspi_d (siu_etpubd) figure 7-44. emios select register for dspi_d (siu_emiosd) figure 7-45. dspidh/l select regi ster for dspi_d (siu_dspidhld) siu_base + 0xd70 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r etpub 21 etpub 20 etpub 19 etpub 18 etpub 17 etpub 16 0 0 0 0 etpub 29 etpub 28 etpub 27 etpub 26 etpub 25 etpub 24 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-64. siu_etpuad field descriptions field description 0?31 etpub x etpub channel select 0 this bit in the dspi_d serialized output frame will not use the respective etpub channel 1 this bit in the dspi_d serialized output frame will use the respective etpub channel siu_base + 0xd74 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 emios 11 emios 10 emios 13 emios 12 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7-65. siu_emiosd field descriptions field description 0?31 emios x emios channel select 0 this bit in the dspi_d serialized output frame will not use the respective emios channel 1 this bit in the dspi_d serialized output frame will use the respective emios channel siu_base + 0xd78 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
system integration unit (siu) 7-86 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.3.1.35 gpio pin data input register s (siu_gpdi0_3 - siu_gpdi508_511) - standard previous devices are limited to s upporting a maximum of 256 ge neral purpose input registers, and thus a maximum gpio input assignm ent of gpio[0:255]. the re ason is that only 256 bytes of siu address space is allocated for the gpio pin da ta input registers, and adjacent memory locations are unavailable. to accommodate the extended number of the gpio pads, this device has a new memo ry map definition of 512 bytes for allocating up to 512 gpio pin data input registers. for compatibility, the first used 256 gpio pin data input registers ar e mapped to both the old and new locations. the memory map is shown in table 7-66 . the gpdi x _ x registers are read-only registers that allow reading of the in put state of an ex ternal gpio pin. each byte of a register represents the input state of a single external gpio pin. the first 256 gpdix_x registers corresponds to the sa me gpdi inputs described in section 7.3.1.15, gpio pin data input registers 0?255 (siu_gpdin) . figure 7-46. gpio pin data in register 0 (siu_gpdi0) table 7-66. gpio pin data input registers memory map address offset from siu_base number 0x0e00 - 0x0e4a reserved 0x0e4b - 0x0e6e gpio pin data input registers 75 - 110 0x0e6f - 0x0e70 reserved 0x0e71 - 0x0ecc gpio pin data input registers 113- 204 0x0ecd - 0x0ecf reserved 0x0ed0 - 0x0ed1 gpio pin data input registers 208- 209 reserved 0x0ed3 gpio pin data input registers 211 reserved 0x0ed5 gpio pin data input registers 213 reserved 0x0ee7 - 0x0efd gpio pin data input registers 231 - 253 reserved 0x0f00 - 0x0f33 gpio pin data input registers 256 - 307 reserved 0x0fb0 - 0x0fb5 gpio pin data input registers 432 - 437 reserved 0x0fb8 - 0x0fd8 gpio pin data input registers 440 - 472 reserved siu_base+0x0e00 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 pdi0 w reset: 0 0 0 0 0 0 0 u
system integration unit (siu) freescale semiconductor 7-87 pxr40 microcontroller reference manual, rev. 1 figure 7-47. gpio pin data in register 511 (siu_gpdi511) 7.4 functional description the following sections provide a func tional overview of the siu operation. 7.4.1 pad configuration the pad configuration registers (siu _pcr) in the siu allow software co ntrol over the following electrical characteristics of the external pads: ? weak pullup/down enable/disable ? weak pullup/down selection ? slew-rate sele ction for outputs ? drive strength selection for outputs ? input buffer enable (when direct ion is configured for output) ? input hysteresis enable/disable ? open drain/push-pull output selection ? multiplexed function selection ? data direction selection the pad configuration register s are provided to allow centralized cont rol over external pins that are shared by more than one module. each pad confi guration register controls a single pin. siu_base+0xffc 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 pdi511 w reset: 0 0 0 0 0 0 0 u table 7-67. siu_emiosd field descriptions field description 0?31 pdi x this bit reflects the input state on the external gpio pin for the register. if pcr n [ibe] = 1, then: 0 signal on pin is a logic 0 1 signal on pin is a logic 1
system integration unit (siu) 7-88 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.4.2 reset control the reset controller logic is located in the siu. refer to section 7.2.1.1, reset input (reset) , and section 7.2.1.2, reset output (rstout) , for details on the reset operations. 7.4.2.1 reset boot configuration the bootcfg[0:1] pins are latched cfg_samp le_clks prior to the negation of the rstout pin, except in the case of a software external reset. the values latched are placed in the bootcfg field of the reset status register. refer to section 4.7.1.1, rchw overview , for details on the rchw. 7.4.2.2 reset pin glitch detect the reset controller provides a gl itch detect feature on the reset pin. if the reset controller detects that the reset pin is asserted for more than tw o clock cycles, the event is latche d. after the latch is set, if the reset pin is negated before 10 clock cycles is reac hed, the reset controller sets the rgf bit without affecting any of the other bits in the reset status re gister (siu_rsr). the latch is cleared when the rgf bit is set or a valid reset is rec ognized. the rgf bit remains set until cleared by a software or the reset signal asserts for 10 clock cycles. the reset controll er does not respond to as sertions of the reset pin if a reset cycle is already being processed. 7.4.3 external interrupts there are 16 external interrupt inputs irq [0]?irq [15] to the siu. the irq in puts can be configured for rising-edge events, falling-edge events, or both. external interrupt requests are trigge red by rising- and/or fal ling-edge events that are enabled by setting a bit in: ? irq rising-edge event enab le register (siu_ireer) ? irq falling-edge event en able register (siu_ifeer) if the bit is set in both registers, both rising- and falling-e dge events trigger an in terrupt request. each irq has a counter that tracks the number of system clock cycles that occur be tween the rising- and falling-edge events. an irq counter exists for each irq rising- or falling-edge event enable bit. the digital filter length field in th e irq digital filter re gister (siu_idfr) speci fies the minimum number of system clocks that the irq signa l must hold a logic value to qualify the edge-triggered event as a valid state change. when the number of syst em clocks in the irq counter equals the value in the digital filter length field, the irq state latches and the irq counter is cleared. if the previous filtered state of the irq does not matc h the current state, and th e rising- or falling-edge event is enabled, the irq flag bit is set to 1. for exam ple, the irq flag bit is set if a rising-edge event occurs under the following conditions: ? previous filtered irq state was a logic 0 ? current latched irq state is a logic 1 ? rising-edge event is enabled for the irq
system integration unit (siu) freescale semiconductor 7-89 pxr40 microcontroller reference manual, rev. 1 when the counter for an irq is not enabled, the state of the irq is held in the current and previous state latches. the irq counter ope rates independently of the irq or overrun flag bit. clearing the irq flag or overrun flag bits does not cl ear or reload the counter. refer to the following sections for more information: ? section 7.3.1.4, external interrupt status register (siu_eisr) ? section 7.3.1.9, irq rising-edge event enable register (siu_ireer) ? section 7.3.1.10, irq falling-edge even t enable register (siu_ifeer) ? section 7.3.1.11, irq digital filter register (siu_idfr) 7.4.3.0.1 external interrupts the irq signals map to 16 independent interrupt reque sts output from the siu. the irq flag bit is set when a rising-edge and/or falling-e dge event occurs for the irq. an ex ternal irq signal is asserted when all of the following occur: ? enable bit is set in the irq rising- and/or fa lling-edge event register s (siu_ireer, siu_ifeer) ? irq flag bit is set in the external interrupt status register (siu_eisr) ? enable bit is cleared in the dma/interr upt request enable re gister (siu_direr) ? select bit is cleared in the dma/in terrupt select regi ster (siu_dirsr) the nmi pin function or platform swt can generate either an nmi or a critical interrupt. when wkpcfg_nmi_gpio213 is en abled as nmi, the pin w ill override the pcr configuration after reset. siu_direr selects between critical and non maskable interrupt use, siu_ eisr reports status of nmi and siu_ifeer selects edge sensitivity of nmi input refer to the following sections for more information: ? section 7.3.1.5, dma/interrupt request enable register (siu_direr) ? section 7.3.1.6, dma/interrupt request select register (siu_dirsr) 7.4.3.0.2 dma transfers dma irq signals (irq [0] through irq [3]) map to four inde pendent dma transfer or interrupt request outputs configured in the siu. a dma transfer or interrupt request asserts when al l of the following occur: ? irq flag bit is set in the external interrupt status register (siu_eisr) ? enable bit is set in the dma transfer or in terrupt request enable register (siu_direr) ? select bit is set in the dma transfer or in terrupt request select register (siu_dirsr) the siu receives a ?dma transf er done? signal for each dma or interrupt request transmitted. when the ?dma done? signal asserts, the irq flag bit is cleared. refer to the following sections for more information: ? section 7.3.1.5, dma/interrupt request enable register (siu_direr) ? section 7.3.1.6, dma/interrupt request select register (siu_dirsr)
system integration unit (siu) 7-90 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 7.4.3.0.3 overruns an overrun irq exists for each overrun flag bit in the overrun status register (siu_osr). an overrun irq asserts when all of the following occur: ? enable bit is set in the irq rising- and/or fa lling-edge event register s (siu_ireer, siu_ifeer) ? irq flag bit is set in the external interrupt status register (siu_eisr) ? bit is set in the overrun request enable a nd overrun status register s (siu_orer, siu_osr) ? rising- or falling-edge even t triggers an interrupt request the siu outputs one overrun irq bit that is the logical or of all of the irq overrun bits. refer to the following sections for more information: ? section 7.3.1.4, external interrupt status register (siu_eisr) ? section 7.3.1.7, overrun status register (siu_osr) ? section 7.3.1.8, overrun request en able register (siu_orer) 7.4.3.0.4 edge-detect events an irq asserts when an: ? edge-detect event is enabled ? edge-detect event occurs to assert an irq when an edge-detect event occurs: 1. set the enable bit in the irq rising- and falling-edge event enable registers (siu_ireer, siu_ifeer) 2. clear the enable bits for the dma/interr upt request enable register (siu_direr) the irq bit is set in the external irq status regist er (siu_eisr) when an edge-detect event occurs for that irq. refer to the following sections for more information: ? section 7.3.1.4, external interrupt status register (siu_eisr) ? section 7.3.1.9, irq rising-edge event enable register (siu_ireer) ? section 7.3.1.10, irq falling-edge even t enable register (siu_ifeer)
system integration unit (siu) freescale semiconductor 7-91 pxr40 microcontroller reference manual, rev. 1 figure 7-48. siu dma/inte rrupt request diagram 7.4.4 gpio operation all gpio functions for the device ar e provided by the siu. each device pad that has a gpio signal has a pin configuration register (pcr) in the siu where the gpio function is selected. in addition, each device gpio signal has an input data register (siu_gpdi n ) and an output data register (siu_gpdo n ). the siu also implements several pa rallel gpio registers (siu_pgpdo x_x and siu_pgpdi x_x ) that can be used to access up to 32 gpio bits in a single- and word-sized accesses. the values read/written to these parallel registers are c oherent with the data read/written to the siu_gpdo x _ x and siu_gpdi x_x registers . 7.4.5 internal multiplexing the internal multiplexing select registers (siu_isel4-7, siu_eiisr, and siu_di sr) select the input source for the following components: ? eqadc command fifo trigger sources. ? siu external interrupt request signals ? dspi signals used for chaining se rial and parallel dspi modules a block diagram of the internal multiplexing feature is shown in figure 7-49 . the figure shows the multiplexing of four external signals to an siu output. interrupt controller dma/ interrupt select ? ? ? ? ? 0 1 2 3 4 15 imux interrupt request dma request dma ? ? ? 0 1 15 siu_osr siu_eisr overrun request eirq pins or internal source ? ? ? ? ? ? ? ? ? ? ? ? ? ? interrupt request siu_disr siu
system integration unit (siu) 7-92 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 7-49. four-to-one internal multiplexing block diagram 7.4.5.1 eqadc external trigger input multiplexing the eqadc external trigge r inputs can connect to one of the following pins: ? external pin ? etpu channel ? emios channel ? periodic interrupt timer the input source for each eqadc external trigger is configured in the eqadc command fifo trigger source select - imux select regist ers (siu_isel4-7). for example, you can select one of the following signals to source the etrig[0 ] input trigger for the eqadc: ? txdc_etrig[0]_gpio[244] pin ? etpua[30] output channel ? emios[10] output channel ? extended trigger s ource selection (see table 7-27 ) all etrig inputs are multiplexed in the same manner. if an etpu or emios channel is selected as an etrig input to the eqadc, you can activate the alternate function of that etpu or emios signal on the external pin. to chip-level signal external to the siu from chip-level signals external to the siu siu siu_isel4-7, siu_e iisr, and siu_disr
system integration unit (siu) freescale semiconductor 7-93 pxr40 microcontroller reference manual, rev. 1 an example of the multiplexing of an eqadc (e qadc_a) external trigger input is given below. figure 7-50. eqadc external trigger input multiplexing siu_isel4-7 always provides one of four choices based on the most-si gnificant two bits of each ctsel field. when those bits are 0b00, the extended trigger selection is chosen and the remaining bits in ctsel select among a longer list of trigger sources. 7.4.5.2 siu external interrupt input multiplexing the sixteen siu external interrupt inputs can be connect ed to either an external pin or to output signals from a dspi module. the input sour ce for each siu external interrupt is individually specified in the external irq input select register (siu_eiisr). as shown in the following figure, the irq [0] input of the siu can be connected to either the irq [0]_gpio[450] pin, the pcsb[0] input signal, the pcsc[1] deserialized output si gnal, or the pcsd[2] deserialized output signal. the rema ining irq inputs are multiplexed in the same manner. the inputs to the irq from each dspi module are offset by one so th at if more than one dspi module is connected to the same external device type, a sepa rate interrupt can be generated for each device. this also applies to dspi modules connected to external de vices of a different type that have status bits in the same bit location of the deserialized information. an example of the multiplexing of an si u external interrupt input is given in figure 7-51 . figure 7-51. dspi serialized input multiplexing 7.4.5.3 multiplexed inputs for dspi multiple transfer operation each dspi module can be combined in a serial or parallel chain (multiple tr ansfer operation). serial chaining allows spi operation with an external de vice that has more bits than one dspi module. siu_isel5[ctsel0_0[0:1]] etrig[0] extended trigger selection txdc_etrig[0]_gpio[244] etpua[30] output channel emios[10] output channel siu_isel5[ctsel0_0[2:6]] irq [0] irq [0]_gpio[450] dspi b[0] serialized input dspi c[1] serialized input dspi d[2] serialized input esel[0] esel[1]
system integration unit (siu) 7-94 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 in a serial chain, one dspi module ope rates as a master, the second, third, or fourth dspi modules operates as aslaves.the slave dspi and extern al spi device use the master peri pheral chip select (pcs) and clock (sck). the trigger input of the master allows a slave dspi to trigger a transf er when a data change occurs in the slave dspi and the slave dspi is operating in change in data mo de. the trigger input of the master is connected to the mtrig output of the slave. if mo re than two dspis are chaine d in change in data mode, a chain must be connected of mtrig outputs to trigger i nputs through the slaves with the last slave mtrig output connected to the master trigger input. an example of a serial chain is shown in figure 7-52 . parallel chaining allows the pcs and sck from one dspi to be used by mo re than one exte rnal spi device, thus reducing pin utilization of the device mcu. in this example, the sout and sin of the two dspis connect to separate exte rnal spi devices, which share a common pcs and sck. to support multiple transfer operatio n of the dspis, an input multip lexor is required for the sin, ss , sck in, and trigger signals of each ds pi. the input source for the sin inpu t of a dspi can be a pin or the sout of any of the other three ds pis. the input source for the ss input of a dspi can be a pin or the pcs x [0] of any of the other th ree dspis. the input source for the sck input of a ds pi can be a pin or the sck output of any of the other th ree dspis. the input source for the trigger input can be the pcss output of any of the other three dspis. th e input source for each dspi sin, ss , sck, and trigger signal is individually specified in the dspi input select register (siu_disr). an example of a parall el chain is shown in figure 7-53 . figure 7-52. dspi serial chaining sout sout sin sin pcs[0] ss sck sck in ss sck in sin sout external spi device mtrig tr i g g e r soutb scka pcsa[0] sina dspi b (master) dspi c (slave)
system integration unit (siu) freescale semiconductor 7-95 pxr40 microcontroller reference manual, rev. 1 figure 7-53. dspi parallel chaining sout sout sin sin pcs[0] ss sck sck in ss sck in sin sout external spi device sin sck in ss sout external spi device mtrig trigger dspi a (master) dspi b (slave)
system integration unit (siu) 7-96 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 8-1 chapter 8 system information module 8.1 sim overview the system information module (sim) contains the calibration constants for the on-chip temperature sensor and a 128-bit device id consta nt that is unique to every chip. all values are read-only, and may not be changed by software. two 32-bit locations are reserved for temperature sensor calibration consta nts. a descripti on of their usage is provided in the temperature sensor chapter. the unique device id is encoded and stored in four adjacent memory locations. ther e is no specific user information provided in the device id. table 8-1 shows the organization of the constants. 8.1.1 sim constants table 8-1. sim constants offset from 0xfffe_c000 0:15 16:31 0x00 temperature sensor calibration constant 0x04 temperature sensor calibration constant 0x08 reserved 0x0c 0x10 unique device id 0x14 unique device id 0x18 unique device id 0x1c unique device id 0x20 reserved 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c
system information module pxr40 microcontroller reference manual, rev. 1 8-2 freescale semiconductor
freescale semiconductor 9-1 pxr40 microcontroller reference manual, rev. 1 chapter 9 boot assist module (bam) 9.1 overview the boot assist module (bam) is a 4-kb block of read-only memory , containing the boot program code for the mcu. the bam program sup ports the following boot modes: ? boot from internal flash ? serial boot via sci or can interface with optional baud-rate detection ? boot from a memory connected to the mcu development bus (ebi 1 ) with multiplexed or separate address and data lines the bam program is executed by the mcu core just after the mcu resets. depending on the boot mode, the program initializes the appropriate minimum mcu resources to start user application code. 9.2 features ? initial mcu core mmu setup with minimum addr ess translation for all internal mcu resources ? mmu configuration to boot user application, compiled as clas sic powerpc book e code or as freescale vle code ? passes control to user appli cation code in the internal flash or external memory device ? automatic switch to serial b oot mode if internal or extern al flash is blank or invalid ? serial boot by loading user program via can bus or esci to the internal sram ? user programmable 64 bit password protection ? optional automatic detection of the host sci or can speed ? boot from an external memory device, connected to the ebi 1 ? option to boot from 16 bit memory device with separa te data and address lines ? option to boot from 32/16 bi t memory device with multiple xed data and address lines ? controls mcu core watchd og timer and/or the software watchdog timer (swt) 9.3 modes of operation 9.3.1 normal mode the bam program is executed immediat ely following the negation of reset . 1. ebi not available on all packages.
boot assist module (bam) 9-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 9.3.2 debug mode the bam program is not executed when the mcu exit s reset in once debug mode . before accessing the mcu resources, use the developmen t tool to initialize the mcu. 9.3.3 internal boot mode use this operating mode to boot from internal flash memory, which holds all of the code and configuration data. 9.3.4 serial boot mode use this mode to load a user program into internal sram, using the esci or can serial interface, then to execute that program. the program can then control ? the download of data, and ? erasing and programming of the inte rnal or external flash memory. 9.3.5 development bus boot mode this boot mode is intended for pack aged versions of the device that have the development bus pinned out. the development bus (ebi) boot mode can be used for application code development. 9.4 memory map the bam occupies 16 kb of memo ry space, 0xffff_c000 to 0xffff_ffff. the actual code size of the bam program is less than 4 kb and starts at 0x ffff_f000, repeating itself every 4 kb in the bam address space. the cpu starts the bam program execu tion at its reset vector from address 0xffff_fffc. the bam exits to the user code at 0xffff_fff8. the last instruction the bam executes is a blr. the link register is pre-loaded with the user application start address. the value of the start address depends on the boot mode: ? booting from internal or extern al flash ? 32-bit word followi ng a valid rchw holds the start address value ? serial boot ? set according to the serial boot protocol table 9-1 shows the bam address map. table 9-1. bam memory map address description 0xffff_c000 ? 0xffff_efff bam program mirrored 0xffff_f000 ? 0xffff_ffff bam program 0xffff_fffc mcu reset vector 0xffff_fff8 bam last executed instruction
boot assist module (bam) freescale semiconductor 9-3 pxr40 microcontroller reference manual, rev. 1 9.5 functional description 9.5.1 bam program flow chart figure 9-1 shows the bam program flow. figure 9-1. bam program flow chart reset config. mmu for internal boot bootcfg y n search for rchw found rchw? y n setup ebi and development bus pins for separate check rchw found rchw? y n serial boot exit to user code = 00 bootcfg = 01 n y bootcfg = 10 n y address and 16 bit data operation setup ebi and development bus pins for multiplexed address and 16 bit data operation configure mmu for ebi boot parse rchw and execute rchw options
boot assist module (bam) 9-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 9.5.2 bam program operation after negation of reset , the mcu core accesses the bam before user code starts. first, the bam program configures the core mmu to allow access to all mcu internal resources, according to table 9-2 . this mmu setup remains untouched th rough internal flash boot mode. the mmu regions are mapped with logical addresses the same as physical addresses except for the external bus interface (ebi). the l ogical ebi address space is mapped to physical address space of the internal flash memory. this allows code, written to run from external memory, to execute from internal flash. after the mmu configuration, the bam program starts the boot sequence depending on the siu_rsr[bootcfg] value, as shown in table 9-3 . depending on the values stored in the censorship word and serial boot control word in the shadow row of the internal flash memory, the internal flash memory can be enabled or disabled, the nexus port can be enabled or disabled, the password received in the se rial boot mode is compared with the fixed public password or compared to a user programmabl e password in the internal flash memory. table 9-2. mmu configuration for internal flash boot tlb entry region logical base address physical base address size attributes 0 peripheral bridge b and bam 0xfff0_0000 0xfff0_0000 1 mb guarded big endian global pid cache inhibit 1 internal flash 0x0000_0000 0x0000_0000 16 mb not guarded big endian global pid 2 ebi 0x2000_0000 0x0000_0000 16 mb not guarded big endian global pid 3 internal sram 0x4000_0000 0x4000_0000 256 kb not guarded big endian global pid cache inhibit 4 peripheral bridge a 0xc3f0_0000 0xc3f0_0000 1 mb guarded big endian global pid cache inhibit
boot assist module (bam) freescale semiconductor 9-5 pxr40 microcontroller reference manual, rev. 1 the censorship word is a 32 bit word of data stored in the shadow row of internal flash memory. this memory location is read by hardware as part of th e boot process and is used in conjunction with the bootcfg pins to enable and disable the internal flash memory and the nexus interface. the censorship word consists of two fields: cens orship control and serial boot co ntrol. the censorship word is programmed during manufactur ing to be 0x55aa_55aa. this results in a device that is not censored and uses a flash-based passwo rd for serial boot mode. table 9-3. boot modes boot mode name bootcfg[1:0] censorship control 0x00ff_fde0 serial boot control 0x00ff_fde2 internal flash state nexus state serial password internal - censored 00 any value except 0x55aa don't care enabled disabled flash internal - public 0x55aa enabled enabled public serial - flash password 01 don't care 0x55aa enabled disabled flash serial - public password any value except 0x55aa disabled enabled public development bus separate address and data, flash is censored 10 0x55aa don't care enabled enabled public development bus separate address and data, flash is not censored any value except 0x55aa disabled development bus multiplexed address and data, flash is censored 11 0x55aa don't care enabled enabled development bus multiplexed address and data, flash is not censored any value except 0x55aa disabled address: 0x00ff_fde0 value: 0x55aa 0123456789101112131415 binary value0101010110101010 hex value 5 5 a a censorship control field?default value configures the device as uncensored. address: 0x00ff_fde2 value: 0x55aa 0123456789101112131415 binary value0101010110101010 hex value 5 5 a a serial boot control field?default value reads a password from internal flash. figure 9-2. censorship word
boot assist module (bam) 9-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the bam program uses siu_ccr[disnex], which reflec ts the nexus module state, to determine if the serial password received in serial boot mode should be compared to: ? public password (0xfeed_face_caf e_beef) if disnex is cleared ? flash password (64-bit value, stored in th e shadow block of internal flash at address 0x00ff_fdd8) if disnex is set note regardless of the boot mode used, pr ogram a valid serial password. this allows you to rescue the device using se rial boot mode if the flash content is corrupted. figure 9-3. serial boot flash password 9.5.3 reset configuration half word (rchw) the reset configuration half word defines boot options and must be pr ogrammed to predefined locations in the internal flash or at the be ginning of the external flash device. the 32 bit word after the rchw must be programmed with the user appl ication?s starting address. the bam passes control to the user application at this starting address. table 9-6 provides possible rchw locations in the intern al flash. when booting from the external flash device, the rchw must reside in the first 16 bit half word of the flash. flash password@ 0x00ff_fdd8 ? 0x00ff_fddf 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 11111110 1 1 1 0 1 1 0 1 serial boot password (0x00ff_fdd8) - 0xfeed (factory default) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 11111010 1 1 0 0 1 1 1 0 serial boot password (0x00ff_fdda) - 0xface (factory default) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 11001010 1 1 1 1 1 1 1 0 serial boot password (0x00ff_fddc) - 0xcafe (factory default) 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 10111110 1 1 1 0 1 1 1 1 serial boot password (0x00ff_ fdde) - 0xbeef (factory default) boot_block_address 0123456789101112131415 swtwteps0vle01011010 boot identifier = 0x5a figure 9-4. reset configuration half word
boot assist module (bam) freescale semiconductor 9-7 pxr40 microcontroller reference manual, rev. 1 when enabled by rchw[swt, wte] bits, the watchdog timeout pe riods are as shown in the table 9-5 . note the following: ? the core wd timeout for 20 and 40 mhz crystal is the same because the pllcfg[2] pin should be set for 40 mhz crystal, which has the effect of doubling the pll input divider. ? the swt clock source is direct ly from the crystal oscillator. th e core wd is clocked by the pll. ? the core wd timeouts reported here correspond to the pll settings after reset. core wd timeouts will change as soon as the pll is programmed with different multipliers. table 9-4. rchw field descriptions field description 0?3 reserved. these bit values are ignored when the halfw ord is read. program to 0 for future compatibility. 4 swt software watchdog timer enable. this bit determines if the software watchdog timer is enabled after passing control to the user application code. 0 disable software watchdog timer 1 enable software watchdog timer after reset. the ti meout period is 392400 cl ock cycles (the default swt clock is the crystal oscillator). 5 wte mcu core watchdog timer enable. this bit determines if the core software watchdog timer is enabled.after passing control to the user application code. 0 disable core software watchdog timer 1 enable core watchdog timer after reset. the timeout period is 2.5*2 17 system clocks. 6 ps0 port size. defines the width of the data bus connected to the memory on d_cs0. after system reset, the bam changes d_cs0 to a 16-bit port to fetch the rchw from either 16- or 32-bit exte rnal memories. then the bam reconfigures the ebi as a 16- or 32-bit port, depending on this bit. 0 32-bit d_cs0 port size 1 16-bit d_cs0 port size note: used in development bus boot modes only (not availa ble on all packages). do not clear this bit if the device only has a 16-bit data bus. 7 vle vle code indicator. this bit configures the mmu entr ies 1-3 coded as classic book e instructions or as freescale vle instructions. 0 user code executes as classic book e code 1 user code executes as freescale vle code 8?15 bootid boot identifier. this field serves two functions: ? indicates which block in flash memory contains the boot program ? indicates if the flash memory is programmed (bootid=0x5a) or invalid table 9-5. watchdog timeout vs. crystal frequency 1 1 with the pll in normal mode and crystal oscillator as a reference clock source. crystal frequency (mhz) core wd timeout (ms) swt timeout (ms) 827.349 12 18.3 32.7 16 13.7 24.5 20 11 19.6 40 9.8
boot assist module (bam) 9-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 9.5.3.1 application start address register application start a ddress register ( figure 9-5 ) is the 32-bit word after the rchw in the application code memory device (internal or external flash). the bam uses the value from this location as a start address of the user application to pass control to. figure 9-5. application start address register 9.5.4 internal boot mode when the bam program detects in ternal flash boot mode, the bam: 1. configures a machine check exception handler, si nce it will be accessing flash memory locations that may be corrupted and cause a bus error 2. searches for a valid rchw in six pre-defined locations, as shown in table 9-6 3. if a valid rchw is not found, the bam program switches to serial boot mode 4. if the bam program finds a valid rchw: ? boot_block_address is the address (from table 9-6 ) of the valid rchw ? the bam program fetches the a pplication start address from boot_block_address + 0x4 ? the bam branches to this start address (shown in figure 9-5 ) ? the core watchdog is enabled (if rchw[w te] = 1) and/or swt is disabled (if rchw[swt] = 0) ? the mmu tlb entries 1,2,3 are programmed w ith vle attribute if the rchw[vle] = 1. 9.5.5 serial boot mode when serial boot mode is detected, either becaus e of the bootcfg configur ation or because a valid rchw word was not found in any of the expected lo cations in the flash, the bam program does the following: boot_block_address + 0x0000_0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 a16a17a18a19a20a21a22a23 a24 a25 a26 a27 a28 a29 a30 a31 table 9-6. possible rchw locations in the internal flash block address 0 0x0000_0000 1 0x0000_4000 2 0x0001_0000 3 0x0001_c000 4 0x0002_0000 5 0x0003_0000
boot assist module (bam) freescale semiconductor 9-9 pxr40 microcontroller reference manual, rev. 1 ? uses message buffers in can_a for program stack and variables ? polls the fmpll_syncr[lock] bit until it indicates that the pll has locked ? switches the system clock source to the pll, by setting siu_sysdiv[sysclksel] = 0x2 ? disables the core watchdog timer and se ts the swt timeout period to 2.5 x 2 27 cycles ? waits for the host to send a 64-bit password by either the can or sci ? receives start address, size of dow nload code in bytes, and vle bit ? receives the appl ication code data ? disables the swt and enable s the core watchdog timer with a timeout period of 2.5 x 2 27 systemclock cycles ? branches to the loaded code at the start address the mmu setup depends on how the ba m entered the serial boot mode. if it attempted to boot from the development bus but switch ed to serial boot because it could not find a valid rchw in flash, the mmu is set up as for that mode (see table 9-11 ). otherwise the mmu setup matches the table 9-2 . the serial boot mode can run in two modes, depending on the state of the evto pin during reset (the siu_rsr[abr] bit reflects the inve rted state of the evto pin): ? standard serial boot mode ? fixe d baud rates derived from the mc u system frequency. evto pin is kept high during reset. ? baud rate detection serial boot mode ? allo ws communication with adaptable speed, based on measured baud rate of the host transmission. evto pin has to be driven low for this mode. the evto pin is pulled up by an internal pull-up. acti vely driven low evto pin selects the baud rate detection mode. when the fixed baud rate mode is selected, the bam program configures the rxd_a pin to be the input of the esci_a module, cnrx_a pin as an input, and cntx_a as an output of the can_a module. when baud rate detection mode is sel ected, the bam program configures rxd_a and cnrx_a pins as gpi inputs for polling their state by the cpu. the sci and can controllers pins conf iguration summary is shown in the table 9-7 . table 9-7. can/esci pins configuration fo r can/esci fixed baud rate boot modes pins reset function initial serial boot mode serial boot mode after a valid can message received serial boot mode after a valid esci message received function pad configuration function pad configuration function pad configuration cntx_a gpio cntx_a push/pull output, with medium slew rate cntx_a push/pull output, with medium slew rate gpio ? cnrx_a gpio cnrx_a input with pull-up and hysteresis cnrx_a input with pull-up and hysteresis gpio ? txd_a gpio gpio ? gpio ? txd_a push/pull output, with medium slew rate rxd_a gpio rxd_a input with pull-up and hysteresis gpio ? rxd_a input with pull-up and hysteresis
boot assist module (bam) 9-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the bam configures the communication modules for reception with fixed baud rates as shown in the table 9-8 and waits for data reception. . if a message containing 8 bytes with id 0x11 is r eceived by the can controlle r first, the bam program: ? transitions to se rial can boot mode ? disables the esci ? configures rxd_a to its reset state ? transitions to the can seri al download protocol routine if a byte from esci is rece ived first, the bam program: ? transitions to the se rial sci boot sub-mode ? disables can_a module ? configures can_a?s pins to their reset state ? transitions to the sci seri al download protocol routine 9.5.5.1 can controller configurat ion in the fixed baud rate mode the can controller is configured to operate at a baud rate equal to system frequency divided by 60, using the standard 11 bit identifier format detailed in can 2.0a specification. see table 9-8 for examples of baud rates. only one message buffer 0 is used for all communications. the bit timing is configured as shown in figure 9-6 . table 9-8. serial boot mode ? baud rate and watchdog summary 1 1 with the pll in normal mode and crystal oscillator as a reference clock source. crystal frequency (mhz) system clock frequency (mhz) desired baud rate (baud) actual esci baud rate (baud) can baud rate (baud) core watchdog timeout period 2 (s) 2 the core wd is disabled during serial boot and is then enabled after serial boot finis hes (with timeouts indicated here) swt timeout period during serial boot 3 (s) 3 the swt is enabled during serial boot, but disabled after serial boot finishes. f xtal f sys = 1.5*f xtal ?f sys / 1248 f sys / 60 2.5 * 2 27 / f sys 2.5 * 2 27 / f xtal 8 12 9600 9615 200k 27.96 41.9 12 18 14400 14423 300k 18.64 28 16 24 19200 19230 400k 13.98 21 20 30 24000 24038 500k 11.18 16.8 40 60 48000 48077 1000k 8.4
boot assist module (bam) freescale semiconductor 9-11 pxr40 microcontroller reference manual, rev. 1 figure 9-6. can bit timing the bam program ignores can errors and all rece ived messages are assumed to be good. received messages are transmitted back. the host processor mu st compare the mcu transmissions with the sent data and restart th e process if an error is detected. 9.5.5.2 sci controller configurat ion in fixed baud rate mode the esci is configured for 1 start bi t, 8 data bits, no parity , 1 stop bit and operates at a baud rate equal to system clock divided by 1248. see table 9-8 for examples of baud rates. the bam program ignores the esci errors: all data received is assumed to be good and is sent back through the txd pin. the host processo r must compare the mcu transmitted data with the sent data and restart the process if an error is detected. 9.5.5.3 serial boot mode download protocol the download protocol follows four steps: 1. host sends 64-bit password. 2. host sends start address, size of download code in bytes, and vle bit. 3. host sends the application code data. 4. the mcu switches to the loaded code at the start address. the communication is done in half-duplex manner; a ny transmission from host is followed by the mcu transmission. the host computer s hould not send data until it receives echo from th e mcu. all multi byte data structures must be sent most-significant byte (msb) first. when the can is used for serial download, the data is packed into standard can messages in the following manner: ? a message with 0x11 id and 8-byte length to send the password. the mcu transmits back the same data, but with id of 0x1. ? a message with 0x12 id and 8-byte length to send the start address, lengt h, and the vle mode bit. the mcu transmits back the same data, but with id of 0x2. sync_seg time segment 1 time segment 2 nrz signal 1 time quanta 1 bit time 9 time quanta 2 time quanta transmit point sample point note: 1 time quanta = 5 system clock periods
boot assist module (bam) 9-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? messages with 0x13 id are used to send the downloaded data. the mcu transmits back the same data with id of 0x3. when the sci is used for serial download, the da ta must be sent on a byte-by-byte basis. the mcu transmits back the received bytes. since the mcu has to initialize itself to execute the serial boot there is a d ead time from mcu rstout negation when the host should wait be fore sending first data frame. th is time should be more than 5000 system clock periods. 9.5.5.4 download protocol execution the bam program executes th e serial boot as following: 1. download 64-bit password. a) the received 8-byte password is checked for va lidity. for a password to be valid, none of its four 16-bit half words mu st equal 0x0000 or 0xffff. b) the bam program then checks the censorship status of the mcu. if siu_ccr[disnex] is set, the mcu is considered to be censored and the password is compared with a password stored in the shadow row in internal flash memory. c) if siu_ccr[disnex] is cleare d, the mcu is not considered to be censored and the password is compared to the fixed value of 0xfeed_face_cafe_beef. d) if the password check fails, th e mcu stops responding. assert reset to force the mcu out of this state. e) if the password check passes, the bam tran sitions to the next st ep in the protocol. 2. download start address, si ze of download, and vle bit. the bam considers the next 8 bytes to contain a 32-bit start addr ess, the vle mode bit, and a 31-bit code length (see figure 9-7 ). figure 9-7. start address, vle bit and download size in bytes ? start_address defines where the received data is stored and where the mcu branches after the download is finished. th e two least significant bits of the start address are ignored by the bam program, thus the loaded code should be 32-bit word aligned. ? code_length defines how many data bytes to be loaded. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 start_address[0:15] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 start_address[16:31] 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 vle code_length[0:14] 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 code_length[15:30]
boot assist module (bam) freescale semiconductor 9-13 pxr40 microcontroller reference manual, rev. 1 ? vle instructs the mcu to program mmu entrie s 1?3 with vle attribute. if it is 1, the downloaded code must be compiled to vle instructions, if it is 0 the code contains classic power book e architecture instructions. 3. download data. each byte of data received is stored in the mcu memory, starting at the start_address specified in the previous step. the data increm ents through memory until the number of bytes stored matches code_length speci fied in the previous step. the bam program buffers incoming data, collecting up to eight bytes. the buffered data is written to the ram with 64-bit writes to prevent ec c errors, which may happen if the mcu ram is protected by 64- bit ecc code. once the buffered data is written to th e ram the bam program refreshes the swt. note only system ram supports 64-bit wr ites; therefore, attempting to download data to other ram apart from system ram causes errors. if the start address of the downloade d data is not on an 8-byte boundary, the bam writes 0x0 to the memory locat ions from the proceeding 8-byte boundary to the start address (maximum 4 bytes). the bam also writes 0x0 to all memory locations from the la st byte of data downloaded to the following 8 byte boundary (maximum 7 bytes). an additional 8 zero bytes are written to prevent possible ecc er rors that may be caused by the cpu pre-fetching. the bam appends an additional two zero double-words at the end of the code loaded into system ram in order to prevent possible ecc errors, which could otherwise happen due to the cpu pre-fetching data after the last instruction where th e ram is not initialized. the last loaded code address must not equal or exceed 0x4003_fff0 (the highest ram address allowed by mm u settings minus the two zero double-words, written by bam at the end of code download). 4. switch to the loaded code. the bam program waits for the last echo message transmission to complete, then the active communication controller is disable d. its pins revert to gpio inputs. to provide compatibility with older devices, the bam ? writes the core?s time base registers (tbu and tbl) with 0x0 ? enables the core watchdog to cause a re set after a time-out period of 2.5 x 2 27 system clock cycles ? disables software watchdog (swt) see table 9-8 for examples of time out periods. the bam code passes control to the loaded code at start_address, which was received in step 2 of the protocol.
boot assist module (bam) 9-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the loaded code must periodically refresh the core watchdog timer or change the timeout period to a valu e that does not cause resets during normal operation. 9.5.5.5 baud rate detection procedure when evto pin is driven low during reset, the ba m program enters into baud rate detection mode. following additional steps are taken: 1. the baud rate detection routine is copied to th e beginning of the system ram from the bam rom to improve baud rate detection accuracy 2. the cpu branches to the ram 3. the mcu configures the cnrx_a and rxd_a pins as general purpose inputs 4. the mcu polls these gpis until one of them goes low a) if the cnrx_a pin transitions first, the bam program starts c an baud rate detection routine, ignoring rxd_a. after detecting the can baud rate, the bam program transitions to the can download protocol routine described above. b) if the rxd_a pin transitions fi rst, the sci baud rate detection and download protocol routines are called, ignoring any fu rther can pins activity. the host, executing the serial boot , should send a test frame in order the mcu can detect the host communication speed. when booting through the sci, the host should send a zero byte as the test frame. when booting through the can, the host should send ze ro id, zero length message as the test frame. the mcu requires some time to setup its communica tion interfaces speed. to accommodate this the host should send serial password not earlier th an after 2000 mcu system clock periods. 9.5.5.5.1 sci baud rate detection. the host must send a zero byte to allow the mcu to dete ct the serial link baud ra te. the host transmits one start bit, eight zero data bits and one stop bit (the mcu does not echo it). the mcu polls the rxd_a pin for high to low transition and starts the e 200 core time base counter (tb). then the mcu polls for low to high transition on the pin an d when it happens, th e mcu turns off the tb counter. the tb content is used to calculate incoming signal baud-rate. th e sci baud rate is equal to the tb content divided by 288. (measured over 9 bits with 16 system clocks per bit and the core frequency is two times higher than system frequency). 9.5.5.6 can baud rate detection. the host transmits a zero length messa ge with zero 11 bit id and mcu measures time over 40 bits, polling cnrx_a pin for high and low, accord ing to the sent data. the mcu doe s not acknowledges this message. the can baud rate depends on the numbe r of quantas per bit and serial cl ock frequency, which is defined by a prescaler. the can baud rate de tection routine selects these para meters to maximize number of
boot assist module (bam) freescale semiconductor 9-15 pxr40 microcontroller reference manual, rev. 1 quantas per bit and achieve minimum difference between measured valu e and duration of the 40 can bits, to be programmed with select ed pair of the parameters. the can controller can be programme d with 8 to 25 number of quantas pe r bit. the bit timing parameters, can be selected by the baud rate de tection routine, are shown in the table 9-9 . see the parameters descriptions in the flexcan block guide) . maximum and minimum speeds of the serial comm unication modules are defined by the mcu system frequency and shown in the table 9-10 . table 9-9. lookup table for can bit timing. time quanta per bit time segment 1 time segment 2 rjw propseg pseg1 pseg2 8 1332 9 2332 10 3332 11 4332 12 3442 13 4443 14 5443 15 6444 16 7443 17 8443 18 7554 19 8554 20 7664 21 8664 22 7664 23 8664 24 7774 25 8774 table 9-10. maximum and minimum detectable baud rates 1 1 when the mcu operates with the pll in normal mode with crystal oscillator as a reference clock source. f xtal l (mhz) f sys = 1.5*f xtal (mhz) max baud rate for can (f sys /9) 2 (bps) 2 limited by 1mbps by can standard min can baud rate (f sys /25/256) bps max baud rate for sci (f sys /160)(bps) min baud rate for sci (f sys /16/2 16 )(bps) 8 12 1m 1875 75k 11.5 12 18 2812.5 112.5k 17.2 16 24 3750 150k 23 20 30 4687.5 187.5k 28.6 40
boot assist module (bam) 9-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 9.5.6 booting from the development bus if the mcu boots in one of the developm ent bus boot modes, the bam program: ? reprograms the mmu entries fo r ebi and internal flash (see table 9-11 ) ? sets up the ebi and development bus pins ? tries to read rchw fr om logical address 0x2000_0000 if the valid rchw is read from that address, the bam program: ? reads the user application code start address from 0x2000_0004 address ? parses rchw ? sets up watchdogs ? updates ebi, sram and internal flash mmu entries(1-3), according to rchw[vle] ? passes control to the user code if no valid rchw was read, bam sw itches to the serial boot mode. 9.5.6.1 ebi configuration for separa te address and data development bus boot mode the bam program sets up ebi rela ted registers as shown in the table 9-12 . rchw[ps0] must be programmed to ?1 ?, since the development bus doe s not support 32-bit port size in that sub-mode. table 9-11. mmu configuration for development bus boot modes tlb entry region logical base address physical base address size attributes 1 internal flash 0x0000_0000 0x2000_0000 16 mb not guarded big endian global pid 2 ebi 0x2000_0000 0x2000_0000 16 mb not guarded big endian global pid table 9-12. development bus/ebi register settings for separate address data lines mode register function value comments ebi_cal_br0 ? 0x2000_0803 sets the base address to 0x2000_0000,16-bit wide bus, burst inhibit ebi_cal_or0 ? 0xff80_00f0 set 15 wait states, 8mb siu_pcr259? siu_pcr293 d_add[12:30], d_add_dat[0:15] 0x0440 set pads to 20pf drive strength siu_pcr305? siu_pcr307 d_add[9:11] siu_pcr256 d_cs0 0x443 set pads to 20pf drive strength and pull-up enable siu_pcr295 d_we0 siu_pcr297 d_oe siu_pcr298 d_ts
boot assist module (bam) freescale semiconductor 9-17 pxr40 microcontroller reference manual, rev. 1 9.5.6.2 ebi configuration for multiplexed address and data development bus boot mode the bam program sets up ebi rela ted registers as shown in the table 9-13 . if the boot memory device is 32 bit wide, the rchw mu st be programmed in two first half-words of the memory because when the mcu tries to read rchw, the ebi is configured to use data lines 16?31 for 16-bit port accesses. 9.5.7 enabling debug of a censored device when a device is in a censored state, the debug por t (jtag/nexus) is disabled and only jtag bsdl commands can be used. ac cess to the nexus/jtag cl ients on a censored device requires inputting the proper password into the jtag censorsh ip control register during reset. note when the debug port is enabled on a censo red device, it is enabled only until the next reset. figure 9-8 shows the logic that enables access to nexus cl ients in a censored device using the jtag port. table 9-13. development bus/ebi register settings multiplexed mode. register function value comments the following registers are programmed when rchw[ps0] = 1 ebi_mcr ? 0x0000_0806 ad multiplexed mode, small port size use d16-31 ebi_cal_br0 ? 0x2000_0883 sets the base address to 0x2000_0000,16-bit wide bus, ad multiplexed mode, burst inhibit ebi_cal_or0 ? 0xff80_00f0 set 15 wait states, 8mb siu_pcr259- siu_pcr262 d_add[12:15], 0x440 set pads to 20pf drive strength siu_pcr305- siu_pcr307 d_add[9:11] siu_pcr263? siu_pcr277 d_add_dat[16:30] 0x840 set pads to 20pf drive strength siu_pcr257 d_add_dat[31] siu_pcr278- siu_pcr293 d_add_dat[0:15] 0x440 set pads to 20pf drive strength siu_pcr256 d_cs0 0x443 set pads to 20pf drive strength and pull-up enable siu_pcr295 d_we0 siu_pcr297 d_oe siu_pcr298 d_ts siu_pcr299 d_ale the following register is reprogrammed when rchw[ps0] = 0 ebi_cal_br0 ? 0x2000_0083 sets the base address to 0x2000_0000,32-bit wide bus, ad multiplexed mode, burst inhibit
boot assist module (bam) 9-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 9-8. enabling jtag/nexus port access on a censored device the steps to enable the debug port on a censored device are as follows: 1. after the rstout pin has is negated, hold the device in system reset state using a debugger or other tool. 2. while the device is being held in system reset state shift the 64-bit password into the censor_ctrl register (see section 32.3.4, censor_ctrl register ) via the jtag port using the jtag enable_censor_ctrl instruction. the jtag serial password is compared against the serial boot flash password from the flash shadow block. 3. if there is a match the nexus client tap contro ller enters normal operation mode and the disnex flag in the siu_ccr register is negated, indica ting nexus is enabled. upon negation of reset the debug / calibration tool is able to access the device vi a nexus port and jtag. if the jtag serial password does not match the serial boot flash passw ord or the serial boot flash password is an illegal password then the debug / calibrati on tool is not able to access the device. after the debug port is enabled, the tool can access the censored device and can erase and reprogram the shadow flash block in order to uncensor the device. compare 64-bit password jtag port controller censor_ctrl register nexus client tap controller debug/calibration tool access 64-bit password enable/disable censored flash array other nexus clients ?edma ? e200z7 core . . .
boot assist module (bam) freescale semiconductor 9-19 pxr40 microcontroller reference manual, rev. 1 warning if the shadow flash block is eras ed without reprogramming a new valid password and censorship control word be fore a reset occurs it will contain an illegal password and the debug port wi ll be inaccessible. also, if code does not exist in the first bootable regi on of the internal flash to reprogram the shadow flash with the proper censo rship control word and password, the device will be in a censored state and may no longer be usable. 4. subsequent resets will clear the jtag cens or password register a nd the nexus client tap controller will hold in reset again. therefore, th e tool must resend the jtag serial password, as described above, in order to enable th e nexus client tap controller again.
boot assist module (bam) 9-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 10-1 pxr40 microcontroller reference manual, rev. 1 chapter 10 interrupts and interrupt controller (intc) 10.1 introduction this chapter describes the interrupt controller (int c), which schedules interr upt requests (irqs) from software and internal peripherals to the e200z7 co re. the intc provides inte rrupt prioritization and preemption, interrupt masking, interrupt prio rity elevation, and protocol support. interrupts implemented by the mcu are defined in the e200z7 core reference manual . 10.1.1 block diagram figure 4-1 shows details of the interrupt controller. figure 10-1. intc block diagram end-of- interrupt register software set clear interrupt registers flag bits priority select registers 8 peripheral interrupt requests 1 n 1 priority arbitrator n 1 highest priority interrupt requests n 1 request selector lowest vector interrupt request n 1 vector encoder interrupt vector 9 x 4-bits interrupt acknowledge register interrupt vector 9 hardware vector enable vector table entry size 1 module configuration register 1 highest priority 4 priority comparator new 4 current 4 priority current priority register priority 4 popped 4 priority pushed priority priority lifo slave interface for reads and writes 1 push/update/acknowledge 1 pop slave bus signals 1 interrupt acknowledge 1 update interrupt vector 1 interrupt request to processor memory-mapped registers logic not memory-mapped 1 although n (largest addressable irq vector number) = 479, this does not indicate the total number of interrupts available on this device. the total number of available interrupts on this device is 480: 410 peripheral irqs, 8 software-configurable irqs, and 62 reserved.
interrupts and interrupt controller (intc) 10-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 10.1.2 overview interrupt functionality for the device is handled betw een the e200z7 core and the interrupt controller. the cpu core has 19 exception sources, each of which ca n interrupt the core. one exception source is from the interrupt controller (intc). the intc provides priority-based scheduling of interrupt requests and supports programmable preemp tion. this scheduling scheme is suita ble for statically scheduled hard real-time systems. the intc is optimized for a large number of interrupt requests. table 10-1 displays the interrupt sources and the numb er of interrupts available for each module; figure 10-2 shows a general diagram of intc software vector mode. table 10-1. interrupt sources available interrupt source (irqs) number of interrupts available software 8 watchdog 1 memory 1 edma 99 fmpll 2 external irq input pins (siu) 6 emios 32 etpu engine a 33 etpu engine b 32 eqadc 62 dspi 20 esci 3 flexcan 84 flexray 8 stm 2 decimation filter 16 system (pit, rti, pmc, etc.) 7
interrupts and interrupt controller (intc) freescale semiconductor 10-3 pxr40 microcontroller reference manual, rev. 1 figure 10-2. intc software vector mode two modes are available to determine the vector for the interrupt request source: software vector mode and hardware vector mode. in soft ware vector mode, as shown in figure 10-2 , the e200z7 branches to a common interrupt exception handler whose location is determined by an address derived from special purpose registers ivpr and ivor4. the interrupt except ion handler reads the in tc_iackr to determine the vector of the interrupt request source. typical pr ogram flow for software ve ctor mode is shown in figure 10-3 . figure 10-3. program flow?software vector mode n is the largest vector number ( 479) with the greatest hexadecima l address (ivpr + 0x1df0) that is available in the interrupt memory map for this de vice. because blocks of memory throughout the total memory map are used for other purposes, the maximu m vector number does not i ndicate the total number of available interrupt sources for this device. the total number of entries in th e interrupt memory map on this de vice is 480: 410 peripheral irqs, 8 software-configurable irqs, and 62 reserved. in hardware vector mode, the core branches to an interrupt exception handler unique for each interrupt request source. typical program flow fo r hardware vector mode is shown in figure 10-4 . irqs interrupt controller (intc) external interrupt exception request e200z7 core isr isr 0 address isr 0 isr isr 1 ? ? ? isr isr n ? ? ? isr isr n isr n address isr n address isr 1 address ? ? ? ? ? ? prolog (including using iackr to get vector then bl isr_n epilog ivpr + ivor4 irq [n] taken iackr data table address instructions address vtba of addresses
interrupts and interrupt controller (intc) 10-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 10-4. program flow?hardware vector mode the intc supports a hardware vector mode that reduces the time betw een assertion of an interrupt and execution of the service routine. it also provides 16 priorities so that lower priority isrs do not delay the execution of higher priority isrs. th e priority assigned to each interrupt source is programmable in the range 0 to 15, with 0 being the lowest and 15 being the highest priority. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority level can be raised tempor arily so that no task can preempt another task that shares the same resource. multiple processors can assert interrupt requests to each other through software configurable interrupt requests, i.e., by using applicatio n software to assert an interrupt request. these same software configurable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. the high priority po rtion is initiated by a peripheral interrupt request, but then the isr can assert a software confi gurable interrupt request to finish the servicing in a lower priority isr. 10.1.3 features features include the following: ? total number of interrupt vectors is 480, of which: ? 410 are peripheral interrupt vectors ? 8 are software configurable sources ? 62 are reserved sources ? 9-bit unique vector for each interrupt re quest source in hardware vector mode. ? each interrupt source can be progr ammed to one of 16 priorities. ? preemption. ? preemptive prioritized inte rrupt requests to processor. prolog b handler 0 handler 0 isr ? ? ? ? ? ? isr ? ? ? ? ? ? instructions note: ?b isr_n? is technically epilog prolog epilog isr prolog epilog handler n handler n b handler 1 ? ? ? b handler 2 ? ? ? b handler n b handler n ivpr + 0x0000 ivpr + 0x0010 ivpr + 0x0020 ivpr + n [0x0010] refer to definition of n irq [n] taken address part of the handler.
interrupts and interrupt controller (intc) freescale semiconductor 10-5 pxr40 microcontroller reference manual, rev. 1 ? isr at a higher priority preempts isrs or tasks at lower priorities. ? automatic pushing or popping of preemp ted priority to or from a lifo. ? ability to modify the isr or task priority. modi fying the priority can be used to implement the priority ceiling protocol fo r accessing shared resources. ? low latency?three clocks from receipt of interr upt request from peripheral to interrupt request to processor. 10.1.4 modes of operation the interrupt controller has two handshaking modes with the processor: software vector mode and hardware vector mode. the state of the hardware vector enable bit, intc _mcr[hven], determines which mode is used. in debug mode the interrupt controlle r operation is identical to its nor mal operation of software vector mode or hardware vector mode. 10.1.4.1 software vector mode in software vector mode, there is a common interrupt excep tion handler address which is calculated by hardware as shown in figure 10-5 . the upper half of the in terrupt vector prefix re gister (ivpr) is added to the offset contained in the external input interrupt vector offset register (ivo r4). note that since bits ivor4[28:31] are not part of the offset value, the vector offset must be located on a quad-word (16-byte) aligned location in memory. in software vector mode, the interrupt exception handler software must r ead the intc interrupt acknowledge register (intc_iackr) to obtain the vector number an d base address of the handler associated with the corresponding pe ripheral or software interrupt re quest. the intc_iackr register contains a 21-bit or 20-bit address fo r a vector table base address (vtb a). the address is then used to branch to the corresponding routine for that peripheral or software interrupt source. figure 10-5. software vector mode: interrupt exception handler address calculation reading the intc_iackr acknowledges the intc?s inte rrupt request and negates the interrupt request to the processor. the interrupt reque st to the processor does not clear if a higher priority interrupt request arrives. even in this case, intvec does not update to the higher priori ty request until the lower priority 31 16 15 0 ivpr 31 28 27 16 15 0 + ivor4 31 28 27 16 15 0 0x00 0x00 offset offset prefix 0x0000 prefix = interrupt exception 0x0000 handler address
interrupts and interrupt controller (intc) 10-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 interrupt request is acknowledged by reading the in tc_iackr. the reading also pushes the pri value in the intc current priority regi ster (intc_cpr) onto the lifo and updates pri in the intc_cpr with the priority of the interrupt request. the intc_cpr masks any peripheral or software configurable interrupt request at the same or lo wer priority of the current value of the pri field in intc_cpr from generating an interrupt request to the processor. the interrupt exception handler must write to the end-of-int errupt register (intc_ eoir) to complete the operation (assuming the source of the interrupt has b een cleared). writing to the intc_eoir ends the servicing of the interrupt request. the intc?s lifo is popped into the intc_cpr's pri field by writing to the intc_eoir, and the size of a write does not affect th e operation of the write. those values and sizes written to this register neither update the intc_e oir contents nor affect whether the lifo pops. for possible future compatibility, write four bytes of all 0s to the intc_eoir. the timing relationship between popping the lifo and disabling recognition of external input has no restriction. the writes can happen in either order. however, disabling recognition of th e external input before popping the lifo eases the calculation of the maximum stack depth at the cost of postponing the servicing of the next interrupt request. 10.1.4.2 hardware vector mode in hardware vector mode, the interr upt exception handler address is spec ific to the peripheral or software configurable interrupt source rather than being comm on to all of them. no ivor is used. the interrupt exception handler addre ss is calculated by hardware as shown in figure 10-6 . the upper half of the interrupt vector prefix register (ivp r) is added to an offset which corr esponds to the peripheral or software interrupt source which caused the interrupt request. the offset matches the value in the interrupt vector field, intc_iackr[intvec]. each interrupt excep tion handler address is aligned on a four-word (16-byte) boundary. ivor4 is not used in this mode, and software does not need to read intc_iackr to get the interrupt vector number. figure 10-6. hardware vector mode: interrupt exception handler address calculation the processor negates intc?s interrupt request wh en automatically acknowledgi ng the interrupt request. however, the interrupt request to th e processor do not negate if a higher priority inte rrupt request arrives. even in this case, the interrupt vector number does not update to the higher priori ty request until the lower priority request is ackno wledged by the processor. 31 16 15 0 ivpr 31 28 27 16 15 0 0 + hardware vector 15 0 0b0000 intc_iackr[intvec] prefix 0x0000 prefix 18 0b000 19 0x0000 31 28 27 16 0b0000 irq specific offset 18 0b000 19 16 = interrupt exception handler address mode offset
interrupts and interrupt controller (intc) freescale semiconductor 10-7 pxr40 microcontroller reference manual, rev. 1 the assertion of the interrupt ac knowledge signal pushes the pri value in the intc_cpr onto the lifo and updates pri in the intc_c pr with the new priority. 10.2 external signal description the intc does not have any direct external mcu signals. however, ther e are sixteen external pins which can be configured in the siu as external interrupt request input pins. when configured for an external interrupt request function, an interrupt on that pin sets an external inte rrupt flag. these flags cause one of five peripheral interr upt requests to the interrupt controller. for more information on external interrupts, the pins used, and how to configure them: ? refer to the signals chapter for a list and number of the external interrupt pins. ? refer to the siu chapter for more information on how to configure these pins. 10.3 memory map and register definition table 10-2 is the intc memory map. note to ensure compatibility with all powe r architecture devices, the tlb entry covering the intc memory map must be configured as guarded, both in software and hardware vector modes. ? in software vector mode, the intc_iackr must not be read speculatively. ? in hardware vector mode, guarde d writes to the intc_cpr or intc_eoir complete befo re the interrupt acknow ledge signal from the processor asserts. table 10-2. intc memory map address register bits access reset value section/page base (0xfff4_8000) intc_mcr?intc module configuration register 32 r/w 0x0000_0000 10.3.1.1/10-9 base + 0x0004 reserved base + 0x0008 intc_cpr?intc current priority register 32 r/w 0x0000_000f 10.3.1.2/10-1 0 base + 0x000c reserved base + 0x0010 intc_iackr?intc interrupt acknowledge register 1 32 r/w 0x0000_0000 10.3.1.3/10-1 0 base + 0x0014 reserved base + 0x0018 intc_eoir?intc end-of-interrupt register 32 w/o 0x0000_0000 10.3.1.4/10-1 1 base + 0x001c reserved
interrupts and interrupt controller (intc) 10-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 base + 0x0020 intc_sscir0?intc software set/clear interrupt register 0 8 r/w 0x00 10.3.1.5/10-1 2 base + 0x0021 intc_sscir1?intc software set/clear interrupt register 1 8 r/w 0x00 10.3.1.5/10-1 2 base + 0x0022 intc_sscir2?intc software set/clear interrupt register 2 8 r/w 0x00 10.3.1.5/10-1 2 base + 0x0023 intc_sscir3?intc software set/clear interrupt register 3 8 r/w 0x00 10.3.1.5/10-1 2 base + 0x0024 intc_sscir4?intc software set/clear interrupt register 4 8 r/w 0x00 10.3.1.5/10-1 2 base + 0x0025 intc_sscir5?intc software set/clear interrupt register 5 8 r/w 0x00 10.3.1.5/10-1 2 base + 0x0026 intc_sscir6?intc software set/clear interrupt register 6 8 r/w 0x00 10.3.1.5/10-1 2 base + 0x0027 intc_sscir7?intc software set/clear interrupt register 7 8 r/w 0x00 10.3.1.5/10-1 2 base + (0x0028?0x003f) reserved base + (0x0040?0x0219) intc_psr n ?intc priority select registers 2 0 ? 479 8 r/w 0x00 10.3.1.6/10-1 3 1 when the hven bit in the intc_mcr is asserted, a read of the intc_iackr has no side effects. 2 the pri fields are ?reserved? for peripheral interrupt requests whose vectors are labeled as reserved in table 10-7 . table 10-2. intc memory map (continued) address register bits access reset value section/page
interrupts and interrupt controller (intc) freescale semiconductor 10-9 pxr40 microcontroller reference manual, rev. 1 10.3.1 register descriptions with the exception of the intc_ssci n and intc_psr n registers, all of the registers are 32-bits wide. any combination of accessing the 4 bytes of a register with a singl e access is supported, provided that the access does not cross a register boundary. these suppor ted accesses include types and sizes of 8 bits, aligned 16 bits, and aligned 32 bits. although intc_ssci n and intc_psr n are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided th at the access does not cross a 32-bit boundary. in software vector mode, the side effects of a read of the intc interrupt acknowledge register (intc_iackr) are the same regardless of the size of the read. in eith er software or hardware vector mode, the size of a write to the intc end-of-interrupt register (intc_eoir) doe s not affect the operation of the write. 10.3.1.1 intc module configur ation register (intc_mcr) the intc_mcr is used to configure options of the intc. address: base + 0x0000 (intc_mcr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 vtes 0 0 0 0 hven w reset00000000000000000000000000 0 0000 0 figure 10-7. intc module configuration register (intc_mcr) table 10-3. intc_mcr field descriptions field description 0?25 reserved, must be cleared. 26 vtes vector table entry size. controls the numb er of ?0?s to the right of intvec in section 10.3.1.3, intc interrupt acknowledge register (intc_iackr) . if the contents of intc_iackr are used as an address of an entry in a vector table as in software vector mode, then the number of righ t-most ?0?s determines the size of each vector table entry. vtes impacts software vector mode operation but also affects the intc_iackr[intvec ] position in both hardware vector mode and software vector mode. 0 4 bytes 1 8 bytes 27?30 reserved, must be cleared. 31 hven hardware vector enable. controls whether the intc is in hardware vector mode or software vector mode. refer to section 10.1.4, modes of operation , for the details of the handshaking with the processor in each mode. 0 software vector mode 1 hardware vector mode
interrupts and interrupt controller (intc) 10-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 10.3.1.2 intc current priority register (intc_cpr) the intc_cpr masks any peripheral or software configurable interrupt request set at the same or lower priority as the current value of the intc_cpr[pri] field from genera ting an interrupt request to the processor. when the intc interrupt acknowledge regi ster (intc_iackr) is r ead in software vector mode or the interrupt acknowledge signal from the pr ocessor is asserted in ha rdware vector mode, the value of pri is pushed onto the li fo, and pri is updated with the pr iority of the preempting interrupt request. when the intc end-of-inter rupt register (intc_eoir) is wr itten, the lifo is popped into the intc_cpr?s pri field. the masking priority can be raised or lowered by wr iting to the pri field, supporting the pcp. refer to section 10.5.5, priority ceiling protocol . note on some power architecture mcus, a store to raise the pri field which closely precedes an access to a shared resource can result in a non-coherent access to that resource unless an mbar or msync followed by an isync sequence of instructions is executed between the accesses. an mbar or msync instruction is also necessary afte r accessing the resource but before lowering the pri field. refer to section 10.5.5.2, ensuring coherency . 10.3.1.3 intc interrupt acknowledge register (intc_iackr) the intc_iackr provides a value that can be used to load th e address of an isr from a vector table. the vector table can be composed of addresses of the isrs specific to their respective interrupt vectors. in software vector mode, reading the intc_iackr acknowledges the intc?s interrupt request. refer to section 10.1.4.1, software vector mode , for a detailed description of the effect on the interrupt request to the processor. the reading also pushes the pri value in the intc current prior ity register (intc_cpr) onto the lifo and updates pri in the intc_cpr with the priority of the interrupt request. the side effect address: base + 0x0008 (intc_cpr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 0000000000 pri w reset00000000000000000000000000001111 figure 10-8. intc current priority register (intc_cpr) table 10-4. intc_cpr field descriptions field description 0?27 reserved, must be cleared. 28?31 pri priority. pri is the priority of the currently execut ing isr according to the field values defined below. 1111 priority 15 (highest) 1110 priority 14 ... 0001 priority 1 0000 priority 0 (lowest)
interrupts and interrupt controller (intc) freescale semiconductor 10-11 pxr40 microcontroller reference manual, rev. 1 from the reads in software vector mode, that is, the effect on the interrupt reque st to the processor, the current priority, and the li fo, are the same regardless of the size of the read reading the intc_iackr does not have si de effects in hardware vector mode. note in software vector mode, the intc_i ackr must be read before setting msr[ee]. no synchronization instruct ion is needed after reading the intc_iackr and before setting msr[ee]. however, the time for the processor to recognize the assertion or negation of the external input to it is not defined by the book e architecture and can be greater than 0. therefore, insert in structions between the reading of the intc_iackr and the setting of msr[ ee] that consumes at least two processor clock cycles. this length of time allows the interrupt request negation to propagate through the pr ocessor before msr[ee] is set. 10.3.1.4 intc end-of-interrupt register (intc_eoir) writing to the intc_eoir signals th e end of the servicing of the inte rrupt request. when the intc_eoir is written, the priority last pushed on the lifo is popped into intc_cpr. the values and size of data address: base + 0x0010 (intc_iackr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba intvec 00 w reset00000000000000000000000000000000 figure 10-9. intc interrupt acknowledge register (intc_iac kr)?intc_mcr[vtes] = 0 address: base + 0x0010 (intc_iackr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba intvec 0 00 w reset00000000000000000000000000000000 figure 10-10. intc interrupt acknowledge register (intc_iackr) ?intc_mcr[vtes] = 1 table 10-5. intc_iackr field descriptions field description 0?20 vtba vector table base address. can be the base address of a vector table of addresses of isrs. the vtba only uses the left-most 20 bits when the vtes bit in intc_mcr is asserted. 21?29 intvec interrupt vector. vector of peripheral or software-configurable interrupt requests that caused the interrupt request to the processor. when the interrupt request to the processor asserts, the intvec is updated, whether the intc is in software or hardware vector mode. note: if intc_mcr[vtes] = 1, then the intvec field is sh ifted left one position to bits 20?28. vtba is then shortened by one bit to bits 0?19. 30?31 reserved, must be cleared.
interrupts and interrupt controller (intc) 10-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 written to the intc_eoir are ignored. those values a nd sizes written to this re gister neither update the intc_eoir contents or affect whet her the lifo pops. for possible future compatib ility, write four bytes of all 0?s to the intc_eoir. reading the intc_eoir has no effect on the lifo. 10.3.1.5 intc software set/clear in terrupt registers (intc_sscir0?7) the intc_sscir n support the setting or clearing of software configurable interrupt requests. these registers contain eight independent se ts of bits to set and clear a corre sponding flag bit by software. with the exception of being set by software, this flag bit behaves th e same as a flag bit set within a peripheral. this flag bit generates an interrupt request within the intc just like a peripheral interrupt request. writing a 1 to set n leaves set n unchanged at 0 but sets clr n . writing a 0 to set n has no effect. clr n is the flag bit. writing a 1 to clr n clears it. writing a 0 to clr n has no effect. if a 1 is written to a pair set n and clr n bits at the same time, clr n is asserted, regardless of whether clr n was asserted before the write. although intc_ssci n is 8 bits wide, it can be accessed with a single 16-bi t or 32-bit access, provided that the access does not cross a 32-bit boundary. address: base + 0x0018 (intc_eoir) access: w/o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 0000000000 0 0 00 w eoir reset00000000000000000000000000000000 figure 10-11. intc end-of-interrupt register (intc_eoir) address: base + 0x0020 + n (intc_sscir n ); n = 0?7 access: r/w 01234567 r 0 0 0 0000 clr n w set n reset00000000 figure 10-12. intc software set/clear interrupt register (intc_sscir n ) table 10-6. intc_sscir n field descriptions field description 0?5 reserved, must be cleared. 6 set n set flag bits. writing a 1 sets the corresponding clr n bit. writing a 0 has no effect. each set n is always read as a 0. 7 clr n clear flag bits. clr n is the flag bit. writing a 1 to clr n clears it provided that a 1 is not written simultaneously to its corresponding set n bit. writing a 0 to clr n has no effect. 0 interrupt request not pending within intc. 1 interrupt request pending within intc.
interrupts and interrupt controller (intc) freescale semiconductor 10-13 pxr40 microcontroller reference manual, rev. 1 10.3.1.6 intc priority select registers (intc_psr0?479) the intc_psr n allows you to select a priority for each in terrupt request source (peripheral irqs or software-configurable irqs). each priority select register (intc_psr n) is assigned to the irq source vector with the same number. for example, the so ftware-configurable irqs 0?7 are assigned vectors 0?7, and their priorities are configured in intc_psr0?intc_psr7, re spectively. the peripheral interrupt requests are assigned vector s 8?479 and their priorities are configured in priority select registers intc_psr8 through intc_psr479, respectively. although intc_psr n is 8 bits wide, you can use a single 16-bit or 32-bit access, provide d that it does not cross a 32-bit boundary. note do not modify the pri n field in intc_psr n when the irq is asserted. 10.4 functional description 10.4.1 interrupt request sources the intc has two types of interr upt requests, peripheral and softwa re configurable. the assignments between the interrupt requests from the modules to the vectors for input to the e200z7 are shown in table 10-8 . the hardware vector mode offset column list s the irq-specific offsets when using hardware vector mode. the source column shows the c language syntax for the register bit label: module_register[bit]. interrupt request s from the same module location are ored together. the individual interrupt priorities ar e selected in intc_psr n , where the priority select re gister is assi gned according to the vector number. address: base + 0x0040 + n (intc_psr n ); n = 0?479 access: r/w 01234567 r 0 0 0 0 pri n w reset00000000 figure 10-13. intc priority select registers (intc_psr n ) table 10-7. intc_psr n field descriptions field description 0?3 reserved, must be cleared. 4?7 pri n priority select. selects the priority for corresponding interrupt request. 1111 priority 15 (highest) 1110 priority 14 ... 0001 priority 1 0000 priority 0 (lowest)
interrupts and interrupt controller (intc) 10-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 10-8. interrupt request sources hardware vector mode offset vector number 1 source 2 description software 0x0000 0 intc_sscir0[clr0] intc software configurable. clear flag 0. 0x0010 1 intc_sscir1[clr1] intc software configurable. clear flag 1. 0x0020 2 intc_sscir2[clr2] intc software configurable. clear flag 2. 0x0030 3 intc_sscir3[clr3] intc software configurable. clear flag 3. 0x0040 4 intc_sscir4[clr4] intc software configurable. clear flag 4. 0x0050 5 intc_sscir5[clr5] intc software configurable. clear flag 5. 0x0060 6 intc_sscir6[clr6] intc software configurable. clear flag 6. 0x0070 7 intc_sscir7[clr7] intc software configurable. clear flag 7. watchdog / ecc 0x0080 8 ecsm_swtir[swtic] ecsm software watchdog interrupt flag 0x0090 9 ecsm_esr[rnce] ecsm_esr[fnce] ecsm combined interrupt requests: ? internal sram non-correctable error ? flash non-correctable error edma2 a 0x00a0 10 edma_erl[err31:err0] edma_a channel error flags 31?0 0x00b0 11 edma_irqrl[int00] edma_a channel interrupt 0 0x00c0 12 edma_irqrl[int01] edma_a channel interrupt 1 0x00d0 13 edma_irqrl[int02] edma_a channel interrupt 2 0x00e0 14 edma_irqrl[int03] edma_a channel interrupt 3 0x00f0 15 edma_irqrl[int04] edma_a channel interrupt 4 0x0100 16 edma_irqrl[int05] edma_a channel interrupt 5 0x0110 17 edma_irqrl[int06] edma_a channel interrupt 6 0x0120 18 edma_irqrl[int07] edma_a channel interrupt 7 0x0130 19 edma_irqrl[int08] edma_a channel interrupt 8 0x0140 20 edma_irqrl[int09] edma_a channel interrupt 9 0x0150 21 edma_irqrl[int10] edma_a channel interrupt 10 0x0160 22 edma_irqrl[int11] edma_a channel interrupt 11 0x0170 23 edma_irqrl[int12] edma_a channel interrupt 12 0x0180 24 edma_irqrl[int13] edma_a channel interrupt 13 0x0190 25 edma_irqrl[int14] edma_a channel interrupt 14 0x01a0 26 edma_irqrl[int15] edma_a channel interrupt 15
interrupts and interrupt controller (intc) freescale semiconductor 10-15 pxr40 microcontroller reference manual, rev. 1 0x01b0 27 edma_irqrl[int16] edma_a channel interrupt 16 0x01c0 28 edma_irqrl[int17] edma_a channel interrupt 17 0x01d0 29 edma_irqrl[int18] edma_a channel interrupt 18 0x01e0 30 edma_irqrl[int19] edma_a channel interrupt 19 0x01f0 31 edma_irqrl[int20] edma_a channel interrupt 20 0x0200 32 edma_irqrl[int21] edma_a channel interrupt 21 0x0210 33 edma_irqrl[int22] edma_a channel interrupt 22 0x0220 34 edma_irqrl[int23] edma_a channel interrupt 23 0x0230 35 edma_irqrl[int24] edma_a channel interrupt 24 0x0240 36 edma_irqrl[int25] edma_a channel interrupt 25 0x0250 37 edma_irqrl[int26] edma_a channel interrupt 26 0x0260 38 edma_irqrl[int27] edma_a channel interrupt 27 0x0270 39 edma_irqrl[int28] edma_a channel interrupt 28 0x0280 40 edma_irqrl[int29] edma_a channel interrupt 29 0x0290 41 edma_irqrl[int30] edma_a channel interrupt 30 0x02a0 42 edma_irqrl[int31] edma_a channel interrupt 31 pll 0x02b0 43 fmpll_synsr[locf] fmpll loss-of-clock flag 0x02c0 44 fmpll_synsr[lolf] fmpll loss-of-lock flag siu 0x02d0 45 siu_osr[ovf15:ovf0] siu combined overrun interrupt requests of the external interrupt overrun flags 15?0 0x02e0 46 siu_eisr[eif0] siu external interrupt flag 0 0x02f0 47 siu_eisr[eif1] siu external interrupt flag 1 0x0300 48 siu_eisr[eif2] siu external interrupt flag 2 0x0310 49 siu_eisr[eif3] siu external interrupt flag 3 0x0320 50 siu_eisr[eif15:eif4] siu external interrupt flags 15?4 emios 0x0330 51 emios_gfr[f0] emios channel 0 flag 0x0340 52 emios_gfr[f1] emios channel 1 flag 0x0350 53 emios_gfr[f2] emios channel 2 flag 0x0360 54 emios_gfr[f3] emios channel 3 flag table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x0370 55 emios_gfr[f4] emios channel 4 flag 0x0380 56 emios_gfr[f5] emios channel 5 flag 0x0390 57 emios_gfr[f6] emios channel 6 flag 0x03a0 58 emios_gfr[f7] emios channel 7 flag 0x03b0 59 emios_gfr[f8] emios channel 8 flag 0x03c0 60 emios_gfr[f9] emios channel 9 flag 0x03d0 61 emios_gfr[f10] emios channel 10 flag 0x03e0 62 emios_gfr[f11] emios channel 11 flag 0x03f0 63 emios_gfr[f12] emios channel 12 flag 0x0400 64 emios_gfr[f13] emios channel 13 flag 0x0410 65 emios_gfr[f14] emios channel 14 flag 0x0420 66 emios_gfr[f15] emios channel 15 flag etpu a 0x0430 67 etpu_mcr[mgea] etpu_mcr[mgeb] etpu_mcr[ilfa] etpu_mcr[ilfb] etpu_mcr[scmmisf] etpu global exception 0x0440 68 etpu_cisr_a[cis0] etpu engine a channel 0 interrupt status 0x0450 69 etpu_cisr_a[cis1] etpu engine a channel 1 interrupt status 0x0460 70 etpu_cisr_a[cis2] etpu engine a channel 2 interrupt status 0x0470 71 etpu_cisr_a[cis3] etpu engine a channel 3 interrupt status 0x0480 72 etpu_cisr_a[cis4] etpu engine a channel 4 interrupt status 0x0490 73 etpu_cisr_a[cis5] etpu engine a channel 5 interrupt status 0x04a0 74 etpu_cisr_a[cis6] etpu engine a channel 6 interrupt status 0x04b0 75 etpu_cisr_a[cis7] etpu engine a channel 7 interrupt status 0x04c0 76 etpu_cisr_a[cis8] etpu engine a channel 8 interrupt status 0x04d0 77 etpu_cisr_a[cis9] etpu engine a channel 9 interrupt status 0x04e0 78 etpu_cisr_a[cis10] etpu engine a channel 10 interrupt status 0x04f0 79 etpu_cisr_a[cis11] etpu engine a channel 11 interrupt status 0x0500 80 etpu_cisr_a[cis12] etpu engine a channel 12 interrupt status 0x0510 81 etpu_cisr_a[cis13] etpu engine a channel 13 interrupt status 0x0520 82 etpu_cisr_a[cis14] etpu engine a channel 14 interrupt status table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-17 pxr40 microcontroller reference manual, rev. 1 0x0530 83 etpu_cisr_a[cis15] etpu engine a channel 15 interrupt status 0x0540 84 etpu_cisr_a[cis16] etpu engine a channel 16 interrupt status 0x0550 85 etpu_cisr_a[cis17] etpu engine a channel 17 interrupt status 0x0560 86 etpu_cisr_a[cis18] etpu engine a channel 18 interrupt status 0x0570 87 etpu_cisr_a[cis19] etpu engine a channel 19 interrupt status 0x0580 88 etpu_cisr_a[cis20] etpu engine a channel 20 interrupt status 0x0590 89 etpu_cisr_a[cis21] etpu engine a channel 21 interrupt status 0x05a0 90 etpu_cisr_a[cis22] etpu engine a channel 22 interrupt status 0x05b0 91 etpu_cisr_a[cis23] etpu engine a channel 23 interrupt status 0x05c0 92 etpu_cisr_a[cis24] etpu engine a channel 24 interrupt status 0x05d0 93 etpu_cisr_a[cis25] etpu engine a channel 25 interrupt status 0x05e0 94 etpu_cisr_a[cis26] etpu engine a channel 26 interrupt status 0x05f0 95 etpu_cisr_a[cis27] etpu engine a channel 27 interrupt status 0x0600 96 etpu_cisr_a[cis28] etpu engine a channel 28 interrupt status 0x0610 97 etpu_cisr_a[cis29] etpu engine a channel 29 interrupt status 0x0620 98 etpu_cisr_a[cis30] etpu engine a channel 30 interrupt status 0x0630 99 etpu_cisr_a[cis31] etpu engine a channel 31 interrupt status eqadc a 0x0640 100 eqadc_fisr x [torf] eqadc_fisr x [rfof] eqadc_fisr x [cfuf] eqadc a combined overrun interr upt request s from all of the fifos: ? trigger overrun, ? receive fifo overflow, ? command fifo underflow 0x0650 101 eqadc_fisr0[ncf] eqadc a co mmand fifo 0 non-coherency flag 0x0660 102 eqadc_fisr0[pf] eqadc a command fifo 0 pause flag 0x0670 103 eqadc_fisr0[eoqf] eqadc a command fifo 0 command queue end-of-queue flag 0x0680 104 eqadc_fisr0[cfff] eqadc a command fifo 0 fill flag 0x0690 105 eqadc_fisr0[rfdf] eqadc a receive fifo 0 drain flag 0x06a0 106 eqadc_fisr1[ncf] eqadc a co mmand fifo 1 non-coherency flag 0x06b0 107 eqadc_fisr1[pf] eqadc a command fifo 1 pause flag 0x06c0 108 eqadc_fisr1[eoqf] eqadc a command fifo 1 command queue end-of-queue flag 0x06d0 109 eqadc_fisr1[cfff] eqadc a command fifo 1 fill flag 0x06e0 110 eqadc_fisr1[rfdf] eqadc a receive fifo 1 drain flag table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x06f0 111 eqadc_fisr2[ncf] eqadc a co mmand fifo 2 non-coherency flag 0x0700 112 eqadc_fisr2[pf] eqadc a command fifo 2 pause flag 0x0710 113 eqadc_fisr2[eoqf] eqadc a command fifo 2 command queue end-of-queue flag 0x0720 114 eqadc_fisr2[cfff] eqadc a command fifo 2 fill flag 0x0730 115 eqadc_fisr2[rfdf] eqadc a receive fifo 2 drain flag 0x0740 116 eqadc_fisr3[ncf] eqadc a co mmand fifo 3 non-coherency flag 0x0750 117 eqadc_fisr3[pf] eqadc a command fifo 3 pause flag 0x0760 118 eqadc_fisr3[eoqf] eqadc a command fifo 3 command queue end-of-queue flag 0x0770 119 eqadc_fisr3[cfff] eqadc a command fifo 3 fill flag 0x0780 120 eqadc_fisr3[rfdf] eqadc a receive fifo 3 drain flag 0x0790 121 eqadc_fisr4[ncf] eqadc a co mmand fifo 4 non-coherency flag 0x07a0 122 eqadc_fisr4[pf] eqadc a command fifo 4 pause flag 0x07b0 123 eqadc_fisr4[eoqf] eqadc a command fifo 4 command queue end-of-queue flag 0x07c0 124 eqadc_fisr4[cfff] eqadc a command fifo 4 fill flag 0x07d0 125 eqadc_fisr4[rfdf] eqadc a receive fifo 4 drain flag 0x07e0 126 eqadc_fisr5[ncf] eqadc a co mmand fifo 5 non-coherency flag 0x07f0 127 eqadc_fisr5[pf] eqadc a command fifo 5 pause flag 0x0800 128 eqadc_fisr5[eoqf] eqadc a command fifo 5 command queue end-of-queue flag 0x0810 129 eqadc_fisr5[cfff] eqadc a command fifo 5 fill flag 0x0820 130 eqadc_fisr5[rfdf] eqadc a receive fifo 5 drain flag dspi b, dspi c, dspi d 0x0830 131 dspi_bsr[tfuf] dspi_bsr[rfof] dspi b combined overrun interrupt requests: ? transmit fifo underflow ? receive fifo overflow 0x0840 132 dspi_bsr[eoqf] dspi b transmit fifo end-of-queue flag 0x0850 133 dspi_bsr[t fff] dspi b tx fifo fill request 0x0860 134 dspi_bsr[tcf ] dspi b tx complete 0x0870 135 dspi_bsr[rfdf] dspi b rx fifo drain request 0x0880 136 dspi_csr[tfuf] dspi_csr[rfof] dspi c combined overrun interrupt requests: ? transmit fifo underflow ? receive fifo overflow 0x0890 137 dspi_csr[eoqf] dspi c tr ansmit fifo end-of-queue flag 0x08a0 138 dspi_csr[tfff] dspi c tx fifo fill request table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-19 pxr40 microcontroller reference manual, rev. 1 0x08b0 139 dspi_csr[tcf] dspi c tx complete 0x08c0 140 dspi_csr[rfdf] dspi c rx fifo drain request 0x08d0 141 dspi_dsr[tfuf] dspi_dsr[rfof] dspi d combined overrun interrupt requests: ? transmit fifo underflow ? receive fifo overflow 0x08e0 142 dspi_dsr[eoqf] dspi d tr ansmit fifo end-of-queue flag 0x08f0 143 dspi_dsr[tfff] dspi d tx fifo fill request 0x0900 144 dspi_dsr[tcf] dspi d tx complete 0x0910 145 dspi_dsr[rfdf] dspi d rx fifo drain request esci a and b 0x0920 146 escia_ifsr1[tdre] escia_ifsr1[tc] escia_ifsr1[rdrf] escia_ifsr1[idle] escia_ifsr1[or] escia_ifsr1[nf] escia_ifsr1[fe] escia_ifsr1[pf] escia_ifsr1[berr] escia_ifsr2[rxrdy] escia_ifsr2[txrdy] escia_ifsr2[lwake] escia_ifsr2[sto] escia_ifsr2[pberr] escia_ifsr2[cerr] escia_ifsr2[ckerr] escia_ifsr2[frc] escia_ifsr2[ovfl] escia_ifsr2[ureq] combined interrupt requests of esci module a: ? lin status register 1 ? lin status register 2 ? sci status register 2 ? transmit data register empty ? transmit complete ? receive data register full ? idle line ?overrun ? noise flag ? framing error flag ? parity error flag interrupt requests ? bit error interrupt request ? receive data ready ? transmit data ready ? received lin wakeup signal ? slave timeout ? physical bus error ?crc error ? checksum error ? frame complete interrupts requests ? receive register overflow ? unrequested data received 0x0930?0x0940 147?148 reserved table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x0950 149 escib_ifsr1[tdre] escib_ifsr1[tc] escib_ifsr1[rdrf] escib_ifsr1[idle] escib_ifsr1[or] escib_ifsr1[nf] escib_ifsr1[fe] escib_ifsr1[pf] escib_ifsr1[berr] escib_ifsr2[rxrdy] escib_ifsr2[txrdy] escib_ifsr2[lwake] escib_ifsr2[sto] escib_ifsr2[pberr] escib_ifsr2[cerr] escib_ifsr2[ckerr] escib_ifsr2[frc] escib_ifsr2[ovfl] escib_ifsr2[ureq] combined interrupt requests of esci module b: ? lin status register 1 ? lin status register 2 ? sci status register 2 ? transmit data register empty ? transmit complete ? receive data register full ? idle line ?overrun ? noise flag ? framing error flag ? parity error flag interrupt requests ? bit error interrupt request ? receive data ready ? transmit data ready ? received lin wakeup signal ? slave timeout ? physical bus error ?crc error ? checksum error ? frame complete interrupts requests ? receive register overflow ? unrequested data received 0x0960?0x0970 150?151 reserved flexcan a and flexcan c 0x0980 152 cana_esr[boff_int] cana_esr[twrn_int] cana_esr[rwrn_int] flexcan a bus off interrupt flexcan a transmit warning interrupt flexcan a receive warning interrupt 0x0990 153 cana_esr[err_int] fl excan a error interrupt 0x09a0 154 reserved 0x09b0 155 cana_ifrl[buf0] flexcan a buffer 0 interrupt 0x09c0 156 cana_ifrl[buf1] flexcan a buffer 1 interrupt 0x09d0 157 cana_ifrl[buf2] flexcan a buffer 2 interrupt 0x09e0 158 cana_ifrl[buf3] flexcan a buffer 3 interrupt 0x09f0 159 cana_ifrl[buf4] flexcan a buffer 4 interrupt 0x0a00 160 cana_ifrl[buf5] flexcan a buffer 5 interrupt 0x0a10 161 cana_ifrl[buf6] flexcan a buffer 6 interrupt 0x0a20 162 cana_ifrl[buf7] flexcan a buffer 7 interrupt 0x0a30 163 cana_ifrl[buf8] flexcan a buffer 8 interrupt 0x0a40 164 cana_ifrl[buf9] flexcan a buffer 9 interrupt 0x0a50 165 cana_ifrl[buf10] flexcan a buffer 10 interrupt 0x0a60 166 cana_ifrl[buf11] flexcan a buffer 11 interrupt table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-21 pxr40 microcontroller reference manual, rev. 1 0x0a70 167 cana_ifrl[buf12] flexcan a buffer 12 interrupt 0x0a80 168 cana_ifrl[buf13] flexcan a buffer 13 interrupt 0x0a90 169 cana_ifrl[buf14] flexcan a buffer 14 interrupt 0x0aa0 170 cana_ifrl[buf15] flexcan a buffer 15 interrupt 0x0ab0 171 cana_ifrl[buf31:buf16] flexcan a buffers 31?16 interrupts 0x0ac0 172 cana_ifrh[buf63:buf32] flexcan a buffers 63?32 interrupts 0x0ad0 173 canc_esr[boff_int] canc_esr[twrn_int] canc_esr[rwrn_int] flexcan c bus off interrupt flexcan c transmit warning interrupt flexcan c receive warning interrupt 0x0ae0 174 canc_esr[err_int] flexcan c error interrupt 0x0af0 175 reserved 0x0b00 176 canc_ifrl[buf0] flexcan c buffer 0 interrupt 0x0b10 177 canc_ifrl[buf1] flexcan c buffer 1 interrupt 0x0b20 178 canc_ifrl[buf2] flexcan c buffer 2 interrupt 0x0b30 179 canc_ifrl[buf3] flexcan c buffer 3 interrupt 0x0b40 180 canc_ifrl[buf4] flexcan c buffer 4 interrupt 0x0b50 181 canc_ifrl[buf5] flexcan c buffer 5 interrupt 0x0b60 182 canc_ifrl[buf6] flexcan c buffer 6 interrupt 0x0b70 183 canc_ifrl[buf7] flexcan c buffer 7 interrupt 0x0b80 184 canc_ifrl[buf8] flexcan c buffer 8 interrupt 0x0b90 185 canc_ifrl[buf9] flexcan c buffer 9 interrupt 0x0ba0 186 canc_ifrl[buf10] flexcan c buffer 10 interrupt 0x0bb0 187 canc_ifrl[buf11] flexcan c buffer 11 interrupt 0x0bc0 188 canc_ifrl[buf12] flexcan c buffer 12 interrupt 0x0bd0 189 canc_ifrl[buf13] flexcan c buffer 13 interrupt 0x0be0 190 canc_ifrl[buf14] flexcan c buffer 14 interrupt 0x0bf0 191 canc_ifrl[buf15] flexcan c buffer 15 interrupt 0x0c00 192 canc_ifrl[buf31:buf16] flexcan c buffers 31?16 interrupts 0x0c10 193 canc_ifrh[buf63:buf32] fl excan c buffers 63?32 interrupts 0x0c20?0x0c40 194?196 reserved decimation filter a 0x0c50 197 dec_a decimation filter a input (fill) table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x0c60 198 dec_a decimation filter a output (drain) 0x0c70 199 dec_a decimation filter a error stm 0x0c80 200 stm[0] system timer module 0x0c90 201 stm[1:3] system timer module emios 0x0ca0 202 emios_gfr[f16] emios channel 16 flag 0x0cb0 203 emios_gfr[f17] emios channel 17 flag 0x0cc0 204 emios_gfr[f18] emios channel 18 flag 0x0cd0 205 emios_gfr[f19] emios channel 19 flag 0x0ce0 206 emios_gfr[f20] emios channel 20 flag 0x0cf0 207 emios_gfr[f21] emios channel 21 flag 0x0d00 208 emios_gfr[f22] emios channel 22 flag 0x0d10 209 emios_gfr[f23] emios channel 23 flag edma2 a (continued) 0x0d20 210 edma_erl[err63:err32] edma_a channel error flags 63?32 0x0d30 211 edma_irqrh[int32] edma_a channel interrupt 32 0x0d40 212 edma_irqrh[int33] edma_a channel interrupt 33 0x0d50 213 edma_irqrh[int34] edma_a channel interrupt 34 0x0d60 214 edma_irqrh[int35] edma_a channel interrupt 35 0x0d70 215 edma_irqrh[int36] edma_a channel interrupt 36 0x0d80 216 edma_irqrh[int37] edma_a channel interrupt 37 0x0d90 217 edma_irqrh[int38] edma_a channel interrupt 38 0x0da0 218 edma_irqrh[int39] edma_a channel interrupt 39 0x0db0 219 edma_irqrh[int40] edma_a channel interrupt 40 0x0dc0 220 edma_irqrh[int41] edma_a channel interrupt 41 0x0dd0 221 edma_irqrh[int42] edma_a channel interrupt 42 0x0de0 222 edma_irqrh[int43] edma_a channel interrupt 43 0x0df0 223 edma_irqrh[int44] edma_a channel interrupt 44 0x0e00 224 edma_irqrh[int45] edma_a channel interrupt 45 0x0e10 225 edma_irqrh[int46] edma_a channel interrupt 46 table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-23 pxr40 microcontroller reference manual, rev. 1 0x0e20 226 edma_irqrh[int47] edma_a channel interrupt 47 0x0e30 227 edma_irqrh[int48] edma_a channel interrupt 48 0x0e40 228 edma_irqrh[int49] edma_a channel interrupt 49 0x0e50 229 edma_irqrh[int50] edma_a channel interrupt 50 0x0e60 230 edma_irqrh[int51] edma_a channel interrupt 51 0x0e70 231 edma_irqrh[int52] edma_a channel interrupt 52 0x0e80 232 edma_irqrh[int53] edma_a channel interrupt 53 0x0e90 233 edma_irqrh[int54] edma_a channel interrupt 54 0x0ea0 234 edma_irqrh[int55] edma_a channel interrupt 55 0x0eb0 235 edma_irqrh[int56] edma_a channel interrupt 56 0x0ec0 236 edma_irqrh[int57] edma_a channel interrupt 57 0x0ed0 237 edma_irqrh[int58] edma_a channel interrupt 58 0x0ee0 238 edma_irqrh[int59] edma_a channel interrupt 59 0x0ef0 239 edma_irqrh[int60] edma_a channel interrupt 60 0x0f00 240 edma_irqrh[int61] edma_a channel interrupt 61 0x0f10 241 edma_irqrh[int62] edma_a channel interrupt 62 0x0f20 242 edma_irqrh[int63] edma_a channel interrupt 63 etpu b 0x0f30 243 etpu_cisr_b[cis0] etpu engine b channel 0 interrupt status 0x0f40 244 etpu_cisr_b[cis1] etpu engine b channel 1 interrupt status 0x0f50 245 etpu_cisr_b[cis2] etpu engine b channel 2 interrupt status 0x0f60 246 etpu_cisr_b[cis3] etpu engine b channel 3 interrupt status 0x0f70 247 etpu_cisr_b[cis4] etpu engine b channel 4 interrupt status 0x0f80 248 etpu_cisr_b[cis5] etpu engine b channel 5 interrupt status 0x0f90 249 etpu_cisr_b[cis6] etpu engine b channel 6 interrupt status 0x0fa0 250 etpu_cisr_b[cis7] etpu engine b channel 7 interrupt status 0x0fb0 251 etpu_cisr_b[cis8] etpu engine b channel 8 interrupt status 0x0fc0 252 etpu_cisr_b[cis9] etpu engine b channel 9 interrupt status 0x0fd0 253 etpu_cisr_b[cis10] etpu engine b channel 10 interrupt status 0x0feo 254 etpu_cisr_b[cis11] etpu engine b channel 11 interrupt status 0x0ff0 255 etpu_cisr_b[cis12] etpu engine b channel 12 interrupt status table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x1000 256 etpu_cisr_b[cis13] etpu engine b channel 13 interrupt status 0x1010 257 etpu_cisr_b[cis14] etpu engine b channel 14 interrupt status 0x1020 258 etpu_cisr_b[cis15] etpu engine b channel 15 interrupt status 0x1030 259 etpu_cisr_b[cis16] etpu engine b channel 16 interrupt status 0x1040 260 etpu_cisr_b[cis17] etpu engine b channel 17 interrupt status 0x1050 261 etpu_cisr_b[cis18] etpu engine b channel 18 interrupt status 0x1060 262 etpu_cisr_b[cis19] etpu engine b channel 19 interrupt status 0x1070 263 etpu_cisr_b[cis20] etpu engine b channel 20 interrupt status 0x1080 264 etpu_cisr_b[cis21] etpu engine b channel 21 interrupt status 0x1090 265 etpu_cisr_b[cis22] etpu engine b channel 22 interrupt status 0x10a0 266 etpu_cisr_b[cis23] etpu engine b channel 23 interrupt status 0x10b0 267 etpu_cisr_b[cis24] etpu engine b channel 24 interrupt status 0x10c0 268 etpu_cisr_b[cis25] etpu engine b channel 25 interrupt status 0x10d0 269 etpu_cisr_b[cis26] etpu engine b channel 26 interrupt status 0x10e0 270 etpu_cisr_b[cis27] etpu engine b channel 27 interrupt status 0x10f0 271 etpu_cisr_b[cis28] etpu engine b channel 28 interrupt status 0x1100 272 etpu_cisr_b[cis29] etpu engine b channel 29 interrupt status 0x1110 273 etpu_cisr_b[cis30] etpu engine b channel 30 interrupt status 0x1120 274 etpu_cisr_b[cis31] etpu engine b channel 31 interrupt status dspi a 0x1130 275 dspi_asr[tfuf] dspi_asr[rfof] dspi a combined overrun interrupt requests: ? transmit fifo underflow ? receive fifo overflow 0x1140 276 dspi_asr[eoqf] dspi a transmit fifo end-of-queue flag 0x1150 277 dspi_asr[tfff] dspi_a tx fifo fill request flag 0x1160 278 dspi_asr[tcf] dspi_a transfer complete flag 0x1170 279 dspi_asr[rfdf] dspi_a rx fifo drain request flag flexcan b 0x1180 280 canb_esr[boff_int] canb_esr[twrn_int] canb_esr[rwrn_int] flexcan b bus off interrupt flexcan b transmit warning interrupt flexcan b receive warning interrupt 0x1190 281 canb_esr[err_int] fl excan b error interrupt 0x11a0 282 reserved table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-25 pxr40 microcontroller reference manual, rev. 1 0x11b0 283 canb_ifrl[buf0] flexcan b buffer 0 interrupt 0x11c0 284 canb_ifrl[buf1] flexcan b buffer 1 interrupt 0x11d0 285 canb_ifrl[buf2] flexcan b buffer 2 interrupt 0x11e0 286 canb_ifrl[buf3] flexcan b buffer 3 interrupt 0x11f0 287 canb_ifrl[buf4] flexcan b buffer 4 interrupt 0x1200 288 canb_ifrl[buf5] flexcan b buffer 5 interrupt 0x1210 289 canb_ifrl[buf6] flexcan b buffer 6 interrupt 0x1220 290 canb_ifrl[buf7] flexcan b buffer 7 interrupt 0x1230 291 canb_ifrl[buf8] flexcan b buffer 8 interrupt 0x1240 292 canb_ifrl[buf9] flexcan b buffer 9 interrupt 0x1250 293 canb_ifrl[buf10] flexcan b buffer 10 interrupt 0x1260 294 canb_ifrl[buf11] flexcan b buffer 11 interrupt 0x1270 295 canb_ifrl[buf12] flexcan b buffer 12 interrupt 0x1280 296 canb_ifrl[buf13] flexcan b buffer 13 interrupt 0x1290 297 canb_ifrl[buf14] flexcan b buffer 14 interrupt 0x12a0 298 canb_ifrl[buf15] flexcan b buffer 15 interrupt 0x12b0 299 canb_ifrl[buf31:buf16] fl excan b buffers 31?16 interrupts 0x12c0 300 canb_ifrh[buf63:buf32] fl excan b buffers 63?32 interrupts system 0x12d0 301 pit[0] 0x12e0 302 pit[1] 0x12f0 303 pit[2] 0x1300 304 pit[3] 0x1310 305 rti 0x1320 306 pmc 0x1330 307 ecc correction flexcan d 0x1340 308 cand_esr[boff_int] cand_esr[twrn_int] cand_esr[rwrn_int] flexcan d bus off interrupt flexcan d transmit warning interrupt flexcan d receive warning interrupt 0x1350 309 cand_esr[err_int] flexcan d error interrupt 0x1360 310 reserved table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x1370 311 cand_ifrl[buf0] flexcan d buffer 0 interrupt 0x1380 312 cand_ifrl[buf1] flexcan d buffer 1 interrupt 0x1390 313 cand_ifrl[buf2] flexcan d buffer 2 interrupt 0x13a0 314 cand_ifrl[buf3] flexcan d buffer 3 interrupt 0x13b0 315 cand_ifrl[buf4] flexcan d buffer 4 interrupt 0x13c0 316 cand_ifrl[buf5] flexcan d buffer 5 interrupt 0x13d0 317 cand_ifrl[buf6] flexcan d buffer 6 interrupt 0x13e0 318 cand_ifrl[buf7] flexcan d buffer 7 interrupt 0x13f0 319 cand_ifrl[buf8] flexcan d buffer 8 interrupt 0x1400 320 cand_ifrl[buf9] flexcan d buffer 9 interrupt 0x1410 321 cand_ifrl[buf10] flexcan d buffer 10 interrupt 0x1420 322 cand_ifrl[buf11] flexcan d buffer 11 interrupt 0x1430 323 cand_ifrl[buf12] flexcan d buffer 12 interrupt 0x1440 324 cand_ifrl[buf13] flexcan d buffer 13 interrupt 0x1450 325 cand_ifrl[buf14] flexcan d buffer 14 interrupt 0x1460 326 cand_ifrl[buf15] flexcan d buffer 15 interrupt 0x1470 327 cand_ifrl[buf31:buf16] flexcan d buffers 31?16 interrupts 0x1480 328 cand_ifrh[buf63:buf32] fl excan d buffers 63?32 interrupts 0x1490?0x15d0 329?349 reserved for flexcan flexray 0x15e0 350 gifer[mif] flexray mif 0x15f0 351 gifer[prif] flexray prif 0x1600 352 gifer[chif] flexray chif 0x1610 353 gifer[wup_if] flexray wup_if 0x1620 354 gifer[fbne_f] flexray fbne_f 0x1630 355 gifer[fane_f] flexray fane_f 0x1640 356 gifer[rbif] flexray rbif 0x1650 357 gifer[tbif] flexray tbif 0x1660?0x16d0 358?365 reserved decimation filter b 0x16e0 366 dec_b decimation filter b input (fill) table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-27 pxr40 microcontroller reference manual, rev. 1 0x16f0 367 dec_b decimation filter b output (drain) 0x1700 368 dec_b decimation filter b error 0x1710 369 reserved 0x1720?0x1890 370?393 reserved eqadc_b 0x18a0 394 eqadc_fisr x [torf] eqadc_fisr x [rfof] eqadc_fisr x [cfuf] eqadc b combined overrun interr upt request s from all of the fifos: ? trigger overrun, ? receive fifo overflow, ? command fifo underflow 0x18b0 395 eqadc_fisr0[ncf] eqadc b co mmand fifo 6 non-coherency flag 0x18c0 396 eqadc_fisr0[pf] eqadc b command fifo 6 pause flag 0x18d0 397 eqadc_fisr0[eoqf] eqadc b command fifo 6 command queue end-of-queue flag 0x18e0 398 eqadc_fisr0[cfff] eqadc b command fifo 6 fill flag 0x18f0 399 eqadc_fisr0[rfdf] eqadc b receive fifo 6 drain flag 0x1900 400 eqadc_fisr1[ncf] eqadc b co mmand fifo 7 non-coherency flag 0x1910 401 eqadc_fisr1[pf] eqadc b command fifo 7 pause flag 0x1920 402 eqadc_fisr1[eoqf] eqadc b command fifo 7 command queue end-of-queue flag 0x1930 403 eqadc_fisr1[cfff] eqadc b command fifo 7 fill flag 0x1940 404 eqadc_fisr1[rfdf] eqadc b receive fifo 7 drain flag 0x1950 405 eqadc_fisr2[ncf] eqadc b co mmand fifo 8 non-coherency flag 0x1960 406 eqadc_fisr2[pf] eqadc b command fifo 8 pause flag 0x1970 407 eqadc_fisr2[eoqf] eqadc b command fifo 8 command queue end-of-queue flag 0x1980 408 eqadc_fisr2[cfff] eqadc b command fifo 8 fill flag 0x1990 409 eqadc_fisr2[rfdf] eqadc b receive fifo 8 drain flag 0x19a0 410 eqadc_fisr3[ncf] eqadc b co mmand fifo 9 non-coherency flag 0x19b0 411 eqadc_fisr3[pf] eqadc b command fifo 9 pause flag 0x19c0 412 eqadc_fisr3[eoqf] eqadc b command fifo 9 command queue end-of-queue flag 0x19d0 413 eqadc_fisr3[cfff] eqadc b command fifo 9 fill flag 0x19e0 414 eqadc_fisr3[rfdf] eqadc b receive fifo 9 drain flag 0x19f0 415 eqadc_fisr4[ncf] eqadc b comma nd fifo 10 non-coherency flag 0x1a00 416 eqadc_fisr4[pf] eqadc b command fifo 10 pause flag 0x1a10 417 eqadc_fisr4[eoqf] eqadc b command fifo 10 command queue end-of-queue flag table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x1a20 418 eqadc_fisr4[cfff] eqadc b command fifo 10 fill flag 0x1a30 419 eqadc_fisr4[rfdf] eqadc b receive fifo 10 drain flag 0x1a40 420 eqadc_fisr5[ncf] eqadc b comma nd fifo 11 non-coherency flag 0x1a50 421 eqadc_fisr5[pf] eqadc b command fifo 11 pause flag 0x1a60 422 eqadc_fisr5[eoqf] eqadc b command fifo 11 command queue end-of-queue flag 0x1a70 423 eqadc_fisr5[cfff] eqadc b command fifo 11 fill flag 0x1a80 424 eqadc_fisr5[rfdf] eqadc b receive fifo 11 drain flag edma_b 0x1a90 425 edma_erl[err31:err0] edma_b channel error flags 31?0 0x1aa0 426 edma_irqrl[int00] edma_b channel interrupt 0 0x1ab0 427 edma_irqrl[int01] edma_b channel interrupt 1 0x1ac0 428 edma_irqrl[int02] edma_b channel interrupt 2 0x1ad0 429 edma_irqrl[int03] edma_b channel interrupt 3 0x1ae0 430 edma_irqrl[int04] edma_b channel interrupt 4 0x1af0 431 edma_irqrl[int05] edma_b channel interrupt 5 0x1b00 432 edma_irqrl[int06] edma_b channel interrupt 6 0x1b10 433 edma_irqrl[int07] edma_b channel interrupt 7 0x1b20 434 edma_irqrl[int08] edma_b channel interrupt 8 0x1b30 435 edma_irqrl[int09] edma_b channel interrupt 9 0x1b40 436 edma_irqrl[int10] edma_b channel interrupt 10 0x1b50 437 edma_irqrl[int11] edma_b channel interrupt 11 0x1b60 438 edma_irqrl[int12] edma_b channel interrupt 12 0x1b70 439 edma_irqrl[int13] edma_b channel interrupt 13 0x1b80 440 edma_irqrl[int14] edma_b channel interrupt 14 0x1b90 441 edma_irqrl[int15] edma_b channel interrupt 15 0x1ba0 442 edma_irqrl[int16] edma_b channel interrupt 16 0x1bb0 443 edma_irqrl[int17] edma_b channel interrupt 17 0x1bc0 444 edma_irqrl[int18] edma_b channel interrupt 18 0x1bd0 445 edma_irqrl[int19] edma_b channel interrupt 19 0x1be0 446 edma_irqrl[int20] edma_b channel interrupt 20 0x1bfo 447 edma_irqrl[int21] edma_b channel interrupt 21 table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-29 pxr40 microcontroller reference manual, rev. 1 0x1c00 448 edma_irqrl[int22] edma_b channel interrupt 22 0x1c10 449 edma_irqrl[int23] edma_b channel interrupt 23 0x1c20 450 edma_irqrl[int24] edma_b channel interrupt 24 0x1c30 451 edma_irqrl[int25] edma_b channel interrupt 25 0x1c40 452 edma_irqrl[int26] edma_b channel interrupt 26 0x1c50 453 edma_irqrl[int27] edma_b channel interrupt 27 0x1c60 454 edma_irqrl[int28] edma_b channel interrupt 28 0x1c70 455 edma_irqrl[int29] edma_b channel interrupt 29 0x1c80 456 edma_irqrl[int30] edma_b channel interrupt 30 0x1c90 457 edma_irqrl[int31] edma_b channel interrupt 31 0x1ca0 458 reserved emios 0x1cb0 459 emios_gfr[f24] emios channel 24 flag 0x1cc0 460 emios_gfr[f25] emios channel 25 flag 0x1cd0 461 emios_gfr[f26] emios channel 26 flag 0x1ce0 462 emios_gfr[f27] emios channel 27 flag 0x1cf0 463 emios_gfr[f28] emios channel 28 flag 0x1d00 464 emios_gfr[f29] emios channel 29 flag 0x1d10 465 emios_gfr[f30] emios channel 30 flag 0x1d20 466 emios_gfr[f31] emios channel 31 flag decimation filter c 0x1d30 467 dec_c decimation filter c input (fill) 0x1d40 468 dec_c decimation filter c output (drain) 0x1d50 469 dec_c decimation filter c error decimation filter d 0x1d60 470 dec_d decimation filter d input (fill) 0x1d70 471 dec_d decimation filter d output (drain) 0x1d80 472 dec_d decimation filter d error esci c table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) 10-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the peripheral or software configurable interrupt request asserts when the pri n value in the interrupt priori ty select register (intc_psr n ) is greater than the pri n value in interrupt current priority register (intc_cpr). if an asserted peripheral or software configurable interr upt request negates before the processor acknowledges it s request, the interrupt request can reassert and remain asserted. if th is occurs, the processor uses the intc_psr n value to locate the irq vector, and updates the pri n value in the intc_cpr with the pri n value in intc_psr n . 0x1d90 473 escic_sr[tdre] escic_sr[tc] escic_sr[rdrf] escic_sr[idle] escic_sr[or] escic_sr[nf] escic_sr[fe] escic_sr[pf] escic_sr[berr] escic_sr[rxrdy] escic_sr[txrdy] escic_sr[lwake] escic_sr[sto] escic_sr[pberr] escic_sr[cerr] combined interrupt requests of esci module c: ? lin status register 1 ? lin status register 2 ? sci status register 2 ? transmit data register empty ? transmit complete ? receive data register full ? idle line ?overrun ? noise flag ? framing error flag ? parity error flag interrupt requests ? bit error interrupt request ? receive data ready ? transmit data ready ? received lin wakeup signal ? slave timeout ? physical bus error ? crc error 0x1da0 474 reserved 0x1db0 475 reserved decimation filter e?h 0x1dc0 476 dec_e decimation filter e 0x1dd0 477 dec_f decimation filter f 0x1de0 478 dec_g decimation filter g 0x1df0 479 dec_h decimation filter h 1 the maximum vector number (479) is used to identify the location of the last available interrupt vector in memory for this devi ce. because blocks of memory throughout the total memory map ar e used for other purposes, the maximum vector number does not indicate the total number of available interrupt sources for this device. 2 interrupt requests from the same mo dule location are ored together. table 10-8. interrupt request sources (continued) hardware vector mode offset vector number 1 source 2 description
interrupts and interrupt controller (intc) freescale semiconductor 10-31 pxr40 microcontroller reference manual, rev. 1 clearing the peripheral interrupt reque st enable bit for the peripheral initiating the request, or setting the irq mask bit has the same consequences as clearing its flag bit. setting its enable bit or cl earing its mask bit while its flag bit is asserted has the same effect on the intc as an interrupt event setting the flag bit. 10.4.1.1 peripheral interrupt requests an interrupt event in a peripheral?s ha rdware sets a flag bit which resides in that pe ripheral. the interrupt request from the peripheral is driven by that flag bit. the time from when the peripheral starts to drive its peripheral interrupt request to the intc to the time that the intc starts to drive the interrupt request to the processor is three clocks. 10.4.1.2 software configurable interrupt requests the software set/clear inte rrupt registers (intc_sscir x_x ) support the setti ng or clearing of software-configurable interrupt request s. these registers contain eight inde pendent sets of bits to set and clear a corresponding flag bit by software. with the except ion of being set by software , this flag bit behaves the same as a flag bit set within a peripheral. this flag bit generates an interrupt request within the intc just like a peripheral interrupt request. an interrupt request is triggered by software writing a 1 to the set n bit in intc software set/clear interrupt registers (intc_sscir0?int c_sscir7). this write sets a clr n flag bit that generates an interrupt request. the interrupt request is cleared by writing a 1 to the clr n bit. specific behavior includes the following: ? writing a 1 to set n leaves set n unchanged at 0 but sets the flag bit (clr n bit). ? writing a 0 to set n has no effect. ? writing a 1 to clr n clears the flag (clr n ) bit. ? writing a 0 to clr n has no effect. ? if a 1 is written to a pair of set n and clr n bits at the same time, the flag (clr n ) is set, regardless of whether clr n was asserted before the write. the time from the write to the set n bit to the time that the intc starts to drive the interrupt request to the processor is four clocks. 10.4.1.3 unique vector for each interrupt request source each peripheral and software confi gurable interrupt request is assigne d a hardwired unique 9-bit vector. software configurable interrupts 0?7 are assigned vectors 0?7, respectively. the peripheral interrupt requests are assigned vectors 8 to as high as needed to c over all of the periphera l interrupt requests. 10.4.2 priority management the asserted interrupt requests are comp ared to each other based on their pri n values in intc priority select registers (intc_psr0?intc_psr 479). the result of that comparison also is compared to pri in
interrupts and interrupt controller (intc) 10-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 intc current priority register (i ntc_cpr). the results of those comparisons are used to manage the priority of the isr being executed by the processor. the lifo also as sists in managing that priority. 10.4.2.1 current prio rity and preemption the priority arbitrator, selector, encode r, and comparator submodules shown in figure 10-1 are used to compare the priority of the asserted interrupt requests to the current priority. if th e priority of any asserted peripheral or software configurable interrupt request is higher than the current priority, then the interrupt request to the processor is asserted. also, a unique vector for the preempti ng peripheral or software configurable interrupt request is generated for intc interrupt acknow ledge register (intc_iackr), and if in hardware vector mode, for the in terrupt vector provided to the processor. 10.4.2.1.1 priority ar bitrator submodule the priority arbitrator submodule compares all the priori ties of all of the assert ed interrupt requests, both peripheral and software configurable . the output of the priority arbitr ator submodule is the highest of those priorities. also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the request selector submodule. 10.4.2.1.2 request se lector submodule if only one interrupt request from the priority arbitrator submo dule is asserted, then it is passed as asserted to the vector encoder submodule. if mu ltiple interrupt requests from the priority arbitrat or submodule are asserted, then only the one with the lowest vector is passed as asserted to the vector encoder submodule. the lower vector is chosen regardless of the time or der of the assertions of the peripheral or software configurable interrupt requests. 10.4.2.1.3 vector encoder submodule the vector encoder submodule generates the unique 9-bit vector for the asserted in terrupt request from the request selector submodule. 10.4.2.1.4 priority co mparator submodule the priority comparator submodule compares the highe st priority output from the priority arbitrator submodule with pri in intc_c pr. if the priority comparator submodul e detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the processor. this interrupt request to the processor asserts whether this highest priority is raised above the value of pri in intc_cpr or the pri value in intc_cpr is lowered be low this highest priority. this high est priority then becomes the new priority which is written to pri in intc_cpr when the interrupt request to the processor is acknowledged. interrupt requests whose pri n in intc_psr n are zero does not cause a preemption because their pri n is not higher than pri in intc_cpr. another function of the pr iority comparator subblock is to signa l an update of the intc_iackr_prc0 and intc_iackr_prc1 with th e vector number of the first interrupt th at arrives that has a priority higher than the current priority. once the vector number and priority are captured, they cannot be superseded by a higher priority interrupt until an update of the intc_cpr_p rc0 or intc_cpr_prc1 occurs.
interrupts and interrupt controller (intc) freescale semiconductor 10-33 pxr40 microcontroller reference manual, rev. 1 one consequence of the priority co mparator design is that once a highe r priority interrupt request is captured, it must be acknowledged by the cpu before a subsequent interrupt request of even higher priority can be captured. for example, if the cpu is executing a priority level 1 interrupt, and a priority level 2 interrupt request is captured by the intc, fo llowed shortly by a priority level 3 interrupt request, the level 2 interrupt must be acknow ledged by the cpu before a new leve l 3 interrupt will be generated. 10.4.2.2 lifo the lifo stores the preempted pri values from the intc_cpr. therefore, becau se these priorities are stacked within the intc, if interrupt s need to be enabled during the isr, at the beginning of the interrupt exception handler the pri value in the intc_cpr does not need to be loaded from the intc_cpr and stored onto the context stack. likewise at the end of the interrupt exce ption handler, the priority does not need to be loaded from the context stack and stored in to the intc_cpr. the pri value in the intc_cpr is pushed onto the li fo when the intc_iackr is read in software vector mode or the interrupt acknowl edge signal from the processor is as serted in hardware vector mode. the priority is popped into pri in the in tc_cpr whenever the intc_eoir is written. although the intc supports 16 priorities , an isr executing with pri in the intc_cpr equal to 15 is not preempted. therefore, the lifo supp orts the stacking of 15 priorities . however, the lifo is only 14 entries deep. an entry for a prior ity of 0 is not needed because of how pushing onto a full lifo and popping an empty lifo are treat ed. if the lifo is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. a priority of 0 is an ove rwritten priority. however, the lifo pop zeros if it is popped more times than it is pushed. therefore, alth ough a priority of 0 was overw ritten, it is regenerated with the popping of an empty lifo. the lifo is not memory mapped. 10.4.3 details on hand shaking with processor 10.4.3.1 software vect or mode handshaking 10.4.3.1.1 acknowledging inte rrupt request to processor a timing diagram of the interrupt request and acknow ledge handshaking in software vector mode, along with the handshaking near th e end of the interrupt exce ption handler, is shown in figure 10-14 . the intc examines the peripheral and software configurable interrupt requests. when it finds an asserted peripheral or software configurable interrupt re quest with a higher priority than pri in intc current priority register (intc_cpr), it asserts the interrupt request to th e processor. the intvec field in intc interrupt acknowledge register (intc_iackr) is updated with the preempting inte rrupt request?s vector when the interrupt request to the processor is asserted. the intv ec field retains that value until the next time the interrupt request to the proce ssor is asserted. the rest of the handshaking is described in section 10.1.4.1, software vector mode .
interrupts and interrupt controller (intc) 10-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 10.4.3.1.2 end-of-inter rupt exception handler before the interrupt exception handli ng completes, intc end-of-interrupt register (intc_eoir) must be written. when it is written, the lifo is popped so that the preempted priori ty is restored into pri of the intc_cpr. before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configur able interrupt request is negated. note to ensure proper operation across all power architecture mcus, execute an mbar or msync instruction between the access to clear the flag bit and the write to the intc_eoir. when returning from the preemption, the intc does not search for the pe ripheral or software configurable interrupt request whose isr was pr eempted. depending on how much the isr progressed, that interrupt request can no longer be asserted. when pri in intc _cpr is lowered to the priority of the preempted isr, the interrupt request for the pr eempted isr or any other asserted pe ripheral or software configurable interrupt request at or be low that priority does not cause a preemption. instead, af ter the restoration of the preempted context, the processor return s to the instruction address that it was to next execute before it was preempted. this next instruction is part of the pree mpted isr or the interrupt exception handler?s prolog or epilog. figure 10-14. software vector mode handshaking timing diagram 10.4.3.2 hardware vector mode handshaking a timing diagram of the in terrupt request and acknow ledge handshaking in hard ware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 10-15 . as in software vector mode, the intc exam ines the peripheral and software c onfigurable interrupt requests, and when it finds an asserted one with a higher priority than pri in intc_cpr, it as serts the interrupt request clock interrupt request to processor hardware vector enable interrupt acknowledge interrupt vector read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 0 0 108 10
interrupts and interrupt controller (intc) freescale semiconductor 10-35 pxr40 microcontroller reference manual, rev. 1 to the processor. the intvec field in the intc_i ackr is updated with the preempting peripheral or software configurable interr upt request?s vector when the interrupt re quest to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. in addition, the value of the interrupt v ector to the processor matches the value of the intvec field in the intc_iackr. the rest of the handshaking is described in section 10.1.4.2, hardware vector mode . the handshaking near the end of the interrupt excepti on handler, that is the wri ting to the intc_eoir, is the same as in software vector mode. refer to section 10.4.3.1.2, end-of-interrupt exception handler . figure 10-15. hardware vector mode handshaking timing diagram 10.5 initialization and application information 10.5.1 initialization flow after exiting reset, all of the pri n fields in intc priority select registers (intc_psr0?intc_psr479) is zero, and pri in intc current pr iority register (intc_cpr) is 15. th ese reset values prevent the intc from asserting the interrupt request to the processor. the enable or mask bits in the peripherals are reset such that the peripheral in terrupt requests are negated. an initialization sequence that allows the periphera l and software configurab le interrupt requests to generate an interrupt reque st to the processor is: interrupt_request_initialization: configure vtes and hven in intc_mcr configure vtba in intc_iackr raise the pri n fields in intc_psr n set the enable bits or clear the mask bits for the peripheral interrupt requests lower pri in intc_cpr to zero enable processor recognition of interrupts clock interrupt request to processor hardware vector enable interrupt acknowledge interrupt vector read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 0108 0 108 01
interrupts and interrupt controller (intc) 10-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 10.5.2 interrupt exception handler these example interrupt exception handlers use power architecture assembly code. 10.5.2.1 software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save srr0 and srr1 lis r3,intc_iackr@ha # form adjusted upper half of intc_iackr address lwz r3,intc_iackr@l(r3) # load intc_iackr, which clears request to processor lwz r3,0x0(r3) # load address of isr from vector table wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi mtlr r3 # move the intc_iackr address into the link register blrl # branch to isr; link register updated with epilog # address epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi vector_table_base_address: address of isr for interrupt with vector 0 address of isr for interrupt with vector 1 . . . address of isr for interrupt with vector 510 address of isr for interrupt with vector 511 isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # return to epilog
interrupts and interrupt controller (intc) freescale semiconductor 10-37 pxr40 microcontroller reference manual, rev. 1 10.5.2.2 hardware vector mode this interrupt exception handler is useful with processor and system bus implementations that support a hardware vector. in this example, each interrupt_exception_handler x has space for only four instructions, and therefore a branch to interrupt_ exception_handler_continued x is needed. interrupt_exception_handler x : b interrupt_exception_handler_continued x # 4 instructions available, branch to continue interrupt_exception_handler_continued x : code to create stack frame, save working register, and save srr0 and srr1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi bl isr x # branch to isr for interrupt with vector x epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # branch to epilog 10.5.3 isr, rtos, and task hierarchy the rtos and all of the tasks under it s control typically execute with pri in intc current priority register (intc_cpr) having a value of 0. the rtos execute the tasks according to whatever priority scheme that it has, but that priority sc heme is independent and has a lower priority of execution than the priority scheme of the intc. in other words, the is rs execute above intc_cpr priority 0 and outside th e control of the rtos, the rtos executes at intc_cpr priority 0, an d while the tasks execute at different priorities under the control of the rtos, they al so execute at intc_cpr priority 0. if a task shares a resource with an isr and the pcp is being used to mana ge that shared resource, then the task?s priority can be elevated in the intc _cpr while the shared resource is being accessed.
interrupts and interrupt controller (intc) 10-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 an isr whose pri n in intc priority select registers (int c_psr0?intc_psr479) has a value of 0 does not cause an interrupt request to the processor, even if its peripheral or softwa re configurable interrupt request is asserted. for a peripheral interrupt request, not setting its enable bit or disabling the mask bit causes it to remain negated, which consequently also does not cause an interrupt request to the processor. since the isrs are outside the control of the rtos, this isr does not run unless called by another isr or the interrupt exception handler, perh aps after executing another isr. 10.5.4 order of execution an isr with a higher priority can pr eempt an isr with a lower priority , regardless of the unique vectors associated with each of their periphe ral or software configur able interrupt requests. however, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the intc selects the one with the lowest unique vector regardless of the order in time that they assert ed. however, the ability to meet deadlines with this scheduling scheme is no less than if the isrs execute in the time order that their peripheral or software configurable interrupt requests asserted. the example in table 10-9 shows the order of execution of both is rs with different priorities, and with the same priority. table 10-9. order of isr execution example step step description code executing at end of step pri in intc_cpr at end of step rtos isr108 1 isr208 isr308 isr408 interrupt exception handler 1 rtos at priority 0 is executing. x 0 2 peripheral interrupt request 100 at priority 1 asserts. interrupt taken. x1 3 peripheral interrupt request 400 at priority 4 asserts. interrupt taken. x4 4 peripheral interrupt request 300 at priority 3 asserts. x4 5 peripheral interrupt request 200 at priority 3 asserts. x4 6 isr408 completes. interrupt exception handler writes to intc_eoir. x1 7 interrupt taken. isr208 starts to execute, even though peripheral interrupt request 300 asserted first. x3 8 isr208 completes. interrupt exception handler writes to intc_eoir. x1 9 interrupt taken. isr308 starts to execute. x3
interrupts and interrupt controller (intc) freescale semiconductor 10-39 pxr40 microcontroller reference manual, rev. 1 10.5.5 priority ceiling protocol 10.5.5.1 elevating priority the pri field in intc current priori ty register (intc_cpr) is elevated in the osek pcp to the ceiling of all of the priorities of the isrs that share a res ource. this protocol therefor e allows coherent accesses of the isrs to that shared resource. for example, isr1 has a priority of 1, isr2 has a priority of 2, and isr3 has a priority of 3. they all share the same resource. before isr1 or isr2 can access that resource, they must raise the pri value in intc_cpr to 3, the ceiling of all of the isr priorities. after they rel ease the resource, the pri value in intc_cpr can be lowe red. if they do not raise their priority, th en isr2 can preempt isr1, and isr3 can preempt isr1 or isr2, possibly co rrupting the shared resource. anot her possible failure mechanism is deadlock if the higher priority isr needs the lower pr iority isr to release the resource before it can continue, but the lower priority isr can not release the resource until the higher priority isr completes and execution returns to the lower priority isr. using the pcp instead of disabli ng processor recognition of all inte rrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. for ex ample, while isr3 cannot preempt isr1 while it is accessing the shared resource, all of the isrs with a priority higher than 3 can preempt isr1. 10.5.5.2 ensuring coherency 10.5.5.2.1 interrupt with blocked priority non-coherent accesses to a shared resource can occur. as an example, isr1 and isr2 both share a resource. isr1 has a lower priority, therefore it executes and then writes the new pri value in the current priority register (intc_cpr). the next instruction writes a value to a shared coherent data block. if intc asserts the isr2 interrupt reque st to the processor just before or at the same time as the first isr1 write, it is possible for bot h the isr1 and isr2 writes to execute while the pro cessor responds to the intc 10 isr308 completes. interrupt exception handler writes to intc_eoir. x1 11 isr108 completes. interrupt exception handler writes to intc_eoir. x0 12 rtos continues execution. x 0 1 isr108 executes for peripheral interrupt request 100 because th e first eight isrs are for software configurable interrupt requests. table 10-9. order of isr execution example (continued) step step description code executing at end of step pri in intc_cpr at end of step rtos isr108 1 isr208 isr308 isr408 interrupt exception handler
interrupts and interrupt controller (intc) 10-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 request, discards the transactions, and flushes the pr ocessing pipeline. however, isr2 cannot access the data block coherently because the data block is now corrupted. osek uses the getresource and rele aseresource system services to mana ge access to a shared resource. to prevent corrupting a coherent data block, use th e following code to modify the pri in intc_cpr. interrupts must be enabled before executi ng the following getr esource code sequence: getresource: raise pri mbar isync releaseresource: mbar lower pri 10.5.5.2.2 raised priority preserved before the instruction after the getresource system service executes, all pendi ng transactions have completed. these pending transactions can include an isr for a peripheral or soft ware settable interrupt request whose priority was equal to or lower than the raised priority. also, during the epilog of the interrupt exception handler for this preempting isr, the raised priority has been restored from the lifo to pri in intc_cpr. the shared coherent data block now can be accessed coherently. figure 10-16 shows the timing diagram for this scenario, and table 10-10 explains the events. the exam ple is for software vector mode, but except for the method of retrieving the vect or and acknowledging the interrupt request to the processor, hardware vector mode is identical.
interrupts and interrupt controller (intc) freescale semiconductor 10-41 pxr40 microcontroller reference manual, rev. 1 figure 10-16. raised priority preserved timing diagram table 10-10. raised priority preserved events event description a peripheral interrupt request 200 asserts during execution of isr108 running at priority 1. b interrupt request to processor asserts. intvec in intc _iackr updates with vector for that peripheral interrupt request. c isr108 writes to intc_cpr to raise priority to 3 before accessing shared coherent data block. d pri in intc_cpr now at 3, reflecting the write. this write, just before accessing data bloc k, is the last instruction the processor executes before being interrupted. e interrupt exception handler prolog acknow ledges interrupt by reading intc_iackr. f pri of 3 pushed onto lifo. pri in intc_cpr updates to 2, the priority of isr208. g isr208 clears its flag bit, deasserting its peripheral interrupt request. h interrupt exception handler epilog writes to intc_eoir. i lifo pops 3, restoring the raised priority onto pri in in tc_cpr. next value to pop from lifo is the priority from before peripheral interrupt request 100 interrupted. isr1 08 now can access data block coherently after interrupt exception handler executes rfi instruction. last in / first out entry in lifo write intc_cpr clock interrupt request to processor hardware vector enable interrupt acknowledge interrupt vector read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108 1 208 23 peripheral interrupt request 200 030 3 a b c d e f g h i
interrupts and interrupt controller (intc) 10-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 10.5.6 selecting priorities ac cording to request rates and deadlines the selection of the priorities for the isrs can be made using rate monotonic scheduling (rms) or a superset of it, deadline monotonic scheduling (dms). in rms, the is rs which have higher request rates have higher priorities. in dms, if th e deadline is before the next time th e isr is requested, then the isr is assigned a priority according to the time from the request for the isr to the deadline, not from the time of the request for the isr to the next request for it. for example, isr1 executes every 100 ? s, isr2 executes every 200 ? s, and isr3 executes every 300 ? s. isr1 has a higher priority than isr2 which has a hi gher priority than isr3. however, if isr3 has a deadline of 150 ? s, then it has a higher priority than isr2. the intc has 16 priorities, which can be much less than the number of isrs. in this case, group the isrs with other isrs that have similar deadlines. for exam ple, when a priority is allocated for every time the request rate doubles: isrs with reque st rates around 1 ms share a priori ty; isrs with request rates around 500 ? s share a priority; isrs with request rates around 250 ? s share a priority, etc. with this approach, a range of isr request rates of 2 16 can be covered, regardless of the number of isrs. reducing the number of priorities doe s reduce the processor's ability to meet its deadlines. however, it also allows easier management of isrs with similar deadlines that share a resource. they do not need to use the pcp to access the shared resource. 10.5.7 software configur able interrupt requests the software configurable interrupt requests can be used in two ways. they can be used to schedule a lower priority portion of an isr a nd for processors to interrupt other processors in a multiple processor system. 10.5.7.1 scheduling a lower priority portion of an isr a portion of an isr needs to be executed at the pri n value in intc prior ity select registers (intc_psr0?intc_psr479), which becomes the pri value in intc current priority register (intc_cpr) with the interrupt acknowledgement. the is r, however, can have a por tion of it which does not need to be executed at this higher priority. ther efore, executing this later portion which does not need to be executed at this higher priori ty can prevent the execution of isrs which do not have a higher priority than the earlier portion of the isr but do have a higher priority than what the later portion of the isr needs. this preemptive scheduling ineffi ciency reduces the processor's ability to meet its deadlines. one option is for the isr to complete the earlier higher priority portion, but then schedule through the rtos a task to execute the later lower priority por tion. however, some rtoss can require a large amount of time for an isr to schedule a task. therefore, a second option is fo r the isr, after co mpleting the higher priority portion, to set a set n bit in intc software set/clear interrupt registers (intc_sscir0?intc_sscir7). writing a 1 to set n causes a software confi gurable interrupt request. this software configurable interrupt request, which usually has a lower pri n value in the intc_psr n , therefore does not cause preemptive scheduling inefficiencies.
interrupts and interrupt controller (intc) freescale semiconductor 10-43 pxr40 microcontroller reference manual, rev. 1 after generating a software configur able interrupt request, the higher pr iority isr completes. the lower priority isr is scheduled according to its priority. execution of the highe r priority isr is not resumed after the completion of the lower priority isr. 10.5.7.2 scheduling an is r on another processor since the set n bits in the intc_sscir n are memory mapped, processors in multiple processor systems can schedule isrs on the other proce ssors. one application is that one processor simply wants to command another processor to perfor m a piece of work, and the initiating processor does not need to use the results of that work. if the initiating proc essor is concerned that processor executing the software configurable isr has not completed the work before asking it to again execute that isr, it can check if the corresponding clr n bit in intc_sscir n is asserted before again writing a 1 to the set n bit. another application is the sharing of a block of data. for example, a first processor has completed accessing a block of data and wants a second processo r to then access it. furt hermore, after the second processor has completed accessing th e block of data, the first proce ssor again wants to access it. the accesses to the block of data must be done coherently. the procedure is that the first processor writes a 1 to a set n bit on the second processor. the second processor, after accessing the block of data, clears the corresponding clr n bit and then writes 1 to a set n bit on the first processor, informing it that it now can access the block of data. 10.5.8 lowering priori ty within an isr in implementations without the software-configurable interrupt requests in the intc software set/clear interrupt registers (intc_sscir0?i ntc_sscir7), a way ? besides sc heduling a task through an rtos ? to prevent preemptive scheduling in efficiencies with an isr whose wo rk spans multiple priorities (as described in section 10.5.7.1, scheduling a lower pr iority portion of an isr ) is to lower the current priority. however, the intc has a lifo whose depth is determined by the number of priorities. note lowering the pri value in intc curr ent priority register (intc_cpr) within an isr to below the isr?s co rresponding pri value in intc priority select registers (intc_psr0?intc_psr 479) allows more preemptions than the depth of the lifo can support. therefore, through its use of the lifo the intc does not support loweri ng the current priority within an isr as a way to avoid preempt ive scheduling inefficiencies. 10.5.9 negating an interrupt request outside of its isr 10.5.9.1 negating an interrupt request as a side effect of an isr some peripherals have flag bits wh ich can be cleared as a side effect of servicing a pe ripheral interrupt request. for example, reading a sp ecific register can clear the fl ag bits, and consequently their corresponding interrupt requests too. this clearing as a side effect of servic ing a peripheral interrupt request can cause the negation of other peripheral inte rrupt requests besi des the peripheral interrupt request
interrupts and interrupt controller (intc) 10-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 whose isr presently is executing. this negating of a peripheral interrupt request outside of its isr can be a desired effect. 10.5.9.2 negating multiple in terrupt requests in one isr an isr can clear other flag bits besides its own flag bit. one reason that an isr clears multiple flag bits is because it serviced those other fl ag bits, and therefore the isrs for th ese other flag bits do not need to be executed. 10.5.9.3 proper setting of interrupt request priority whether an interrupt request negates outside of its own isr due to the si de effect of an isr execution or the intentional clearing a flag bit, th e priorities of the peri pheral or software config urable interrupt requests for these other flag bits must be selected properly. their pri n values in intc priority select registers (intc_psr0?intc_psr479) must be selected to be at or lower than the priority of the isr that cleared their flag bits. otherwise, those flag bits still can cause the interrupt request to the processor to assert. furthermore, the clearing of these ot her flag bits also has the same ti ming relationship to the writing to intc end-of-interrupt regist er (intc_eoir) as the clear ing of the flag bit that caused the present isr to be executed. refer to section 10.4.3.1.2, end-of-inter rupt exception handler , for more information. a flag bit whose enable bit or mask bit is negating its peripheral interrupt reque st can be cleared at any time, regardless of the peripheral interrupt request?s pri n value in intc_psr n . 10.5.10 examining lifo contents normally you do not need to know the contents of th e lifo, or even how deep the lifo is nested. although the lifo contents are not memory mapped, you can read the contents by popping the lifo and reading the pri field in the intc current priority register (intc_cp r). disabling processor recognition of interrupts while examining the lifo contents provi des a coherent view of the preempted priorities. the code sequence is: pop_lifo: store to intc_eoir load intc_cpr, examine pri, and store onto stack if pri is not zero or value when interrupts were enabled, branch to pop_lifo when you are finished examining the lifo contents, you can restore it in software vector mode using the following code sequence. in hardware vector mode, reading the intc_i ackr does not push the intc_cpr[pri] onto the lifo, therefor e the lifo contents cannot be rest ored in hardware vector mode. push_lifo: load stacked pri value and store to intc_cpr load intc_iackr if stacked pri values are not depleted, branch to push_lifo
interrupts and interrupt controller (intc) freescale semiconductor 10-45 pxr40 microcontroller reference manual, rev. 1 note reading the intc_iackr acknowledges the interrupt request to the processor and updates the intc_cpr[p ri] with the priority of the preempting interrupt request. if the pr ocessor recognition of interrupts is disabled during the lifo re storation, interrupt reque sts to the processor can go undetected. however, since the peri pheral or software configurable interrupt requests are not cleared, th e peripheral interrupt request to the processor re-asserts when intc_cpr[pri ] is lower than the priorities of those peripheral or software c onfigurable interrupt requests.
interrupts and interrupt controller (intc) 10-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 11-1 pxr40 microcontroller reference manual, rev. 1 chapter 11 general-purpose static ram (sram) 11.1 introduction the sram provides 256 kb of general-purpose stat ic ram (sram). the firs t 32 kb of sram is powered by a separate power supply pin for standby operation. figure 11-1 shows the internal sram block diagram. figure 11-1. internal sram block diagram the sram controller has these features: ? read/write accesses can map to sram from any master ? 32 kb with a separate power source for standby operation ? byte, halfword, word, and doubleword addressable ?8-bit ecc 11.2 sram operating modes table 11-1 lists and describes th e sram operating modes. 11.3 external signal description the external signal for sram is the v stby ram power supply. if the standby feature of the sram is not used, tie the v stby pin to v ss . table 11-1. sram operating modes mode description normal (functional) allows reads and writes of sram. standby preserves the 32 kb of standby memory when the v dd (1.5 v) power drops below the level of v stby (0.8?1.2 v) . updates to standby sram are inhibited during system reset or during standby mode. sram v stby 32 kb standby sram
general-purpose static ram (sram) 11-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 11.4 register memory map the sram occupies 256 kb of memory star ting at the base address as shown in table 11-2 . the internal sram has no regist ers. registers for the sram ecc are located in the ecsm. see chapter 17, error correction status module (ecsm) , for more information. 11.5 functional description ecc checks are performed during the read portion of an sram ecc read/wri te (r/w) operation, and ecc calculations are performed dur ing the write portion of a read/w rite (r/w) operation. because the ecc bits can contain random data after the device is powered on, you must initialize the sram by executing 64-bit write instructions to the entire sram. for more information, see section 11.7, initialization and appl ication information . 11.6 sram ecc mechanism the sram ecc detects the following condi tions and produces the following results: ? detects and corrects all 1-bit errors ? detects and flags all 2-bit erro rs as non-correctable errors ? detects 72-bit reads (64-bit data bus plus the 8-bit ecc) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag sram does not detect all errors gr eater than 2 bits. internal sram writes are done on byte boundaries: ? 1 byte (0:7 bits) ? 2 bytes (0:15 bits) ? 4 bytes or 1 word (0:31 bits) ? 8 bytes or 2 words (0:63 bits) if the entire 64 data bits are written to sram, no re ad operation is performed and the ecc is calculated across the 64-bit data bus. the 8-bit ecc is appended to the data segment and written to sram. if the write operation is less than the entire 64-bit data wi dth (1-, 2-, or 4-byte segment), the following occurs: 1. the ecc mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or flagging errors. 2. the write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64 bits on the data bus. 3. the ecc is then calculated on the resulti ng 64 bits formed in the previous step. 4. the 8-bit ecc result is appended to the 64 bits from the data bus, and th e 72-bit value is then written to sram. table 11-2. sram memory map address register name register description size base (0x4000_0000) ? sram powered by v stby 32 kb base + 0x8000 ? 224-kb ram 224 kb
general-purpose static ram (sram) freescale semiconductor 11-3 pxr40 microcontroller reference manual, rev. 1 11.6.1 access timing the system bus is a two-stage pipe lined bus, which makes the timing of any access dependent on the access during the previous clock. table 11-3 lists the various combin ations of read and wr ite operations to sram and the number of wait states used for the each operation. the table columns contain the following information: current operation lists the type of sram operation executing currently previous operation lists the valid types of sram operations that can precede the current sram operation (valid operation dur ing the preceding clock) wait states lists the number of wait states (bus clocks) the operation requires which depends on the combination of the cu rrent and previous operation table 11-3. number of wait states required for sram operations current operation previou s operation number of wait states required read operation read idle 1 pipelined read burst read 64-bit write 2 8-, 16-, or 32-bit write 0 (read from the same address) 1 (read from a different address) pipelined read read 0 burst read idle 1,0,0,0 pipelined read burst read 64-bit write 2,0,0,0 8-, 16-, or 32-bit write 0,0,0,0 (read from the same address) 1,0,0,0 (read from a different address)
general-purpose static ram (sram) 11-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 11.6.2 reset effects on sram accesses if a reset event asserts during a read or write opera tion to sram, the completion of that access depends on the cycle at which the reset occurs. data read from or written to sram before the reset event occurred is retained, and no other address locations are accessed or changed. if the system sram is cached, cache lines can retain indeterminate data that is not written to memory unless the region is se t for write-through mode. note standby memory can contain the previous data values if a reset occurs while cache is running in copy back mode. 11.7 initialization and application information to use the sram, the ecc must check all bits that require initialization after power on. use a 64-bit cache-inhibited write to each sram location to initia lize the sram array as part of the application initialization code. all writes must specify an even number of regist ers performed on 64-bit word-aligned boundaries. if the write is not the enti re 64-bits (8-, 16-, or 32-bits), a read / modify / write operation is generated that checks the ecc value upon the read. see section 11.6, sram ecc mechanism . note you must initialize sram, even if th e application does not use ecc reporting. write operation 8-, 16-, or 32-bit write idle 1 read pipelined 8-, 16-, or 32-bit write 2 64-bit write 8-, 16-, or 32-bit write 0 (write to the same address) pipelined 8-, 16-, or 32-bit write 8-, 16-, or 32-bit write 0 64-bit write idle 0 64-bit write read 64-bit burst write idle 0,0,0,0 64-bit write read table 11-3. number of wait states required for sram operations (continued) current operation previou s operation number of wait states required
general-purpose static ram (sram) freescale semiconductor 11-5 pxr40 microcontroller reference manual, rev. 1 11.7.1 example code to initialize sram correctly, use a store multiple word ( stmw) instruction to implem ent 64-bit writes to all sram locations. the stmw instruction concatenates two 32-bit registers to implem ent a single 64-bit write. to ensure the writes are 64-bits, specify an even number of registers and write on 64-bit word-aligned boundaries. the following example code illustrates the use of the stmw instruction to initialize the sram ecc bits. init_ram: lis r11,0x4000 # base address of the sram, 64-bit word aligned ori r11,r11,0 # not needed for this address but could be for others li r12,2048 # loop counter to get all of sram; # 256*1024/4 bytes/32 gprs =2048 mtctr r12 init_ram_loop: stmw r0,0(r11) # write all 32 gprs to sram addi r11,r11,128 # inc the ram ptr; 32 gprs * 4 bytes = 128 bdnz init_ram_loop # loop for 256k of sram blr # done
general-purpose static ram (sram) 11-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 12-1 pxr40 microcontroller reference manual, rev. 1 chapter 12 flash memory array and control 12.1 introduction this section presents information about the following components on this device: ? the flash memory blocks ? the flash memory controller the primary function of the flash memory module is to serve as electrically programmable and erasable non-volatile memory. the nvm memory can be used for instruction and data storage. the flash memory module contains two physical arrays (flash_a and flash_b) that are organized to provide a contiguous address range for program code and data. each flash array has three address spaces: low-address space, mid-address spac e, and high-address space that are subdivided into blocks as shown in figure 12-1 .
flash memory array and control 12-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 12-1. flash segmentation 12.1.1 block diagram 12.1.1.1 flash memory module figure 12-3 shows a block diagram of the flash memory module. program ex ecution and data fetches from the flash module are performed thro ugh the fbiu. control and status registers, used for flash memory reprogramming purposes are accessed through pbridge_a. note: the first 16 bytes of every 32-byte aligned row fall in array a and the last 16 bytes fall in array b. flash_a array blocks 128-bits wide flash_b array blocks 128-bits wide low address space 256kb (128 bits wide) 8 x16 kb + 2 x 64 kb mid address space 256kb (128 bits wide) 2 x128 kb low address space 256kb (128 bits wide) 1 x 256 kb mid address space 256kb (128 bits wide) 1 x 256 kb high address space 3mb (256 bits wide) 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb 1 x 256 kb
flash memory array and control freescale semiconductor 12-3 pxr40 microcontroller reference manual, rev. 1 figure 12-2. flash memory module block diagram 12.1.2 features the flash memory module has these major features: ? support for a 64-bit data bus for instruction fetch. ? support for a 32-bit data bus for cpu loads and dma access. byte, halfword, word and doubleword reads are supported. only aligned word and doubleword wr ites are supported. ? configurable read buffering and line prefetch suppor t. two sets of buffers (one for 128-bit accesses and one for 256-bit accesses) and a prefetch cont roller are used to support single-cycle read responses for hits in the buffers. ? hardware and software configur able read and write access protec tions on a per-master basis. ? interface to the flash array c ontroller is pipelined with a dept h of 1, allowing overlapped accesses to proceed in parallel. ? configurable access timing allowing use in a wide range of system frequencies. ? multiple-mapping support and mapping-based bl ock access timing (0-31 additional cycles) allowing use for emulati on of other memory types. flash bus interface unit ( fbiu ) flash memory flash_a array flash core control/status registers interface (mi) flash memory flash_b array flash core control/status registers interface (mi) xbar pbridge_a
flash memory array and control 12-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? software programmable block progr am/erase restriction control for low, mid and high address spaces. ? erase of selected block(s). ? read page size of 128 bits (l ow/mid-address space) and 256 bi ts (for high-address space). ? ecc with single-bit correction, single- bit detection, and double-bit detection. ? minimum program size is 2 cons ecutive 32 bit words, aligned on a 0-modulo-8 byte address, due to ecc. ? embedded hardware program and erase algorithm. ? read while write with multiple partitions. ? erase suspend, program suspe nd and erase-suspended program. ? automotive flash which meets automotive endurance and reliability requirements. ? shadow information stored in non-volatile shadow block. ? independent program/erase of the shadow block. 12.1.3 modes of operation 12.1.3.1 flash user mode user mode is the default operating mode of the flash module. in this mode , it is possible to read and write, program and erase the flash module. 12.1.3.2 user test mode user test (utest) mode is where a portion of the freescale test modes are made available to end users. this mode is protected, but accessible. 12.2 memory map and registers this section provides a detailed descri ption of all flash memory registers. 12.2.1 module memory map the flash memory map is shown below. the addresses are given as an offset to the flash memory base address. there are no program-visible registers that physically re side in the flash. the flas h controller contains the registers to control and configure the flash (see table 12-3 ). only reference these registers with 32-bit accesses.
flash memory array and control freescale semiconductor 12-5 pxr40 microcontroller reference manual, rev. 1 table 12-2 shows the shadow block space. the 16k region of the shadow block for flash b space mirrors from 0x00e0_0000 to 0x00ef_ffff and shadow a mirrors every 16k from 0x00f0_0000 through 0x00ff_ffff. mirrored operation is not guaranteed flash_a and flash_b arrays have se parate configuration and control registers for programming and erase operations. flash bus configuration re gisters are common to both arrays. table 12-1. memory map offset from flash_base (0x0000_0000) use flash a block flash b block partition flash a block size flash b block size data width 0x0000_0000 low-address space (flash a) l0 ? 1 16k ? 128 0x0000_4000 l1 ? 16k ? 128 0x0000_8000 l2 ? 16k ? 128 0x0000_c000 l3 ? 16k ? 128 0x0001_0000 l4 ? 2 16k ? 128 0x0001_4000 l5 ? 16k ? 128 0x0001_8000 l6 ? 16k ? 128 0x0001_c000 l7 ? 16k ? 128 0x0002_0000 l8 ? 3 64k ? 128 0x0003_0000 l9 ? 64k ? 128 0x0004_0000 mid-address space (flash a) m0 ? 4 128k ? 128 0x0006_0000 m1 ? 128k ? 128 0x0008_0000 low-address space (flash b) ? l0 5 ? 256k 128 0x000c_0000 mid-address space (flash b) ? m0 ? 256k 128 0x0010_0000 high-address space 1 1 see figure 12-1 to see how flash a and flash b, together, make up the high address space. h0 h0 6 256k 256k 256 0x0018_0000 h1 h1 256k 256k 256 0x0020_0000 h2 h2 7 256k 256k 256 0x0028_0000 h3 h3 256k 256k 256 0x0030_0000 h4 h4 8 256k 256k 256 0x0038_0000 h5 h5 256k 256k 256 0x0040_0000 reserved 0x00ef_c000 shadow block (flash b space) (see ta b l e 1 2 - 2 ) ? s0 all 2 2 for read while write operations, the shadow row behaves as if it is in all partitions. ? 16k 128 0x00ff_c000 shadow block (flash a space) (see ta b l e 1 2 - 2 ) s0 ? 16k ? 128 0x0100_c000 reserved
flash memory array and control 12-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 12-2. shadow block memory map offset from flash_base (0x0000_0000) shadow block use 0x00ef_c000 flash b general use 0x00ef_dde8 flash_b_lmlr reset configuration 0x00ef_ddf0 flash_b_hlr reset configuration 0x00ef_dde8 flash_b_slmlr reset configuration 0x00ff_c000?0x00ff_fdd7 flash a general use 0x00ff_fdd8 serial passco de (0xfeed_face_cafe_beef) 0x00ff_fde0 censorship control word (0x55aa_55aa) 0x00ff_fde4 general use 0x00ff_fde8 flash_a_lmlr reset configuration (0x0010_0000) 0x00ff_fdec general use 0x00ff_fdf0 flash_a_hlr reset configuration (0x0fff_ffff) 0x00ff_fdf4 general use 0x00ff_fdf8 flash_a_slmlr reset configuration (0x000f_ffff) 0x00ff_fe00 flash_biucr2 reset configuration (0xffff_ffff) 0x00ff_fdfc?0x00ff_ ffff general use table 12-3. flash configuration register memory map offset from flash_regs_ base (0xc3f8_8000) register bits access reset value 1 section/page 0x0000 flash_a_mcr?module config uration register 32 r/w 0x0000_0400 12.2.2.1/12-8 0x0004 flash_a_lmlr?low-/mid-address space block locking register 32 r/w ? 12.2.2.2/12-12 0x0008 flash_a_hlr?high-address space block locking register 32 r/w ? 12.2.2.3/12-14 0x000c flash_a_slmlr?secondary low-/mid-address space block locking register 32 r/w ? 12.2.2.4/12-16 0x0010 flash_a_lmsr?low-/mid-address space block select register 32 r/w 0x0000_0000 12.2.2.5/12-17 0x0014 flash_a_hsr?high-address space block select register 32 r/w 0x0000_0000 12.2.2.6/12-18 0x0018 flash_a_ar?address register 32 r/w 0x0000_0000 12.2.2.7/12-18 0x001c flash_biucr?flash bus interface configuration register 32 r/w 0x0000_ff00 12.2.2.8/12-19 0x0020 flash_biuapr?flash bus interface access protection register 32 r/w 0xffff_ffff 12.2.2.9/12-22
flash memory array and control freescale semiconductor 12-7 pxr40 microcontroller reference manual, rev. 1 12.2.2 register descriptions this section lists the flash memory re gisters in address order and describes the register s and their bit fields. note each of the two flash arrays (fla sh_a and flash_b) have separate configuration registers and control registers for programming and erase operations. in the following register de scriptions, the letter ?x? represents ?a? for flash_a registers, and ?b? for flash_b registers. registers without the ?x? designator are common to both arrays and are used to control the flash bus interface. 0x0024 flash_biucr2?flash bus interface configuration register 2 32 r/w ? 12.2.2.10/12-23 0x0028 ? 0x0038 reserved 0x003c flash_a_ut0?utest 0 register 32 r/w 0x0000_0001 12.2.2.11/12-24 0x0040 flash_a_ut1?utest 1 register 32 r/w 0x0000_0001 12.2.2.12/12-27 0x0044 flash_a_ut2?utest 2 register 32 r/w 0x0000_0001 12.2.2.13/12-27 0x0048 ? 0x3fff reserved 0x4000 flash_b_mcr?module config uration register 32 r/w 0x0000_0400 12.2.2.1/12-8 0x4004 flash_b_lmlr?low-/mid-address space block locking register 32 r/w ? 12.2.2.2/12-12 0x4008 flash_b_hlr?high-address space block locking register 32 r/w ? 12.2.2.3/12-14 0x400c flash_b_slmlr?secondary low-/mid-address space block locking register 32 r/w ? 12.2.2.4/12-16 0x4010 flash_b_lmsr?low-/mid-address space block select register 32 r/w 0x0000_0000 12.2.2.5/12-17 0x4014 flash_b_hsr?high-address space block select register 32 r/w 0x0000_0000 12.2.2.6/12-18 0x4018 flash_b_ar?address register 32 r/w 0x0000_0000 12.2.2.7/12-18 0x401c ? 0x4038 reserved 0x403c flash_b_ut0?utest 0 register 32 r/w 0x0000_0001 12.2.2.11/12-24 0x4040 flash_b_ut1?utest 1 register 32 r/w 0x0000_0001 12.2.2.12/12-27 0x4044 flash_b_ut2?utest 2 register 32 r/w 0x0000_0001 12.2.2.13/12-27 0x4048 ? 0x7fff reserved 1 a value of ??? means that the register is loaded from the shadow block described in figure 12-2 . table 12-3. flash configuration register memory map offset from flash_regs_ base (0xc3f8_8000) register bits access reset value 1 section/page
flash memory array and control 12-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12.2.2.1 module configurat ion register (flash_ x _mcr) the flash _ x_mcr register is defined figure 12-3 and table 12-4 . offset 0x0000 / 0x4000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 size 0 las 0 0 0 mas w reset 0 0 0 0 0 1 0 1 0 ? 1 ? 1 ? 1 000? 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eer rwe sbc 0 peas done peg 0 0 0 0 pgm psus ers esus ehv w w1c w1c w1c reset 0 0 0 0 0 1 1 0 0 0000000 1 see register description below. figure 12-3. module configurat ion register (flash_x_mcr) table 12-4. flash_x_mcr field descriptions field description 0?4 reserved 5?7 size array space size. the value of the size field is dependen t upon the size of the flash array. size is read only. 101 2.0 mb. (256 kb of las, 256 kb of mas, and 1.5 mb of has) (both flash_a and flash_b) all others are reserved. 8 reserved 9?11 las[2:0] low address space. the value of the las field corre sponds to the configurat ion of the low address space. las is read only. 000 one 256 kb blocks. (flash_b) 100 eight 16 kb, two 64 kb blocks. (flash_a) all others are reserved. 12?14 reserved 15 mas mid address space. the value of the mas field corre sponds to the configuration of the mid address space. mas is read only. 0 two 128 kb blocks. (flash_a) 1 one 256 kb blocks. (flash_b) 16 eer ecc event error. eer provides information on previous reads. if a double bit detection occurred, the eer bit is set to a 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. this bit may not be set by the user. in the event of a si ngle bit detection and correction, this bit is not be set. if eer is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of eer) are correct. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0 reads are occurring normally. 1 an ecc error occurred during a previous read.
flash memory array and control freescale semiconductor 12-9 pxr40 microcontroller reference manual, rev. 1 17 rwe read while write event error. rwe provides information on previous rww reads. if a read while write error occurs, this bit is set to 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. this bit may not be written to a 1 by the user. if rwe is not set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) are correct. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0 reads are occurring normally. 1 a read while write error occurred during a previous read. 18 sbc single bit correction. sbc provides information on previous reads provided the flash_x_ut0[spce] is set. if a single bit correction occurred, the sbc bit is se t to a 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. if sbc is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of sbc) did not r equire a correction. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to t he register location. a write of 0 has no effect. 0 reads are occurring without corrections. 1 a single bit correction occurred during a previous read. 19 reserved 20 peas program/erase access space. peas is used to indica te which space is valid for program and erase operations, either main array space or shadow spac e. peas = 0 indicates that the main address space is active for all fc program and eras e operations. peas = 1 indi cates the shadow address space is active for program/erase. the value in peas is captured a nd held when the shadow block is enabled with the first interlock write done for program or erase operat ions. the value of peas is retained between sampling events (i.e. subsequent first interlock writes). the value in peas may be changed during erase-suspended program, and reverts back to its? or iginal state once the erase-suspended program is completed. peas is read only. 0 shadow address space is disabled for program/erase and main address space enabled. 1 shadow address space is enabled for program/erase and main address space disabled. 21 done state machine status. done indicate s if the flash module is performing a high voltage operation. done is set to a 1 on termination of the flash module re set. done is read only. done is cleared within tdone of a 0 to 1 transition of ehv which initiates a high voltage operation. done is cleared within tres of resuming a suspended operation. done is set to a 1 at the end of program and erase high voltage sequences. done is set to a 1 within tdones of a 1 to 0 transition of ehv which aborts a high voltage operation. 0 flash is executing a high voltage operation. 1 flash is not executing a high voltage operation. 22 peg program/erase good. the peg bit indicates the comple tion status of the last flash program or erase sequence for which high voltage operations were init iated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation causes peg to be cleared, indicating the sequence fa iled. peg is set to a 1 wh en the module is reset. peg is read only. the value of peg is valid only when pgm = 1 and/or ers = 1 and after done transitions from 0 to 1 due to an abort or the completion of a program/erase o peration. peg is valid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 transition of done caused by psus or esus being set to logic 1. if pg m and ers are both 1 when done makes a qualifying 0 to 1 transition the value of peg indicates the comp letion status of the pgm sequence. this happens in an erase-suspended program operation. 0 program or erase operation failed. 1 program or erase operation successful. note: if program or erases are attempted on blocks that are locked, the response from flash is peg = 1, indicating that the operation was successful, and th e contents of the block are properly protected from the program or erase operation. table 12-4. flash_x_mcr field descriptions (continued) field description
flash memory array and control 12-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23?26 reserved 27 pgm program. pgm is used to set up flash for a program operation. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under one of the following conditions: ? user mode read (ers is low and ute is low). ? erase suspend (ers and esus are 1) with ehv low. pgm can be cleared by the user only when psus and ehv are low and done is high. pgm is cleared on reset. 0 flash is not executing a program sequence. 1 flash is executing a program sequence. note: in an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt fc data. this should be avoided due to reliability implications. 28 psus program suspend. psus is used to indicate the flash module is in program suspend or in the process of entering a suspend state. the module is in program suspend when psus = 1 and done = 1. psus can be set high only when pgm and ehv are high. a 0 to 1 transition of psus starts the sequence which sets done and places the flash module in program suspe nd. the module enters susp end within tpsus of this transition. psus can be cleared only when done and ehv are high. a 1 to 0 transition of psus with ehv = 1 starts the sequence which clears done and returns the flash module to program. the module cannot exit program suspend and clear done while ehv is low. psus is cleared on reset. 0 program sequence is not suspended. 1 program sequence is suspended. 29 ers erase. ers is used to set up flash for an erase oper ation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can only be set only in user mode read (pgm is low and ute is low). ers can be clear ed by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0 flash is not executing an erase sequence. 1 flash is executing an erase sequence. table 12-4. flash_x_mcr field descriptions (continued) field description
flash memory array and control freescale semiconductor 12-11 pxr40 microcontroller reference manual, rev. 1 12.2.2.1.1 flash_x_mcr simu ltaneous bit write priority a number of flash_x_mcr bits are pr otected against write wh en another bit, or set of bits, is in a specific state. these write locks ar e covered on a bit by bit basis in th e preceding section. the write locks detailed in the previous section do not consider the effects of trying to write two or more bits simultaneously. the effects of writ ing bits simultaneously which put the module in an illegal state are detailed here. the flash module does not allow the user to write bits simultaneously wh ich put the device into an illegal state. this is implemented through a priority mech anism among the bits. the bit changing priorities are detailed in table 12-5 . 30 esus erase suspend. esus is used to indicate that the flash module is in erase suspend or in the process of entering a suspend state. the module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is lo w. a 0 to 1 transition of esus starts the sequence which sets done and places the flash in erase susp end. the flash module enters suspend within tesus of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1 to 0 transition of esus with ehv = 1 starts the sequence which clears done and returns the module to erase. the flash module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0 erase sequence is not suspended. 1 erase sequence is suspended. 31 ehv enable high voltage. the ehv bit enables the flash module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set, initiating a program/erase, after an interlock under one of the following conditions: ? erase (ers = 1, esus = 0). ? program (ers = 0, esus = 0, pgm = 1, psus = 0). ? erase-suspended program (ers = 1, esus = 1, pgm = 1, psus = 0). if a program operation is to be initiated while an eras e is suspended the user must clear ehv while in erase suspend before setting pgm. in normal operation, a 1 to 0 transition of eh v with done high, psus and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 tr ansition of ehv with done low and the suspend bit for the current program/erase sequence low. an abort c auses the value of peg to be cleared, indicating a failed program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a suspended operation cannot be aborted. ehv may be written during suspend. ehv must be high for the flash module to exit suspend. ehv may not be written after a suspend bit is set high and before done transitions high. ehv may not be set low after the current suspend bit is set low and before done transitions low. 0 flash is not enabled to perform a high voltage operation. 1 flash is enabled to perform a high voltage operation. note: aborting a high voltage operation leaves fc addresse s in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. table 12-4. flash_x_mcr field descriptions (continued) field description
flash memory array and control 12-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if the user attempts to write two or more flash _x_mcr bits simultaneously then only the bit with the lowest priority level is wr itten. setting two bits with the same priority level is prevented by existing write locks or do not put the flash in an illegal state. for example, setting ers and pgm simultaneously re sults in only ers being set. attempting to clear ehv while setting psus results in ehv being cleared, while psus is unaffected. 12.2.2.2 low/mid address space bl ock locking register (flash_ x _lmlr) the low/mid address block locki ng register (flash_x_lmlr) provide s a means to protect blocks from being modified. these bits, along with bits in the secondary llock (flash_ x _slmlr), determine if the block is locked from program or erase. an ?or? of flash_ x _lmlr and flash_x_slmlr determine the final lock status. note a reset value of 1* in figure 12-4 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. the following field and bit de scriptions fully define th e flash_x_lmlr register ( figure 12-4 ). flash_x_lmlr register functions, as shown in table 12-6 . table 12-5. flash_x_mcr bit set/clear priority levels priority level flash_x_mcr bit(s) 1ers 2pgm 3ehv 4 esus, psus offset 0x0004 / 0x4004 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 121314 15 16171819202122232425262728293031 r lme 0 00000000 0 slock 00 mlock 000000 llock w reset 0 0 0 0 0 0 0 0 0 0 0 1* 0 0 1* 1* 0 0 0 0 0 0 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* figure 12-4. flash_x_lmlr register
flash memory array and control freescale semiconductor 12-13 pxr40 microcontroller reference manual, rev. 1 table 12-6. flash_x_lmlr field descriptions field description 0 lme low/mid address lock enable. this bit is used to enable the lock registers (slock, mlock and llock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to se t this bit is to write a password, and if the password matches, the lme bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. for lme, the password 0xa1a1_1111 must be written to the flash_x_lmlr register. 0 low/mid address locks are disabled, and can not be modified. 1 low/mid address locks are enabled to be written. 1?10 reserved 11 slock shadow lock. this bit is used to lock the shadow block from programs and erases. a value of 1 in the slock register signifies that the shadow block is locked for program and erase. a value of 0 in the slock register signifies that the shadow block is available to receive program and erase pulses. the slock register is not writable once an interloc k write is completed until flash_x_mcr[done] is set at the completion of the requested operation. likewise , slock register is not writable if a high voltage operation is suspended. slock is also not writ eable during utest operations, when aie is high. upon reset, information from the shadow block is loaded into the slock register. the slock bit may be written as a register. reset causes the bits to go back to their shadow block value. the default value of the slock bits (assuming erased shadow location) is locked. slock is not writable unless lme is high. 12?13 reserved 14?15 mlock[1:0] mid address space block lock. a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lock register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for mid address space is given in the table below, and is different for flash_a and flash_b. the lock register is not writable once an interl ock write is completed until flash_x_mcr[done] is set at the completion of the requested operation. likewise, the lock register is not writable if a high voltage operation is suspended. mlock is also not writea ble during utest operations, when aie is high. upon reset, information from the shadow block is l oaded into the block registers. the lock bits may be written as a register. reset causes the bits to go back to their shadow block value. the default value of the lock bits (assuming erased shadow location) is locked. in the event that blocks are not present (due to c onfiguration or total memory size), the lock bits default to be locked, and are not writable. the reset value is always 1 (independent of the shadow block), and register writes have no effect. mlock is not writable unless lme is high. mlock bit flash_a block flash_b block 0m0 m0 1 m1 none
flash memory array and control 12-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12.2.2.3 high address sp ace block locking register (flash_x_hlr) the high address space block locking register (flash_x_hlr) provides a me ans to protect blocks from being modified. note a reset value of 1* in figure 12-5 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. the following field and bit descriptions fully define the flash_x_hlr register ( figure 12-5 ). 16?21 reserved 22?31 llock low address space block lock. a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lock register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for low address space is given in the table below, and is different for flash_a and flash_b. for more details on llock, please see mlock bit description. llock is not writable unless lme is high. table 12-6. flash_x_lmlr fiel d descriptions (continued) field description llock bit flash_a block flash_b block 0l0 l0 1 l1 none 2 l2 none 3 l3 none 4 l4 none 5 l5 none 6 l6 none 7 l7 none 8 l8 none 9 l9 none
flash memory array and control freescale semiconductor 12-15 pxr40 microcontroller reference manual, rev. 1 flash_x_hlr register fu nctions, as shown in table 12-7 . offset 0x0008 / 0x4008 access: user read/write 0 12345678910111213141516171819202122232425262728293031 rhb e 000000000000000000000 hlock w reset 0 0000000000000000000001*1*1*1*1*1*1*1*1*1* figure 12-5. flash_x_hlr register table 12-7. flash_x_hlr field descriptions field description 0 hbe high address lock enable this bit is used to enable the lock registers (hlock) to be set or cleared by register writes. this bit is a st atus bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the hbe bit is set to reflect the status of enabled, and is enabled un til a reset operation occurs. for hbe, the password 0xb2b2_2222 must be written to the flash_x_hlr register. 0 high address locks are disabled, and can not be modified. 1 high address locks are enabled to be written. 1?21 reserved 22?31 hlock high address space block lock. hlock has the same characteristics as llock. please see this description for more information. the block numbering for high address space is given in the table below, and is the same for flash_a and flash_b. hlock is not writable unless hbe is high. hlock bit flash_a block flash_b block 0h0 h0 1h1 h1 2h2 h2 3h3 h3 4h4 h4 5h5 h5 6h6 h6 7h7 h7 8h8 h8 9h9 h9
flash memory array and control 12-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12.2.2.4 secondary low/mid address space block locking register (flash_x_slmlr) the secondary low/mid address block locking regi ster (flash_x_slmlr) prov ides an alternative means to protect blocks from being modified. this has the effect of creating a ?tiered? locking scheme to enable different flash users to provide different default locking on blocks. thes e bits, along with bits in the llock (flash_x_lmlr), determine if the block is locked from program or erase. an ?or? of flash_x_lmlr and flash_x_slmlr de termine the final lock status. note a reset value of 1* in figure 12-6 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. the following field and bit de scriptions fully define th e flash_x_slmlr register ( figure 12-6 ). note writing the password 0xc3c3_3333 to this register does not modify the sslock, smlock, or sllock fields. only the sle bit changes. flash_x_slmlr register functions, as shown in table 12-8 . offset 0x000c / 0x400c access: user read/write 0 123456 7 8910 11 1213141516171819202122232425262728293031 r sle000000 0 000 ss lock 00 sm lock 000000 sllock w reset 0 000000 0 000 1* 0 01*1* 0000001*1*1*1*1*1*1*1*1*1* figure 12-6. flash_x_slmlr register table 12-8. flash_x_slmlr field descriptions field description 0 sle secondary low/mid address lock enable. this bi t is used to enable the lock registers (sslock, smlock, and sllock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the sl e bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle, the password 0xc3c3_3333 must be written to the flash_x_slmlr register 0 secondary low/mid address locks are disabled, and can not be modified. 1 secondary low/mid address locks are enabled to be written. 1?10 reserved 11 sslock secondary shadow lock. this bit is an alternative method that may be used to lock the shadow block from programs and erases. sslock has the same description as slock in the flash_x_lmlr register (see figure 12-4 ). sslock is not writable unless sle is high. 12?13 reserved
flash memory array and control freescale semiconductor 12-17 pxr40 microcontroller reference manual, rev. 1 12.2.2.5 low/mid address space bloc k select register (flash_x_lmsr) the low/mid address space block sele ct register (flash_ x_lmsr) provides a mean s to select blocks to be operated on during erase. the following field and bit de scriptions fully define th e flash_x_lmsr register ( figure 12-7 ). flash_x_lmsr register f unctions, as shown in table 12-9 . 14?15 smlock secondary mid address block lock. this bit is an alternative method that may be used to lock the mid address space blocks from programs and er ases. smlock has the same description as mlock in the flash_x_lmlr register. smlock is not writable unless sle is high. 16?21 reserved 22?31 sllock secondary low address block lock. this bit is an alternative method that may be used to lock the low address space blocks from programs and erases. sllock has the same description as llock in the flash_x_lmlr register. sllock is not writable unless sle is high. offset 0x0010 / 0x4010 access: user read/write 012345678910111213141516171819202122232425262728293031 r0000000000000 0 msel 000000 lsel w reset0000000000000 0 0 00000000000000000 figure 12-7. flash_x_lmsr register table 12-9. flash_x_lmsr field descriptions field description 0?13 reserved 14?15 msel mid address space block select. a value of 1 in the sele ct register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected. the reset value for the select registers is 0, or un-selected. the blocks must be selected (or un-selected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until flash_x_mcr[done] is set at the completion of the requested operation, or if a high voltage operation is suspended. msel is also not writeable during utest operations, when aie is high. in the event that blocks are not pres ent (due to configuration or total memory size), the corresponding select bits default to un-selected, and are not writab le. the reset value is always 0, and register writes have no effect. msel bits are mapped to block numbers in the sa me way as described for the mlock bits of the flash_x_lmlr register. table 12-8. flash_x_slmlr field descriptions (continued) field description
flash memory array and control 12-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12.2.2.6 high address sp ace block select register (flash_x_hsr) the high address space block select register (flash _x_hsr) provides a means to select blocks to be operated on during erase. the following field and bit descriptions fully define the flash_x_hsr register ( figure 12-8 ). flash_x_hsr register fu nctions, as shown in table 12-10 . 12.2.2.7 address register (flash_x_ar) the address register (flash_x_ar) provides the first failing address in the event module failures (ecc or pgm/erase state machine). this a ddress is the internal array address. to convert to a logical system address, a formula must be applied: 16?21 reserved 22?31 lsel[9:0] low address space block select. a value of 1 in the se lect register signifies that the block is selected for erase. a value of 0 in the select register signifie s that the block is not selected. the reset value for the select registers is 0, or un-selected. the blocks must be selected (or un-selected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until flash_x_mcr[done] is set at the completion of the requested operation, or if a high voltage operation is suspended. lsel is also not writeable during utest operations, when aie is high. in the event that blocks are not pres ent (due to configuration or total memory size), the corresponding select bits default to un-selected, and are not writab le. the reset value is always 0, and register writes have no effect. lsel bits are mapped to block numbers in the same way as described for the llock bits of the flash_x_lmlr register. offset 0x0014 / 0x4014 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000000000000000000 hsel w reset00000000000000000000000000000000 figure 12-8. flash_x_hsr register table 12-10. flash_x_hsr field descriptions field description 0?24 reserved 26?31 hsel[5:0] high address space block select. high address block select has the same characteristics as lsel. table 12-9. flash_x_lmsr field descriptions (continued) field description
flash memory array and control freescale semiconductor 12-19 pxr40 microcontroller reference manual, rev. 1 the following field and bit descriptio ns fully define the flash_x_ar ( figure 12-9 ). flash_x_ar functions, as shown in table 12-11 . 12.2.2.8 flash bus interface confi guration register (flash_biucr) flash_biucr is used to specify opera tion of the dual-flash controller. th is register must not be written while executing from flash. array address range operation a 0x00_0000 - 0x07_ffff no change a 0x08_0000 - 0x1f_ffff logical address[17:3] = addr[16:4],0,addr[3]} b 0x00_0000 - 0x07_ffff add 0x08_0000 b 0x08_0000 - 0x1f_ffff logical address[17:3] = addr[16:4],1,addr[3]} offset 0x0018 / 0x4018 access: user read/write 0 12345678910111213141516171819202122232425262728293031 rsad000000000000 0 addr 000 w reset 0 000000000000 0 0 00000000000000000 figure 12-9. flash_x_ar register table 12-11. flash_x_ar field descriptions field description 0 sad shadow address. the sad bit qualifies the address captured during an ecc event error, single bit correction, or state machine operation. the sad register is not writable. 0 address captured is from main array space. 1 address captured is from shadow array space. 1?13 reserved 14?28 addr[17:3] address. the flash_x_ar provides the first failing address in the event of ecc event error (flash_x_mcr[eer] set), single bit correction (flash_x_mcr[sbc] set), as well as providing the address of a failure that may have occurred in a state machine operation (flash_x_mcr[peg] cleared). ecc event errors take priority over single bit corrections, which take priority over state machine errors. this is especially valuable in t he event of a rww operation, where the read senses an ecc error or single bit correction, and the state ma chine fails simultaneously. this address is always a double word address that selects 64 bits. the flash_x_ar is writable, and can be used in the utest ecc logic check. if the ecc logic check is enabled (flash_x_ut0[eie] = 1) then the flash_ x_ar will not update for ecc event error, single bit correction or state machine errors. if flash_x_mcr[eer] or flash_x_mcr[sbc] are set, the flash_x_ar is locked from writing. flash_x_mcr[peg] does not affect the writability of the flash_x_ar. 29?31 reserved
flash memory array and control 12-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 offset: 0x001c access: user read/write 0123456 7 8 9 10 11 12 13 14 15 r0000000 m8pfe 0 m6pfe m5pfe m4pfe 000 m0pfe w reset0000000 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r apc wwsc rwsc 0 dpfen 0 ifpfen 0 pflim bfen w reset1111111 1 0 0 0 0 0 0 0 0 figure 12-10. flash bus interface conf iguration register (flash_biucr) table 12-12. flash_biucr field descriptions field description 0?15 m n pfe master n prefetch enable, where n represents the master id number in the table below. these bits are used to control whether prefetching may be triggered based on the master id of a requesting master. these bits are cleared by hardware reset. 0 no prefetching may be triggered by this master 1 prefetching may be triggered by this master note: these bits refer to the master id, not the master port number, as shown in the following: 16?18 apc address pipelining control. this field is used to c ontrol the number of cycles between pipelined access requests. it must be set to a value corresponding to the operating frequency of the flash.higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b111 by hardware reset. 000 accesses may be pipelined back-to-back 001 access requests require one additional hold cycle 010 access requests require two additional hold cycles ... 110 access requests requir e six additional hold cycles 111 no address pipelining note: the settings for apc and rwsc must be the same. note: valid settings are specified in product data sheet. master id module 0z7 core 1 ? reserved ? 2 ? reserved ? 3 ? reserved ? 4edma_a 5edma_b 6flexray
flash memory array and control freescale semiconductor 12-21 pxr40 microcontroller reference manual, rev. 1 19?20 wwsc write wait state control - this field is used to co ntrol the number of wait-states to be added to the best-case flash array access time for writes. the best -case flash array access time for writes is two cycles. this field must be set to a value corresponding to the operating frequency of the flash. higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b11 by hardware reset. 00 no additional wait-states are added 01 one additional wait-state is added 10 two additional wait-states are added 11 three additional wait-states are added 21?23 rwsc read wait state control - this field is used to c ontrol the number of wait-states to be added to the best-case flash array access time for reads. the best-c ase flash array access time for reads is one cycle. this field must be set to a value corresponding to th e operating frequency of the flash and the actual read access time of the flash. higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b111 by hardware reset. 000 no additional wait-states are added 001 one additional wait-state is added ... 111 seven additional wait-states are added note: the settings for apc and rwsc must be the same. note: valid settings are specified in the product data sheet. 24 reserved 25 dpfen data prefetch enable - this field enables or disables prefetching initiated by a data read access. this field is cleared by hardware reset. 0 no prefetching is triggered by a data read access 1 prefetching may be triggered by any data read access 26 reserved 27 ipfen instruction prefetch enable - this bit enables or di sables prefetching initiated by an instruction read access. this field is cleared by hardware reset. 0 no prefetching is triggered by an instruction read access 1 prefetching may be triggered by any instruction read access 28 reserved 29?30 pflim flash prefetch limit - this field controls the prefetch algorithm used by the flash prefetch controller. this field defines a limit on the maximum number of seq uential prefetches which will be attempted between buffer misses. in all situations when enabled, only a sing le prefetch is initiated on each buffer miss or hit. this field is cleared by hardware reset. 00 no prefetching or buffering is performed. 01 the referenced line is prefetched on a buffer miss, i.e., prefetch on miss. 1x the referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if not already present), i.e., prefetch on miss or hit. 31 bfen flash line read buffers enable - this bit enables or disables line read buffer hits. it is also used to invalidate the buffers. this bit is cleared by hardware reset. 0 the line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 the line read buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. table 12-12. flash_biucr field descriptions
flash memory array and control 12-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12.2.2.9 flash bus interf ace access protection register (flash_biuapr) this register is used to control bus master r ead and write access attri butes to the flash array. offset: 0x0020 access: user read/write 0123456789101112131415 r11111111111111 m8ap w reset1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1 1 m6ap m5ap m4ap 111111 m0ap w reset1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1* figure 12-11. flash bus interface access protection register (flash_biuapr) table 12-13. flash_biuapr bit field descriptions field description 0?1316?17 24?29 reserved 14?15 18?23 30?31 m n ap master n access protection, where n represents the master id number in the table below. these fields are used to control whether read and write accesses to the flash are allowed based on the master id of a requesting master. 00 no accesses may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master note: these bits refer to the master id, not the master port number, as shown in the following: master id module 0z7 core 1? reserved ? 2? reserved ? 3? reserved ? 4edma_a 5edma_b 6flexray 7 reserved for ebi test (not for customer use) 8 z7 nexus
flash memory array and control freescale semiconductor 12-23 pxr40 microcontroller reference manual, rev. 1 12.2.2.10 flash bus interface confi guration register 2 (flash_biucr2) note a reset value of 1* in figure 12-12 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. offset: 0x0024 access: user read/write 0123456789101112131415 r lbcfg 00000000000000 w reset1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1* figure 12-12. flash bus interface conf iguration register 2 (flash_biucr2) table 12-14. flash_biucr2 bit field descriptions field description 0?1 lbcfg_p0 line buffer configuration. this field controls the confi guration of all the line buffers in the flash bus interface unit. the buffers can be organized as a ?pool? of avai lable resources, or with a fixed partition between instruction and data buffers. in all cases, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and the just-fetched entry then marked as most-recently-us ed. if the flash access is for the next-sequential line, the buffer is not marked as most-recently-use d until the given address produces a buffer hit. this field is initialized by hardware reset to the va lue contained in address0x00ff_fe00 of the shadow block of the flash array. the initial value is given in ta b l e 1 2 - 2 . this field controls the configuration of both the 4 x 128 and 4 x 256 line buffers. 00 all four buffers are available for any flash access, i.e ., there is no partitioning of the buffers based on the access type. 01 reserved 10 the buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 the buffers are partitioned into two groups with buffer s 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. 2?31 reserved
flash memory array and control 12-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note a reset value of 1* in figure 12-13 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. 12.2.2.11 user test register 0 (flash_x_ut0) the user test register 0 (flash_x _ut0) provides a means to control utest. the utest mode gives the users of the flash module the ability to perform test features on the fl ash. this register is only writable when the flash is put into utest mode by writing a passcode. offset: 0x0024 access: user read/write 0123456789101112131415 r lbcfg 00000000000000 w reset1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1* figure 12-13. flash bus interface conf iguration register 2 (flash_biucr2) offset: 0x003c / 0x403c access: user read/write 0123456789101112131415 r ute scbe 000000 dsi w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 ea 0 mre mrv eie ais aie aid w reset0000000010000001 figure 12-14. user test register 0 (flash_x_ut0)
flash memory array and control freescale semiconductor 12-25 pxr40 microcontroller reference manual, rev. 1 table 12-15. flash_x_ut0 field descriptions field description 0 ute utest enable. this status bit gives indication when ut est is enabled. all bits in flash_x_ut0, flash_x_ut1, flash_x_ut2 are locked when this bit is 0. this bit is not writeable to a 1, but may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabled until it is clear ed by a register write. the ute password will only be accepted if flash_x_mcr[pgm] = 0 and flash_x_m cr [ers] = 0 (program and erase are not being requested). ute can only be cleared if flash_x_ut0[aid] = 1, flash_x_ut0[aie] and flash_x_ut0[eie] = 0. while clearing ute, writes to set aie or set eie will be ignored. for ute, the password 0xf9f9_9999 must be written to the flash_x_ut0 register. 1 scbe single bit correction enable. sbc enables single bit correction results to be observed in flash_x_mcr[sbc]. also is used as an enable for interrupt signals created by the c90fl module (see c90fl integration guide). ecc corrections that occur when sbce is cleared will not be logged. 0 single bit corrections observation is disabled. 1 single bit correction observation is enabled. 2?7 reserved 8?15 dsi data syndrome input. these bits enable checks of ecc logic by allowing check bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dsi[7:0] correspond to the 8 ecc check bits on a double word. 16?23 reserved 24 ea ecc algorithm. ea is a status bit that provides informat ion about the ecc algorithm used within the flash. either a modified hamming code is used, or a modified hsiao code is used. 0 ecc is implemented with a modified hamming algorithm. 1 ecc is implemented with a modified hsiao algorithm. 25 reserved 26 mre margin read enable. mre combined with mrv enables factory margin reads to be done. margin reads are only active during array integrity checks. normal user reads are not affected by mre. mre is not writable if aid is low. 0 margin reads are not enabled. 1 margin reads are enabled during array integrity checks. 27 mrv margin read value. mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv = 1) or to a programmed level (mrv = 0). in order for this value to be valid, mre must also be set. mrv is not writable if aid is low. 0 zero?s margin reads are requested. 1 one?s margin reads are requested. 28 eie ecc data input enable. eie enables the input registers (dsi and dai) to be the source of data for the array. this is useful in the ecc logic check. if this bit is set, da ta read through a biu read request will be from the dsi and dai registers when an address match is achieved to the fl ash_x_ar. eie is not simultaneously writable to a 1 as uti is being cleared to a 0. 0 data read is from the flash array. 1 data read is from the dsi and dai registers. 29 ais array integrity sequence. ais determines the address s equence to be used during array integrity checks. the default sequence (ais = 0) is meant to replicate sequenc es normal ?user? code follows, and thoroughly checks the read propagation paths. this sequenc e is proprietary. the alternative sequence (ais = 1) is just logically sequential. it should be noted that the time to run a sequential se quence is significantly shorter than the time to run the proprietary sequence. if mre is set, ais has no effect. 0 array integrity sequence is proprietary sequence. 1 array integrity sequence is sequential.
flash memory array and control 12-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30 aie array integrity enable. aie set to one starts the array integrity check done on all selected and unlocked blocks. the address sequence selected is determined by ais, and the misr (um0 through um4) can be checked after the operation is complete, to determine if a correct signa ture is obtained. once an ar ray integrity operation is requested (aie = 1), it may be terminated by clearing aie if the operation has finished (aid = 1) or aborted by clearing aie if the operation is ongoing (aid = 0). aie is not simultaneously writ able to a 1 as uti is being cleared to a 0. 0 array integrity checks are not enabled. 1 array integrity checks are enabled. 31 aid array integrity done. aid is cleared upon an array inte grity check being enabled (to signify the operation is ongoing). once completed, aid is set to indicate th at the array integrity check is complete. at this time the misr (umr registers) can be checked. aid ca n not be written, and is status only. 0 array integrity check is ongoing. 1 array integrity check is done. table 12-15. flash_x_ut0 field descriptions (continued) field description
flash memory array and control freescale semiconductor 12-27 pxr40 microcontroller reference manual, rev. 1 12.2.2.12 user test register 1 (flash_x_ut1) the user test register 1 (flash_x_ut1) provides added controllability to utest. 12.2.2.13 user test register 2 (flash_x_ut2) offset: 0x0040 / 0x4040 access: user read/write 0123456789101112131415 r dai w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai w reset0000000000000000 figure 12-15. user test register 1 (flash_x_ut1) table 12-16. flash_x_ut1 field descriptions field description 0?31 dai data array input. these bits enable checks of ecc logic by allowing data bits to be input into the ecc logic and then read out by doing array reads or array integr ity checks. the dai[31:0] correspond to the 32 array bits representing word 0 of the double word selected in the flash_x_ar. offset: 0x0044 / 0x4044 access: user read/write 0123456789101112131415 r dai w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai w reset0000000000000000 figure 12-16. user test register 2 (flash_x_ut2) table 12-17. flash_x_ut2 field descriptions field description 0?31 dai data array input. these bits enable checks of ecc logic by allowing data bits to be input into the ecc logic and then read out by doing array reads or array inte grity checks. the dai[63:32] correspond to the 32 array bits representing word 1of the double word selected in the flash_x_ar.
flash memory array and control 12-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12.3 functional description 12.3.1 flash user mode in user mode the flash module can be read and written (register writes and interlock writes), programmed or erased. the following sub-sections define al l actions that can be performed in user mode. 12.3.2 flash read and write the default state of the flash module is read. the main and shadow addr ess space can be read only in the read state. the module configurat ion register (flash_x_mcr) is alwa ys available for read. the flash module enters the read state on reset. the flash mo dule is in the read state under these conditions: ? the read state is active when pgm = 1 or ers = 1 in the flash_x_mcr and high-voltage operation is ongoing (read while write). note reads done to the partition(s) be ing operated on (either erased or programmed) will result in an error and the rwe bit in the flash_x_mcr will be set. ? the read state is active when pgm = 1 and ps us = 1 in the flash_x_mcr (program suspend). ? the read state is active when ers = 1 and es us = 1 and pgm = 0 in the flash_x_mcr (erase suspend). in flash user mode, registers can be written. array can be wr itten to do interlock writes. interlock writes attempted to invalid locations (due to bloc ks that do not exist in non 2 n array sizes), will result in an interlock occurring, but attempts to program or erase these bl ocks will not occur since they are forced to be locked. 12.3.3 read while write (rww) the flash core is divided into parti tions. partitions are alwa ys comprised of two or more blocks. partitions are used to determine read-while-w rite (rww) groupings. while a write (p rogram or erase) is being done within a given partition, a read can be simultaneously executed to any ot her partition. partitions are listed in table 12-1 . for each flash array, the high address space of each rww partition is physically comprised of two 256k blocks as shown in figure 12-1 . however, because the high address sp ace blocks are interleaved every 16 bytes between flash array a and flas h array b, the practical size of the high address space rww partitions is effectively four 256k blocks. the shadow block has unique rww restrictions described in section 12.3.6, flash shadow block . the fc is also divided into blocks to implement independent erase or progr am protection. the shadow block exists outside the normal address space and is programmed, erased, and read independently of the other blocks. the shadow block is included to support systems that requi re nvm for security or system initialization information.
flash memory array and control freescale semiconductor 12-29 pxr40 microcontroller reference manual, rev. 1 a software mechanism is provided to independently lock or unlock each block in high-, mid-, and low-address space against program and erase. two hardwa re locks are also provided to enable/disable the fc for program/erase. see section 12.3.4.1, software locking, for more information. 12.3.4 flash programming programming changes the value stored in an array b it from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. addresses in locked/disabled bloc ks cannot be programmed. the user can program the values in any or al l of four words within a page in a single program sequence. word addresses are selected using bi ts 3:2 of the page-bound word. whenever a program operation occu rs, ecc bits are programmed. ec c is handled on a 64-bit boundary. thus, if only one word in any given 64-bit ecc se gment is programmed, the adjoining word (in that segment) should not be programmed because ecc calculation ha s already completed for that 64-bit segment. attempts to program the adjoining word wi ll probably result in an operation failure. it is recommended that all programming ope rations be from 64 bits to 128 bits, and be 64-bit aligned. the programming operation should completely fill selected ecc segments within the page. the program operation consists of the following sequence of events: 1. change the value in the flash_ x_mcr[pgm] bit from a 0 to a 1. note ensure the block that contains the address to be programmed is unlocked. see section 12.2.2.2, low/mid address sp ace block locking register (flash_x_lmlr), section 12.2.2.3, high address space block locking register (flash_x_hlr), and section 12.2.2.4, secondary low/mid address space block locki ng register (flash_x_slmlr), for more information. 2. write the first address to be pr ogrammed in the flash module with the program data. this write is referred to as a program data inte rlock write. an interloc k write may be either be an aligned word or doubleword. 3. if more than one word or doubleword is to be programmed, write each additional address in the page with data to be programmed. this is referred to as a program data wr ite. all unwritten data words default to 0xffff_ffff. 4. write a logic 1 to the flash_x_m cr[ehv] bit to start the internal program sequence or skip to step 9 to terminate. 5. wait until the flash_x_mcr[done] bit goes high. 6. confirm flash_x_mcr[peg] = 1. 7. write a logic 0 to the flash_x_mcr[ehv] bit. 8. if more addresses are to be programmed, return to step 2. 9. write a logic 0 to the flash_x_mcr[pgm] bit to terminate the program sequence. the program sequence is pr esented graphically in figure 12-17 . the program suspe nd operation detailed in figure 12-17 is discussed in section 12.3.4.1.1, flash program suspend/resume.
flash memory array and control 12-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the first write after a program is initiated determines the page addr ess to be programmed. program may be initiated with the 0 to 1 transition of the flash_x_mcr[pgm] bit or by clearing the flash_x_mcr[ehv] bit at the end of a previous program. this first write is referred to as an interlock write. if the program is not an er ase-suspended program, the interlock wr ite determines if the shadow or normal array space will be programmed and cau ses flash_x_mcr[peas] to be set/cleared. note only the first write after a program is initiated does the interlock write and all later writes only look at bits 2 and 3 of the address so be careful that all writes after the interlock write are for that same 128 bit section. in the case of an erase-suspended program, the va lue in flash_x_mcr[peas], is retained from the erase. an interlock write must be performed before setting flash_x_mcr[ehv]. th e user may terminate a program sequence by clearing flash_x_mcr[p gm] prior to setting flash_x_mcr[ehv]. if multiple writes are done to the same location the data for the la st write is used in programming. while flash_x_mcr[done] is low, flash_x_mcr[ ehv] is high, and flash_x_mcr[psus] is low, the user may clear flash_x_mcr[ehv], resulti ng in a program abort. a program abort forces the module to step 8 of the program sequence. an aborted program wi ll result in flash_x_mcr[peg] being set low, indicating a failed operation. the data spa ce being operated on before the abort will contain indeterminate data. the user may not abort a program sequence while in program suspend. note aborting a program operation will leav e the flash core addresses being programmed in an indete rminate data state. th is may be recovered by executing an erase on the affected blocks.
flash memory array and control freescale semiconductor 12-31 pxr40 microcontroller reference manual, rev. 1 figure 12-17. program sequence erase suspend user mode read state write mcr pgm = 1 program write step 1 step 2 step 3 write mcr ehv = 1 high voltage active access mcr done step 4 write psus = 1 read mcr done = 1 program suspend pgm = 0 user mode read state peg = 0 read mcr done = 1 done = 0 write mcr psus = 0 ehv = 1 abort write ehv = 0 step 5 step 6 peg success peg = 1 write mcr failure peg = 0 step 7 ehv = 0 pgm more words step 8 ? no yes write mcr pgm = 0 user mode read state step 9 go to step 2 note: peg will remain valid under this condition until ehv is set high or pgm is cleared. note: psus cannot be cleared while ehv = 0. psus and ehv cannot both be changed in a single write operation. peg valid period last write ? yes no esus ? 0 1 erase suspend or erase suspend ? value ?
flash memory array and control 12-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12.3.4.1 software locking a software mechanism is provided to independently lock/unlock each high-, mid-, and low-address space against program and erase. software locking is done through the flash_x_lmlr (low-/mid-addres s space block locking register), flash_x_slmlr (secondary low-/mi d-address space bloc k locking register), or flash_x_hlr (high-address space block locking re gister). these can be written thr ough register writes and read through register reads. when the program/erase operations are enabled thr ough hardware, software locks are enforced through doing register writes. 12.3.4.1.1 flash program suspend/resume the program sequence may be suspended to allow read acc ess to the flash core. it is not possible to erase or program during a program suspend. interlock writ es should not be attempte d during program suspend. a program suspend can be initiated by changing the value of the flash_x_mcr[psus] bit from a 0 to a 1. flash_x_mcr[psus] can be set high at any time when flash_x_mcr[pgm] and flash_x_mcr[ehv] are high. a 0 to 1 transition of flash_x_mcr[psu s] causes the flash module to start the sequence to enter progr am suspend, which is a read state. the module is not suspended until flash_x_mcr[done] = 1. at this time flash core reads may be attemp ted. after it is suspended, the flash core may be read only. reads to the blocks being programmed/erased re turn indeterminate data. the program sequence is resumed by writ ing a logic 0 to flash_x_mcr[psus]. flash_x_mcr[ehv] must be set to a 1 before clearing flash_x_mcr[psus] to resume operation. when the operation resumes, the flash module conti nues the program sequence from one of a set of predefined points. this may extend the time required for the program operation. 12.3.5 flash erase erase changes the value stored in all bits of the select ed blocks to logic 1. locked or disabled blocks cannot be erased. if multiple blocks ar e selected for erase during an erase sequence, the blocks are erased sequentially starting with the lowest numbered block and term inating with the highes t. aborting an erase operation will leave the flash core blocks being erased in an indeterm inate data state. this can be recovered by executing an erase on the affected blocks. the erase sequence consists of th e following sequence of events: 1. change the value in the flash_x_mcr[ers] bit from 0 to a 1. 2. select the block, or blocks, to be erased by writing 1s to the appropriate registers in flash_x_lmsr or flash_x_hsr. if the shadow row is to be eras ed, this step may be skipped, and flash_x_lmsr and flash_x_hsr are igno red. for shadow row erase, see section section 12.3.6, flash shadow block, for more information.
flash memory array and control freescale semiconductor 12-33 pxr40 microcontroller reference manual, rev. 1 note lock and select are independent. if a bl ock is selected a nd locked, no erase will occur. see section 12.2.2.2, low/mid address space block locking register (flash_x_lmlr), section 12.2.2.3, high a ddress space block locking register (flash_x_hlr), and section 12.2.2.4, secondary low/mid address space block lo cking register (flash_x_slmlr), for more information. 3. write to any address in flash within the flash ar ray a or b (i.e. if you inte nd to erase a b block, you need to make sure the address is in array b). th is is referred to as an erase interlock write. 4. write a logic 1 to the flash_x_mcr [ehv] bit to start an internal erase sequence or skip to step 9 to terminate. 5. wait until the flash_x_mcr[done] bit goes high. 6. confirm flash_x_mcr[peg] = 1. 7. write a logic 0 to the flash_x_mcr[ehv] bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the flash_x_mcr[ers] bit to terminate the erase. the erase sequence is presented graphically in figure 12-18 . the erase suspend operation detailed in figure 12-18 is discussed in section section 12.3.5.1, flash erase suspend/resume. after setting flash_x_mcr[ers], one write (referred to as an inte rlock write) must be performed before flash_x_mcr[ehv] can be set to a 1. data wo rds written during erase sequence interlock writes are ignored. the user may termin ate the erase sequence by clearing flash_x_mcr[ers] before setting flash_x_mcr[ehv]. an erase operation may be aborted by clearing flash_x_mcr[ehv] assuming flash_x_mcr[done] is low, fl ash_x_mcr[ehv] is high, and fl ash_x_mcr[esus] is low. an erase abort forces the module to step 8 of the er ase sequence. an aborted erase will result in flash_x_mcr[peg] being set low, indicating a failed operation. the blocks being operated on before the abort contain indeterminate data . the user may not abort an eras e sequence while in erase suspend. note aborting an erase operation w ill leave the flash core blocks being erased in an indeterminate da ta state. this may be rec overed by executing an erase on the affected blocks. 12.3.5.1 flash erase suspend/resume the erase sequence may be suspended to allow read access to the flash core. the erase sequence may also be suspended to program (erase -suspended program) the flash core . a program started during erase suspend can be suspended. one erase suspend and one program suspend are allowed at a time during an operation. it is not possible to eras e during an erase suspend, or prog ram during a program suspend. during suspend, all reads to flash core locations targeted for program and blocks ta rgeted for erase return indeterminate data. program ming locations in blocks targeted fo r erase during erase-suspended program may result in corrupted data.
flash memory array and control 12-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 an erase suspend operation is initiated by setting the flash_x_mcr[esus] bit. flash_x_mcr[esus] can be set to a 1 at any time when fl ash_x_mcr[ers] and flash_x_mcr[ehv] are high and flash_x_mcr[ pgm] is low. a 0 to 1 transition of flash_x_mcr[esus] causes the flas h module to start the sequence whic h places it in erase suspend. the user must wait until flash_x_mcr[done] = 1 befo re the module is suspended and further actions are attempted. after it is suspended, the array may be read or a program sequence may be initiated (erase-suspended program). befo re initiating a program sequen ce the user must first clear flash_x_mcr[ehv]. if a program sequence is initiated, the value of the flash_x_mcr[peas] is not reset. these values are fixed at the time of the fi rst interlock of the erase. flash core reads from the blocks being erased while flash_x_mc r[esus] = 1 return indeterminate data. the erase operation is resumed by cl earing the flash_x_mcr[esus] bit. the flash continues the erase sequence from one of a set of predef ined points. this can extend the ti me required for the erase operation. caution in an erase-suspended program, progr amming flash locations in blocks which were being operated on in the erase may corrupt flash core data.
flash memory array and control freescale semiconductor 12-35 pxr40 microcontroller reference manual, rev. 1 figure 12-18. erase sequence 12.3.6 flash shadow block the flash shadow block is a memory-mapped block in the flash memory map. program and erase of the shadow block are enabled when flash_x_mcr[peas] = 1 only. after the user has begun an erase operation on the shadow block, the operation cannot be suspended to program the main address space and vice-versa. the user must terminate the shadow er ase operation to program or erase the main address space. user mode read state write mcr ers = 1 select blocks erase interlock write step 1 step 2 step 3 write mcr ehv = 1 high voltage active access mcr done ? step 4 write esus = 1 read mcr done = 1 erase suspend ers = 0 user mode read state peg = 0 read mcr done = 1 done = 0 write mcr esus = 0 ehv = 1 abort write ehv = 0 step 5 step 6 peg ? success peg = 1 write mcr failure peg = 0 step 7 ehv = 0 erase more blocks step 8 ? no yes write mcr ers = 0 user mode read state step 9 ehv = 0 write mcr pgm = 1 program, step 2 go to step 2 note: peg will remain valid under this condition until ehv is set high or ers is cleared. note: esus cannot be cleared while ehv = 0. esus and ehv cannot be changed in a single write operation. peg valid period
flash memory array and control 12-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note if an erase of user space is requested, and a suspend is done with attempts to erase suspend program shadow spa ce, this attempted program will be directed to user space as dictated by the state of flash_x_mcr[peas]. likewise an attempted erase suspended program of user space, while the shadow space is being eras ed, will be directed to shadow space as dictated by the state of flash_x_mcr[peas]. the shadow block cannot use the rww feature. after an operation is started in the shadow block, a read cannot be done to the shadow block, or any other bloc k. likewise, after an operati on is started in a block in low-/mid-/high-address space, a read cannot be done in the shadow block. the shadow block contains information a bout how the lock registers are reset. the shadow block may be locked/unlocked agains t program or erase by us ing the flash_x_lmlr or flash_x_slmlr discussed in section 12.2.2, register descriptions. warning if the shadow flash block is eras ed without reprogramming a new valid password and censorship control word be fore a reset occurs it will contain an illegal password and the debug port wi ll be inaccessible. also, if code does not exist in the first bootable regi on of the internal flash to reprogram the shadow flash with the proper censo rship control word and password, the device will be in a censored state and may no longer be usable. programming the shadow row has similar restrictions to programming the array in terms of how ecc is calculated. see section 12.3.4, flash programming, for more information. only one program is allowed per 64 bit ecc segment betw een erases. erase of the sh adow row is done similarly as an array erase. see section section 12.3.5, flash erase, for more information. 12.3.7 flash reset a reset is the highest priority operation for the flash and terminates all other operations. the flash uses reset to initialize register and status bits to their default reset values. if the flash is executing a program or erase operation and a reset is issued, the operation will be aborted a nd the flash will disable the high voltage logic without damage to the high-voltage circuits. rese t aborts all operations and forces the flash into user mode ready to receive accesses. after reset is negated, register acce sses can be performed, although it shoul d be noted that registers that require updating from shadow informat ion, or other inputs, cannot read updated until flash exits reset.
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-1 chapter 13 core (e200z7) overview 13.1 overview the pxr40 is a dual-issue, 32-bit powerpc book e co mpliant design with 64-bit general purpose registers (gprs). powerpc book e floating-point instructions are not supported in hardwa re, but are trapped and may be emulated by software. an embedded floating-point apu is provided to support real-time single-precision embedded numerics operations using the general-purpose registers. a second generation signal pr ocessing extension apu is provided to support real-time simd fixed point and single-precision, embedded numeric s operations using the general-pur pose registers. all arithmetic instructions that execute in the co re operate on data in the general pur pose registers (gprs). the gprs are 64-bits in order to support vector instructions defined by the spe2 apu. these instructions operate on 8-bit, 16-bit or 32-bit data types, an d deliver vector and scalar results. in addition to the base powerpc book e instruction se t support, the pxr40 core also implements the vle (variable-length encoding) technol ogy, providing improved code densit y. the vle technology is further documented in ?powerpc vle definiti on, version 1.03", a separate document. the pxr40 processor integrates a pa ir of integer execution units, a bran ch control unit, instruction fetch unit and load/store unit, and a multi-ported register file capable of sustaining six read and three write operations per clock. most integer instructions execute in a single clock cycle. branch target prefetching is performed by the branch unit to allo w single-cycle branches in many cases. the pxr40 contains a 16kbyte instruction cache, a 16kbyte data cache, as well as a memory management unit. a nexus class 3+ module is also integrated. 13.2 register model the figures below show the complete pxr40 register set for supervisor and user modes. the number to the right of the special-purpose regi sters (sprs) is the decimal number us ed in the instruction syntax to access the register (for example, the inte ger exception register (xer) is spr 1).
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-2 freescale semiconductor esr spr 62 exception syndrome data exception address spr general exception handling/control registers save and restore mmu assist 1 memory management registers supervisor mode programmer?s model sprs and gprs decrementer timers time base (writeonly) mas0 mas1 mas2 mas3 mas4 mas6 spr 624 spr 625 spr 626 spr 627 spr 628 spr 630 sprg0 sprg1 sprg2 sprg3 sprg4 sprg5 sprg6 sprg7 sprg8 sprg9 spr 272 spr 273 spr 274 spr 275 spr 276 spr 277 spr 278 spr 279 spr 604 spr 605 dear spr 61 spr 26 spr 27 spr 58 spr 59 spr 574 spr 575 spr 570 spr 571 tbl spr 284 tbu spr 285 dec spr 22 process id pid0 spr 48 decar spr 54 ivor0 ivor1 ivor15 spr 400 spr 401 spr 415 interrupt vector prefix ivpr spr 63 interrupt vector offset control and status tcr spr 340 tsr spr 336 spr 528 spr 531 ivor32 1 ivor35 1 control & configuration spr 1012 spr 1015 spr 688 spr 689 cache control 1 spr 1010 l1csr0 mmucsr0 mmucfg tlb0cfg tlb1cfg cache registers spr 515 cache configuration (read-only) l1cfg0 spr 256 user spr usprg0 spe /efpu apu status and control register spr 512 spefscr spe/efpu registers spr 1016 l1finv0 machine check syndrome register mcsr spr 572 btb control 1 spr 1013 bucsr btb register spr 516 l1cfg1 spr 1011 l1csr1 spr 959 l1finv1 srr0 srr1 csrr0 csrr1 dsrr0 1 dsrr1 1 mcsrr0 1 mcsrr1 1 machine check address register mcar spr 573 machine state msr pvr processor control registers processor id pir spr 286 processor version hardware implementation dependent 1 hid0 hid1 spr 1008 spr 1009 spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr gpr0 gpr1 gpr31 spr 1 xer xer general registers spr 287 system version 1 svr spr 1023 accumulator acc iac1 iac2 iac3 iac4 iac5 iac6 iac7 iac8 debug registers 2 debug control dbcr0 dbcr1 dbcr2 dbcr3 1 dbcr4 1 dbcr5 1 dbcr6 1 dberc0 1 devent 1 ddam 1 spr 308 spr 309 spr 310 spr 561 spr 563 spr 564 spr 603 spr 569 spr 975 spr 576 instruction address compare spr 312 spr 313 spr 314 spr 315 spr 565 spr 566 spr 567 spr 568 data address compare dac1 dac2 spr 316 spr 317 debug status dbsr spr 304 debug counter 1 dbcnt spr 562 data value compare dvc1 dvc2 spr 318 spr 319 1 - these pxr40-specific registers may not be supported by other powerpc processors 2 - optional registers defined by the powerpc book-e architecture 3 - read-only registers
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-3 supervisor mode programm er?s model dcrs and pmrs psu registers 1 1 - these pxr40-specific registers may not be supported by other powerpc processors performance monitor registers 1 control pmgc0 pmlca0 pmlca1 pmlca2 pmlca3 pmlcb0 pmlcb1 pmlcb2 pmlcb3 pmr 400 pmr 144 pmr 145 pmr 146 pmr 147 pmr 272 pmr 273 pmr 274 pmr 275 user control (read-only) upmgc0 upmlca0 upmlca1 upmlca2 upmlca3 upmlcb0 upmlcb1 upmlcb2 upmlcb3 pmr 384 pmr 128 pmr 129 pmr 130 pmr 131 pmr 256 pmr 257 pmr 258 pmr 259 counters pmc0 pmc1 pmc2 pmc3 pmr 16 pmr 17 pmr 18 pmr 19 user counters (read-only) upmc0 upmc1 upmc2 upmc3 pmr 0 pmr 1 pmr 2 pmr 3 psu pscr pssr pshr pslr psctr psuhr psulr dcr 272 dcr 273 dcr 274 dcr 275 dcr 276 dcr 277 dcr 278 cache access registers 1 cdacntl cdadata dcr 351 dcr 350
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-4 freescale semiconductor 13.3 cache this section lists the most commonly used registers, instructions, and features of cache. for a complete listing of all registers and features refer to z759n3 core reference manual . 13.3.1 cache overview the pxr40 supports a pair of 16kbyte, 4-way set-associ ative, split instruction and data caches with a 32-byte line size. the caches improve system perfor mance by providing low-latency data to the pxr40 instruction and data pipelines, wh ich decouples processor performance from system memory performance. the caches are virtually indexed and physically tagged. instruction and data addresses from the processor to the caches are virtual addresses used to index the cache array. the mmu provides the virtual to physical translation fo r use in performing the cache tag compare. if the physical a ddress matches a valid cache tag entry, the access hits in the cache. for a read operation, the cache supplies the data to the processor, and for a wr ite operation, the data from the processor updates the cache. if the acc ess does not match a vali d cache tag entry (mis ses in the cache) or a write access must be written through to memory, the cache performs a bus cycle on the system bus. user mode programmer?s model registers timers (read only) time base spr 515 cache configuration l1cfg0 tbl spr 268 tbu spr 269 cache register (read-only) spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr spr 1 xer xer general registers spr general (read-only) control registers sprg4 sprg5 sprg6 sprg7 spr 260 spr 261 spr 262 spr 263 spr 256 user spr usprg0 spe/efpu apu status and control register spr 512 spefscr apu registers gpr0 gpr1 gpr31 accumulator acc spr 516 l1cfg1 debug devent spr 975 ddam spr 576
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-5 13.3.2 cache registers 13.3.2.1 l1 cache control and status register 0 (l1csr0) the l1 cache control and status regi ster 0 (l1csr0) is a 32- bit register used for general control of the data cache as well as pr oviding general control over disabling ways in both caches. the l1csr0 register is accessed using a mfspr or mtspr instruction. the spr number for l1 csr0 is 1010 in decimal. the l1csr0 register is shown below. the l1csr0 bits are described below. wid wdd 0 dcwm dcwa 0 dcece dcei 0 dcedt dcslc dcul dclo dclfc dcloa dcea 0 dcbz32 dcabt dcinv dce 012345678910111213141516171819202122232425262728293031 spr - 1010; read/write; reset - 0x0 figure 13-1. l1 cache control and status register 0 (l1csr0) table 13-1. l1csr0 field descriptions field description 0?3 wid way instruction disable. 0 the corresponding way in the instruction cache is available for replacement by instruction miss line fills. 1 the corresponding way instruction cache is not available for replacement by instruction miss line fills. bit 0 corresponds to way 0. bit 1 corresponds to way 1. bit 2 corresponds to way 2. bit 3 corresponds to way 3. the wid bits may be used for locking ways of the instruction cache, and also are used in determining the replacement policy of the instruction cache. 4?7 wdd way data disable. 0 the corresponding way in the data cache is available for replacement by data miss line fills. 1 the corresponding way in the data cache is not available for replacement by data miss line fills. bit 4 corresponds to way 0. bit 5 corresponds to way 1. bit 6 corresponds to way 2. bit 7 corresponds to way 3. the wdd bits may be used for locking ways of the data cache, and also are used in determining the replacement policy of the data cache. 8?10 reserved 1
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-6 freescale semiconductor 11 dcwm data cache write mode 0 data cache operates in writethrough mode 1 data cache operates in copyback mode when set to writethrough mode, the ?w? page attribute from the mmu is ignored and all writes are treated as writethrough requir ed. when set, write accesses are performed in copyback mode unless the ?w? page attribute from the mmu is set. 12?13 dcwa data cache write allocation policy 00 cache line allocation on a cacheable write miss is disabled 01 cache line allocation on a cacheable copyback write miss is enabled 10 cache line allocation on a cacheable copyback or writethrough write miss is enabled 11 reserved this field also controls merging of store data into the linefill buffer while a cache linefill is in progress. store data will not be merged when write allocation is disabled. if dcwa is non-zero, store data merging is enabled regardless of the type (writethrough/copyback) of write. 14 reserved 1 15 dcece data cache error checking enable 0 error checking is disabled 1 error checking is enabled 16 dcei data cache error injection 0 cache error injection is disabled 1 parity errors will be purposefully injected into every byte subsequently written into the cache. the parity bit of each 8-bit data element written will be inverted. this includes writes due to store hits as we ll as writes due to cache line refills. dcei will cause injection of errors regardless of the setting of dcece, although reporting of errors will be masked while dcece = 0. 17 reserved 1 18?19 dcedt data cache error detection type 00 parity error detection is selected for both the tag and data arrays reserved (defaults to dcedt=01(edc) actions) 01 edc error detection is selected for the tag array and parity is selected for the data arrays 1x reserved 20 dcslc data cache snoop lock clear 0 snoop has not invalidated a locked line 1 snoop has invalidated a locked line indicates a cache line lock was cleared by a snoop operation which caused an invalidation. this bit is set by hardware and will remain set until cleared by software writing 0 to this bit location. 21 dcul data cache unable to lock indicates a lock set instructio n was not effective in locking a cache line. this bit is set by hardware on an ?unable to lock? condition (other than lock overflows), and will remain set until cleared by softwar e writing 0 to this bit location. table 13-1. l1csr0 field descriptions (continued) field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-7 22 dclo data cache lock overflow indicates a lock overflow (overlocking) condition occurred. this bit is set by hardware on an ?overlocking? condition, and will remain set until cleared by software writing 0 to this bit location. 23 dclfc data cache lock bits flash clear when written to a ?1?, a cache lock bits flash clear operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while a flash clear operation is in progress will result in an undefined operation. writing a ?0? to this bit while a flash clear operation is in progress will be ignored. ca che lock bits flash clear operations require approximately 134 cycles to co mplete. clearing occurs rega rdless of the enable (dce) value. 24 dcloa data cache lock overflow allocate set by software to allow a lock request to replace a locked line when a lock overflow situation exists. 0 indicates a lock overflow condition will not replace an existing locked line with the requested line 1 indicates a lock overflow condition will replace an existing locked line with the requested line 25?26 dcea data cache error action 00 error detection causes machine check exception. 01 error detection causes correction/auto-invalidation. no machine check is generated for uncorrectable errors unless the cache line was locked and invalidated or is dirty. dirty lines are not auto-invalidated. in edc mode, correction is performed for single-bit tag errors, single-bit lock errors, and single or multi-bit dirty errors. in parity mode, tag and lock errors will result in invalidation of clean lines. for both modes, correction is performed for data errors by reloading of the line. 1x reserved 27 reserved 1 28 dcbz32 data cache dcba , dcbz , operation length 0 dcba , dcbz , operations operate on an entire cache line 1 dcba , dcbz , operations operate on 32 bytes of a cache line note: this bit is implemented for forward compatibility. since cache lines are 32 bytes, this bit is ignored for dcba , dcbz , operations 29 dcabt data cache operation aborted indicates a cache invalidate or a cache lock bits flash clear operation was aborted prior to completion. this bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit location. table 13-1. l1csr0 field descriptions (continued) field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-8 freescale semiconductor 13.3.2.2 l1 cache control and status register 1 (l1csr1) the l1 cache control and status regi ster 1 (l1csr1) is a 32- bit register used for general control of the instruction cache. the l1csr1 register is accessed using a mfspr or mtspr instruction. the spr number for l1csr0 is 1011 in decimal. the l1csr1 register is shown below. the l1csr1 bits are described below. 30 dcinv data cache invalidate 0 no cache invalidate 1 cache invalidation operation when written to a ?1?, a cache invalidation operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while an invalidation operation is in progress will result in an undefined operat ion. writing a ?0? to this bit while an invalidation operation is in progress will be ignored. cache invalidation operations require approximately 134 cycles to complete . invalidation occurs regardless of the enable (dce) value. during cache invalidations, the parity check bits are written with a value dependent on the dcedt selection. dcedt should be writ ten with the desired value for subsequent cache operation when dcinv is set to ?1? for proper operation of the cache. 31 dce data cache enable 0 cache is disabled 1 cache is enabled when disabled, cache lookups are not performed for normal load or store accesses, or for snoop requests. other l1csr0 cache control operations are still available. also, operation of the store buffer is not affected by dce. 1 these bits are not implemented and should be written with zero for future compatibility. 0 icece icei 0 icedt 0 icul iclo iclfc icloa icea 0 icabt icinv ice 012345678910111213141516171819202122232425262728293031 spr - 1011; read/write; reset - 0x0 figure 13-2. l1 cache control and status register 1 (l1csr1) table 13-2. l1csr1 field descriptions field description 0?14 reserved 1 15 icece instruction cache error checking enable 0 error checking is disabled 1 error checking is enabled table 13-1. l1csr0 field descriptions (continued) field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-9 16 icei instruction cache error injection enable 0 cache error injection is disabled 1 when icedt=00, parity errors will be purposefully injected into every byte subsequently written into the cache. the pari ty bit of each 8-bit data element written will be inverted on cache linefills. when icedt=01, a double-bit error will be injected into each doubleword written into the cache by inverting the two uppermost parity check bits (p_chk[0:1]). icei will cause injection of errors regardle ss of the setting of icece, although reporting of errors will be masked when icece=0. 17 reserved 1 18?19 icedt instruction cache error detection type 00 parity error detection is selected for both the tag and data arrays reserved (defaults to icedt=01(edc) actions) 01 edc error detection is selected 1x reserved 20 reserved 1 21 icul instruction cache unable to lock indicates a lock set instruction was not effect ive in locking a cache line. this bit is set by hardware on an ?unable to lock? condition (other than lock overflows), and will remain set until cleared by software writing 0 to this bit location. 22 iclo instruction cache lock overflow indicates a lock overflow (overlocking) condition occurred. this bit is set by hardware on an ?overlocking? condition, and will remain set until cleared by software writing 0 to this bit location. 23 iclfc instruction cache lock bits flash clear when written to a ?1?, a cache lock bits flash clear operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while a flash clear operation is in progress will result in an undefined operation. writing a ?0? to this bit while a flash clear operation is in progress will be ignored. cache lock bits flash clear operations require approximately 134 cycles to complete. clearing occurs re gardless of the enable (ice) value. 24 icloa instruction cache loc k overflow allocate set by software to allow a lock request to replace a locked line when a lock overflow situation exists. 0 indicates a lock overflow condition will not replace an existing locked line with the requested line 1 indicates a lock overflow condition will replace an existing locked line with the requested line 25?26 icea instruction cache error action 00 error detection causes machine check exception. 01 error detection causes correction/auto-invalidation. no machine check is generated unless a locked line is invalidated. correction is performed for single-bit tag and lock errors, and lines with multi-bit tag or lock errors are invalidated. in parity mode, tag or lock errors will result in invalidation of lines. correction is performed for single or multi-bit data errors by reloading of the line. 1x reserved 27?28 reserved 1 table 13-2. l1csr1 field descriptions (continued) field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-10 freescale semiconductor 13.3.2.3 l1finv0 this register is used to flush/i nvalidate cache sets/ways in the da ta cache. the spr number for l1finv0 is 1016 in decimal. the l1finv0 register is shown below. 29 icabt instruction cache operation aborted indicates a cache invalidate or a cache lock bits flash clear operation was aborted prior to completion. this bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit location. 30 icinv instruction cache invalidate 0 no cache invalidate 1 cache invalidation operation when written to a ?1?, a cache invalidation operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while an invalidation operation is in progress will result in an undefined operation. writing a ?0? to this bit while an invalidation operation is in progress will be ignored. cache invalidation operations require approximately 134 cycles to complete. invalidation occurs regardless of the enable (ice) value. during cache invalidations, the parity check bits are written with a value dependent on the icedt selection. icedt should be wri tten with the desired value for subsequent cache operation when icinv is set to ?1? for proper operation of the cache. 31 ice instruction cache enable 0 cache is disabled 1 cache is enabled when disabled, cache lookups are not performed for instruction accesses. other l1csr1 cache control oper ations are still available and are not affected by ice. 1 these bits are not implemented and should be written with zero for future compatibility. 0 cway 0 cset 0 ccmd 012345678910111213141516171819202122232425262728293031 spr - 1016; read/write; reset - 0x0 figure 13-3. l1 flush/invalidate register 0 (l1finv0) table 13-3. l1finv0 field descriptions field description 0?5 reserved 1 for way extension 6?7 cway cache way specifies the data cache way to be selected 8?19 reserved 1 for set extension 20?26 cset cache set specifies the cache set to be selected table 13-2. l1csr1 field descriptions (continued) field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-11 13.3.2.4 l1finv1 this register is used to flush/invalidate cache se ts/ways in the instruction cache. the spr number for l1finv1 is 959 in decimal. the l1fi nv1 register is shown below. 13.4 mmu this section lists the most commonly used registers, instructions, and features of mmu. for a complete listing of all registers and features refer to z759n3 core reference manual . 27?29 reserved 1 for set/command extension 30?31 ccmd cache command 00 the data contained in this entry is invalidated without flushing 01 the data contained in this entry is flus hed if dirty and valid without invalidation 10 the data contained in this entry is flushed if dirty and valid and then is invalidated 11 reset way replacement pointer to the way indicated by cway 1 these bits are not implemented and should be written with zero for future compatibility. 0 cway 0 cset 0 ccmd 012345678910111213141516171819202122232425262728293031 spr - 959; read/write; reset - 0x0 figure 13-4. l1 flush/invalidate register 1 (l1finv1) table 13-4. l1finv1 field descriptions field description 0?5 reserved 1 1 these bits are not implemented and should be written with zero for future compatibility. 6?7 cway cache way specifies the instruction cache way to be selected 8?19 reserved 1 20?26 cset cache set specifies the instruction cache set to be selected 27?29 reserved 1 f 30?31 ccmd cache command 00 the data contained in this entry is invalidated 01 reserved 10 reserved 11 reset way replacement pointer to the way indicated by cway table 13-3. l1finv0 field descriptions (continued) field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-12 freescale semiconductor 13.4.1 overview the pxr40 memory management unit is a 32-bit powerpc book e compliant implementation, with the following feature set: ? translates from 32-bit effectiv e to 32-bit real addresses ? 64-entry fully associative tlb with support for twenty-three page sizes (1k, 2k, 4k, 8k, 16k, 32k, 64k, 128k, 256k, 512k, 1m, 2m, 4m, 8m, 16m, 32m, 64m, 128m, 256m, 512m, 1g, 2g, 4g) ? hardware assist for tlb miss exceptions ? software managed by tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions 13.4.2 mmu instructions 13.4.3 tlb read entry instruction (tlbre) the tlb read entry instruction causes the content of a single tlb entry to be placed in the mmu assist registers. the entry is specified by the tlbsel and es el fields of the mas0 register. the entry contents are placed in the mas1, mas2, and mas3 registers.
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-13 tlbre tlbre tlb read entry tlb_entry_id = mas0(tlbsel, esel) result = mmu(tlb_entry_id) mas1, mas2, mas3 = result 13.4.4 tlb write entry instruction (tlbwe) the tlb write entry instruction causes the contents of certain fields within the mmu assist registers mas1, mas2, and mas3 to be written into a single tl b entry in the mmu. the entry written is specified by the tlbsel, and esel fields of the mas0 register. 31 0 1 1 1 0 1 1 0 0 1 0 0 0 5 6 2021 3031
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-14 freescale semiconductor tlbwe tlbwe tlb write entry tlb_entry_id = mas0(tlbsel, esel) mmu(tlb_entry_id) = mas1, mas2, mas3 13.4.5 mmu registers 13.4.5.1 dear register the data exception address register is loaded with the effective address of the data access which results in an alignment, data tlb miss, or dsi exception. the dear register can be read or written using the mfspr and mtspr instructions. 13.4.5.2 mmu control and stat us register 0 (mmucsr0) the mmu control and status register 0 (mmucs r0) is a 32-bit register. the spr number for mmucsr0 is 1012 in decimal. mmucsr0 controls th e state of the mmu. the mmucsr0 register is shown below. the mmucsr0 bits are described below. 31 0 1 1 1 1 0 1 0 0 1 0 0 0 5 6 2021 3031 effective page address 012345678910111213141516171819202122232425262728293031 spr - 61; read/ write; reset - unaffected figure 13-5. dear 0 tlb1_fi 0 012345678910111213141516171819202122232425262728293031 spr - 1012; read/ write; reset - 0x0 figure 13-6. mmu control and status register 0 (mmucsr0)
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-15 13.4.5.3 mmu assist registers (mas) the pxr40 uses special purpose registers (mas0, ma s1, mas2, mas3, mas4 and mas6) to facilitate reading and writing the tlbs. the mas regi sters can be read or written using the mfspr and mtspr instructions. the mas0 register is shown below. table 13-5. mmucsr0 - mmu control and status register 0 field description 0?29 reserved 1 1 these bits are not implemented, will be read as zero, and writes are ignored. 30 tlb1_fi tlb1 flash invalidate 0 - no flash invalidate 1 - tlb1 invalidation operation when written to a ?1?, a tlb1 invalidation operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while an invalidation operation is in progress will result in an undefined operation. writing a ?0? to this bit while an invalidation operation is in progress will be ignored. tlb1 invalidation operations require 3 cycles to complete. 31 reserved 1 0 tlbsel (01) 0 esel 0 nv 012345678910111213141516171819202122232425262728293031 spr - 624; read/ write; reset - unaffected figure 13-7. mmu assist register 0 (mas0) fields are defined below.
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-16 freescale semiconductor the mas1 register is shown below. table 13-6. mas0 ?mmu read/write and replacement control field comments, or function when set 0?1 reserved 1 1 these bits are not implemented, will be read as zero, and writes are ignored. 2?3 reserved, should be written to 01 for future compatibility 4?9 reserved 1 10?15 esel entry select for tlb. 16?25 reserved 1 26?31 nv next replacement victim for tlb1 (software managed) software updates this field; it is copied to the esel field on a tlb error valid iprot 0 tid 0 ts tsiz 0 012345678910111213141516171819202122232425262728293031 spr - 625; read/ write; reset - unaffected figure 13-8. mmu assist register 1 (mas1) fields are defined below. table 13-7. mas1 ?descriptor context and configuration control field comments, or function when set 0 valid tlb entry valid 0 this tlb entry is invalid 1 this tlb entry is valid 1 iprot invalidation protect 0 entry is not protected from invalidation 1 entry is protected from invalidation as described in as described in the e200z759n3 reference manual?s iprot invalidation protection section. protects tlb entry from invalidation by tlbivax (tlb1 only), or flash invalidates through mmuscr0[tlb1_fi]. 2?7 reserved 1 8?15 tid translation id bits this field is compared with the current process ids of the effective address to be translated. a tid value of 0 defines an entry as global and matches with all process ids. 16?18 reserved 1
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-17 the mas2 register is shown below. 19 ts translation address space this bit is compared with the is or ds fields of the msr (depending on the type of access) to determine if this tlb entry may be used for translation. 20?24 tsize entry?s page size supported page sizes are: 0b00000 - 1kb 0b00001 - 2kb 0b00010 - 4kb 0b00011 - 8kb 0b00100 - 16kb 0b00101 - 32kb 0b00110 - 64kb 0b00111 - 128kb 0b01000 - 256kb 0b01001 - 512kb 0b01010 - 1mb 0b01011 - 2mb 0b01100 - 4mb 0b01101 - 8mb 0b01110 - 16mb 0b01111 - 32mb 0b10000 - 64mb 0b10001 - 128mb 0b10010 - 256mb 0b10011 - 512mb 0b10100 - 1gb 0b10101 - 2gb 0b10110 - 4gb all other values are undefined 25?31 reserved 1 1 these bits are not implem ented, will be read as zero, and writes are ignored. epn 0 v l e wimge 012345678910111213141516171819202122232425262728293031 spr - 626; read/ write; reset - unaffected figure 13-9. mmu assist register 2 (mas2) fields are defined below. table 13-7. mas1 ?descriptor context and configuration control field comments, or function when set
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-18 freescale semiconductor the mas3 register is shown below. table 13-8. mas2 - epn and page attributes field comments, or function when set 0?21 epn effective page number [0:21] 22?25 reserved 1 26 vle powerpc vle 0 this page is a standard booke page 1 this page is a powerpc vle page 27 w write-through required 0 this page is considered write-back wit h respect to the caches in the system 1 all stores performed to this page are written through to main memory 28 i cache inhibited 0 this page is considered cacheable 1 this page is considered cache-inhibited 29 m memory coherence required 0 memory coherence is not required 1 memory coherence is required 30 g guarded 0 access to this page are not guarded, and can be performed before it is known if they are required by the sequential execution model 1 all loads and stores to this page are perf ormed without speculation (i.e. they are known to be required) pxr40 uses the guarded attribute as described in the e200z759n3 reference manual?s page table control bits section. 31 e endianness 0 the page is accessed in big-endian byte order. 1 the page is accessed in true little-endian byte order. 1 these bits are not implemented, will be read as zero, and writes are ignored. rpn u 0 u 1 u 2 u 3 u x s x u w s w u r s r 012345678910111213141516171819202122232425262728293031 spr - 627; read/ write; reset - unaffected figure 13-10. mmu assist register 3 (mas3)
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-19 the mas4 register is shown below. table 13-9. mas3 - rpn and access control field comments, or function when set 0?21 rpn real page number [0:21] only bits that correspond to a page nu mber are valid. bits that represent offsets within a page are ignored and should be zero. 22?25 u0-u3 user bits [0-3] for use by system software 26?31 permis permission bits (ux, sx, uw, sw, ur, sr) 0 tlbseld (01) 0 tidseld 0 tsized 0 vled wd id md gd ed 012345678910111213141516171819202122232425262728293031 spr - 628; read/ write; reset - unaffected figure 13-11. mmu assist register 4 (mas4) fields are defined below. table 13-10. mas4 - hardware replacement assist configuration register field comments, or function when set 0?1 reserved 1 2?3 tlbseld default tlb selected 00 tlb0 01 tlb1 4?13 reserved 1 14?15 tidseld default pid# to load tid from 00 pid0 01 reserved, do not use 10 reserved, do not use 11 tidz (8?h00)) (use all zeros, the globally shared value) 16?19 reserved 1 20?24 tsized default tsize value 25 reserved 1
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-20 freescale semiconductor the mas6 register is shown below. 13.5 exceptions this section provides an ove rview of core exceptions. fo r detailed explanation see z759n3 core reference manual . 26 vled default vle value 27?31 dwimge default wimge values 1 these bits are not implemented, will be read as zero, and writes are ignored. 0spid 0 sas 012345678910111213141516171819202122232425262728293031 spr - 630; read/ write; reset - unaffected figure 13-12. mmu assist register 6 (mas6) fields are defined below. table 13-11. mas6 - tlb search context register 0 field comments, or function when set 0?7 reserved 1 1 these bits are not implemented, will be read as zero, and writes are ignored. 8?15 spid pid value for searches 16?30 reserved 1 31 sas as value for searches table 13-10. mas4 - hardware replacement assist configuration register field comments, or function when set
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-21 13.5.1 exception syndrome register the exception syndrome register (esr) provides a syndrome to differentiate between exceptions that can generate the same interrupt type. the esr bits are defined below. 0 pil ppr ptr fp st 0 dlk ilk ap puo bo pie 0 spe 0 vlemi 0 mif 0 012345678910111213141516171819202122232425262728293031 spr - 62; read/write; reset - 0x0 figure 13-13. exception syndrome register (esr) table 13-12. esr bit settings field description associ ated interrupt type 0?3 reserved ? 4 pil illegal instruction exception program 5 ppr privileged instruction exception program 6 ptr trap exception program 7 fp floating-point operation program 8 st store operation alignment data storage data tlb 9reserved ? 10 dlk data cache locking data storage 11 ilk instruction cache locking data storage 12 ap reserved ? 13 puo unimplemented operation exception program 14 bo byte ordering exception mismatched instruction storage exception data storage instruction storage 15 pie reserved 16?23 reserved ?
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-22 freescale semiconductor 13.6 machine state register the machine state register define s the state of the processor. the msr bits are defined below. 24 spe spe/efpu apu operation spe/efpu unavailable efpu floating-point data exception efpu floating-point round exception alignment data storage data tlb 25 reserved ? 26 vlemi vle mode instruction spe/efpu unavailable efpu floating-point data exception efpu floating-point round exception data storage data tlb instruction storage alignment program system call 27?29 reserved ? 30 mif misaligned instruction fetch instruction storage instruction tlb 31 reserved ? 0 ucle spe 0 we ce 0 ee pr fp me 00 de 00 is ds 0 pmm ri 0 012345678910111213141516171819202122232425262728293031 read/ write; reset - 0x0 field description 0?4 reserved 1 5 ucle user cache lock enable 0 - execution of the cache locking instructions in user mode (msr pr =1) disabled; dsi exception taken instead, and ilk or dlk set in esr. 1 - execution of the cache lock in structions in user mode enabled. table 13-12. esr bit settings (continued) field description associ ated interrupt type
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-23 6 spe spe/efpu available 0 - execution of spe and efpu apu ve ctor instructions, and efpu dpfp instructions is are disabled; spe/efpu unavailable exceptio n taken in stead, and spe bit is set in esr. 1 - execution of spe and efpu apu ve ctor instructions, and efpu dpfp instructions is are enabled. 7?12 reserved 1 13 we wait state (power management ) enable. this bit is defined as optional in the powerpc book e architecture. 0 - power management is disabled. 1 - power management is enabled. the processor can enter a power-saving mode when additional conditions are present. the mode chosen is determined by the doze, nap, and sleep bits in the hid0 register. 14 ce critical interrupt enable 0 - critical input and watchdog timer interrupts are disabled. 1 - critical input and watchdog timer interrupts are enabled. 15 reserved 1 16 ee external interrupt enable 0 - external input, decrementer, and fi xed-interval timer interrupts are disabled. 1 - external input, decrementer, and fi xed-interval timer interrupts are enabled. 17 pr problem state 0 - the processor is in supervisor mode, can execute any instruction, and can access any resource (e.g. gprs, sprs, msr, etc.). 1 - the processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged resource. 18 fp floating-point available 0 - floating-point unit is unavailable. th e processor cannot execute floating-point instructions, including floating-point loads, stores, and moves. (an fp unavailable interrupt will be generated on attempted execution of floating point instructions). 1 - floating-point unit is available. the processor can execute floating-point instructions. (note that fo r pxr40, the floating point unit is not supported, and an unimplemented operation exception will be generated for attempted execution of floating-point instructions when fp is set). 19 me machine check enable 0 - asynchronous machine check interrupts are disabled. 1 - asynchronous machine check interrupts are enabled. 20 reserved 1 21 reserved 1 22 de debug interrupt enable 0 - debug interrupts are disabled. 1 - debug interrupts are enabled. 23?25 reserved 1 26 is instruction address space 0 - the processor directs all instruction fetches to address space 0 (ts=0 in the relevant tlb entry). 1 - the processor directs all instruction fetches to address space 1 (ts=1 in the relevant tlb entry). field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-24 freescale semiconductor 13.6.1 machine check syndrome register (mcsr) when the processor takes a machine check interrupt , it updates the machine check syndrome register (mcsr) to differentiate betw een machine check conditions. table below describes mcsr fields. the mcsr i ndicates the source of a machine check condition. all bits in the mcsr are implemente d as ?write ?1? to clear?. software in the machine check handler is expected to clear the mcsr bits it has sampled prior to re-enabling msr me to avoid a redundant machine check exception and to prepare for updated status bit information on the next machine check interrupt. hardware will not clear a bit in the mcsr other than at reset. note that any set bit in the mcsr other than stat us-type bits will cause a subsequent machine check interrupt once msr me =1. 27 ds data address space 0 - the processor directs all data storage accesses to address space 0 (ts=0 in the relevant tlb entry). 1 - the processor directs all data storage accesses to address space 1 (ts=1 in the relevant tlb entry). 28 reserved 1 29 pmm pmm performance monitor mark bit. system software can set pmm when a marked process is running to enable statistics to be gathered only during the execution of the marked process. msr pr and msr pmm together define a state that the pr ocessor (supervisor or user) and the process (marked or unmarked) may be in at any time. if this state matches an individual state specified in the performance monitor registers pmlca n, the state for which monitoring is enabled, counting is enabled. 30 ri recoverable interrupt - this bit is provided for software use to detect nested exception conditions. this bit is cleared by hardware when a machine check interrupt is taken 31 reserved 1 1 these bits are not implemented, will be read as zero, and writes are ignored. mcp ic_dperr cp_perr dc_dperr excp_err ic_tperr dc_tperr ic_lkerr dc_lkerr 0 nmi mav mea 0 if ld st g 0 snperr bus_irerr bus_drerr bus_wrerr 0 012345678910111213141516171819202122232425262728293031 spr - 572; read/clear; reset - 0x0 figure 13-14. machine check syndrome register (mcsr) field description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-25 table 13-13. machine check syndrome register (mcsr) field description exception type 1 recoverable 0 mcp machine check input pin async mchk maybe 1 ic_dperr instruction cache data array parity error async mchk precise 2 cp_perr data cache push parity error async mchk unlikely 3 dc_dperr data cache data array parity error async mchk maybe 4 excp_err isi, itlb, or bus error on first instruction fetch for an exception handler async mchk precise 5 ic_tperr instruction cache tag parity error async mchk precise 6 dc_tperr data cache tag parity error async mchk maybe 7 ic_lkerr instruction cache lock error indicates a cache control operation or invalidation operation invalidated one or more locked lines in the icache or encountered an uncorrectable lock error, or that an icache miss with an uncorrectable lock error occurred. may also be set on locked line refill error. status ? 8 dc_lkerr data cache lock error indicates a cache control operation or invalidation operation invalidated one or more locked lines in the dcache or encountered an uncorrectable lock error, or that an icache miss with an uncorrectable lock error occurred. may also be set on locked line refill error. status ? 9?10 reserved, should be cleared. ? 11 nmi nmi input pin nmi ? 12 mav mcar address valid indicates that the address contained in the mcar was updated by hardware to correspond to the first detected async mchk error condition status ? 13 mea mcar holds effective address if mav=1,mea=1 indicates that the mcar contains an effective address and mea=0 indicates that the mcar contains a physical address status ? 14 reserved, should be cleared. ? 15 if instruction fetch error report an error occurred during the attempt to fetch an instruction. this could be due to a parity error, or an external bus error. mcsrr0 contains the instruction address. error report precise
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-26 freescale semiconductor 16 ld load type instruction error report an error occurred during the attempt to execute the load type instruction located at the address stored in mcsrr0. this could be due to a parity error or an external bus error. error report precise 17 st store type instruction error report an error occurred during the attempt to execute the store type instruction locate d at the address stored in mcsrr0. this could be due to a parity error, or on certain external bus errors. error report precise 18 g guarded instruction error report an error occurred during the attempt to execute the load or store type instruction loca ted at the address stored in mcsrr0 and the access was guarded and encountered an error on the external bus. error report precise 19?25 reserved, should be cleared. ? 26 snperr snoop lookup error an error occurred during certain snoop operations. this is typically due to a data cache tag parity error, in which case dc_tperr will also be set. async mchk unlikely? 27 bus_irerr read bus error on instruction fetch or linefill async mchk precise if data used 28 bus_drerr read bus error on data load or linefill async mchk precise if data used 29 bus_wrerr write bus error on store or cache line push async mchk unlikely 30?31 reserved, should be cleared. ? 1 the exception type indicates the exceptio n type associated with a given syndrome bit - ?error report? indicates that this bit is only set for error report exceptions which cause machine check interrupts. these bits are only updated when the machine check interrupt is actually taken. error report exceptions are not gated by msr me . these are synchronous exceptions. these bits will remain set until cleared by software writing a ?1? to the bit position(s) to be cleared. - ?status? indicates that this bit is provides addi tional status information regarding the logging of a machine check exception. these bits will remain set until cleared by software writing a ?1? to the bit position(s) to be cleared. - ?nmi? indicates that this bit is only set for the non-maskable in terrupt type exception which causes a machine check interrupt. this bit is only updated when the machine check interrupt is actually taken. nmi exceptions are not gated by msr me . this is an asynchronous exception. this bit will remain set until cleared by software writing a ?1? to the bit position. - ?async mchk? indicates that this bit is set for an asynchronous machine check exception. these bits are set immediately upon detection of the error. once any ?async mchk? bit is set in the mcsr, a machine check interrupt will occur if msr me =1. if msr me =0, the machine check exception will remain pending. these bits will remain set until cleared by so ftware writing a ?1? to the bit position(s) to be cleared. table 13-13. machine check syndrome register (mcsr) (continued) field description exception type 1 recoverable
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-27 13.7 interrupt vector prefix registers (ivpr) the interrupt vector prefix regist er is used during interrupt proce ssing for determining the starting address of a software handler used to handle an inte rrupt. the value contained in the vector offset field of the ivor selected for a part icular interrupt type is c oncatenated with the value he ld in the interrupt vector prefix register (ivpr) to form an instruction addr ess from which execution is to begin. the format of ivpr is shown below. the ivpr fields are defined in table 13-14 . 13.8 interrupt vector o ffset registers (ivorxx) the interrupt vector offset registers are used dur ing interrupt processing fo r determining the starting address of a software handler used to handle an inte rrupt. the value contained in the vector offset field of the ivor selected for a part icular interrupt type is c oncatenated with the value he ld in the interrupt vector prefix register (ivpr) to form an instruction addr ess from which execution is to begin. the format of a pxr40 ivor is shown below. vector base 0 012345678910111213141516171819202122232425262728293031 spr - 63; read/write figure 13-15. pxr40 interrupt vector prefix register (ivpr) table 13-14. ivpr register fields field description 0?15 vec base vector base this field is used to define the base location of the vector table, aligned to a 64kbyte boundary. this field provides the high-order 16 bits of the location of all in terrupt handlers. the contents of the ivorxx register appropriate for the type of exception being processed are concatenated with the ivpr vector base to form the address of the handler in memory. 16?31 reserved 0 vector offset 0 012345678910111213141516171819202122232425262728293031 spr - 400-415, 528-530; read/write figure 13-16. pxr40 interrupt vector offset register (ivor)
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-28 freescale semiconductor the ivor fields are defined in table 13-15 . 13.9 interrupt definitions 13.9.1 critical input interrupt (ivor0) a critical input exception is signalled to the processor by the assertion of the critical interrupt pin. when the core detects the exception, if the exception is enabled by msr ce , the core takes the critical input interrupt. the critical input is a level-sensitive signal expected to remain asserted until the core acknowledges the interrupt. if critical input is negated early, recogniti on of the interrupt request is not guaranteed. after the co re begins execution of the cr itical interrupt handler, the system can safely negate critical input. table below lists register settings when a critical input interrupt is taken. table 13-15. ivor register fields field description 0?15 reserved 16?27 vector offset vector offset this field is used to provide a quadword index from the base address provided by the ivpr to locate an interrupt handler. 28?31 reserved table 13-16. critical input interrupt?register settings register setting description csrr0 set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. csrr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce 0 ee 0 pr 0 fp 0 me ? fe0 0 de ?/0 1 1 de is cleared when the debug apu is disabled. clearing of de is optionally supported by control in hid0 when the debug apu is enabled. fe1 0 is 0 ds 0 pmm 0 ri ? esr unchanged mcsr unchanged dear unchanged vector ivpr 0:15 || ivor0 16:27 || 4b0000 (autovectored) ivpr 0:15 || p_voffset[0:11] || 4b0000 (non-autovectored)
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-29 13.9.2 machine check interrupt (ivor1) the machine check apu defines a separate set of sa ve/restore registers (mcsrr0/1), a machine check syndrome register (mcsr) to reco rd the source(s) of machine chec ks, and a machine check address register (mcar) to hold an address associated with a machine check for certain classes of machine checks. return from machine check instructions ( rfmci , se_rfmci ) are also provided to support returns using mcsrr0/1. the msr ri status bit is provided for software use in determining if multiple nested machine check exceptions have occurred. softwa re may interrogate the mcsrr1 ri bit to determine if a machine check occurred during the initial portion of a machine check handler prior to handler code which sets msr ri to ?1? to indicate that the handler can now tolerate another machine check condition without losing state necessary for recovery. 13.9.2.1 machine check causes machine check causes are divi ded into different types: ? error report machine check conditions ? non-maskable interrupt (nmi ) machine check exceptions ? asynchronous machine check exceptions 13.9.2.2 machine check interrupt actions machine check interrupts for ?error report? conditions and nmi are enab led and taken regardless of the state of msr me . machine check interrupts due to an ?async mchk? syndrome bit being set in mcsr are only taken when msr me =1. when a machine check interrupt is taken, registers are updated as shown below. table 13-17. machine check interrupt - register settings register setting description mcsrr0 on a best-effort basis, the core sets this to the address of some instruction that was executing or about to be executing when the machine check condition occurred. mcsrr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce 0 ee 0 pr 0 fp 0 me 0 fe0 0 de 0/? 1 fe1 0 is 0 ds 0 pmm 0 ri 0 esr unchanged mcsr updated to reflect the source(s) of a machine check. hardware only sets appropriate bits, no previously set bits are cleared by hardware. mcar see vector ivpr 0:15 || ivor1 16:27 || 4b0000
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-30 freescale semiconductor the machine check syndrome register is provided to identify the sour ce(s) of a machine check, and in conjunction with mcsrr1 ri , may be used to identify recoverable events. 13.9.3 data storage interrupt (ivor2) a data storage interrupt (dsi) may occur if no higher priority exception exists and one of the following exception conditions exists: ? read or write access control exception condition ? byte ordering exception condition ? cache locking exception condition table below lists register settings when a dsi is taken. 1 de is cleared when the debug apu is disabled. clearing of de is optionally supported by control in hid0 when the debug apu is enabled. table 13-18. data storage interrupt?register settings register setting description srr0 set to the effective address of the excepting load/store instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr access: byte ordering: cache locking: [st], [spe], [vlemi]. a ll other bits cleared. [st], [spe], [vlemi], bo. all other bits cleared. (dlk, ilk), [vlemi], [st]. all other bits cleared. mcsr unchanged dear for access and byte ordering exceptions, set to th e effective address of a byte within the page whose access caused the violation. undefined on cache locking exceptions (dear is not updated on a cache locking exception) vector ivpr 0:15 || ivor2 16:27 || 4b0000
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-31 13.9.4 instruction storage interrupt (ivor3) an instruction storage interrupt (isi) occurs when no higher priority exception exists and an execute access control exception occurs. table below lists register settings when an isi is taken. 13.9.5 external input interrupt (ivor4) an external input exception is signalled to the proc essor by the assertion an interrupt from the interrupt controller. the input is a level-sensitive signal expe cted to remain asserted until core acknowledges the external interrupt. if input is negated early, rec ognition of the interrupt reques t is not guaranteed. when the core detects the exce ption, if the exception is enabled by msr ee , it takes the external input interrupt. table 13-19. isi exceptions and conditions interrupt type interrupt vector offset register causing conditions instruction storage ivor 3 1. access control. 2. byte ordering due to misaligned instruction across page boundary to pages with mismatched vle bits, or access to page with vle set, and e indicating little-endian. 3. misaligned instruction fetch due to a change of flow to an odd halfword instruction boundary on a book e (non-vle) instruction page. table 13-20. instruction storage interrupt?register settings register setting description srr0 set to the effective address of the excepting instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr [bo, mif, vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr 0:15 || ivor3 16:27 || 4b0000
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-32 freescale semiconductor table below lists register settings when an external input interrupt is taken. ivor4 is the vector offset register used by autove ctored external input interrupts to determine the interrupt handler location. the pxr40 also provides th e capability to directly vector external input interrupts to multiple handlers by allowing a external input interrupt request to be accompanied by a vector offset. 13.9.6 alignment interrupt (ivor5) an alignment exception is generated when any of the following occurs: ? the operand of lmw or stmw not word aligned. ? the operand of lwarx or stwcx. not word aligned. ? the operand of lharx or sthcx. not halfword aligned. ? execution of a dcbz instruction is attempted with a disabled cache. ? execution of a dcbz instruction with an enab led cache and w or i =1. ? execution of a spe apu load or store in struction which is not properly aligned. table 13-21. external input interrupt?register settings register setting description srr0 set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr unchanged mcsr unchanged dear unchanged vector ivpr 0:15 || ivor4 16:27 || 4b0000 ivpr 0:15 || p_voffset[0:11] || 4b0000 (non-autovectored)
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-33 table below lists register settings wh en an alignment interrupt is taken. 13.9.7 program interrupt (ivor6) a program interrupt occurs when no higher priority exception exists and one or more of the following exception conditions occur: ? illegal instruction exception ? privileged instruction exception ? trap exception ? unimplemented operation exception the pxr40 will invoke an illegal instruction program exception on at tempted execution of the following instructions: ? unimplemented instructions ? instruction from the il legal instruction class ? mtspr and mfspr instructions with an undefined spr specified ? mtdcr and mfdcr instructions with an undefined dcr specified the pxr40 will invoke a privileged instruction program exception on attempted execution of the following instructions when msr pr =1 (user mode): ? a privileged instruction ? mtspr and mfspr instructions which specify a sprn value with sprn 5 =1 (even if the spr is undefined). the pxr40 will invoke a trap exception on execution of the tw and twi instructions if the trap conditions are met and the exception is not al so enabled as a debug interrupt. table 13-22. alignment interrupt?register settings register setting description srr0 set to the effective address of the excepting load/store instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr [st], [spe], [vlemi]. all other bits cleared. mcsr unchanged dear set to the effective address of a byte of t he load or store whose access caused the violation. vector ivpr 0:15 || ivor5 16:27 || 4b0000
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-34 freescale semiconductor table below lists register settings when a program interrupt is taken. 13.9.8 floating-point unavailable interrupt (ivor7) the floating-point unavailable ex ception is not used by the pxr40. 13.9.9 system call interrupt (ivor8) a system call interrupt occurs when a system call ( sc , se_sc ) instruction is executed and no higher priority exception exists. table below lists register settings wh en a system call in terrupt is taken. table 13-23. program interrupt?register settings register setting description srr0 set to the effective address of the excepting instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr illegal: privileged: tr a p : unimplemented: pil, [vlemi]. all other bits cleared. ppr, [vlemi]. all other bits cleared. ptr, [vlemi]. all other bits cleared.puo, [fp], [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr 0:15 || ivor6 16:27 || 4b0000 table 13-24. system call interrupt?register settings register setting description srr0 set to the effective address of the instruction following the sc instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr [vlemi] all other bits cleared. mcsr unchanged
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-35 13.9.10 auxiliary processor un available interrupt (ivor9) the pxr40 does not utilize this interrupt. 13.9.11 decrementer interrupt (ivor10) a decrementer interrupt occurs when no higher priority exception exists, a decrementer exception condition exists (tsr dis =1), and the interrupt is enabled (both tcr die and msr ee =1). the timer status register (tsr) holds the decremente r interrupt bit set by the timer facility when an exception is detected. softwa re must clear this bit in the interrupt handler to avoid re peated decrementer interrupts. table below lists register settings wh en a decrementer interrupt is taken. 13.9.12 fixed-interval timer interrupt (ivor11) the triggering of the exception is caused by selected bits in the time base register changing from 0 to 1. a fixed-interval timer interrupt occurs when no hi gher priority exception exists, a fit exception exists (tsr fis =1), and the interrupt is enabled (both tcr fie and msr ee =1). the timer status register (tsr) holds the fit interrupt bit set by the timer facility when an exception is detected. software must clear th is bit in the interrupt handler to avoid repeated fit interrupts. dear unchanged vector ivpr 0:15 || ivor8 16:27 || 4b0000 table 13-25. decrementer interrupt?register settings register setting description srr0 set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr unchanged mcsr unchanged dear unchanged vector ivpr 0:15 || ivor10 16:27 || 4b0000 table 13-24. system call interrupt?register settings (continued)
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-36 freescale semiconductor table below lists register settings when a fit interrupt is taken. 13.9.13 watchdog timer interrupt (ivor12) the triggering of the exception is cause d by the first enabled watchdog time-out. a watchdog timer interrupt occurs when no higher priority exception ex ists, a watchdog timer exception exists (tsr wis =1), and the interrupt is enabled (both tcr wie and msr ce =1). the timer status register (tsr) holds the watchdog interrupt bit set by the timer facility when an exception is detected. software must clear this bit in the interrupt handler to avoid repeated watchdog interrupts. table below lists register settings wh en a watchdog timer interrupt is taken. table 13-26. fixed-interval timer interrupt?register settings register setting description srr0 set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr unchanged mcsr unchanged dear unchanged vector ivpr 0:15 || ivor11 16:27 || 4b0000 table 13-27. watchdog timer interrupt?register settings register setting description csrr0 set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. csrr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce 0 ee 0 pr 0 fp 0 me ? fe0 0 de 0/? 1 fe1 0 is 0 ds 0 pmm 0 ri ? esr unchanged mcsr unchanged
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-37 13.9.14 data tlb error interrupt (ivor13) a data tlb error interrupt occurs when no higher priority exception exists and a data tlb error exception exists due to a data tr anslation lookup miss in the tlb. table below lists register settings when a dtlb interrupt is taken. 13.9.15 instruction tlb error interrupt (ivor14) a instruction tlb error interrupt oc curs when no higher prio rity exception exists and an instruction tlb error exception exists due to an instru ction translation lo okup miss in the tlb. exception extensions implemented in the pxr40 for powerpc vle involve extending the definition of the instruction tlb error interr upt to include updating the esr. table 13-29 below lists register settings when an itlb interrupt is taken. dear unchanged vector ivpr 0:15 || ivor12 16:27 || 4b0000 1 de is cleared when the debug apu is disabled. clearing of de is optionally supported by control in hid0 when the debug apu is enabled. table 13-28. data tlb error interrupt?register settings register setting description srr0 set to the effective address of the excepting load/store instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr [st], [spe], [vlemi], all other bits cleared. mcsr unchanged dear set to the effective address of a byte of t he load or store whose access caused the violation. vector ivpr 0:15 || ivor13 16:27 || 4b0000 table 13-29. instruction tlb error interrupt?register settings register setting description srr0 set to the effective address of the excepting instruction. srr1 set to the contents of the msr at the time of the interrupt table 13-27. watchdog timer interrupt?register settings
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-38 freescale semiconductor 13.9.16 debug interrupt (ivor15) there are multiple sources that can signal a debug exception. a debug interrupt occurs when no higher priority exception exists, a debug exception exists in the debug stat us register, and de bug interrupts are enabled (both dbcr0 idm =1 (internal debug mode) and msr de =1). msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr [mif] all other bits cleared. mcsr unchanged dear unchanged vector ivpr 0:15 || ivor14 16:27 || 4b0000 table 13-29. instruction tlb error interrupt?register settings (continued)
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-39 table below lists register settings when a debug interrupt is taken. 13.9.17 spe/efpu apu unava ilable interrupt (ivor32) the spe apu unavailable ex ception is taken if msr spe is cleared and executi on of a spe or efpu apu instruction other than the scalar floating-point instructions or brinc is attempted. when the spe/efpu table 13-30. debug interrupt?register settings register setting description csrr0/ dsrr0 1 1 assumes that the debug interrupt is precise set to the effective address of the excepting in struction for iac, brt, ret, cret, and trap. set to the effective address of th e next instruction to be executed following the excepting instruction for dac and icmp. for a ude, irpt, cirpt, dcnt, or devt type exception, set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. csrr1/ dsrr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ?/0 2 ee ?/0 2 pr 0 2 conditional based on control bits in hid0 fp 0 me ? fe0 0 de 0 fe1 0 is 0 ds 0 pmm 0 ri ? dbsr 3 3 note that multiple dbsr bits may be set unconditional debug event: instr. complete debug event: branch taken debug event: interrupt taken debug event: critical interrupt taken debug event: trap instruction debug event: instruction address compare: data address compare: return debug event: critical return debug event: debug counter event: external debug event: and optionally, an imprecise debug event flag ude icmp brt irpt cirpt trap {iac1, iac2, iac3, iac4} {dac1r, dac1w, dac2r, dac2w} ret cret {dcnt1, dcnt2} {devt1, devt2} {ide} esr unchanged mcsr unchanged dear unchanged vector ivpr 0:15 || ivor15 16:27 || 4b0000
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-40 freescale semiconductor apu unavailable exception occurs, the processor s uppresses execution of the instruction causing the exception. table below lists regist er settings when a spe/efpu unavailable interrupt is taken. 13.9.18 embedded floating-point data interrupt (ivor33) the embedded floating-point data interrupt is taken if no higher priority exce ption exists and a efpu floating-point data exception is generated. when a floating-point data exception occurs, the processor suppresses execution of the inst ruction causing the exception. table below lists register settings when a efpu floating-point data interrupt is taken. table 13-31. spe/efpu unavailable interrupt?register settings register setting description srr0 set to the effective address of the excepting spe/ef pu instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr spe, [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr 0:15 || ivor32 16:27 || 4b0000 table 13-32. embedded floating-point data interrupt?register settings register setting description srr0 set to the effective address of the excepting efpu instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr spe, [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr 0:15 || ivor33 16:27 || 4b0000
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-41 13.9.19 embedded floating-point round interrupt (ivor34) the embedded floating-point round inte rrupt is taken when a efpu floa ting-point instruction generates an inexact result and inexact exceptions are enabled. table below lists register settings when a efpu floating-point r ound interrupt is taken. 13.9.20 performance monitor interrupt (ivor35) the pxr40 provides a performance m onitor interrupt that may be gene rated by an enabled condition or event. an enabled condition or event is as follows: a pmc x register overflow condition occurs with the following settings: ?pmlca x ce = 1; that is, for the given counte r the overflow condition is enabled. ?pmc x ov = 1; that is, the given c ounter indicates an overflow. for a performance monitor interrupt to be si gnaled on an enabled condition or event, pmgc0 pmie must be set. although an exception condition may occur with msr ee = 0, the interrupt cannot be taken until msr ee =1. table below lists register settings when an performance monitor interrupt is taken. table 13-33. embedded floating-point round interrupt?register settings register setting description srr0 set to the effective address of the instruction following the excepting efpu instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr spe, [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr 0:15 || ivor34 16:27 || 4b0000 table 13-34. performance monitor interrupt?register settings register setting description srr0 set to the effective address of the next instruction to be executed. srr1 set to the contents of the msr at the time of the interrupt
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-42 freescale semiconductor 13.10 special features this section describes the wait instructi on, vle save/restore, and performance monitor. 13.10.1 wait apu the wait instruction allows software to shutdown the core and wait for an asynchronous interrupt or debug interrupt to occur. the instruction can be used to cease processor activity in both user and supervisor modes. asynchronous interrupts which will cause the waiting state to be exit ed if enabled ar e critical input, external input, machine check pin, and non-maskable interrupts (nmi). executing a wait instruction ensures that all instru ctions have completed before the wait instruction completes, causes processo r instruction fetching to c ease, and ensures that no s ubsequent instructions are initiated until an asynchronous interr upt or a debug interrupt occurs. once the wait instruction has completed, the program counter will point to the next se quential instruction. wait instruction can be used in conjunction with the siu_halt m echanism and siu_hltack registers to enter a low power state while waiting. software must ensure that interrupt s responsible for exiting the waitin g state are enabled before executing a wait instruction. msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 pmm 0 ri ? esr unchanged mcsr unchanged dear unchanged vector ivpr 0:15 || ivor35 16:27 || 4b0000 table 13-34. performance monitor interrupt?register settings (continued) register setting description
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 13-43 wait wait wait for interrupt wait 13.10.2 volatile context save/restore apu the pxr40 implements volatile cont ext save/restore apu to support th e capability to quickly save and restore volatile register context on en try into an interrupt handler. to support this functionality, a new set of instructions is defi ned as part of the apu. ? e_lmvgprw, e_stmvgprw - load/store multiple volatile gprs (r0, r3:r12) ? e_lmvsprw, e_stmvsprw - load/store multiple volatile sprs (cr, lr, ctr, and xer) ? e_lmvsrrw, e_stmvsrrw - load/store multiple volatile srrs (srr0, srr1) ? e_lmvcsrrw, e_stmvcsrrw - load/store multiple volatile cs rrs (csrr0, csrr1) ? e_lmvdsrrw, e_stmvdsrrw - load/store multiple volatile dsrrs (dsrr0, dsrr1) ? e_lmvmcsrrw, e_stmvmcsrrw - load/store multiple volatile mcsrrs (mcsrr0, mcsrr1) these instructions are available in v le instruction pages to perform a mul tiple register load or store to a word aligned memory address. 13.10.3 performance monitor the performance monitor provides the ability to count predefined events and processor clocks associated with particular operations, such as cache misses, mi s-predicted branches, or the number of cycles an execution unit stalls. the count of su ch events can be used to trigge r the performance monitor interrupt. the performance monitor can be used to do the following: ? improve system performance by monitoring software execution a nd then recoding algorithms for more efficiency. for example, memory hierarc hy behavior can be monitored and analyzed to optimize task scheduling or da ta distribution algorithms. ? characterize processors in environments not easily characterized by benchmarking. ? help system developers bri ng up and debug their systems. for a complete description of performance monitor see z759n3 core reference manual . 0 5 6 1011 1516 2021 31 011111 /// 0 000111110 /
core (e200z7) overview pxr40 microcontroller reference manual, rev. 1 13-44 freescale semiconductor
freescale semiconductor 14-1 pxr40 microcontroller reference manual, rev. 1 chapter 14 amba crossbar switch (xbar) 14.1 introduction this chapter describes the multi-por t crossbar switch (xbar), which supports simultane ous connections between master ports and slave por ts. xbar supports a 32-bit address bus width and a 64-bit data bus width at all master and slave ports a nd runs at half the system frequency. 14.1.1 overview the xbar allows concurrent transactions to occur fr om any master port to any slave port. it is possible for all master ports and slave ports to be in use at the same time as a re sult of independent master requests. if a slave port is simultaneously requested by more th an one master port, arbitrat ion logic selects the higher priority master and grant it ownership of the slave port. all other masters reque sting that slave port are stalled until the higher priority master completes its transactions. by default, requesting masters are granted access base d on a fixed priority. a ro und-robin priority mode also is available. in this mode, re questing masters are treate d with equal priority a nd are granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. a block diagram of the xbar is shown in figure 14-1 . the xbar can place a slave port in a low-power park mode to avoi d dissipating any pow er transitional address, control or data signals when the master por t is not actively accessing th e slave port. there is a one-cycle arbitration overhead fo r exiting low-power park mode.
amba crossbar switch (xbar) 14-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 14.1.2 block diagram figure 14-1 shows a block diagram of the crossbar switch. figure 14-1. xbar block diagram table 14-1 gives the crossbar switch port for each master and slave, and the assigned and fixed id number for each master. the following tabl e shows the master id numbers as they relate to the master port numbers: 14.1.3 features ? multiple master and slave ports with programmable prioriti es and attributes. table 14-1. xbar switch ports module port master id type number e200z7 core0 ? cpu instruction master 0 0 e200z7 core0 ? data master 1 0 nexus 3 8 edma_a master 4 4 edma_b master 5 5 flexray master 6 6 reserved 1 1 this port is not usable by customers, but exists in the device. therefore, the priority must be set to a unique value in the master priority registers. master 7 3 on-chip flash (accessed by core 0 only) slave 0 ? ebi (development bus) slave 1 ? on-chip sram slave 2 ? peripheral bridge a (pbridge_a) slave 6 ? peripheral bridge b (pbridge_b) slave 7 ? master crossbar switch slave master modules slave modules master master slave slave . . . . . . . .
amba crossbar switch (xbar) freescale semiconductor 14-3 pxr40 microcontroller reference manual, rev. 1 ? 32-bit address, 64-bit data paths ? fully concurrent transfers betwee n independent master and slave ports 14.1.4 modes of operation 14.1.4.1 normal mode in normal mode, the xbar provides the register in terface and logic that controls crossbar switch configuration. 14.1.4.2 debug mode the xbar operation in debug mode is identical to operation in normal mode. 14.2 memory map and register definition the memory map for the xbar program -visible registers is shown in table 14-2 . table 14-2. xbar register memory map address register bits access reset value section/page base = 0xfff0_4000 xbar_mpr0?mast er priority register for slave port 0 32 r/w 0x7654_3210 14.2.1.1/14-4 base + (0x0004?0x000f) reserved base + 0x0010 xbar_sgpcr0 ?general-purpose control register for slave port 0 32 r/w 0x0000_0000 14.2.1.2/14-6 base + (0x0014?0x00ff) reserved base + 0x0100 xbar_mpr1?master priority register for slave port 1 32 r/w 0x7654_3210 14.2.1.1/14-4 base +(0x0104?0x010f) reserved base + 0x0110 xbar_sgpcr1 ?general-purpose control register for slave port 1 32 r/w 0x0000_0000 14.2.1.2/14-6 base + (0x0114?0x01ff) reserved base + 0x0200 xbar_mpr2?master priority register for slave port 2 32 r/w 0x7654_3210 14.2.1.1/14-4 base +(0x0204?0x020f) reserved base + 0x0210 xbar_sgpcr2 ?general-purpose control register for slave port 2 32 r/w 0x0000_0000 14.2.1.2/14-6 base + (0x0214?0x05ff) reserved base + 0x0600 xbar_mpr6?master priority register for slave port 6 32 r/w 0x7654_3210 14.2.1.1/14-4 base + (0x0604?0x060f) reserved
amba crossbar switch (xbar) 14-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 14.2.1 register descriptions there are two registers for each slav e port of the xbar. the registers ca n only be accessed in supervisor mode using 32-bit accesses. the slave sgpcr also features a bit (ro), which when written with a 1, prevents all slave registers for that port from being written to again until a reset oc curs. the registers remain readable, but future write attempts have no effect on the registers and are terminat ed with an error response. 14.2.1.1 master priority registers (xbar_mpr n ) the xbar_mpr for a slave port sets the priority of each master port when operating in fixed priority mode. they are ignored in round-robi n priority mode unless more than one master has been assigned high priority by a slave. note masters must be assigned unique priority levels. the master priority register can only be accessed in supervisor mode with 32-bit accesses. after the read only (ro) bit is set in the slave ge neral-purpose control register, the mast er priority regi ster can only be read. attempts to write to it have no ef fect on the mpr and re sult in an error. note xbar_mpr must be written with a read/modify/write for code compatibility. base + 0x0610 xbar_sgpcr6 ?general-purpose control register for slave port 6 32 r/w 0x0000_0000 14.2.1.2/14-6 base + (0x0614?0x06ff) reserved base + 0x0700 xbar_mpr7?master priority register for slave port 7 32 r/w 0x7654_3210 14.2.1.1/14-4 base + (0x0704?0x070f) reserved base + 0x0710 xbar_sgpcr7?gene ral-purpose control register for slave port 7 32 r/w 0x0000_0000 14.2.1.2/14-6 base + ( 0x0714? x07ff) reserved table 14-2. xbar register memory map (continued) address register bits access reset value section/page
amba crossbar switch (xbar) freescale semiconductor 14-5 pxr40 microcontroller reference manual, rev. 1 address: base + 0x0000 (xbar_mpr0) base + 0x0100 (xbar_mpr1) base + 0x0200 (xbar_mpr2) base + 0x0600 (xbar_mpr6) base + 0x0700 (xbar_mpr7) access: supervisor r/w 0123456789101112131415 r01010 mstr6 0 mstr5 0 mstr4 w 0 1 0 1 0 0 0 reset0101010000110010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 mstr1 0 mstr0 w 0 0 0 0 0 0 0 0 0 0 reset0000000000010000 figure 14-2. master priority registers (xbar_mpr n ) table 14-3. xbar_mpr n descriptions field description 0?3 reserved, must be set to 0b0101. undefined operation if not. 4 reserved, must be cleared. 5?7 mstr6 master 6 priority. set the arbitration priority for master port 6 on the associated slave port. 000 master 6 has the highest priority when accessing slave port n . 101 master 6 has the lowest priority when accessing slave port n . 110?111 invalid values 8 reserved, must be cleared. 9?11 mstr5 master 5 priority. set the arbitration priority for master port 5 on the associated slave port. 000 master 5 has the highest priority when accessing slave port n . 101 master 5 has the lowest priority when accessing slave port n . 110?111 invalid values 12 reserved, must be cleared. 13?15 mstr4 master 4 priority. set the arbitration priority for master port 4 on the associated slave port. 000 master 4 has the highest priority when accessing slave port n . 101 master 4 has the lowest priority when accessing slave port n . 110?111 invalid values 16-24 reserved, must be cleared. .... .... ....
amba crossbar switch (xbar) 14-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 14.2.1.2 slave general-purpose control registers (xbar_sgpcr n ) the xbar_sgpcr n of a slave port controls several features of the slave port, including the following: ? round-robin or fixed arbitration po licy for a particular slave port ? write protection of a ny slave port registers ? parking algorithm used for a slave port the park field indicates which master port this slave port parks on when no active access attempts are being made to the slave and the parking contro l field is set to park on a specific master. xbar_sgpcr n [park] must only be programmed to select ma ster ports that are actually available on the device, otherwise undefined behavior results. the low-power park feature can result in an overall power savings if the slave port is not saturated; howev er, an extra clock of latency results whenever any master tries to access a slave (not being accessed by another master) because it is not parked on any master. the xbar_sgpcr can only be accessed in supervisor mode with 32-bit accesse s. after the ro (read only) bit is set in the xbar_sgp cr, the xbar_sgpcr and the sbar_m pr can only be read. attempts to write to them have no effect and results in an error. note some of the unused bits in the sgpcr n registers are writeable and readable, but they serve no function. setting any of these bits has no effect on the operation of this module. 25?27 mstr1 master 1 priority. set the arbitration priority for master port 1 on the associated slave port. 000 master 1 has the highest priority when accessing slave port n . 101 master 1 has the lowest priority when accessing slave port n . 110?111 invalid values 28 reserved, must be cleared. 29?31 mstr0 master 0 priority. set the arbitration priority for master port 0 on the associated slave port. 000 master 0 has the highest priority when accessing slave port n . 101 master 0 has the lowest priority when accessing slave port n . 110?111 invalid values table 14-3. xbar_mpr n descriptions (continued) field description .... ....
amba crossbar switch (xbar) freescale semiconductor 14-7 pxr40 microcontroller reference manual, rev. 1 address : base + 0x0010 (xbar_sgpcr0) base + 0x0110 (xbar_sgpcr1) base + 0x0210 (xbar_sgpcr2) base + 0x0610 (xbar_sgpcr6) base + 0x0710 (xbar_sgpcr7) access: r/w 0123456789101112131415 r ro 1 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 arb 00 pctl 0 pa r k w reset0000000000000000 1 after this bit is set, only a hardware reset clears it. figure 14-3. slave general-purpos e control registers (xbar_sgpcr n ) table 14-4. xbar_sgpcr n field descriptions field description 0 ro read only. used to force all of a slave port?s registers to be read only. after written to 1, it can only be cleared by hardware reset. 0 all this slave port?s registers can be written. 1 all this slave port?s registers are read only and cannot be written (attempted writes have no effect and result in an error response). 1?21 reserved, must be cleared. 22?23 arb arbitration mode. used to select the arbitration policy for the slave port. this field is initialized by hardware reset. 00 fixed priority using mpr 01 round-robin priority 10 invalid value 11 invalid value 24?25 reserved, must be cleared. 26?27 pctl parking control. used to select the parking algorithm used by the slave port. this field is initialized by hardware reset. 00 when no master is making a request, the arbiter parks the slave port on the master port defined by the park control field. 01 pol?park on last. when no master is making a req uest, the arbiter parks the slave port on the last master to own the slave port. 10 lpp?low-power park. when no master is making a request, the arbiter parks the slave port on no master and drives all slave port outputs to a safe state. 11 invalid value
amba crossbar switch (xbar) 14-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28 reserved, must be cleared. 29?31 pa r k park. used to determine which master port this slave port parks on when no masters are actively making requests. pctl must be set to 0b00. 000 park on master port 0 001 park on master port 1 010 invalid value 011 invalid value 100 park on master port 4 101 park on master port 5 110 park on master port 6 111 invalid value table 14-4. xbar_sgpcr n field descriptions (continued) field description
amba crossbar switch (xbar) freescale semiconductor 14-9 pxr40 microcontroller reference manual, rev. 1 14.3 functional description this section describes the functiona lity of the xbar in more detail. 14.3.1 overview the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate concurrently with mult iple slaves. to maximize data th roughput, it is esse ntial to keep arbitration delays to a minimum. this section examines data throughput from the point of view of mast ers and slaves, detailing when the xbar stalls masters, or in serts bubbles on the slave side. 14.3.2 general operation when a master makes an access to the xbar from an idle master state, the access is taken immediately by the xbar. if the targeted slave por t of the access is availabl e (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses through the xbar by a granted master . if the targeted slave port of the access is busy or parked on a different master port, the reques ting master receives wait states until the targeted slave port can se rvice the master request. the latenc y in servicing the request depends on each master?s priority level a nd the responding slave?s access time. because the xbar appears to be simply another slav e to the master device, the master device has no indication that it owns the slave port it is targeting. while the master doe s not have control of the slave port it is targeting, it is wait-stated. a master is given control of a targ eted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when a master has the following conditions: ? outstanding request to slave por t a that has a long response time ? pending access to a different slave port b ? lower priority master also makes a request to the different slave port b. in this case, the lower priority mast er is granted bus owners hip of slave port b after a cycle of arbitration, assuming the higher priority master sl ave port a access is not terminated. after a master has control of the slav e port it is targeting, the master re mains in control of that slave port until it gives up the slave port by running an idle cycle, leaves that slave port for its next access, or loses control of the slave port to a higher pr iority master with a request to the same slave port. however, because all masters run a fixed-length burst transfer to a slave port, it retain s control of the slave port until that transfer sequence is completed. in round-robin arbitrat ion mode, the current master is forced to hand off bus ownership to an alternately requesting master at the end of its current transfer sequence. when a slave bus is idled by the xbar, it can be pa rked on the master port using the park bits in the xbar_sgpcr (slave general-purpose control register), or on the last master to have control of the slave port. this can avoid the initial clock of the arbitration delay if the master must arbitrate to gain control of the slave port. the slave port can also be pu t into low-power park mode to save power.
amba crossbar switch (xbar) 14-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 14.3.3 master ports the xbar terminates an access and it is not allo wed to pass through the xbar unless the master currently is granted access to the slav e port to which the access is targete d. a master access is taken if the slave port to which the access decodes is either currently servicing the ma ster or is parked on the master. in this case, the xbar is complete ly transparent and the master acces s is immediately transmitted on the slave bus and no arbitration delays are incurred. a ma ster access stall if the access decodes to a slave port that is busy serving another master, parked on a nother master or is in low-power park mode. if the slave port is currently parked on another master or is in low-power park m ode, and no other master is requesting access to the slave port, then only one cl ock of arbitration is incurred. if the slave port is currently serving another master of a lower priority and the master ha s a higher priority than all other requesting masters, then the master gains control over the slave port as soon as the data pha se of the current access is completed. if the slave port is currently serv icing another master of a higher priority, then the master gains control of the slave port after the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. a master access is responded to with an error if th e access decodes to a locati on not occupied by a slave port. this is the only time the xbar directly responds with an error response. all other error responses received by the master are the result of error responses on the slave por ts being passed through the xbar. 14.3.4 slave ports the goal of the xbar with respect to the slave ports is to keep them 100% sa turated when masters are actively making requests. to do this the xbar must not insert any bubbles onto the slave bus unless absolutely necessary. there is only one instance when the xbar forces a bubble onto the slave bus when a master is actively making a request. this occurs when a handoff of bus ownership occurs and there are no wait states from the slave port. a requesting master which does not own the slave port is granted access after a one clock delay. the only other time the xbar has c ontrol of the slave port is when no masters are making access requests to the slave port and the xbar is forced to either park the slave port on a specific master, or place the slave port into low-power park mode. in these cas es, the xbar forces idle for the transfer type. 14.3.5 priority assignment each master port must be a ssigned a unique 2-bit priori ty level in fixed priority mode. if multiple master ports are assigned the same priority level within a register (xbar_mpr) unde fined behavior results. 14.3.6 arbitration xbar supports two arbitration schemes; a simple fi xed-priority comparison algorithm, and a round-robin fairness algorithm. the arbitration scheme is independently programmabl e for each slave port.
amba crossbar switch (xbar) freescale semiconductor 14-11 pxr40 microcontroller reference manual, rev. 1 14.3.6.1 fixed priority operation when operating in fixed-priority arbi tration mode, each master is assi gned a unique priority level in the xbar_mpr. if two masters bot h request access to a slave port, the master with the highest priority in the selected priority register ga ins control over the slave port. any time a master makes a request to a slave port, the slave port ch ecks to see if the new requesting master?s priority level is higher than that of the master that currently has control over the slave port (if any). the slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. if the new requesting master?s priority level is higher than th at of the master that currently has control of the slave port, the higher priority master is grante d control at the terminati on of any currently pending access, assuming the pending transfer is not part of a burst transfer. a new requesting master must wait until the end of th e fixed-length burst transfer, before it is granted control of the slave port. but if the new requesting master ?s priority level is lower than that of the master that currently has control of the slav e port, the new requesting master is fo rced to wait until the master that currently has control of the slave port is finished accessing the current slave port. 14.3.6.2 round-robin priority operation when operating in round-robin mode, each master is as signed a relative priority based on the master port number. this relative priority is co mpared to the port number of the last master to perf orm a transfer on the slave bus. the highest priority re questing master becomes th e owner of the slave bus at the next transfer boundary (accounting for fixed-length bur st transfers). priority is base d on how far ahea d the port number of the requesting master is to th e port number of the last master. after granted access to a slave port, a master may perf orm as many transfers as de sired to that port until another master makes a request to the same slave port. th e next master in line is granted access to the slave port when the current transfer is completed, or possibl y on the next clock cycle if the current master has no pending access request. as an example of arbitration in round-robin mode, assume the three ma sters have id?s 0, 1, and 2. if the last master of the slave port was master 1, and ma sters 0 and 2 make simultaneous requests, they are serviced in the order 2 and then 0 assuming no further requests are made. as another example, if master 1 is waiting on a response from a slow slave and has no further pending access to that slave, no other master s are requesting, and master 0 then makes a request, master 0?s request is granted on the next clock (assuming that master 1? s transfer is not a burst transfer), and the request information for master 0 is driven to the slave as a pending access. if mast er 2 were to make a request after master 0 has been granted access, but prior to mast er 0?s access being accepted by the slave, master 0 maintains the grant on the slave port, and master 2 is delayed until the next arbitration boundary, which occurs after the transfer is complete . the round-robin pointer is reset to 0, so if master 1 has another request that occurs before master 0?s transf er completes, master 1 is the grante d the bus. this implies a worst case latency of n transfers for a system with n masters.
amba crossbar switch (xbar) 14-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 parking may continue to be used in round-robin mode, but affects the round- robin pointer unless the parked master actually performs a transfer. handoff to the next master in line occurs after one cycle of arbitration. the slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. a new requesting master must wait until the end of th e fixed-length burst transfer, before it is granted control of the slave port. if the new re questing master?s priority level is lo wer than that of the master that currently has control of the slave port, the new requesti ng master is forced to wait until the master that currently has control of the sl ave port completes its access. 14.3.6.2.1 parking if no master is currently requesting the slave port, the slave port is parked. the slave port parks in one of three places, indicated by the value of the pctl field in the xbar_sgpcr. ? if park-on-specific master mode is selected, the slave port parks on the master designated by the park field. when the master accesses the slave port again, a one clock arbitration penalty is incurred only for an access reque st made by another master port to the slave port. no other arbitration penalties are incurred. all other masters pay a one clock penalty. ? if park-on-last (pol) mode is selected, then th e slave port parks on the last master to access it, passing that master?s signals through to the slav e bus. when the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave por t made by another master port. all other masters pay a one clock penalty. ? if the low-power-park (lpp) mode is selected, then the slave port enters lo w-power park mode. it is not under control by any master and does not tr ansmit any master signals to the slave bus. all slave bus activity halts because all slave bus signa ls are not toggling. this saves power if the slave port is not used for some time. ho wever, when a master does make a request to a slave port parked in low-power-park, a one clock arbi tration delay is incurred to get ownership of the slave port.
freescale semiconductor 15-1 pxr40 microcontroller reference manual, rev. 1 chapter 15 peripheral bridge (pbridge) 15.1 introduction there are two peripheral br idges, pbridge a and pbri dge b, that act as inte rfaces between the system bus and lower bandwidth peripherals. in this manual, p bridge refers to either of these bridges, as their functionality is identical. the only difference is the peripherals to which they connect. accesses that fall within the address space of the pbri dge are decoded to provide indivi dual module selects for peripheral devices on the slave bus interface. 15.1.1 block diagram the pbridge is the interface between the system bus and on-chip peripherals as shown in figure 15-1 . figure 15-1. pbridge interface 15.1.2 access protections the pbridge provides programmabl e access protections for both ma sters and peripherals. access protections allow the program to: ? override the privilege level of a master to change it to user mode privilege ? designate masters as trusted or untrusted peripherals can implement the following restrictions: off-platform slave peripheral on-platform slave peripheral bridge a (pbridge_b) (pbridge_a) bridge b off-platform slave system bus system bus system bus crossbar switch (xbar) on-platform slave
peripheral bridge (pbridge) 15-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? require supervisor privilege level for access ? restrict access to a trusted master only ? write-protect the peripheral to de ny updates to the peripheral (i.e., not all accesses are denied, reads are still allowed) refer to table 15-1 for a list of master/slave ids and the peripherals for with each master and slave. the shaded areas in the table do not apply. refer to section 12.2.2.9, flash bus interface acce ss protection regist er (flash_biuapr) , in the flash chapter, for more information on access protection. table 15-1. peripheral bridge master/slave id table module internal master id xbar port peripheral e200z7 core?cpu instruction 0 master 0 ? e200z7?data 0 master 1 ? nexus 3 8 ? edma_a 4 master 4 ? edma_b 5 master 5 ? flexray 6 master 6 ? on-chip flash ?slave 0 ? external development bus (ebi) ?slave 1 ? on-chip sram ?slave 2 ? pbridge a ? slave 6 pbridge a ?fmpll ? ebi control ? flash control ?siu ? emios ?pmc ?etpu reg ? etpu pram ? etpu pram mirror ?etpu scm ?pit_rti
peripheral bridge (pbridge) freescale semiconductor 15-3 pxr40 microcontroller reference manual, rev. 1 15.1.3 features the following list summarizes th e key features of the pbridge: ? supports the slave interface signals. this in terface is only meant for slave peripherals. pbridge b ? slave 7 pbridge b ? xbar ?mpu ?swt ?stm ? escm ? edma control ?intc ? eqadc a ? eqadc b ? decimation filter a ? decimation filter b ? decimation filter c ? decimation filter d ?dspi a ?dspi b ?dspi c ?dspi d ?esci a ?esci b ?esci c ? flexcan a ? flexcan b ? flexcan c ? flexcan d ?flexray ? temp sensor ? bam table 15-1. peripheral bridge master/slave id table (continued) module internal master id xbar port peripheral
peripheral bridge (pbridge) 15-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? supports 32-bit slave peripherals. byte, 16-b it halfword, and 32-bit word reads and writes are supported to each slave peripheral. ? supports a pair of slave accesses for 64-bit instruction fetches. ? provides configurable per- module write buffering support. ? provides configurable per-module and per-master access protections. 15.1.4 modes of operation the pbridge has only one operating mode. 15.2 external signal description the pbridge has no external signals. 15.3 memory map and register definitions the memory map for the 32-bit pbridge a registers is shown in table 15-2 . table 15-2. pbridge a memory map address register bits access reset value section/page base (0xc3f0_0000) pbridge_a_mpcr?master privilege control register 32 r/w 0x7777_7777 15.3.1.1/15-6 base + (0x0004?0x001f) reserved base + 0x0020 pbridge_a_pacr0?peripheral access control register 0 32 r/w 0x5444_4444 15.3.1.2/15-7 base + (0x0024?0x003f) reserved base + 0x0040 pbridge_a_opacr0?off-platform peripheral access control register 0 32 r/w 0x4444_4444 15.3.1.2/15-7 base + 0x0044 pbridge_a_opacr1?off-platform peripheral access control register 1 32 r/w 0x4444_4444 15.3.1.2/15-7 base + 0x0048 pbridge_a_opacr2?off-platform peripheral access control register 2 32 r/w 0x4444_4444 15.3.1.2/15-7 base + 0x004c pbridge_a_opacr3?off-platform peripheral access control register 3 32 r/w 0x4444_4444 15.3.1.2/15-7 base + (0x0050?0x0053) reserved
peripheral bridge (pbridge) freescale semiconductor 15-5 pxr40 microcontroller reference manual, rev. 1 the memory map for the 32-bit pbridge b registers is shown table 15-3 . table 15-3. pbridge b memory map address register description bits access reset value section/page base (0xfff0_0000) pbridge_b_mpcr?master privilege control register 32 r/w 0x7777_7777 15.3.1.1/15-6 base + (0x0008?0x001f) reserved base + 0x0020 pbridge_b_pacr0?peripheral access control register 0 32 r/w 0x5444_4444 15.3.1.2/15-7 base + 0x0024 pbridge_b_pacr1?peripheral access control register 1 32 r/w 0x5444_4444 15.3.1.2/15-7 base + 0x0028 pbridge_b_pacr2?peripheral access control register 2 32 r/w 0x5444_4444 15.3.1.2/15-7 base + (0x002c?0x003f) reserved base + 0x0040 pbridge_b_opacr0?off-platform peripheral access control register 0 32 r/w 0x4444_4444 15.3.1.2/15-7 base + 0x0044 pbridge_b_opacr1?off-platform peripheral access control register 1 32 r/w 0x4444_4444 15.3.1.2/15-7 base + 0x0048 pbridge_b_opacr2?off-platform peripheral access control register 2 32 r/w 0x4444_4444 15.3.1.2/15-7 base + 0x004c pbridge_b_opacr3?off-platform peripheral access control register 3 32 r/w 0x4444_4444 15.3.1.2/15-7 base + (0x0050?0x0053) reserved
peripheral bridge (pbridge) 15-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 15.3.1 register descriptions there are three types of re gisters that control each pbridge. all registers are 32-bit registers and must be accessed in supervisor mode by trusted bus masters. additionally, these registers must only be read from or written to by a 32-bit aligned access. pbri dge registers are mapped into the pbridge a and pbridge_b address spaces. the prot ection and access fields of the mpcr, pacr, and opacr registers are 4-bits wide. although these regist ers are read/write, the reserved fields shown do not apply to this device and must remain at the reset va lue, therefore only write the fields? reset value to the reserved fields of these registers. 15.3.1.1 master privilege co ntrol register (pbridge_ x _mpcr) the master privilege c ontrol register (pbridge_ x _mpcr) specifies 4-bit access fields defining the access privilege level associated w ith a bus master in the platform, as well as specifying whether write accesses from this master are bufferable. the registers provi de one field per bus master. the following table describes the fields in th e pbridge master privil ege control register: address: base + 0x0000 access: r/w 0 1 2 3 4 5 6 7 8 9 101112131415 r mbw0 mtr0 mtw0 mpl0 mbw1 mtr1 mtw1 mpl1 01110111 w reset0111011101110111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mbw4 mtr4 mtw4 mpl4 mbw5 mtr5 mtw5 mpl5 mbw6 mtr6 mtw6 mpl6 0111 w reset0111011101110111 figure 15-2. master privilege control registers (pbridge_ x _mpcr) access field 0 access field 1 access field 2 access field 3 access field 4 access field 5 access field 6 access field 7
peripheral bridge (pbridge) freescale semiconductor 15-7 pxr40 microcontroller reference manual, rev. 1 15.3.1.2 peripheral access co ntrol registers (pbridge_ x _pacr) and off-platform peripheral access control registers (pbridge_ x _opacr) each of the pbridge on-platform peripherals has a 4-bit access field in a peripheral access control register (pacr) that defines the access levels suppor ted by the given module. a single pacr contains up to eight of these module-access fields, and the pacr register structure is shown in table 15-2 and table 15-3 . the pacr registers with thei r access fields are shown in figure 15-3 . there are three pacr registers, one for bridge a and two for bridge b. table 15-4. pbridge_ x _mpcr field descriptions field description 0 4 16 20 24 mbw n master buffer writes. determines whether the pbridge is enabled to buffer writes from the master. buffered writes are disabled by default. 0 buffered write accesses from the master are disabled 1 buffered write accesses from the master are enabled 1 5 17 21 25 mtr n master trusted for reads. determines whether the master is trusted for read accesses. trusted by default. 0 read accesses from the module are not trusted 1 read accesses from the module are trusted 2 6 18 22 26 mtw n master trusted for writes. determines whether the mast er is trusted for write accesses. trusted by default. 0 write accesses from the master are not trusted 1 write accesses from the master are trusted 3 7 19 23 27 mpl n master privilege level. determines how the privilege leve l of the master is determined. accesses not forced to user mode by default. 0 accesses from the master are forced to user mode 1 accesses from the master are not forced to user mode 8?15 28?31 reserved n = xbar port number master 0cpu core 1nexus 4edma a 5edma b 6flexray
peripheral bridge (pbridge) 15-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 also, each of the off-platform peripherals has a 4-bi t access field in an off-platform peripheral access control register (pbridge_ x _opacr) that defines the access le vels supported by the given module. each opacr contains up to eight of these module- access fields, and the opacr register structure is shown in table 15-2 and table 15-3 . the opacr registers with their access fields are shown in figure 15-4 . note write pbridge_x_pacr and pbridge_x_opacr with a read/modify/write for code compatibility. the type of peripheral designated by each pacr and opacr access field is shown in table 15-6 . address: base + 0x0020 (pbridge_x_pacr0) base + 0x0024 (pbridge_b_pacr1) base + 0x0028 (pbridge_b_pacr2) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rbw0 1 sp0 2 wp0 tp0 2 bw1 sp1 wp1 tp1 bw2 sp2 wp2 tp2 bw3 sp3 wp3 tp3 w reset 0 1 3 01 3 01 3 0001 3 0001 3 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bw4 sp4 wp4 tp4 bw5 sp5 wp5 tp5 bw6 sp6 wp6 tp6 bw7 sp7 wp7 tp7 w reset 0 1 3 0001 3 0001 3 0001 3 00 1 in the pbridge_a_pacr0 and pbridge_b_pacr0 registers, the bw0 bit is not writeable. 2 the default values are always used for the sp0 an d tp0 bits, even though the bits are writeable. 3 the default value is 0b0000 for pacr peripheral ac cess fields that are unused or not connected. figure 15-3. peripheral access control registers (pbridge_ x _pacr n ) access field 0 access field 1 access field 2 access field 3 access field 4 access field 5 access field 6 access field 7
peripheral bridge (pbridge) freescale semiconductor 15-9 pxr40 microcontroller reference manual, rev. 1 address: base + 0x0040 (pbridge_x_opacr0); base + 0x0044 (pbridge_x_opacr1); base + 0x0048 (pbridge_x_opacr2); base + 0x004c (pbridge_x_opacr3) access: r/w 0 12 3 456789101112131415 rbw0 1 sp0 2 wp0 tp0 2 bw1 sp1 wp1 tp1 bw2 sp2 wp2 tp2 bw3 sp3 wp3 tp3 w reset0 10 0 010001000100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bw4 sp4 wp4 tp4 bw5 sp5 wp5 tp5 bw6 sp6 wp6 tp6 bw7 sp7 wp7 tp7 w reset0 10 0 010001000100 1 in the pbridge_a_pacr0 and pbridge_b_pacr0 registers, the bw0 bit is not writeable 2 the default values are always used for the sp0 and tp0 bits, even though the bits are writeable. figure 15-4. off-platform peripheral access control registers (pbridge_ x _opacr n ) table 15-5. pbridge_ x _pacr n and pbridge_ x _opacr n field descriptions field description 0 4 8 12 16 20 24 28 bw n buffer writes. determines whether write accesses to this peripheral are allowed to be buffered. write accesses not bufferable by default 0 no write accesses are bufferable by the pbridge to this peripheral. 1 write accesses can be buffered by the pbridge to this peripheral. note: in pbridge_a_pacr0 and pbridge_b_pacr0, the bw0 bit is not writeable. 1 5 9 13 17 21 25 29 sp n supervisor protect. determines whether the peripheral requires supervisor privilege level for access. supervisor privilege level required by default. 0 the peripheral does not require supervisor privilege level for accesses. 1 the peripheral requires supervisor privilege level for accesses. the pbridge_x_mpcr[mply] control bit for the mast er must be set. if not, access is terminated with an error response and no peripheral access is initiated on the slave bus. note: for pbridge_a_pacr0 and pbridge_b_pacr0, you must have supervisor privileges to access pbridge registers. note: even though the sp0 bit (1) is writeable, the reset value for sp0 is always used. access field 0 access field 1 access field 2 access field 3 access field 4 access field 5 access field 6 access field 7
peripheral bridge (pbridge) 15-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the presence or absence of a module?s 4-bit acce ss field in pbridge_x_pac r or pbridge_x_opacr is based on whether the peripheral is present on the de vice. when no peripheral is connected, the field is not implemented and is read as zero. writes are ignored. note table 15-6 lists all of the access fields in the pacrs and opacrs in both pbridge a and pbridge b, and each of the peripherals present on the device. 2 6 10 14 18 22 26 30 wp n write protect. determines whether the peripheral allows write accesses. write accesses allowed by default. 0 this peripheral allows write accesses. 1 this peripheral is write protected. if a write acce ss is attempted, the access is terminated with an error response and no peripheral access is initiated on the slave bus. 3 7 11 15 19 23 27 31 tp n trusted protect. determines whether the peripheral allows accesses from an untrusted master. only trusted master privileges can access this register. 0 accesses from an untrusted master are allowed. 1 accesses from an untrusted master are not allowed. if an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the slave bus. note: for pbridge_a_pacr0 and pbridge_b_pacr0, you must have trusted master privileges to access pbridge registers. note: even though the tp0 bit (1) is writeable, the reset value for tp0 is always used. table 15-6. pacr and opacr access control registers and peripheral mapping register register address peripheral access field # peripheral type access field default value pbridge a pbridge_a_pacr0 pbridge_a_base + 0x0020 0 pbridge a 0b0101 1?7 reserved 0b0000 pbridge_a_opacr0 pbridge_a_base + 0x0040 0 fmpll 0b0100 1 ebi control 0b0100 2 flash a control 0b0100 3 flash b control 0b0100 4 siu 0b0100 5?7 reserved 0b0100 table 15-5. pbridge_ x _pacr n and pbridge_ x _opacr n field descriptions (continued) field description
peripheral bridge (pbridge) freescale semiconductor 15-11 pxr40 microcontroller reference manual, rev. 1 pbridge_a_opacr1 pbridge_a_base + 0x0044 0 emios 0b0100 1?6 reserved 0b0100 7 pmc 0b0100 pbridge_a_opacr2 pbridge_a_base + 0x0048 0 etpu 0b0100 1 reserved 0b0100 2 etpu pram 0b0100 3 etpu pram mirror 0b0100 4?5 etpu scm 0b0100 6?7 reserved 0b0100 pbridge_a_opacr3 pbridge_a_base + 0x004c 0?3 reserved 0b0100 4 pit/rti 0b0100 5?7 reserved 0b0100 pbridge b pbridge_b_pacr0 pbridge_b_base + 0x0020 0 pbridge b 0b0101 1 xbar 0b0100 2?3 reserved 0b0000 4 mpu 0b0100 5?7 reserved 0b0000 pbridge_b_pacr1 pbridge_b_base + 0x0024 0?5 reserved 0b0000 6 swt 0b0100 7 stm 0b0100 pbridge_b_pacr2 pbridge_b_base + 0x0028 0 escm 0b0100 1 edma a 0b0100 2 intc 0b0100 3?4 reserved 0b0100 5 edma b 0b0100 6?7 reserved 0b0000 pbridge_b_opacr0 pbridge_b_base + 0x0040 0 eqadc a 0b0100 1 eqadc b 0b0100 2 decimation filters a, b, c, d 0b0100 3 reserved 0b0100 4 dspi a 0b0100 5 dspi b 0b0100 6 dspi c 0b0100 7 dspi d 0b0100 table 15-6. pacr and opacr access control registers and peripheral mapping (continued) register register address peripheral access field # peripheral type access field default value
peripheral bridge (pbridge) 15-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 pbridge_b_opacr1 pbridge_b_base + 0x0044 0?3 reserved 0b0100 4 esci a 0b0100 5 esci b 0b0100 6 esci c 0b0100 7 reserved 0b0100 pbridge_b_opacr2 pbridge_b_base + 0x0048 0 flexcan a 0b0100 1 flexcan b 0b0100 2 flexcan c 0b0100 3 flexcan d 0b0100 4?7 reserved 0b0100 pbridge_b_opacr3 pbridge_b_base + 0x004c 0 flexray 0b0100 1?2 reserved 0b0100 3 temp sensor 0b0100 4-6 reserved 0b0100 7 bam 0b0100 table 15-6. pacr and opacr access control registers and peripheral mapping (continued) register register address peripheral access field # peripheral type access field default value
peripheral bridge (pbridge) freescale semiconductor 15-13 pxr40 microcontroller reference manual, rev. 1 15.4 functional description the pbridge serves as an interface between a system bus and the peripheral (slave) bus. it functions as a protocol translator. suppor t is provided for generating a pair of 32-bit peripheral accesses when targeted by a 64-bit system bus instruction access. no other bus-sizing acce ss support is provided. accesses that fall within the address space of th e pbridge are decoded to provide individual module selects for peripheral devices on the slave bus interface. 15.4.1 access support aligned 64-bit instruction accesses, aligned word an d halfword accesses, as well as byte accesses are supported for 32-bit peripherals. do not misalign instruction accesses to peripheral registers, although no explicit checking is pe rformed by the pbridge. note data accesses that cross a 32 -bit boundary are not supported. 15.4.2 peripheral write buffering the pbridge provides programmable write bufferi ng capability to buffer write accesses in the pbridge for later completion, while terminating th e system bus access early . this provides improved performance in systems where frequent writes to a slow peripheral occur. write buffering is controllable on a pe r-master and per-peripheral basis. enable write buffering for masters and peripherals only when an error termination from the slave bus does not occur or is safe to ignore. when write buffering is enabled, all acces ses through the pbridge must occu r in sequence; bypassing buffered writes is not supported. note the core detects that the write buff ering is complete before the write actually completes in the peripheral. if write buffering is enabled for a peripheral, the actual write takes an ad ditional two system clock cycles plus any additional system clock cycles the register requires. most registers in the mpc5500 family delay th e write by two clock cycl es, but some registers take longer. this early termination, as detected by the core, can defeat the mbar or msync instruction between the write to clear a flag bit and the write to the intc_eoir. therefore, if writ e buffering is enabled for a peripheral that has a flag bit, insert instructions between the mbar or msync instruction and the write to the intc_eoir that consumes at least the number of system clock cycles that the actual write is delayed.
peripheral bridge (pbridge) 15-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 15.4.2.1 read cycles read accesses are possible with the pbridge when the re quested access size is 32-bi ts or smaller, and is not misaligned across a 32-bit boundary. 64-bit data reads (not instructi on) are not supported. 15.4.2.2 write cycles write accesses are possible with the pbridge when the requested access size is 32-bits or smaller. misaligned writes that cross a 32-bit boundary are not supported. 64-bit data writes (not instruction) are not supported. 15.4.2.3 buffered write cycles single clock write responses to the system bus are possible with the pbridge when the requested write access is bufferable. if the requested access does not violate the permissi ons check, and if both master and peripheral are enabled for buffering writes, the pbridge internally buffers the write cycle. the write cycle is terminated early with ze ro system bus wait states. the ac cess proceeds normally on the slave interface, but error responses are ignored. all accesses are initiated and completed in order on the slave interface, regardless of buffering. if the buffer is full, a following write cycle stalls until it can either be buffered (if bufferable) or can be initiated. if the buffer has valid entries, a following read cycle stalls until the buffer is emptied and the read cycle can be completed. 15.4.3 general operation slave peripherals are modules that contain readable/wri table control and status re gisters. the system bus master reads and writes these re gisters through the pbridge. the p bridge generates module enables, the module address, transfer attribut es, byte enables, and writ e data as inputs to th e slave peripherals. the pbridge captures read data from the slave interface and dr ives it on the system bus. separate interface ports are provided for on-platfo rm and off-platform peri pherals. the distinction between on-platform and of f-platform is made to allow platfo rm-based designs incorporating the pbridge to separate the interface por ts to allow for ease of timing cl osure. in addition, module selects and control register storage for on -platform peripherals are allocated at synthesis time, allowing only needed resources to be implemented. off-platform m odule selects and control regi ster storage do not have the same degree of configurability.
peripheral bridge (pbridge) freescale semiconductor 15-15 pxr40 microcontroller reference manual, rev. 1 the modules that are on-platform and those that are off-platform are detailed in table 15-7 . pbridge occupies a 64 mb portion of the address space. a 0.5 mb portion of this space is allocated to on-platform peripherals. the remaining 63.5 mb is available for off-pl atform devices. th e register maps of the slave peripherals are located on 16-kb boundarie s. each slave peripheral is allocated one 16-kb block of the memory map, and is activated by one of the module enables from the pbridge. up to thirty-two 16-kb external slave peripherals can be implemented, oc cupying contiguous blocks of 16 kb. two global external slave module enables are available for the remaining 63 mb of address space to allow for customization and expansion of addressed peripheral de vices. in addition, a si ngle non-global module enable is also asserted whenever any of the 32 non-global module enables is asserted. pbridge is responsible for indicating to slave peripherals if an access is in supervisor or user mode. the pbridge can block user mode accesses to certain sl ave peripherals or it can allow the individual slave peripherals to determine if user mode accesses are allowed. in additi on, peripherals can be designated as write-protected. the pbridge supports the notion of trusted masters fo r security purposes. masters can be individually designated as trusted for reads, trusted for writes, or tr usted for both reads and writes, as well as being forced to look as though all accesses from a master are in user mode privilege level. pbridge also supports buffered writes , allowing write accesses to be te rminated on the system bus in a single clock cycle, and then subse quently performed on the slave interfa ce. write buffering is controllable on a per-peripheral basis. the pbridge im plements a two-entry 32-bit write buffer. table 15-7. on-platform and off-platform peripherals on-platform off-platform enhanced direct memory access (edma) deserial serial peripheral interface (dspi) pbridge a and b enhanced queued analog-to-digital converter (eqadc) interrupt controller (intc) enhanced se rial communication interface (esci) error correction status module (ecsm) flexcan controller area network system bus crossbar switch (x bar) boot assist module (bam) memory protection unit (mpu) system integration unit (siu) software watchdog timer (swt) enhanced modu lar input/output subsystem (emios) system timer module (stm) frequency modulated phase locked loop (fmpll) enhanced time processing unit (etpu) external bus interface (ebi) flash bus interface unit (fbiu) flexray power management controller (pmc) pit_rti decimation filters temp sensor
peripheral bridge (pbridge) 15-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 16-1 pxr40 microcontroller reference manual, rev. 1 chapter 16 memory protection unit (mpu) 16.1 introduction the memory protection unit (mpu) pr ovides hardware access control for a ll memory references generated in a device. using pre-programmed region descriptors that define memo ry spaces and their associated access rights, the mpu concurrently monitors al l system bus transactions and evaluates the appropriateness of each tr ansfer. memory references with sufficie nt access control rights are allowed to complete, but references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. the mpu implements a set of program-visible region de scriptors that monitor al l system bus addresses. the result is a hardware structur e with a two-dimensiona l connection matrix, wher e the region descriptors represent one dimension and the individual system bus addresses and attributes are the second dimension.
memory protection unit (mpu) 16-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16.1.1 block diagram a simplified block diagram illustra tes how the mpu block is connected to the four xbar mpu ports and the shared port splitter (see figure 16-1 and table 16-1 ). figure 16-1. mpu connections to xbar slaves table 16-1 enumerates the mpu ports that ar e attached to slave modules. th e master ids of all bus master modules are also shown, as their valu es are required to conf igure certain mpu regist ers described in this chapter. table 16-1. xbar switch ports module mpu master id mpu slave port e200z7 core?cpu instruction 0 ? e200z7?data 0 ? nexus 3 0 ? edma_a 4 ? edma_b 5 ? flexray 6 ? on-chip flash ? ? ebi (development bus) ? 0 on-chip sram ? 1 peripheral bridge a (pbridge_a) ? 2 peripheral bridge b (pbridge_b) ? 3 xbar on-chip sram pbridge_a ebi edma_a edma_b e200z7 flexray on-chip flash mpu port numbers mpu0 mpu1 mpu2 mpu3 pbrdige_b ports masters slaves e200z7, nexus 3
memory protection unit (mpu) freescale semiconductor 16-3 pxr40 microcontroller reference manual, rev. 1 16.1.2 features the mpu has these major features: ? support for 16 memory region descri ptors, each 128 bits in size ? specification of start and end addresses provide gran ularity for region sizes from 32 bytes to 4gb ? mpu is invalid at reset, thus no access restrictions are enforced ? two types of access control definitions: proc essor core bus master (e200z7) supports the traditional {read, write, execute} permissions with i ndependent definitions for supervisor and user mode accesses; the remaining non-core bus masters (edma_a, edma_b, flexray) support {read, wr ite} attributes ? automatic hardware maintenance of the region de scriptor valid bit rem oves issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control wo rd for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only ? for overlapping region descript ors, priority is given to permission granting over access denying as this approach provides mo re flexibility to system software ? support for four ahb slave port connections ? pbridge_a, pbridge_b, ebi (devel opment bus), general purpose sram ? mpu hardware monitors every ahb slave port access using the pre-programmed memory region descriptors ? an access protection error is det ected if a memory reference doe s not hit in any memory region or the reference is flagged as illegal in all memo ry regions where it does hi t; in the event of an access error, the ahb reference is terminated wi th an error response and the mpu inhibits the bus cycle being sent to the targeted slave device ? 64-bit error registers, one for e ach ahb slave port, capture the la st faulting address, attributes, and detail information
memory protection unit (mpu) 16-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16.2 memory map and registers this section provides a detailed description of all mpu registers. 16.2.1 module memory map the mpu memory map is shown in table 16-2 . the address of each register is given as an offset to the mpu base address. registers are listed in address or der, identified by complete name and mnemonic, and list the type of accesses allowed. the mpu registers can be referen ced using 32-bit (word) accesses only. attempted references using different access sizes, to undefined (r eserved) addresses, or with a non- supported access type (for example, a write to a read-only re gister or a read of a write-only regi ster) generate an error termination. table 16-2. mpu memory map offset from mpu_base (0xfff1_0000) register bits access reset value section/page 0x0000 mpu_cesr ? mpu control/erro r status register 32 r/w 0x0081_4200 16.2.2.1/16-6 0x0004?0x000f reserved 0x0010 mpu_ear0 ? mpu error address register, mpu port 0 32 r ? 1 16.2.2.2/16-7 0x0014 mpu_edr0 ? mpu error detail register, mpu port 0 32 r ? 1 16.2.2.3/16-7 0x0018 mpu_ear1 ? mpu error address register, mpu port 1 32 r ? 1 16.2.2.2/16-7 0x001c mpu_edr1 ? mpu error detail register, mpu port 1 32 r ? 1 16.2.2.3/16-7 0x0020 mpu_ear2 ? mpu error address register, mpu port 2 32 r ? 1 16.2.2.2/16-7 0x0024 mpu_edr2 ? mpu error detail register, mpu port 2 32 r ? 1 16.2.2.3/16-7 0x0028 mpu_ear3? mpu error address register, mpu port 3 32 ro ? 1 16.2.2.2/16-7 0x002c mpu_edr3?mpu error detail register, mpu port 3 32 ro ? 1 16.2.2.3/16-7 0x0030?0x03ff reserved 0x0400 mpu_rgd0 ? mpu region descriptor 0 32 r/w ? 1 16.2.2.4/16-8 0x0410 mpu_rgd1 ? mpu region descriptor 1 32 r/w ? 1 16.2.2.4/16-8 0x0420 mpu_rgd2 ? mpu region descriptor 2 32 r/w ? 1 16.2.2.4/16-8 0x0430 mpu_rgd3 ? mpu region descriptor 3 32 r/w ? 1 16.2.2.4/16-8 0x0440 mpu_rgd4 ? mpu region descriptor 4 32 r/w ? 1 16.2.2.4/16-8 0x0450 mpu_rgd5 ? mpu region descriptor 5 32 r/w ? 1 16.2.2.4/16-8 0x0460 mpu_rgd6 ? mpu region descriptor 6 32 r/w ? 1 16.2.2.4/16-8 0x0470 mpu_rgd7 ? mpu region descriptor 7 32 r/w ? 1 16.2.2.4/16-8 0x0480 mpu_rgd8 ? mpu region descriptor 8 32 r/w ? 1 16.2.2.4/16-8
memory protection unit (mpu) freescale semiconductor 16-5 pxr40 microcontroller reference manual, rev. 1 0x0490 mpu_rgd9 ? mpu region descriptor 9 32 r/w ? 1 16.2.2.4/16-8 0x04a0 mpu_rgd10 ? mpu region descriptor 10 32 r/w ? 1 16.2.2.4/16-8 0x04b0 mpu_rgd11 ? mpu region descriptor 11 32 r/w ? 1 16.2.2.4/16-8 0x04c0 mpu_rgd12 ? mpu region descriptor 12 32 r/w ? 1 16.2.2.4/16-8 0x04d0 mpu_rgd13 ? mpu region descriptor 13 32 r/w ? 1 16.2.2.4/16-8 0x04e0 mpu_rgd14 ? mpu region descriptor 14 32 r/w ? 1 16.2.2.4/16-8 0x04f0 mpu_rgd15 ? mpu region descriptor 15 32 r/w ? 1 16.2.2.4/16-8 0x00500?0x07f f reserved 0x0800 mpu_rgdaac0 ? mpu rgd alternate access control 0 32 w ? 1 16.2.2.5/16-13 0x0804 mpu_rgdaac1 ? mpu rgd alternate access control 1 32 w ? 1 16.2.2.5/16-13 0x0808 mpu_rgdaac2 ? mpu rgd alternate access control 2 32 w ? 1 16.2.2.5/16-13 0x080c mpu_rgdaac3 ? mpu rgd alternate access control 3 32 w ? 1 16.2.2.5/16-13 0x0810 mpu_rgdaac4 ? mpu rgd alternate access control 4 32 w ? 1 16.2.2.5/16-13 0x0814 mpu_rgdaac5 ? mpu rgd alternate access control 5 32 w ? 1 16.2.2.5/16-13 0x0818 mpu_rgdaac6 ? mpu rgd alternate access control 6 32 w ? 1 16.2.2.5/16-13 0x081c mpu_rgdaac7 ? mpu rgd alternate access control 7 32 w ? 1 16.2.2.5/16-13 0x0820 mpu_rgdaac8 ? mpu rgd alternate access control 8 32 w ? 1 16.2.2.5/16-13 0x0824 mpu_rgdaac9 ? mpu rgd alternate access control 9 32 w ? 1 16.2.2.5/16-13 0x0828 mpu_rgdaac10 ? mpu rgd alternate access control 10 32 w ? 1 16.2.2.5/16-13 0x082c mpu_rgdaac11 ? mpu rgd alternate access control 11 32 w ? 1 16.2.2.5/16-13 0x0830 mpu_rgdaac12 ? mpu rgd alternate access control 12 32 w ? 1 16.2.2.5/16-13 0x0834 mpu_rgdaac13 ? mpu rgd alternate access control 13 32 w ? 1 16.2.2.5/16-13 0x0838 mpu_rgdaac14 ? mpu rgd alternate access control 14 32 w ? 1 16.2.2.5/16-13 table 16-2. mpu memory map (continued) offset from mpu_base (0xfff1_0000) register bits access reset value section/page
memory protection unit (mpu) 16-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16.2.2 register descriptions this section lists the mpu registers in address orde r and describes the registers and their bit fields. 16.2.2.1 mpu control/error st atus register (mpu_cesr) the mpu_cesr provides one byte of error status and three bytes of configuration information. a global mpu enable/disable bit is also included in this register. 0x083c mpu_rgdaac15 ? mpu rgd alternate access control 15 32 w ? 1 16.2.2.5/16-13 0x0840?0x08ff reserved 1 see register definition. offset: mpu_base+0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sperr 1 1 each sperr bit can be cleared by wr iting a one to th e bit location. 1 0 0 0 hrl nsp nrgd 0 0 00 0 0 0v l d w (w1c) reset00000000100000010100001000000000 figure 16-2. mpu control/error status register (mpu_cesr) table 16-3. mpu_cesr bit field descriptions field description 0?7 sperr mpu port n error (where the mpu port number matches the bit number (see figure 16-1 )). each bit in this read-only field represents a flag maintained by the mpu for si gnaling the presence of a captured error contained in the mpu_ear n and mpu_edr n registers. the individual bit is set when the hardware detects an error and records the faulting address and attributes. it is cleared when the corresponding bit is written to a logical one. if another error is captured at the exact same cycle as a wr ite of a logical one, this flag remain s set. a find-first-one instruction (or equivalent) can be used to detect the presence of a captured error. 0 the corresponding mpu_ear n /mpu_edr n registers do not contain an unread captured error 1 the corresponding mpu_ear n /mpu_edr n registers do contain an unread captured error note: bit 0 indicates an ebi protection error, bit 1 indicates an sram protection error, bit 2 indicates a peripheral bridge b protection error, and bit 3 indicates a peripheral bridge a protection error. 8?11 reserved 12?15 hrl hardware revision level. this 4-bit read-only field specifie s the mpu?s hardware and definition revision level. it can be read by software to determine the functional definition of the module. this field reads as 0 on this device. 16?19 nsp number of mpu ports. this 4-bit read-only field specif ies the number of slave ports connected to the mpu. this field reads as 0b0100 on this device. table 16-2. mpu memory map (continued) offset from mpu_base (0xfff1_0000) register bits access reset value section/page
memory protection unit (mpu) freescale semiconductor 16-7 pxr40 microcontroller reference manual, rev. 1 16.2.2.2 mpu error address register, mpu port 0 to 3 (mpu_ear n ) when the mpu detects an access error on mpu port n , the 32-bit reference address is captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field set. additional information about the faulting access is captured in the corresponding mpu_edr n register at the same time. 16.2.2.3 mpu error detail register, mpu port 0 to 3 (mpu_edr n ) when the mpu detects an access error on mpu port n , 32 bits of error detail ar e captured in this read-only register and the corresponding bit in the mpu_cesr [sperr] field set. information on the faulting address is captured in the corresponding mpu_ear n register at the same tim e. a read of the mpu_edr n register clears the corresponding bi t in the mpu_cesr[sperr] field. 20?23 nrgd number of region descriptors. this 4-bit read-only field specifies the number of region descriptors implemented in the mpu. the defined encodings include: 0000 8 region descriptors 0010 16 region descriptors this field reads as 0b0010 on this device. 24?30 reserved 31 vld valid. this bit provides a global enable/disable for the mpu. 0 the mpu is disabled 1 the mpu is enabled while the mpu is disabled, all accesses from all bus masters are allowed. offset: mpu_base + 0x0010 (mpu_ear0) mpu_base + 0x0018 (mpu_ear1) mpu_base + 0x0020 (mpu_ear2) mpu_base + 0x0028 (mpu_ear3) access: user read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eaddr w reset???????????????????????????????? figure 16-3. mpu error address register, mpu port n (mpu_ear n ) table 16-4. mpu_ear bit field descriptions field description 0?31 eaddr error address. this read-only field is the reference address from mpu port n that generated the access error. table 16-3. mpu_cesr bit field descriptions (continued) field description
memory protection unit (mpu) 16-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16.2.2.4 mpu region descriptor n (mpu_rgd n ) each 128-bit (16 byte) region descri ptor specifies a given memory space and the access attributes associated with that space. the descriptor definition is fundament al to the operation of the mpu. the region descriptors ar e organized sequentially in the mpu?s pr ogramming model and each of the four 32-bit words are detailed in the subsequent sections. offset: mpu_base + 0x00014 (mpu_edr0) mpu_base + 0x001c (mpu_edr1) mpu_base + 0x0024 (mpu_edr2) mpu_base + 0x002c (mpu_edr3) access: user read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eacd epid emn eattr e r w w reset???????????????????????????????? figure 16-4. mpu error detail register, mpu port n (mpu_edr n ) table 16-5. mpu_edr bit field descriptions field description 0?15 eacd error access control detail. this 16-bit read-only field im plements one bit per region descriptor and is an indication of the region descriptor hit logically-anded with the access error indication. the mpu performs a reference-by-reference evaluation to determine the presence/absence of an access error. when an error is detected, the hit-qualified access contro l vector is captured in this field. if the mpu_edr n register contains a capt ured error and the eacd field is all zeroes, this signals an access that did not hit in any region descriptor. all non-zero eacd values signal references that hit in a region descriptor(s), but failed due to a protection error as defined by the specific set bits. 16?23 epid error process identification. this 8-bit read-only field records the process identi fier of the faulting reference. the process identifier is typically driven by processor cores only; for other bus masters, this field is cleared. 24?27 emn error master number. this 4-bi t read-only field records the logical master number of the faulting reference. this field is used to determine the bus master that generated the access error. 28?30 eattr error attributes. this 3-bit read-only field records attrib ute information about the faulting reference. the supported encodings are defined as: 000 user mode, instruction access 001 user mode, data access 010 supervisor mode, instruction access 011 supervisor mode, data access all other encodings are reserved. for non-core bus masters, the access attribute information is typically wired to supervisor, data (0b011). 31 erw error read/write. this 1-bit read-only field signals the access type (read, write) of the faulting reference. 0 read 1write
memory protection unit (mpu) freescale semiconductor 16-9 pxr40 microcontroller reference manual, rev. 1 16.2.2.4.1 mpu region descriptor n , word 0 (mpu_rgd n .word0) the first word of the mpu region descriptor define s the 0-modulo-32 byte start address of the memory region. writes to this word clear the region descriptor?s valid bit. 16.2.2.4.2 mpu region descriptor n , word 1 (mpu_rgd n .word1) the second word of the mpu region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this word clear the region descriptor?s valid bit. 16.2.2.4.3 mpu region descriptor n , word 2 (mpu_rgd n .word2) the third word of the mpu region de scriptor defines the access control rights of the memory region. the access control privileges are depende nt on two broad classifications of bus masters. bus masters 0?3 are typically reserved for processor cores. the correspondi ng access control is a 6-bit field defining separate privilege rights for user and supervisor mode accesse s as well as the optional inclusion of a process offset: mpu_base + 0x400 + (16* n ) + 0x0 (mpu_rgd n .word0) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r srtaddr 0 0 0 00 w reset00000000000000000000000000000000 figure 16-5. mpu region descript or, word 0 register (mpu_rgd n .word0) table 16-6. mpu_rgd word 0 description field description 0?26 srtaddr start address. this field defines the most significant bi ts of the 0-modulo-32 byte start address of the memory region. 27?31 reserved offset: mpu_base + 0x400 + (16* n ) + 0x4 (mpu_rgd n .word1) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r endaddr 1 1 1 11 w reset (n=0) 11111111111111111111111111111111 reset (n>0) 00000000000000000000000000011111 figure 16-6. mpu region descript or, word 1 register (mpu_rgd n .word1) table 16-7. mpu_rgd word 1 description field description 0?26 endaddr end address. this field defines the most significant bi ts of the 31-modulo-32 byte end address of the memory region. there are no hardware checks to verify that endaddr > srtaddr; the software must properly load these region descriptor fields. 27?31 reserved
memory protection unit (mpu) 16-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 identification field within the definition. bus mast ers 4?7 are typically reserved for data movement engines and their capabilities are limited to separate read and write pe rmissions. for these fields, the bus master number refers to the logical master number defined as the ahb hmaster[3:0] signal. for the processor privilege rights, there are three flags associated with this functi on: {read, write, execute}. in this context, these flags follow the traditional definition: ? read (r) permission refers to th e ability to access the referenced memory address using an operand (data) fetch. ? write (w) permission refers to the ability to upda te the referenced memory address using a store (data) instruction. ? execute (x) permission refers to the ability to read the referenced memory address using an instruction fetch. the evaluation logic defines the processor access type based on multiple ahb signals: read or write as specified by the hwrite signal and the low-or der two bits of hprot[1:0] , which identify a data reference versus an instruction fetch and the operating mode (supervisor, user) of the requesting processor. for non-processor data movement engines (bus masters 4?7), the evaluation logic simply uses hwrite to determine if the access is a read or write. the hprot[1:0] signal is ignored for these masters. writes to this word clear the region descriptor?s valid bit. because it is also expected that system software may adjust only the access controls within a region descriptor (mpu_rgd n .word2) as different tasks execute, an alternate programming view of this 32-bit entity is provided. if only the access controls are being updated, this operation should be performed by writing to mpu_rgdaac n (alternate access control n ) as stores to these locations do not affect the descriptor?s valid bit. offset: mpu_base + 0x400 + (16* n ) + 0x8 (mpu_rgd n .word2) access: user read/write 0123456789101112131415 r0 0 m6re m6we m5re m5we m4re m4we 00 0 000 0 0 w reset (n=0) 0000000001100001 reset (n>0) 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 m0pe m0sm m0um w rwx reset (n=0) 1000011000000000 reset (n>0) 0000000000000000 note: refer to table 16-1 to see the master id assignments. figure 16-7. mpu region descript or, word 2 register (mpu_rgd n .word2)
memory protection unit (mpu) freescale semiconductor 16-11 pxr40 microcontroller reference manual, rev. 1 table 16-8. mpu_rgd word 2 description field description note: for future code compatibility, do not change the value of reserved bits from their reset value 0?1 reserved 2 4 6 m n re bus master id n read enable. if set, this flag allows bus master id n to perform read operations. if cleared, any attempted read by bus master id n terminates with an access error and the read is not performed. note: see ta b l e 1 6 - 1 for the mpu master id list. 3 5 7 m n we bus master id n write enable. if set, this flag allows bus master id n to perform write operations. if cleared, any attempted write by bus master id n terminates with an access error and the write is not performed. note: see ta b l e 1 6 - 1 for the mpu master id list. 8?25 reserved 26 m0pe bus master id 0 process identifier enable. if set, this fl ag specifies that the process identifier and mask defined in mpu_rgd n .word3 are to be included in the region hit evalua tion. if cleared, the region hit evaluation does not include the process identifier. note: see ta b l e 1 6 - 1 for the mpu master id list. 27?28 m0sm bus master id 0 supervisor mode access control. this 2- bit field defines the access controls for bus master id 0 when operating in supervisor mode. the m0sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m0um for user mode note: see ta b l e 1 6 - 1 for the mpu master id list. 29?31 m0um bus master id 0 user mode access control. this 3-bit fi eld defines the access controls for bus master id 0 when operating in user mode. the m0um field consists of th ree independent bits, enabling read, write, and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. note: see ta b l e 1 6 - 1 for the mpu master id list.
memory protection unit (mpu) 16-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16.2.2.4.4 mpu region descriptor n , word 3 (mpu_rgd n .word3) the fourth word of the mpu region descriptor contains the optional process identi fier and mask, plus the region descriptor?s valid bit. because the region descriptor is a 128-bit entity, there are potential coherency issues as this structure is being updated because multiple writes are required to update the entire descriptor. accordingly, the mpu hardware assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from generating spurious acces s errors. in particular, it is expected that a complete update of a region descriptor is typically done with seque ntial writes to mpu_rgd n .word0, then mpu_rgd n .word1, ... and mpu_rgd n .word3. the mpu hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. writes to this word set/clear the valid bit in a normal manner. because it is also expected that system software may adjust the acc ess controls within a region descriptor (mpu_rgdn.word2) only as different tasks execute, an altern ate programming view of this 32-bit entity is provided. if only the acces s controls are being updated, this opera tion must be performed by writing to mpu_rgdaac n (alternate access control n ) as stores to these locations do not affect the descriptor?s valid bit. offset: mpu_base + 0x400 + (16* n ) + 0xc (mpu_rgd n .word3) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pid pidmask 00 00000000 00 0 0 0v l d w reset00000000000000000000000000000000 figure 16-8. mpu region descript or, word 3 register (mpu_rgd n .word3) table 16-9. mpu_rgd word 3 description field description 0?7 pid process identifier. this 8-bit field spec ifies that the optional process identifier is to be included in the determination of whether the current access hits in the region descriptor. this field is combined with the pidmask and included in the region hit determination if mpu_rgd n .word2[mxpe] is set. 8?15 pidmask process identifier mask. this 8-bit fi eld provides a masking capability so th at multiple process identifiers can be included as part of the region hit determination. if a bit in the pidmask is set, the corresponding bit of the pid is ignored in the comparison. this field is combined wit h the pid and included in the region hit determination if mpu_rgd n .word2[mxpe] is set. for more information on the handling of the pid and pidmask, see section 16.3.1.1, access evaluation?hit determination . 16?30 reserved 31 vld valid. this bit signals the region descriptor is valid. any write to mpu_rgd n .word{0,1,2} clears this bit, but a write to mpu_rgd n .word3 sets or clears this bit depending on bit 31 of the write operand. 0 region descriptor is invalid 1 region descriptor is valid
memory protection unit (mpu) freescale semiconductor 16-13 pxr40 microcontroller reference manual, rev. 1 16.2.2.5 mpu region descriptor alternate access control n (mpu_rgdaac n ) as noted in section 16.2.2.4.3, mpu region descript or n, word 2 (mpu_rgdn.word2) , it is expected that because system software may adjust th e access controls within a region descriptor (mpu_rgd n .word2) only as different tasks execute, an alternate programming view of this 32-bit entity is desired. if only the access controls are being updated, this operation s hould be performed by writing to mpu_rgdaac n (alternate access control n ) as stores to these locations do not affect the descriptor?s valid bit. the memory address therefore provides an alternate location for updating mpu_rgd n .word2. because the mpu_rgdaac n register is another memory mapping for mpu_rgd n .word2, the field definitions shown in table 16-10 are identical to those presented in table 16-8 . address: mpu_base + 0x800 + (4* n ) (mpu_rgdaac n ) access: user read/write 0123456789101112131415 r0 0 m6re m6we m5re m5we m4re m4we 00000000 w reset (n=0) 0000000001100001 reset (n>0) 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 m0pe m0sm m0um w rwx reset (n=0) 1000011000000000 reset (n>0) 0000000000000000 figure 16-9. mpu rgd alternate access control n (mpu_rgdaac n ) table 16-10. mpu_rgdaac bit field descriptions field description note: for future code compatibility, do not change the value of reserved bits from their reset value 0?1 reserved 2 4 6 m n re bus master id n read enable. if set, this flag allows bus master id n to perform read operations. if cleared, any attempted read by bus master id n terminates with an access error and the read is not performed. note: see ta b l e 1 6 - 1 for the mpu master id list. 3 5 7 m n we bus master n write enable. if set, this flag allows bus master n to perform write operations. if cleared, any attempted write by bus master n terminates with an access error and the write is not performed. note: see ta b l e 1 6 - 1 for the mpu master id list. 8?25 reserved
memory protection unit (mpu) 16-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16.3 functional description in this section, the functional operati on of the mpu is detailed. in partic ular, subsequent sections discuss the operation of the access evaluation macro as well as the handling of error-terminated ahb bus cycles. 16.3.1 access evaluation as discussed, the basic operation of the mpu is pe rformed in the access evaluation macro, a hardware structure replicated in the two- dimensional connection matrix. the access evaluation macro inputs the ahb system bus address and the cont ents of a region descriptor (rgd n ) and performs two major functions: region hit determination and det ection of an access protection violation. 16.3.1.1 access evaluati on?hit determination to determine if the current ahb re ference hits in the given region, two magnitude comparators are used with the region?s start and end addresses. there ar e no hardware checks to verify that the region end address is greater than or equal to the region start ad dress. the software must properly load appropriate values into these fields of the region descriptor. in addition to the comparison of the ahb reference a ddress versus the region de scriptor?s start and end addresses, the optional process identifier is examin ed against the region desc riptor?s pid and pidmask fields. for ahb bus masters that do not output a process identifier, the mpu forces the pid term to be asserted. 16.3.1.2 access evalua tion?privilege violation determination while the access evaluation macro is making the region hit determinat ion, the logic is also evaluating if the current access is allowed by the permissions defined in the region de scriptor. using the ahb supervisor/user mode signals, a set of permissions is generated from th e appropriate fields in the region descriptor. the protection violat ion logic evaluates the access ag ainst the effective permissions. 26 m0pe bus master 0 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit eval uation. if cleared, then the region hit evaluation does not include the process identifier. 27?28 m0sm bus master 0 supervisor mode access control. this 2-bi t field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m0um for user mode note: see ta b l e 1 6 - 1 for the mpu master id list. 29?31 m0um bus master 0 user mode access control. this 3-bit fi eld defines the access controls for bus master 0 when operating in user mode. the m0um field consists of three independent bits, enabling read, write, and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. note: see ta b l e 1 6 - 1 for the mpu master id list. table 16-10. mpu_rgdaac bit field descriptions (continued) field description
memory protection unit (mpu) freescale semiconductor 16-15 pxr40 microcontroller reference manual, rev. 1 the access evaluation macro th en uses the hit and permission signals to determine if the current access is allowed and the mpu_edr n (error detail regi ster) is updated in the event of an error. 16.3.2 ahb error terminations for each ahb slave port being monito red, the mpu tests any access for permission violations as above. if a violation occurs, the mpu terminates the bus cycle and reports a protection error for three conditions: 1. if the access does not hit in any region descriptor, a protection error is reported. 2. if the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. 3. if the access hits in multiple (overlapping) regions a nd all regions signal prot ection violations, then a protection error is reported. the third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to syst em software in region descriptor assignments. for an example of the use of overlapping region descriptors, see section 16.5, application information . when the mpu causes a termination error to occur, the effect on the system de pends on the bus master requesting the access. if the error wa s caused by a core access, a machin e check is taken. if the error was caused by an edma access, an edma source or destination error occurs in the edma controller, which can be enabled to provide an interrupt request th rough the intc. if the erro r was caused by a flexray access, a controller host interface (chi) illegal system memory access error occurs in the flexray controller, which can be enabled to provi de an interrupt request to the intc. 16.4 initialization information the reset state of mpu_cesr[vld] disables the entire module. while the mpu is disabl ed, all accesses from all bus masters are al lowed. this state also minimizes the pow er dissipation of the mpu. the power dissipation of each access evaluation macr o is minimized when the associated region descriptor is marked as invalid or when mpu_cesr[vld] = 0. typically the appropriate number of region descriptors (mpu_rgd n ) are loaded at system startup, including the setting of the mpu_rgd n .word3[vld] bits, before mpu_ce sr[vld] is set, enabling the module. this approach allows all the loaded region descriptors to be enabled simultaneously. once the mpu is enabled, if a memory reference does not hit in any region descriptor, the attempted access is terminated with an error. 16.5 application information in an application?s system, interf acing with the mpu can generally be classified into the following activities: 1. creation of a new memory region requires load ing the appropriate region descriptor into an available register location. when a ne w descriptor is loaded into a rgd n , it would typically be performed using four 32-bit wo rd writes. as discussed in section 16.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) , the hardware assists in the maintenance of the valid
memory protection unit (mpu) 16-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 bit, so if this approach is foll owed, there are no coherency issues associated with the multi-cycle descriptor writes. deletion/re moval of an existing memory region is performed by clearing mpu_rgd n .word3[vld]. 2. if only the access rights for an existing region de scriptor need to change , a 32-bit write to the alternate version of the access control word (mpu_rgdaac n ) would typically be performed. writes to the region descriptor using this altern ate access control location do not affect the valid bit, so there are, by definition, no coherency i ssues involved with the update. the access rights associated with the memory region switch instanta neously to the new value as the peripheral write completes. 3. if the region?s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the region descriptor: mpu_rgd n .word{0,1,3}, where the writes to word0 and word1 redefine the start and end addresses respectively and the write to word3 re-enables the region descri ptor valid bit. in many situati ons, all four words of the region descriptor would be rewritten. 4. typically, references to the mpu?s programming m odel would be restricted to supervisor mode accesses from a specific processor(s) , so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. 5. when the mpu detects an access error, the curren t ahb bus cycle is terminated with an error response and information on the faulti ng reference captured in the mpu_ear n and mpu_edr n registers. the error-terminated ahb bus cycle typical ly initiates some type of error response in the originating bus master. for example, a proce ssor core may respond with a bus error exception, while a data movement bus master may respond with an error interr upt. in any event, the processor can retrieve the captured error address and detail information simply be reading the mpu_e{a,d}r n registers. information on which error re gisters contain captur ed fault data is signaled by mpu_cesr[sperr]. 6. finally, consider the use of overlapping region descriptors. appl ication of overla pping regions can reduce the number of descriptors required for a gi ven set of access controls. in the overlapping memory space, the protection right s of the corresponding region desc riptors are logically summed together (the boolean or operator) . in the following example of a dual-core system, there are four bus masters: the two processors (cp0, cp1) and two dma engine s (edma, a traditional data movement engine transferring data between ram and peripherals, and flex ray, a second engine transferring data to/from the ra m only). consider the followi ng region descriptor assignments: region description rgdn cp0 cp1 edma flexray cp0 code 0 rwx r-- -- -- flash cp1 code 1 r-- rwx -- -- cp0 data & stack 2 rw- --- -- -- ram cp0 -> cp1 shared data 3 r-- r-- -- -- cp1 -> cp0 shared data cp0 data & stack 4 --- rw- -- -- shared dma data 5 rw- rw- rw rw figure 16-10. overlapping re gion descriptor example
memory protection unit (mpu) freescale semiconductor 16-17 pxr40 microcontroller reference manual, rev. 1 in this example, there are eight de scriptors used to span nine regi ons in the three main spaces of the system memory map (flash, ram, and periphe ral space). each region indicates the specific permissions for each of the four bus masters and this definition provides an appropriate set of shared, private and executable memory spaces. of particular interest are the two overlapping spaces: region descriptors 2 and 3, and 3 and 4. the space defined by rgd2 with no overlap is a private data and st ack area that provides read/write access to cp0 only. the overlapping sp ace between rgd2 and rgd3 defines a shared data space for passing data from cp 0 to cp1 and the access controls are defined by the logical or of the two region descriptors. thus, cp0 has ( rw- | r-- ) = ( rw- ) permissions, while cp1 has ( --- | r-- ) = ( r-- ) permission in this space. both dma engines are excluded from this shared processor data region. the overlapping spaces be tween rgd3 and rgd4 de fines another shared data space, this one for passing data from cp 1 to cp0. for this overlapping space, cp0 has ( r-- | --- ) = ( r-- ) permission, while cp1 has ( rw- | r-- ) = ( rw- ) permission. the non-overlapped space of rgd4 defines a pr ivate data and stac k area for cp1 only. the space defined by rgd5 is a shared data region, accessible by all four bus masters. finally, the slave peripheral space mapped onto the peripheral bus is partitioned into two regions: one (rgd6) containing the mpu?s programming model accessible only to the two processor cores, and the remaining peripheral region (rgd7) accessible to both processors and the traditional edma master. this example is intended to show one possible application of the capabilities of the memory protection unit in a typical system. mpu 6 rw- rw- -- -- peripheral peripherals 7 rw- rw- rw -- region description rgdn cp0 cp1 edma flexray figure 16-10. overlapping re gion descriptor example
memory protection unit (mpu) 16-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 17-1 pxr40 microcontroller reference manual, rev. 1 chapter 17 error correction status module (ecsm) 17.1 introduction the error correction status module (ecsm) provides a se t of registers that confi gure and report ecc errors for the device including accesses to ram and flash memory. the applicat ion may configure the device for the types of memory errors to be re ported, and then query a set of read- only status and information registers to identify any errors that have been signaled. there are two types of ecc errors: correctable and non-correctable. a correctable ecc error is generated when only one bit is wrong in a 64-bit doubleword. in th is case, it is corrected automatically by hardware and no flags or other indication is set that the erro r occurred. a non-correctable ecc error is generated when two or more bits in a 64-bit doubleword are incorrect. non-correctable ecc errors cause an interrupt, and if enabled, additional erro r details are available in the ecsm. error correction is implemented on 64 bits of data at a time, using eight bits for ecc for every 64-bit doubleword. ecc is checked on reads and ca lculated on writes per the following: 1. 64 bits containing the desired byte / halfword / word or doubleword in memory is read and ecc checked. 2. if the access is a write, then ? the new byte / halfword / word / doubl eword is merged into the 64 bits. ? new ecc bits are calculated. ? the 64 bits and the new ecc bits are written back. note to use ecc with sram, the sram memo ry must be written to before ecc is enabled. 17.1.1 features the ecsm has this major feature: ? registers for capturing information on memory errors if error-corr ecting codes (ecc) are implemented.
error correction status module (ecsm) 17-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 17.2 memory map and registers this section provides a detailed de scription of all ecsm registers. 17.2.1 module memory map the ecsm memory map is shown in table 17-1 . the address of each register is given as an offset to the ecsm base address. registers are li sted in address order, identified by complete name and mnemonic, and lists the type of accesses allowed. table 17-1. ecsm memory map offset from ecsm_base_addr (0xfff4_0000) register bits access reset value 1 1 please refer to the register def inition. u = undefined at reset. section/page 0x0000 ecsm_pct?processor core type 16 ro u 17.2.2.1/17-4 0x0002 ecsm_rev?revision 16 ro u 17.2.2.2/17-4 0x0008 ecsm_imc?peripheral on-platform module configuration 32 ro u 17.2.2.3/17-4 0x000f ecsm_mrsr?misc. reset status 8 ro 0x00 17.2.2.4/17-4 0x0010?0x0042 reserved 0x0043 ecsm_ecr?ecc config uration register 8 r/w 0x00 17.2.2.5/17-5 0x0047 ecsm_esr?ecc status register 8 r/w 0x00 17.2.2.6/17-6 0x004a ecsm_eegr?ecc error generation register 16 r/w 0x0000 17.2.2.7/17-7 0x0050 ecsm_fear?flash ecc address register 32 ro u 17.2.2.8/17-9 0x0056 ecsm_femr?flash ecc master register 8 ro 0x0u 17.2.2.9/17-10 0x0057 ecsm_feat?flash ecc attributes register 8 ro u 17.2.2.10/17-11 0x0058 ecsm_fedrh?flash ecc data register high 32 ro u 17.2.2.11/17-11 0x005c ecsm_fedrl?flash ecc data register low 32 ro u 17.2.2.11/17-11 0x0060 ecsm_rear?ram ecc address register 32 ro u 17.2.2.12/17-12 0x0065 ecsm_resr?ram ecc syndrome register 8 ro u 17.2.2.13/17-13 0x0066 ecsm_remr?ram ecc master register 8 ro 0x0u 17.2.2.14/17-15 0x0067 ecsm_reat?ram ecc attributes register 8 ro u 17.2.2.15/17-15 0x0068 ecsm_redrh?ram ecc data register high 32 ro u 17.2.2.16/17-16 0x006c ecsm_redrl?ram ecc data register low 32 ro u 17.2.2.16/17-16 0x0007?0x3fff reserved
error correction status module (ecsm) freescale semiconductor 17-3 pxr40 microcontroller reference manual, rev. 1 17.2.2 register descriptions this section lists the ecsm registers in address or der and describes the regist ers and their bit fields. attempted accesses to reserved addresses result in an error termination; however, attempted writes to read-only registers are ignored a nd do not terminate with an error. note unless noted otherwise, reads and wr ites to the programming model must match the size of the register, e.g., an n -bit register only supports n -bit writes, etc. attempted writes of a di fferent size than the register width produce an error terminati on of the bus cycle and no change to the targeted register. table 17-2. ecsm graphical memory map ecsm offset register 0x0000 processor core type (ecsm_pct) revision (ecsm_rev) 0x0008 ips module configuration (ecsm_imc) 0x000c reserved misc reset status (ecsm_mrsr) 0x0010?0x003f reserved 0x0040 reserved ecc configuration (ecsm_ecr) 0x0044 reserved ecc status register (ecsm_esr) 0x000048 reserved ecc error generation register (ecsm_eegr) 0x004c reserved 0x0050 flash ecc address register (ecsm_fear) 0x0054 reserved flash ecc master register (ecsm_femr) flash ecc attributes register (ecsm_feat) 0x0058 flash ecc data register high (ecsm_fedrh) 0x005c flash ecc data register low (ecsm_fedrl) 0x0060 ram ecc address register (ecsm_rear) 0x0064 reserved ram ecc syndrome (ecsm_resr) ram ecc master (ecsm_remr) ram ecc attributes (ecsm_reat) 0x0068 ram ecc data register high (ecsm_redrh) 0x006c ram ecc data register low (ecsm_redrl)
error correction status module (ecsm) 17-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 17.2.2.1 processor co re type (ecsm_pct) the ecsm_pct is a 16-bit read-only register specifying the architecture of the processor core in the device. the state of this re gister is defined by a module input signal; it ca n only be read fr om the peripheral programming model. any atte mpted write is ignored. 17.2.2.2 revision (ecsm_rev) the ecsm_rev[0:15] field defines a software-visible revision number. the ecsm_rev is a 16-bit read-only register specifyin g a revision number. the state of this register is defined by an input signal; it can only be read from the peripheral programming model. any attempted write is ignored. 17.2.2.3 peripheral module configuration (ecsm_imc) the ecsm_imc is a 32-bit read-onl y register identifying the presen ce/absence of the 32 low-order peripheral modules connected to the pr imary slave bus controller. the state of this register is defined by a module input signal; it can only be read from the peripheral programming model. any attempted write is ignored. a ?0? indicates a peripheral module c onnection to decoded slot ?n? is ab sent. a ?1? indicates a peripheral module connection to decoded slot ?n? is present. 17.2.2.4 miscellaneous reset st atus register (ecsm_mrsr) the ecsm_mrsr contains a bit for each of the reset sources to the devi ce. an asserted bit indicates the last type of reset that occurred. only one bit is set at any time in the ecsm_mrsr, reflecting the cause of the most recent reset as signalled by device rese t input signals. the ecsm_mrsr can only be read from the peripheral progr amming model. any attemp ted write is ignored. address: ecsm base + 0x000f access: user read/write 01234567 r por dir swtr 00000 w reset00000000 figure 17-1. miscellaneous reset status register (ecsm_mrsr) table 17-3. miscellaneous reset status register (ecsm_mrsr) field descriptions field description 0 por power-on reset 1 last recorded event was caused by a power-on reset (based on a device input signal) 1 dir device-input reset 1 last recorded event was a reset caused by a device input reset.
error correction status module (ecsm) freescale semiconductor 17-5 pxr40 microcontroller reference manual, rev. 1 17.2.2.5 ecc configuration register (ecsm_ecr) the ecc configuration register is an 8-bit control register for specif ying which types of memory errors are reported. in all systems with ecc, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. in many cases , this error termination is reported directly by the initiating bus master. however, there are certain si tuations where the occurrence of this type of non-correctable error is not reported by the mast er. examples include speculati ve instruction fetches that are discarded due to a change-of- flow operation and buffer ed operand writes. the ecc reporting logic in the ecsm provides an optional error interrupt mechanism to signal all non-correctable memory errors. in addition to the interrupt generation, the ecsm captures specific inform ation (memory address, attributes and data, bus master number, etc.) that may be useful for subsequent failure analysis. see figure 17-2 and table 17-4 for the ecc configurat ion register definition. 2 swtr platform software watchdog timer reset 1 last recorded event was a reset caused by the platform?s software watchdog timer. 3?7 reserved offset: ecsm_base_addr + 0x004 3 access: user read/write 01234567 r0 0 er1br ef1br 00 erncr efncr w reset00000000 figure 17-2. ecc configuration (ecsm_ecr) register table 17-4. ecsm_ecr field descriptions field description 0?1 reserved 2 er1br enable ram 1-bit reporting. 0 reporting of single-bit ram corrections is disabled. 1 reporting of single-bit ram corrections is enabled. the occurrence of a single-bit ram correction generates an ecsm ecc interrupt request as signalled by the assertion of ecsm_esr[r1bc]. the address, attrib utes and data are also captured in the ecsm_rear, ecsm_resr, ecsm_remr, ecsm_r eat and ecsm_redr registers. 3 ef1br enable flash 1-bit reporting. 0 reporting of single-bit flash corrections is disabled. 1 reporting of single-bit flash corrections is enabled. the occurrence of a single-bit flash correction generates a mcm ecc interrupt request as signalled by the assertion of ecsm_esr[f1bc]. the address, attributes and dat a are also captured in t he ecsm_fear, ecsm_femr, ecsm_feat and ecsm _fedr registers. 4?5 reserved table 17-3. miscellaneous reset status register (ecsm_mrsr) field descriptions (continued) field description
error correction status module (ecsm) 17-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 17.2.2.6 ecc status register (ecsm_esr) the ecc status register is an 8- bit control register for signaling wh ich types of properly-enabled ecc events have been detected. the ecsm_esr signals the last properly-enabled memory event to be detected. an ecc interrupt re quest is asserted if any fl ag bit is asserted and it s corresponding enable bit is asserted. the ecsm allows a maximum of one bit of the ecsm_esr to be a sserted at any given time. this preserves the association between the ecsm_esr and the co rresponding address and attribute registers, which are loaded on each occurrence of an prope rly-enabled ecc event. if there is a pending ecc interrupt and another properly-enab led ecc event occurs, the ecsm ha rdware automatically handles the ecsm_esr reporting, clearing the previous data a nd loading the new state a nd thus guaranteeing that only a single flag is asserted. to maintain the coherent software view of the reported event, the fo llowing sequence in the ecsm error interrupt service routine is suggested: 1. read the ecsm_esr and save it. 2. read and save all the address and attribute reporting registers. 3. re-read the ecsm_esr and verify the current c ontents matches the original contents. if the two values are different, repeat from step one. 4. when the values are identical, write a 1 to the asserted ecsm_esr flag to negate the interrupt request. see figure 17-3 and table 17-5 for the ecc status register definition. 6 erncr enable ram non-correctable reporting. the occurrence of a non-correctable multi-bit ram error generates an ecsm ecc interrupt request as signaled by the assertion of ecsm_esr[rnce]. the faulting address, attributes, and data in either the 512 kb or 80 kb array are also captured in the ecsm_rear, ecsm_resr, ecsm_remr, ecsm_reat, and ecsm_redr registers. 0 reporting of non-correctable ram errors is disabled. 1 reporting of non-correctable ram errors is enabled. 7 efncr enable flash non-correctable reporting. the occurrence of a non-correctable multi-bit flash error generates an ecsm ecc interrupt request as signaled by the assertion of ecsm_esr[fnce]. the faulting address, attributes, and data are also captured in the ecsm_fear, ecsm_femr, ecsm_feat, and ecsm_fedr registers. 0 reporting of non-correctable flash errors is disabled. 1 reporting of non-correctable flash errors is enabled. offset: ecsm_base_addr + 0x004 7 access: user read/write 01234567 r0 0 r1bc f1bc 0 0 rnce fnce w w1c w1c w1c w1c reset00000000 figure 17-3. ecc status (ecsm_esr) register table 17-4. ecsm_ecr field descriptions (continued) field description
error correction status module (ecsm) freescale semiconductor 17-7 pxr40 microcontroller reference manual, rev. 1 if both a flash and ram non-correcta ble error occur at the same time, the ecsm records the event with the highest priority, rnce, and fi nally fnce. if both a 512k and 80k ram non-correctable error occur at the same time, the ecsm records the event with the 512k array. 17.2.2.7 ecc error generati on register (ecsm_eegr) the ecc error generation register is a 16-bit control register used to force the generation of single- and double-bit data inversions in the memo ries with ecc, most notably the ram. this capability is provided for two purposes: ? it provides a software-controlled mechanism for injecting errors into the memories during data writes to verify the integrity of the ecc logic. ? it provides a mechanism to allow testing of the so ftware service routines associated with memory error logging. the intent is to generate errors during data write cycles, such that subsequent reads of the corrupted address locations generate ecc even ts, either single-bit corrections or double-bit noncorrectable errors that are terminated with an error response. table 17-5. ecsm_esr field descriptions field description 0?1 reserved 2 r1bc ram 1-bit correction. this bit can only be set if ecsm_ecr[epr1br] is asserted. the occurrence of a properly-enabled single-bit ram correction generates an ecsm ecc interrupt request. the address, attributes and data are also captured in the ecsm_rear, ecsm_resr, ecsm_remr, ecsm_reat and ecsm_redr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect 0 no reportable single-bit ram correction has been detected. 1 a reportable single-bit ram correction has been detected. 3 f1bc flash 1-bit correction. this bit can only be set if ecsm_ecr[epf1br] is asserted. the occurrence of a properly-enabled single-bit flash correction generates an ec sm ecc interrupt request. the address, attributes and data are also captured in the ecsm_fear, ec sm_femr, ecsm_feat and ec sm_fedr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable single-bit flash correction has been detected. 1 a reportable single-bit flash correction has been detected. 4?5 reserved 6 rnce ram non-correctable error. the occurrence of a properly-enabled non-correctable ram error generates an ecsm ecc interrupt request. the faulting address, attribut es, and data in either the 512k or 80k array are also captured in the ecsm_rear, ecsm_resr, ecsm_rem r, ecsm_reat, and ecsm_redr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable non-correctable ram error has been detected. 1 a reportable non-correctable ram error has been detected. 7 fnce flash non-correctable error. the occurrence of a prope rly-enabled non-correctable flash error generates an ecsm ecc interrupt request. the faulting address, attributes and data are also captured in the ecsm_fear, ecsm_femr, ecsm_feat, and ecsm_fedr re gisters. to clear this interrupt fl ag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable non-correctable flash error has been detected. 1 a reportable non-correctable flash error has been detected.
error correction status module (ecsm) 17-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 see figure 17-4 and table 17-6 for the ecc error genera tion register definition. offset: ecsm_base_addr + 0x004a access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r0 0 frc1bi fr11bi 00 frcnci fr1nci 0 errbit w reset00 0 0 00 0 0 00000000 figure 17-4. ecc error generation (ecsm_eegr) register table 17-6. ecsm_eegr field descriptions field description 0?1 reserved 2 frc1bi force ram continuous 1-bit data inversions. the assertion of this bit forces the ram controller to create 1-bit data inversions, as defined by the bit position specified in errbit, continuously on every write operation. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the ram. after this bit has been enabled to generate another contin uous 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. 0 no ram continuous 1-bit data inversions are generated. 1 1-bit data inversions in the ram are continuously generated. 3 fr11bi force ram one 1-bit data inversion. the assertion of this bit forces the ram controller to create one 1-bit data inversion, as defined by the bit posit ion specified in errbit, on the first write operation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the ram. after this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. 0 no ram single 1-bit data inversion is generated. 1 one 1-bit data inversion in the ram is generated. 4?5 reserved 6 frcnci force ram continuous noncorrectable data inversions. the a ssertion of this bit forces the ram controller to create 2-bit data inversions, as defined by the bit position specif ied in errbit and the overall odd parity bit, continuously on every write operation. after this bit has been enabled to generate another continu ous noncorrectable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the ram. 0 no ram continuous 2-bit data inversions are generated. 1 2-bit data inversions in the ram are continuously generated.
error correction status module (ecsm) freescale semiconductor 17-9 pxr40 microcontroller reference manual, rev. 1 note if an attempt to force a non-co rrectable invers ion by asserting ecsm_eegr[frcnci] or ec sm_eegr[frc1nci], and ecsm_eegr[errbit] equals 64, no data inversion is generated. the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all other values resu lt in undefined behavior. 17.2.2.8 flash ecc addres s register (ecsm_fear) the ecsm_fear is a 32-bit register for capturing the address of th e last, properly-enabled ecc event in the flash memory. depending on the state of the ecc c onfiguration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm_feat, and ecsm_fedr registers and also the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. 7 fr1nc force ram one noncorrectable data inversions. the assert ion of this bit forces the ram controller to create one 2-bit data inversion, as defined by the bit position specified in errbit and the overall odd parity bit, on the first write operation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the ram. after this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. 0 no ram single 2-bit data inversions are generated. 1 one 2-bit data inversion in the ram is generated. 8 reserved 9?15 errbit error bit position. the vector defines t he bit position, which is complemented to create the data inversion on the write operation. for the creation of 2-bit data inversions, the bi t specified by this field plus the odd parity bit of the ecc code are inverted. the platform ram controller follows a vector bit orderi ng scheme where lsb = 0. errors in the ecc syndrome bits can be generated by setting this field to a value greater than the ram width. for example, consider a 64-bit ram implementation. the 64-bit ecc approach requires 8 code bits for a 64-bit double word. for pram data width of 64 bits, the actual sram 64b data + 8b for ecc = 72 bits. the following association between the errbit field and the corrupted memory bit is defined: if errbit = 0, then ram[0] is inverted if errbit = 1, then ram[1] is inverted ... if errbit = 63, then ram[63] is inverted if errbit = 64,then ecc parity[0] is inverted if errbit = 65,then ecc parity[1] is inverted ... if errbit = 71,then ecc parity[7] is inverted table 17-6. ecsm_eegr field descriptions (continued) field description
error correction status module (ecsm) 17-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 this register is read-only; a ny attempted write is ignored. see figure 17-5 and table 17-7 for the flash ecc address register definition. 17.2.2.9 flash ecc master nu mber register (ecsm_femr) the ecsm_femr is an 8-bit register for captu ring the xbar bus master number of the last, properly-enabled ecc event in th e flash memory. depending on the st ate of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm _feat, and ecsm_fedr registers and also the appropriate flag (fnce) in the ecc status register to be asserted. this register is read-only; a ny attempted write is ignored. see figure 17-6 and table 17-8 for the flash ecc master number re gister definition. offset: ecsm_base_addr + 0x0050 access: user read-only 0 123456789101112131415 r fear w reset u 1 1 u = undefined at reset uuuuuuuuuuuuuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fear w resetu uuuuuuuuuuuuuuu figure 17-5. flash ecc address (ecsm_fear) register table 17-7. ecsm_fear field descriptions field description 0?15 fear flash ecc address register. contains the faulting access address of the last, properly enabled flash ecc event. offset: ecsm_base_addr + 0x 0056 access: user read-only 01234567 r0000 femr w reset0000u 1 1 u = undefined at reset uuu figure 17-6. flash ecc master number (ecsm_femr) register table 17-8. ecsm_femr field descriptions field description 0?7 femr flash cc master number register. contains the xbar bus master number of the faul ting access of the last, properly enabled flash ecc event.
error correction status module (ecsm) freescale semiconductor 17-11 pxr40 microcontroller reference manual, rev. 1 17.2.2.10 flash ecc attribut es register (ecsm_feat) the ecsm_feat is an 8-bit regist er for capturing the xbar bus ma ster attributes of the last, properly-enabled ecc event in th e flash memory. depending on the st ate of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm _feat, and ecsm_fedr registers and also the appropriate flag (fnce) in the ecc status register to be asserted. this register is read-only; a ny attempted write is ignored. see figure 17-7 and table 17-9 for the flash ecc attributes register definition. 17.2.2.11 flash ecc data register (ecsm_fedr) the ecsm_fedr is a 64-bit register for capturing the data associated wi th the last properly enabled ecc event in the flash memory. depending on the state of the ecc configurati on register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm_feat, and ecsm_fedr registers and also the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. offset: ecsm_base_addr + 0x 0057 access: user read-only 01234567 r write size protection w reset u 1 1 u = undefined at reset uuuuuuu figure 17-7. flash ecc attributes (ecsm_feat) register table 17-9. ecsm_feat field descriptions field description 0 write 0 read access. 1 write access. 1?3 size 000 8-bit access 001 16-bit access 010 32-bit access 011 64-bit access 1xx reserved 4?7 protection cache: 0xxx non-cacheable 1xxx cacheable buffer: x0xx non-bufferable x1xx bufferable mode: xx0x user mode xx1x supervisor mode ty p e : xxx0 i-fetch xxx1 data
error correction status module (ecsm) 17-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the data captured on a multi-bit non- correctable ecc error is undefined. this register is read-only; a ny attempted write is ignored. see figure 17-9 and table 17-10 for the flash ecc data register definition. 17.2.2.12 ram ecc address register (ecsm_rear) the ecsm_rear is a 32-bit register for capturing the address of the la st, properly-enabled ecc event in the ram memory. depending on the state of the ecc co nfiguration register, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the ecsm_rear, ecsm_resr, ecsm_remr, ecsm_reat, and ecsm_r edr registers and also the appropriate flag (rnce) in the ecc status register to be asserted. this register is read-only; a ny attempted write is ignored. see figure 17-10 and table 17-11 for the ram ecc address register definition. offset: ecsm_base_addr + 0x0058 access: user read-only 0 123456789101112131415 r fedr[0:15] w reset u 1 1 u = undefined at reset uuuuuuuuuuu uuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fedr[16:31] w resetu uuuuuuuuuuu uuuu figure 17-8. flash ecc data high (ecsm_fedrh) register offset: ecsm_base_addr + 0x005c access: user read-only 0 123456789101112131415 r fedr[32:47] w resetu uuuuuuuuuuu uuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fedr[48:63] w resetu uuuuuuuuuuu uuuu figure 17-9. flash ecc data low (ecsm_fedrl) register table 17-10. pecsm_fedr field descriptions field description 0?63 fedr flash ecc data register. contains the data associated wit h the faulting access of the last properly enabled flash ecc event. the register contains the data value taken directly from the platform data bus.
error correction status module (ecsm) freescale semiconductor 17-13 pxr40 microcontroller reference manual, rev. 1 17.2.2.13 ram ecc syndrome register (ecsm_resr) the ecsm_resr is an 8-bit register for capturing the error syndrome of the last properly enabled ecc event in the ram memory. depending on the state of the ecc configurati on register, an ecc event in the ram causes the address, attributes, and data associated with the access to be loaded into the ecsm_rear, ecsm_resr, ecsm_remr, ecsm _reat and ecsm_redr registers, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. this register is read-only; a ny attempted write is ignored. see figure 17-11 and table 17-12 for the ram ecc syndrome regi ster definition. offset: ecsm_base_addr + 0x0060 access: user read-only 0 123456789101112131415 r rear w reset u 1 1 u = undefined at reset uuuuuuuuuuuuuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rear w resetu uuuuuuuuuuuuuuu figure 17-10. ram ecc address (ecsm_rear) register table 17-11. ecsm_rear field descriptions field description 0?31 rear ram ecc address register. contains the faulting access address of the last, properly-enabled ram ecc event. offset: ecsm_base_addr + 0x0065 access: user read-only 01234567 r resr[0:7] w reset u 1 1 u = undefined at reset uuuuuuu figure 17-11. ram ecc syndrome (ecsm_resr) register
error correction status module (ecsm) 17-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 17-12. pecsm_resr field descriptions field description 0?7 resr ram ecc syndrome register. this 8-bit syndrome field includes 7 bits of hamming decoded parity plus an odd-parity bit for the entire 72-bit ( 64-bit data + 8 ecc) code word. the upper 7 bits of the syndrome specify the exact bit position in error for single-bit correctable codewords, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error. for correctable single-bit errors, the mapping shown in associates the upper 7 bits of the syndrome with the data bit in error. table 17-13. ecsm_ resr[0:7] data bit in error ecsm_ resr[0:7] data bit in error ecsm_ resr[0:7] data bit in error 0x00 no error 0x4f data[32] 0xa4 data[41] 0x01 ecc[0] 0x52 data[34] 0xa7 data[42] 0x02 ecc[1] 0x54 data[35] 0xa8 data[43] 0x04 ecc[2] 0x57 data[36] 0xab data[44] 0x08 ecc[3] 0x58 data[37] 0xad data[45] 0x0b data[17] 0x5b data[38] 0xb0 data[46] 0x0e data[16] 0x5d data[39] 0xb5 data[47] 0x10 ecc[4] 0x62 data[56] 0xcb data[1] 0x13 data[18] 0x64 data[57] 0xce data[0] 0x15 data[19] 0x67 data[58] 0xd3 data[2] 0x16 data[20] 0x68 data[59] 0xd5 data[3] 0x19 data[21] 0x6b data[60] 0xd6 data[4] 0x1a data[22] 0x6d data[61] 0xd9 data[5] 0x1c data[23] 0x70 data[62] 0xda data[6] 0x20 ecc[5] 0x75 data[63] 0xdc data[7] 0x23 data[8] 0x80 ecc[7] 0xe3 data[24] 0x25 data[9] 0x8a data[49] 0xe5 data[25] 0x26 data[10] 0x8f data[48] 0xe6 data[26] 0x29 data[11] 0x92 data[50] 0xe9 data[27] 0x2a data[12] 0x94 data[51] 0xea data[28] 0x2c data[13] 0x97 data[52] 0xec data[29] 0x31 data[14] 0x98 data[53] 0xf1 data[30] 0x34 data[15] 0x9b data[54] 0xf4 data[31] 0x40 ecc[6] 0x9d data[55] others multiple 0x4a data[33] 0xa2 data[40]
error correction status module (ecsm) freescale semiconductor 17-15 pxr40 microcontroller reference manual, rev. 1 17.2.2.14 ram ecc master numb er register (ecsm_remr) the ecsm_remr is an 8-bit register for capturi ng the xbar bus master number of the last, properly-enabled ecc event in the ram memory. de pending on the state of the ecc configuration register, an ecc event in the ram cau ses the address, attributes, and data associated with the access to be loaded into the ecsm_rear, ecsm_resr, ecsm_remr, ecsm_reat, and ecsm_redr registers and also the appropriate flag (rnce) in the ecc stat us register to be asserted. this register is read-only; a ny attempted write is ignored. see figure 17-12 and table 17-14 for the ram ecc master number re gister definition. 17.2.2.15 ram ecc attributes register (ecsm_reat) the ecsm_reat is an 8-bit register for capturing th e xbar bus master attribut es of the last properly enabled ecc event in the ram memo ry. depending on the state of the ecc configuration register, an ecc event in the ram causes the addre ss, attributes, and data associated with the access to be loaded into the ecsm_rear, ecsm_resr, ecsm_remr, ecsm _reat, and ecsm_redr registers and also the appropriate flag (rnce) in the ec c status register to be asserted. this register is read-only; a ny attempted write is ignored. see figure 17-13 and table 17-15 for the ram ecc attributes register definition. offset: ecsm_base_addr + 0x 0066 access: user read-only 01234567 r0000 remr w reset0000u 1 1 u = undefined at reset uuu figure 17-12. ram ecc master number (ecsm_remr) register table 17-14. ecsm_remr field descriptions field description 0?7 remr ram ecc master number register. contains the xbar bu s master number of the f aulting access of the last, properly-enabled ram ecc event. offset: ecsm_base_addr + 0x 0067 access: user read-only 01234567 r write size protection w reset u 1 1 u = undefined at reset uuuuuuu figure 17-13. ram ecc attributes (ecsm_reat) register
error correction status module (ecsm) 17-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 17.2.2.16 ram ecc data register (ecsm_redr) the ecsm_redr is a 64-bit register for capturing the data associated wi th the last properly enabled ecc event in the ram memory. depending on the state of the ecc configurati on register, an ecc event in the ram causes the address, attributes, and data associated with the access to be loaded into the ecsm_rear, ecsm_resr, ecsm_r emr, ecsm_reat, and ecsm_r edr registers and also the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. the data captured on a multi-bit non-correctable ecc er ror is undefined. this register is read-only; any attempted write is ignored. see figure 17-15 and table 17-16 for the ram ecc data register definition. table 17-15. ecsm_reat field descriptions field description 0 write 0 read access. 1 write access. 1?3 size 000 8-bit access. 001 16-bit access. 010 32-bit access. 011 64-bit access. 1xx reserved. 4?7 protection cache: 0xxx non-cacheable. 1xxx cacheable. buffer: x0xx non-bufferable. x1xx bufferable. mode: xx0x user mode. xx1x supervisor mode. ty p e : xxx0 i-fetch. xxx1 data. offset: ecsm_base_addr + 0x0068 access: user read-only 0 123456789101112131415 r redr[0:15] w reset u 1 1 u = undefined at reset uuuuuuuuuuu uuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r redr[16:31] w resetu uuuuuuuuuuu uuuu figure 17-14. ram ecc data high (ecsm_redrh) register
error correction status module (ecsm) freescale semiconductor 17-17 pxr40 microcontroller reference manual, rev. 1 offset: ecsm_base_addr + 0x006c access: user read-only 0 123456789101112131415 r redr[32:47] w reset u 1 1 u = undefined at reset uuuuuuuuuuu uuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r redr[48:63] w resetu uuuuuuuuuuu uuuu figure 17-15. ram ecc data low (ecsm_redrl) register table 17-16. redr field descriptions field description 0?63 redr ram ecc data register. contains the dat a associated with the faulting access of the last properly enabled platform ram ecc event. the register contains the data va lue taken directly from the platform data bus.
error correction status module (ecsm) 17-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 18-1 pxr40 microcontroller reference manual, rev. 1 chapter 18 software watchdog timer (swt) 18.1 introduction 18.1.1 overview the software watchdog timer (swt) is a peripheral module that can prev ent system lockup in situations such as software getting trapped in a loop or if a bus transa ction fails to terminate. when enabled, the swt require periodic execution of a wa tchdog servicing operation. the servici ng operation resets the timer to a specified time-out period. if this servicing action does not occur before the timer expires the swt generates an interrupt or ha rdware reset. the swt can be configured to generate a reset or interrupt on an initial time-out; a reset is always ge nerated on a second consecutive time-out. the swt interrupt is ?ored? with the critical inte rrupt signal from the siu and routed to the critical interrupt inputs of the cpu; see the siu chapter for details. the swt includes an interrupt status bit so the isr software can determin e if the critical interrupt request came from the swt or the external cr itical interrupt pin (wkpcfg_gpio213). the swt can assert a reset when the watchdog timer expires. this reset will cause a system reset equivalent to assertion of the rese t pin. bit 6 of the reset status regi ster in the siu indicates the swt as the source of the last reset. 18.1.2 features the swt has the following features: ? 32-bit time-out register to set the time-out period ? programmable selection of system or oscillator clock for timer operation ? programmable selection of window mode or regular servicing ? programmable selection of reset or interrupt on an initial time-out ? programmable selection of fixed or keyed servicing ? master access protection ? hard and soft configuration lock bits 18.1.3 modes of operation the swt supports three device m odes of operation: normal, debug a nd stop. when the swt is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the swt_mcr. if the frz bit is set, the counter is stopped in debug mode, otherwise it
software watchdog timer (swt) 18-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 continues to run. in stop mode, opera tion of the counter is controlled by the stp bit in the swt_mcr. if the stp bit is set, the counter is stopped in stop mode, otherwise it continues to run. 18.2 external signal description the swt module does not have a ny external interface signals. 18.3 memory map and register definition the swt programming model has seve n 32-bit registers. the program ming model can only be accessed using 32-bit (word) accesses. references using a differ ent size are invalid. other types of invalid accesses include: writes to read only regist ers, incorrect values written to the service register when enabled, accesses to reserved addresses and accesses by ma sters without permission. if the ria bit in the swt_mcr is set then the swt generates a system re set on an invalid access otherwise a bus error is generated. if either the hlk or slk bits in the swt_mcr are set then the swt_mcr, swt_to, swt_wn, swt_sk registers are read only. 18.3.1 memory map the swt memory map are shown in table 18-1 . the base address for each swt is given in table 18-1 . 18.3.2 register descriptions the following sections detail the individua l registers within the swt programming model. 18.3.2.1 swt control register (swt_mcr) the swt_mcr contains fields for conf iguring and controlling the swt. this register is read only if either the swt_mcr[hlk] or swt_ mcr[slk] bits are set. table 18-1. swt memory map address offset register bits access reset value section/page 0x0000 swt_mcr?swt module contro l register 32 r/w 0xff00_0*0b 18.3.2.1/2 0x0004 swt_ir?swt interrupt register 32 r/w 0x0000_0000 18.3.2.2/5 0x0008 swt_to?swt time-out register 32 r/w 0x0005_fcd0 18.3.2.3/5 0x000c swt_wn?swt window register 32 r/w 0x0000_0000 18.3.2.4/6 0x0010 swt_sr?swt service register 32 r/w 0x0000_0000 18.3.2.5/6 0x0014 swt_co?swt counter output register 32 r 0x0000_0000 18.3.2.6/7 0x0018 swt_sk?swt service key register 32 r/w 1 notes: 1 if neither hlk or slk lock bit in t he swt_mcr is set, the swt_sk can be initialized by software to a non-zero value. 0x0000_0000 18.3.2.7/8 0x001c?0x3fff reserved
software watchdog timer (swt) freescale semiconductor 18-3 pxr40 microcontroller reference manual, rev. 1 table 18-2. swt_mcr field descriptions offset 0x0000 access: read/write 0123456789101112131415 r map 0 map 1 00 map 4 map 5 map 6 map 7 00000 0 00 w reset1111111100000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000keyria wnd itr hlk slk csl stp frz wen w reset000000*100001 0 11 figure 18-1. swt control register (swt_mcr) field description 0?1 4?7 map n master access protection for master n 0 = access for the master is not enabled 1 = access for the master is enabled master ids are listed in ta b l e 1 4 - 1 . once set, map n bit is cleared only by other masters that are not disabled, or only after the reset. 2?3 8?21 reserved 22 key keyed service mode. 0 = fixed service sequence, the fixed sequence 0xa602, 0xb480 is used to service the watchdog 1 = keyed service mode, two pseudorandom key values are used to service the watchdog 23 ria reset on invalid access. 0 = invalid access to the swt generates a bus error 1 = invalid access to the swt causes a system reset if wen= 1 (watchdog enabled) 24 wnd window mode. 0 = regular mode, service sequence can be done at any time 1 = windowed mode, the service sequence is only valid when the down counter is less than the value in the swt_wn register. 25 itr interrupt then reset. 0 = generate a reset on a time-out 1 = generate an interrupt on an initial time-out, reset on a second consecutive time-out 26 hlk hard lock. this bit is only cleared at reset. 0 = swt_mcr, swt_to, swt_wn and swt_sk are read/write registers if slk=0 1 = swt_mcr, swt_to, swt_wn and swt_sk are read only registers 27 slk soft lock. this bit is cleared by writing the unlock sequence to the service register. 0 = swt_mcr, swt_to, swt_wn and swt_sk are read/write registers if hlk=0 1 = swt_mcr, swt_to, swt_wn and swt_sk are read only registers
software watchdog timer (swt) 18-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28 csl clock selection. selects the clock that drives the internal timer. 0 = system clock. 1 = oscillator clock. 29 stp stop mode control. allows the watchdog timer to be stopped when the device enters stop mode. 0 = swt counter continues to run in stop mode 1 = swt counter is stopped in stop mode 30 frz debug mode control. allows the watchdog timer to be stopped when the device enters debug mode. 0 = swt counter continues to run in debug mode 1 = swt counter is stopped in debug mode 31 wen watchdog enabled. 0 = swt is disabled 1 = swt is enabled field description
software watchdog timer (swt) freescale semiconductor 18-5 pxr40 microcontroller reference manual, rev. 1 18.3.2.2 swt interrupt register (swt_ir) the swt_ir contains the time-out interrupt flag. table 18-3. swt_ir field descriptions 18.3.2.3 swt time-out register (swt_to) the swt time-out (swt_to) register contains the 32- bit time-out period. this register is read only if either the swt_mcr[hlk] or swt_mcr[slk] bits are set. figure 18-3. swt time-out register (swt_to) offset 0x0004 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 0 0 00000tif w reset0000000000000 0 00 figure 18-2. swt interrupt register (swt_ir) field description 0?30 reserved 31 tif time-out interrupt flag. the flag and interrupt are cleared by writing a 1 to this bit. writing a 0 has no effect. 0 = no interrupt request. 1 = interrupt request due to an initial time-out. offset: 0x008 access: read/write 012345678910111213141516171819202122232425262728293031 r wto w reset00000000000001011111110011010000
software watchdog timer (swt) 18-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 18-4. swt_to register field descriptions 18.3.2.4 swt window register (swt_wn) the swt window (swt_wn) register c ontains the 32-bit window start valu e. this register is cleared on reset. this register is read only if either the swt_mcr[hlk] or swt_ mcr[slk] bits are set. figure 18-4. swt window register (swt_wn) table 18-5. swt_wn regi ster field descriptions 18.3.2.5 swt service register (swt_sr) the swt time-out (swt_sr) service register is the ta rget for service operation wr ites used to reset the watchdog timer. figure 18-5. swt service register (swt_sr) field description 0?31 wto watchdog time-out period in clock cycles. an internal 32-bit down counter is loaded with this value or 0x100 which ever is greater when the service sequ ence is written or when the swt is enabled. offset 0x00c access: read/write 012345678910111213141516171819202122232425262728293031 r wst w reset00000000000000000000000000000000 field description 0?31 wst window start value. when window mode is enabled, the service sequence can only be written when the internal down counter is less than this value. offset 0x010 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w wsc reset00000000000000000000000000000000
software watchdog timer (swt) freescale semiconductor 18-7 pxr40 microcontroller reference manual, rev. 1 table 18-6. swt_sr field descriptions 18.3.2.6 swt counter output register (swt_co) the swt counter output (swt_co) regi ster is a read only register that shows the value of the internal down counter when the swt is disabled. figure 18-6. swt counter output register (swt_co) table 18-7. swt_co register field descriptions field description 0?15 reserved 16?31 wsc watchdog service code.this field is used to service the watchdog and to clear the soft lock bit (swt_mcr[slk]). if the swt_mcr[key] bit is set, tw o pseudorandom key values are written to service the watchdog, see section section 18.4, functional description , for details. otherwise, the sequence 0xa602 followed by 0xb480 is written to the wsc field. to clear the soft lock bi t (swt_mcr[slk]), the value 0xc520 followed by 0xd928 is written to the wsc field. offset 0x014 access: read only 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 field description 0?31 cnt watchdog count. when the watchdog is disabled (swt_m cr[wen]=0) this field shows the value of the internal down counter. when the watchdog is enabled the value of this field is 0x0000_0000. values in this field can lag behind the internal counter value for up to six system plus eight counter clock cycles. therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter.
software watchdog timer (swt) 18-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 18.3.2.7 swt service key register (swt_sk) the swt service key (swt_sk) register holds the prev ious (or initial) service ke y value. this register is read only if either the swt_mcr[ hlk] or swt_mcr[slk] bits are set. figure 18-7. swt service key register (swt_sk) table 18-8. swt_sk field descriptions offset 0x018 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 00000000000 sk 1 notes: 1 if neither hlk or slk lock bit in the swt_mcr is set, the swt_sk can be initialized by software to a non-zero value. w reset00000000000000000000000000000000 field description 0?15 reserved 16?31 sk service key. this field is the previous (or initial) service key value used in keyed service mode. if swt_mcr[key] is set, the next key value to be written to the swt_sr is (17*sk+3) mod 2 16 .
software watchdog timer (swt) freescale semiconductor 18-9 pxr40 microcontroller reference manual, rev. 1 18.4 functional description the swt is a 32-bit timer desi gned to enable the system to recover in situations such as software getting trapped in a loop or if a bus trans action fails to terminate. it includ es a control register (swt_mcr), an interrupt register (swt_ir), a ti me-out register (swt_to), a window register (swt_wn), a service register (swt_sr), a counter out put register (swt_co) and a se rvice key register (swt_sk). the swt_mcr includes bits to enable the timer, set configuration options and lo ck configuration of the module. the watchdog is enabled by setting the swt_mcr[wen] bit. the watchdog starts operation automatically after reset is released (wen=1). the swt_to register holds the watc hdog time-out period in clock cycles unless the value is less than 0x100 in which case the time-out period is set to 0x100. th is time-out period is loaded into an internal 32-bit down counter when the swt is enabled and each time a valid service opera tion is performed. the swt_mcr[csl] bit selects which cl ock (system or oscillator) is used to drive the down counter. the configuration of the swt can be lo cked through use of either a soft lock or a hard lock. in either case, when locked the swt_mcr, swt_to, swt_wn and swt_sk registers are read only. the hard lock is enabled by setting the swt_mcr[hlk] bit which ca n only be cleared by a rese t. the soft lock is enabled by setting the swt_mcr[slk] bit and is cl eared by writing the unlock sequence to the service register. the unlock sequence is a write of 0xc520 followed by a writ e of 0xd928 to the swt_sr[wsc] field. there is no timing requireme nt between the two writes. the unl ock sequence logic ignores service sequence writes and recognizes the 0xc520, 0xd928 sequence regardless of previous writes. the unlock sequence can be written at any time and does not require the swt_mcr[we n] bit to be set. when enabled, the swt requires periodi c execution of a servic ing operation which cons ists of writing two values to the swt_sr. writing the proper sequence of values loads the internal down counter with the time-out period. there is no timing requirement between th e two writes and the service sequence logic ignores unlock sequence writes. if the swt_mcr[key] bit is zero, the fixed sequence 0xa602, 0xb480 is written to the swt_sr[wsc] field to service th e watchdog. if the swt_mcr[ke y] bit is set, then two pseudorandom keys are written to the swt_sr[wsc] field to service the watchdog. the key values are determined by the pseudora ndom key generator defined in figure 18-8 . this algorithm will generate a sequence of 2 16 different key values before repeating. the state of the key generator is held in the swt_sk register. for example, if swt_sk[sk] is 0x0100 then the se rvice sequence keys are 0x1103, 0x2136. in this mode, each time a valid key is writte n to the swt_sr register, the swt_sk register is updated. so, after servicing the watchdog by writing 0x1103 and then 0x2136 to the swt_sr[wsc] field, swt_sk[sk] is 0x2136 and the next key sequence is 0x3499, 0x7e2c. figure 18-8. pseudorandom key generator accesses to swt registers occur with no peripheral bus wait states. (the peripheral bus bridge may add one or more system wait states.) however, due to synchronization logic in th e swt design, r ecognition of the service sequence or configurati on changes may require up to three system plus seven counter clock cycles. sk n+1 = (17*sk n +3) mod 2 16
software watchdog timer (swt) 18-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if window mode is enabled (swt_mcr [wnd] bit is set), the service se quence must be performed in the last part of the time-out period defined by the window register. the window is open when the down counter is less than the value in the swt_wn register. outs ide of this window, service sequence wr ites are invalid accesses and generate a bus error or reset depe nding on the value of the swt_mcr[ria] bit. for example, if the swt_to register is set to 5000 and swt_wn register is set to 1000 then the service sequence must be performed in the last 20% of the tim e-out period. there is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. this delay could be up to three system plus four counter clock cycles. the interrupt then reset bit (swt_mcr[itr]) controls the action taken when a time-out occurs. if the swt_mcr[itr] bit is not set, a reset is generate d immediately on a time-out. if the swt_mcr[itr] bit is set, an initial time-out causes the swt to gene rate an interrupt and load the down counter with the time-out period. if the service seque nce is not written before the se cond consecutive time-out, the swt generates a system reset. the interrupt is indicate d by the time-out interrupt flag (swt_ir[tif]). the interrupt request is cleared by writing a one to the swt_ir[tif] bit. refer to section 27.4.1, external interrupt request sources , and section 3.2.1.5, dma/interrupt request enable register (siu_direr) , for details on the enabling and routing of the swt interrupt signals. the swt_co register shows the va lue of the down counter when the watchdog is disabled. when the watchdog is enabled this register is cleared. the value shown in this register can lag behind the value in the internal counter for up to six syst em plus eight counter clock cycles. the swt_co can be used during a so ftware self test of the swt. fo r example, the swt can be enabled and not serviced for a fixed period of time less than the time-out value. then the swt can be disabled (swt_mcr[wen] cleared) and the value of the swt_co read to determine if the internal down counter is working properly.
freescale semiconductor 19-1 pxr40 microcontroller reference manual, rev. 1 chapter 19 system timer module (stm) 19.1 introduction 19.1.1 overview the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). 19.1.2 features the stm has the following features: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? one channel with a dedicated interrupt node ? three channels sharing the same interrupt node ? independent interrupt source for each channel ? counter can be stopped in debug mode 19.1.3 modes of operation the stm supports two device modes of operation: nor mal and debug. when the st m is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the stm_cr register. if the frz bi t is set, the counter is stopped in debug mode, otherwise it continues to run. 19.2 external signal description the stm does not have any external interface signals. 19.3 memory map and register definition the stm programming model has fourt een 32-bit registers. the stm regi sters can only be accessed using 32-bit (word) accesses. attempted refe rences using a different size or to a reserved address generates a bus error termination.
system timer module (stm) 19-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 19.3.1 memory map the stm memory map is shown in table 19-1 . table 19-1. stm memory map address offset register bits access reset value section/page 0x0000 stm_cr?stm control register 32 r/w 0x0000_0000 19.3.2.1/3 0x0004 stm_cnt?stm counter register 32 r/w 0x0000_0000 19.3.2.2/4 0x0008 reserved 0x000c reserved 0x0010 stm_ccr0?stm channel 0 control register 32 r/w 0x0000_0000 19.3.2.3/4 0x0014 stm_cir0?stm channel 0 interrupt register 32 r/w 0x0000_0000 19.3.2.4/5 0x0018 stm_cmp0?stm channel 0 compare register 32 r/w 0x0000_0000 19.3.2.5/5 0x001c reserved 0x0020 stm_ccr1?stm channel 1 control register 32 r/w 0x0000_0000 19.3.2.3/4 0x0024 stm_cir1?stm channel 1 interrupt register 32 r/w 0x0000_0000 19.3.2.4/5 0x0028 stm_cmp1?stm channel 1 compare register 32 r/w 0x0000_0000 19.3.2.5/5 0x002c reserved 0x0030 stm_ccr2?stm channel 2 control register 32 r/w 0x0000_0000 19.3.2.3/4 0x0034 stm_cir2?stm channel 2 interrupt register 32 r/w 0x0000_0000 19.3.2.4/5 0x0038 stm_cmp2?stm channel 2 compare register 32 r/w 0x0000_0000 19.3.2.5/5 0x003c reserved 0x0040 stm_ccr3?stm channel 3 control register 32 r/w 0x0000_0000 19.3.2.3/4 0x0044 stm_cir3?stm channel 3 interrupt register 32 r/w 0x0000_0000 19.3.2.4/5 0x0048 stm_cmp3?stm channel 3 compare register 32 r/w 0x0000_0000 19.3.2.5/5 0x004c -0x3fff reserved
system timer module (stm) freescale semiconductor 19-3 pxr40 microcontroller reference manual, rev. 1 19.3.2 register descriptions the following sections detail the individua l registers within the stm programming model. 19.3.2.1 stm control register (stm_cr) the stm control register (stm_cr) includes the prescale value, free ze control and timer enable bits. table 19-2. stm_cr field descriptions offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cps 0 0 0 0 00 frz ten w reset0000000000000000 figure 19-1. stm control register (stm_cr) field description 0?15 reserved 16?23 cps counter prescaler. selects the clock divide value for the prescaler (1 - 256). 0x00 = divide system clock by 1 0x01 = divide system clock by 2 ... 0xff = divide system clock by 256 24?29 reserved 30 frz freeze. allows the timer counter to be stopped when the device enters debug mode. 0 = stm counter continues to run in debug mode. 1 = stm counter is stopped in debug mode. 31 ten timer counter enabled. 0 = counter is disabled. 1 = counter is enabled.
system timer module (stm) 19-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 19.3.2.2 stm count register (stm_cnt) the stm count register (stm_cnt) holds the timer count value. table 19-3. stm_cnt field descriptions 19.3.2.3 stm channel cont rol register (stm_ccrn) the stm channel control register (stm_ccrn) has the enable bit for channel n of the timer. table 19-4. stm_ccrn field descriptions offset 0x004 access: read/write 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 figure 19-2. stm count register (stm_cnt) field description 0?31 cnt timer count value used as the time base for all chan nels. when enabled, the counter increments at the rate of the system clock divided by the prescale value. offset 0x10+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cen w reset0000000000000 0 00 figure 19-3. stm channel control register (stm_ccrn) field description 0?30 reserved 31 cen channel enable. 0 = the channel is disabled. 1 = the channel is enabled.
system timer module (stm) freescale semiconductor 19-5 pxr40 microcontroller reference manual, rev. 1 19.3.2.4 stm channel interrupt register (stm_cirn) the stm channel interrupt register (stm_cirn) has the interrupt flag for channel n of the timer. table 19-5. stm_cirn field descriptions 19.3.2.5 stm channel comp are register (stm_cmpn) the stm channel compare regi ster (stm_cmpn) holds the compare value for channel n. table 19-6. stm_cmpn register field descriptions offset 0x14+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cif w reset0000000000000 0 00 figure 19-4. stm channel interrupt register (stm_cirn) field description 0?30 reserved 31 cif channel interrupt flag. the flag and interrupt are clear ed by writing a 1 to this bit. writing a 0 has no effect. 0 = no interrupt request. 1 = interrupt request due to a match on the channel. offset 0x18+0x10*n access: read/write 012345678910111213141516171819202122232425262728293031 r cmp w reset00000000000000000000000000000000 figure 19-5. stm channel compare register (stm_cmpn) field description 0?31 cmp compare value for channel n. if the stm_ccrn[cen] bi t is set and the stm_cmpn register matches the stm_cnt register, a channel interrupt request is generated and the stm_cirn[cif] bit is set.
system timer module (stm) 19-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 19.4 functional description the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the stm has one 32-bit up counter (stm_cnt) that is used as the time base for all channels. when enabled, the counter increments at the system clock frequency divided by a prescale value. the stm_cr[cps] field sets the divider to any value in the range from 1 to 256. the counter is enabled with the stm_cr[ten] bit. when enabled in normal m ode the counter continuously increments. when enabled in debug mode the coun ter operation is controlled by the stm_cr[frz] bit. when the stm_cr[frz] bit is set, the counter is stopped in debug mode, otherw ise it continues to run in debug mode. the counter rolls over at 0xffff_ffff to 0x0000_0000 with no restrictions at this boundary. the stm has four identical compare channels. e ach channel includes a channel control register (stm_ccrn), a channel interrupt re gister (stm_cirn) and a channe l compare register (stm_cmpn). the channel is enabled by setting the stm_ccrn[cen ] bit. when enabled, the channel will set the stm_cir[cif] bit and generate an interrupt request when the channel compare register matches the timer counter. the interrupt request is cl eared by writing a 1 to the stm_cirn[cif] bit. a write of 0 to the stm_cirn[cif] bit has no effect.
freescale semiconductor 20-1 pxr40 microcontroller reference manual, rev. 1 chapter 20 periodic interrupt timer (pit_rti) 20.1 introduction 20.1.1 overview this section describes the function of the periodic interrupt timer bloc k (pit_rti). the pit is an array of timers that can be used to generate interrupts. it also provides a dedicated real time interrupt timer (rti), which runs on a separate clock and can be used for system wake up from low power mode.
periodic interrupt timer (pit_rti) 20-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 20.1.2 block diagram a block diagram of the pit_rti module is shown in figure 20-1 . figure 20-1. block diagram of pit_rti 20.1.3 features the main features of this block are: ? timers can be configured to generate interrupts ? all interrupts are maskable ? independent timeout period s for each timer and rti ? rti can be used to generate a cpu wake-up interrupt ? rti clock source is the crystal oscillator, no pre- scalars are used ? pit timer clock source is the pe ripheral clock, no pre-scalars are used rti timer 3 timer 0 . . . pit registers peripheral interrupts timeout load_value peripheral pit_rti . . . independent rti oscillator bus clock bus clock
periodic interrupt timer (pit_rti) freescale semiconductor 20-3 pxr40 microcontroller reference manual, rev. 1 20.2 signal description the pit module has no external pins. 20.3 memory map and register description this section provides a detailed description of all registers accessible in the pit_rti module. 20.3.1 memory map table 20-1 provides an overview off all pit_rti registers. table 20-1. pit_rti memory map base address offset (base = 0xc3ff0000 register bits access reset value section/page 0x000 pit_mcr?pit module cont rol register 32 r/w 0x0000_0000 20.3.2.1/4 0x004?0x0ec reserved 0x0f4 pit_rti_cval?rti current value register 32 r 0x0000_0000 20.3.2.3/5 0x0f8 pit_rti_tctrl?rti timer control register 32 r/w 0x0000_0000 20.3.2.4/5 0x0fc pit_rti_tflag?rti timer flag register 32 r/w 0x0000_0000 20.3.2.5/6 0x100 pit_ch0_ldval?channel 0 load value register 32 r/w 0x0000_0000 20.3.2.2/5 0x104 pit_ch0_cval?channel 0 current value register 32 r 0x0000_0000 20.3.2.3/5 0x108 pit_ch0_tctrl?channel 0 timer control register 32 r/w 0x0000_0000 20.3.2.4/5 0x10c pit_ch0_tflag?channel 0 timer channel flag register 32 r/w 0x0000_0000 20.3.2.5/6 0x110 pit_ch1_ldval?channel 1 load value register 32 r/w 0x0000_0000 20.3.2.2/5 0x114 pit_ch1_cval?channel 1 current value register 32 r 0x0000_0000 20.3.2.3/5 0x118 pit_ch1_tctrl?channel 1 timer control register 32 r/w 0x0000_0000 20.3.2.4/5 0x11c pit_ch1_tflag?channel 1 timer channel flag register 32 r/w 0x0000_0000 20.3.2.5/6 0x120 pit_ch2_ldval?channel 2 load value register 32 r/w 0x0000_0000 20.3.2.2/5 0x124 pit_ch2_cval?channel 2 current value register 32 r 0x0000_0000 20.3.2.3/5 0x128 pit_ch2_tctrl?channel 2 timer control register 32 r/w 0x0000_0000 20.3.2.4/5 0x12c pit_ch2_tflag?channel 2 timer channel flag register 32 r/w 0x0000_0000 20.3.2.5/6
periodic interrupt timer (pit_rti) 20-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 20.3.2 register descriptions this section describes all pit_rti registers and their individual bits. 20.3.2.1 pit module control register (pit_mcr) this register provides a mechanism for enabling and disabling timers, a nd setting whether timers continue to count in debug mode. table 20-2. pitmcr field descriptions 0x130 pit_ch3_ldval?channel 3 load value register 32 r/w 0x0000_0000 20.3.2.2/5 0x134 pit_ch3_cval?channel 3 current value register 32 r 0x0000_0000 20.3.2.3/5 0x138 pit_ch3_tctrl?channel 3 timer control register 32 r/w 0x0000_0000 20.3.2.4/5 0x13c pit_ch3_tflag?channel 3 timer channel flag register 32 r/w 0x0000_0000 20.3.2.5/6 offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 figure 20-2. pit module control register (pit_mcr) field description 0?2 reserved 31 frz freeze. allows the timers to be stopped when the device enters debug mode. 0 = timers continue to run in debug mode. 1 = timers are stopped in debug mode. table 20-1. pit_rti memory map (continued) base address offset (base = 0xc3ff0000 register bits access reset value section/page
periodic interrupt timer (pit_rti) freescale semiconductor 20-5 pxr40 microcontroller reference manual, rev. 1 20.3.2.2 timer load value regi ster (pit_rti_ldval, pit_ch n _ldval) this register selects the timeout period for the timer interrupts. 20.3.2.3 current timer value re gister (pit_rti_cval, pit_ch n _cval) this register indicates the current timer position. 20.3.2.4 timer control regist er (pit_rti_tctrl, pit_ch n _tctrl) this register contains the control bits for each timer. offset: channel_base + 0x00 rti base = 0x0f0 ch0 base = 0x100 ch1 base = 0x110 ch2 base = 0x120 ch3 base = 0x130 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tsv[0:31] w reset00000000000000000000000000000000 figure 20-3. timer load value register (pit_rti_ldval, pit_ch n _ldval) table 20-3. pit_rti_ldval, pit_ch n _ldval field descriptions field description 0?31 tsv time start value bits. these bits set the timer start value. the timer counts down until it reaches 0, then it generates an interrupt and loads this regist er value again. writing a new value to this register does not restart the timer, instead the value is loaded once the timer expires. to abort the current cycle and start a timer period with the new value, th e timer must be disabled and enabled again (see figure 20-8 ). offset: channel_base + 0x04 access: user read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tvl[31:0] w reset00000000000000000000000000000000 figure 20-4. current timer value register (pit_rti_cval, pit_ch n _cval) table 20-4. pit_rti_cval, pit_ch n _cval field descriptions field description 0?31 tvl current timer value. these bits represent the cu rrent timer value. note that the timer uses a downcounter. note: the timer values are frozen in debug mode if the frz bit is set in the pit module control register (see figure 20-2 )
periodic interrupt timer (pit_rti) 20-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 20.3.2.5 timer flag register (pit_rti_tflg, pit_ch n _tflg) this register holds the pit interrupt flag for each timer. offset channel_base + 0x08 rti base = 0x0f0 ch0 base = 0x100 ch1 base = 0x110 ch2 base = 0x120 ch3 base = 0x130 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000000 tie ten w reset0000000000000000 figure 20-5. timer control regi ster (pit_rti_tctrl, pit_ch n _tctrl) table 20-5. pit_rti_tctrl, pit_ch n _tctrl field descriptions field description 0?29 reserved 30 tie timer interrupt enable bit. 0 interrupt requests from timer x are disabled 1 interrupt is requeste d whenever tif is set when an interrupt is pending (tif set), enabling th e interrupt immediately causes an interrupt event. to avoid this, the associated tif flag must be cleared first. 31 ten timer enable bit. 0 timer is disabled 1 timer is active
periodic interrupt timer (pit_rti) freescale semiconductor 20-7 pxr40 microcontroller reference manual, rev. 1 20.4 functional description 20.4.1 general this section gives detailed informat ion on the internal operati on of the module. each timer can be used to generate a unique interrupt vector. 20.4.1.1 timers once enabled, the timers can be configured to generate interrupts at periodic intervals. the timer loads its start value, as specified in the ldval register, then counts down unt il the count reaches 0. then the value in the ldval register is loaded again and the proce ss repeats. each time the timer reaches 0, an interrupt is generated if enabled, and the interrupt flag is set. all interrupts can be enabled or masked (by setting th e tie bits in the tctrl re gisters). a new interrupt can be generated only after th e previous one is cleared. if desired, the current counter value of the timer can be read via the cval registers. offset channel_base + 0x0c rti base = 0x0f0 ch0 base = 0x100 ch1 base = 0x110 ch2 base = 0x120 ch3 base = 0x130 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000 tif w reset0000000000000000 figure 20-6. timer flag register (pit_rti_tflg, pit_ch n _tflg) table 20-6. pit_rti_tflg, pit_ch n _tflg field descriptions field description 0?30 reserved 31 tif time interrupt flag. tif is set to 1 at the end of the timer period.this flag can be cleared only by writing it with a 1. writing a 0 has no effect. if enabled (tie = 1), tif causes an interrupt request. 0 time-out has not yet occurred 1 time-out has occurred
periodic interrupt timer (pit_rti) 20-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the counter period can be restarte d, by first disabling, then enabling the timer with the ten bit (see figure 20-7 ). the counter period of a runni ng timer can be modified, by first disabli ng the timer, settin g a new load value and then enabling the timer again (see figure 20-8 ). in the case of the rti, be cause of the different clock domains (system clock / oscillator clock), a delay must be respected between setting the new value and re-enabling the rti. it is also possible to change th e counter period without restarting the timer by wr iting the ldval register with the new load value. this value is loaded af ter the next trigger (counter reaches 0) event (see figure 20-9 ). figure 20-7. stopping and starting a timer figure 20-8. modifying running timer period figure 20-9. dynamically setting a new load value 20.4.1.2 debug mode in debug mode the timers ma y be configured to stop when the debugge r halts the device. this is intended to aid software development, allowi ng the developer to halt the processo r, investigate the current state of the system (e.g. the timer values) and then continue the operation. p1 p1 timer enabled disable timer p1 start value = p1 trigger event p1 re-enable timer p1 timer enabled disable timer, start value = p1 trigger event re-enable timer p1 set new load value p2 p2 p2 p1 p1 timer enabled new start value p2 set p1 p2 start value = p1 p2 trigger event
periodic interrupt timer (pit_rti) freescale semiconductor 20-9 pxr40 microcontroller reference manual, rev. 1 20.4.2 interrupts all of the timers support in terrupt generation. refer to section 10.4.1, interrupt request sources , for related vector addre sses and priorities. timer interrupts can be disabled by setting the timer pit_ch n _tctrl[tie] bit to zero. the pit_ch n _tflg[tif] bit is set to 1 when a timeout occu rs on the associated timer, and is cleared by writing a 1 to that bit. 20.5 initialization and application information 20.5.1 example configuration in the example configuration: ? the pit clock has a frequency of 50 mhz ? timer 1 shall create an interrupt every 5.12 ms first the pit module is activated by writing a 0 to the mdis bit in the pitctrl register. the 50 mhz clock frequency equates to a clock period of 20 ns. timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles. the value for the ldval register trigger would be calculat ed as (period / clock period) -1. this means that pit_pit_ch1_ldval with 0003e7ff hex. the interrupt for timer 1 is enable d by setting pit_ch1_tctrl[tie] bit. the timer is started by writing a 1 to the pit_ch1_tctrl[ten] bit. the following example pseudo-code matches the described setup: // turn on pit pit_mcr = 0x00; // rti pit_rti_ldval = 0x004c4b3f; // setup rti for 5000000 cycles pit_rti_tctrl[tie] = 1; // let rti generate interrupts pit_rti_tctrl[ten] = 1; // start rti // timer 1 pit_ch1_ldval = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_ch1_tctrl[tie] = 1; // enable timer 1 interrupts pit_ch1_tctrl[ten] = 1; // start timer 1 20.5.2 low power mode ? usin g the rti for system wakeup this section describes the use of the low power mo de, both with and without use of the rti timer for wakeup.
periodic interrupt timer (pit_rti) 20-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 20.5.2.1 low power mode without rti wakeup the siu_halt register may be used to place certain peripherals se lectively in low power mode. see section 7.3.1.28, halt register (siu_hlt) , for more information about th e siu_hlt register. the general process for setting low power modes is: 1. disable interrupts for any peripherals that are to be placed in low power mode a nd ensure there are no pending interrupts. 2. using the bit assignment in the siu_hlt regist er, set the bits for any modules where low power operation is desired. note that the cpu (s iu_hlt[0]) bit should not be selected. 3. the siu_hltack register indicates when a selected peripheral clock has stopped. 4. to re-enable the clock to any peripheral, clear the corresponding bit in the siu_hlt register and re-enable the interrupts for the desired periphe ral. the siu_hltack updates accordingly when the peripheral clock has been re-enabled. note most of the peripherals have a mdis (module disable) bit in the module control register that can be set to disable the module cl ock, reducing power consumption. in most cases the periphe ral registers are still readable and writeable. the siu_halt register perf orms the same function on multiple modules with a single 32- bit write, however usi ng the siu_halt function also disables r/w function on the peri pheral registers for additional power saving. 20.5.2.2 low power mode with rti wakeup the rti can be used in conjunction with the siu_halt register to en ter and exit from low power mode. see section 7.3.1.28, halt regi ster (siu_hlt) , for more information about the siu_halt register. the general procedure for entering a nd exiting low power mode is: 1. configure the interrupt handler for the rti in terrupt. the interrupt handler code can vary, depending on what behavior is required for th e application upon exiting low power mode. more information on configuring and us ing the interrupts is found in section 10.5, initialization and application information , of the interrupt controller chapter. 2. configure the rti for the desire d timeout period as described in section 20.5.1, example configuration . 3. disable interrupts for a ll peripherals to be placed in low pow er mode and ensure there are no pending interrupts. 4. write the desired bits to the siu_hlt register, se lecting the modules that ar e to have the low power mode enabled. note that if the cpu bit is also set for lowest power operation, an rti interrupt is required to exit low power mode. 5. the cpu executes the ?msync?, ?isync?, and ?wait? instructions and the device enters low power mode. note that the ?msync? and ?isync? instruc tions ensure that all current core operations complete before entering low power mode.
periodic interrupt timer (pit_rti) freescale semiconductor 20-11 pxr40 microcontroller reference manual, rev. 1 6. at the programmed rti time interval, the rti timer triggers an interrupt that is serviced by the interrupt controller. (the interrupt controller is not put in low power mode by the siu_halt register.) this interrupt also re-enables the cp u clock so that full cp u operation is restored. 7. in the rti interrupt handler, the siu_halt regi ster may be modified to restore operation as desired. in some cases where peri odic operation is preferred, the interrupt handler may perform a set of tasks, and then write the siu_halt regi ster mask and re-enter the low power mode by executing the ?msync?, ?isync?, and ?wait? inst ructions again. the next rti timeout repeats the process. note the rti is a convenient mechanism for waking up the cp u in a controlled state once placed in low power mode. however, the cpu will also exit low pow er mode under any of the following conditions: ? any external interrupt from interrupt controller ? critical interrupt ? nmi event ? core watchdog timeout ? core fixed interval timeout ? core decrementer timeout ? various debug events
periodic interrupt timer (pit_rti) 20-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 21-1 pxr40 microcontroller reference manual, rev. 1 chapter 21 enhanced direct memory access controller (edma) 21.1 introduction this device includes two enhanced direct memory access controller (edma) blocks. the edma is a second-generation platform block capable of performing complex data movements through n programmable channels ( n =64 for edma_a, n =32 for edma_b), with minimal intervention from the host processor. the hardware mi croarchitecture includes a dma e ngine that performs source and destination address calculations, and the actual data movement opera tions, along with an sram-based memory containing the transfer contro l descriptors (tcd) for the channels.
enhanced direct memory access controller (edma) 21-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.1.1 block diagram figure 21-1 shows a simplified block diagram of each edma. figure 21-1. edma block diagram 21.1.2 features each edma has these major features: ? all data movement via dual-address transfer s: read from source, write to destination ? programmable source, destinat ion addresses, transfer si ze, and support for enhanced addressing modes ? both 32- and 64-channel implementation perfo rms complex data transfers with minimal intervention from a host processor ? 32 bytes of data registers, used as te mporary storage to support burst transfers (refer to ssize bit) ? connections to the crossbar switch for bus mastering the data movement ? transfer control descriptor organized to support two-deep, nested transfer operations ? an inner data transfer loop defi ned by a minor byte transfer count slave interface edma edma done system bus data path control address program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1* edma peripheral request bus read data channel arbitration path sram transfer control descriptor ( tcd ) sram * n = 64 channels for edma_a * n = 32 channels for edma_b
enhanced direct memory access controller (edma) freescale semiconductor 21-3 pxr40 microcontroller reference manual, rev. 1 ? an outer data transfer loop de fined by a major iteration count ? channel activation via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel li nking mechanism for c ontinuous transfers ? peripheral-paced hardware requests (one per channel) all three methods require one activat ion per execution of the minor loop ? support for fixed-priority and round-robin channel arbitration ? support for complex data structures ? support to cancel transfers via software ? channel completion reported vi a optional interrupt requests ? one interrupt per channel, optionally asse rted at completion of major iteration count ? error terminations are optionally enabled per ch annel and logically summed together to form a single error interrupt (32-channel edma) or two error interrupts (64-channel edma). ? support for scatter-gather dma processing ? support for complex data structures ? any channel can be programmed to be suspended by a higher priori ty channel?s activation, before completion of a minor loop. 21.1.3 modes of operation there are two main operating m odes of edma: normal mode and de bug mode. these modes are briefly described in this section. 21.1.3.1 normal mode in normal mode, the edma is used to transfer data between a source and a destination. the source and destination can be a memory block or an i/ o block capable of operation with the edma. 21.1.3.2 debug mode in debug mode, the edma does not acc ept new transfer requests when it s debug input signa l is asserted. if the signal is asserted during transfer of a block of data described by a minor loop in the current active channel?s tcd, the edma continues opera tion until completion of the minor loop. 21.2 external signal description the edma has no external signals..
enhanced direct memory access controller (edma) 21-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.3 memory map and registers this section provides a detailed de scription of all edma registers. 21.3.1 module memory map the edma memory map is shown in table 21-1 . the address of each register is given as an offset to the edma base address. regist ers are listed in address order, identi fied by complete name and mnemonic, and list the type of accesses allowe d. in register names, an ? x ? is used to indicate a or b, depending on which edma?s register you are using. if a regi ster only exists in one of the ed mas, the register description will state that. the edma?s programming model is partitioned into two regions: the first region defines a number of registers providing control functions ; however, the second regi on corresponds to the local transfer control descriptor memory. some registers are implemented as two 32-bit registers, and include h and l suffixes, signaling the high and low portions of the control function. base addresses of edma_ x : ? edma_a_base = 0xfff4_4000 ? edma_b_base = 0xfff5_4000 table 21-1. edma memory map offset from edma _x _base register bits access reset value section/page 0x0000 edma_ x _mcr?edma module control register 32 r/w 0x0000_e400 21.3.2.1/21-13 0x0004 edma _x _esr?edma error status register 32 r 0x0000_0000 21.3.2.2/21-17 0x0008 edma_a_erqrh?edma_a enable request high register (channels 63?32) reserved (edma_b) 32 r/w 0000_0000 21.3.2.3/21-19 0x000c edma _x _erqrl?edma enable request low register (channels 31?00) 32 r/w 0x0000_0000 21.3.2.3/21-19 0x0010 edma_a_eeirlh?edma_a enable error interrupt register (channels 63?32) reserved (edma_b) 32 r/w 0x0000_0000 21.3.2.4/21-21 0x0014 edma _x _eeirl?edma enable error interrupt register (channels 31?00) 32 r/w 0x0000_0000 21.3.2.4/21-21 0x0018 edma _x _serqr?edma set enable request register 8 w 0x00 21.3.2.5/21-23 0x0019 edma _x _cerqr?edma clear enable request register 8 w 0x00 21.3.2.6/21-24 0x001a edma _x _seeir?edma set enable erro r interrupt register 8 w 0x00 21.3.2.7/21-25 0x001b edma _x _ceeir?edma clear enable error interrupt register 8 w 0x00 21.3.2.8/21-26 0x001c edma _x _cirqr?edma clear interrupt request register 8 w 0x00 21.3.2.9/21-27 0x001d edma _x _cer?edma clear error register 8 w 0x00 21.3.2.10/21-27
enhanced direct memory access controller (edma) freescale semiconductor 21-5 pxr40 microcontroller reference manual, rev. 1 0x001e edma _x _ssbr?edma set start bit register 8 w 0x00 21.3.2.11/21-28 0x001f edma _x _cdsbr?edma clear done status bit register 8 w 0x00 21.3.2.12/21-29 0x0020 edma _ a_irqrh?edma_a interrupt request register (channels 63?32) reserved (edma_b) 32 r/w 0x0000_0000 21.3.2.13/21-30 0x0024 edma _x _irqrl?edma interrupt request register (channels 31?00) 32 r/w 0x0000_0000 21.3.2.13/21-30 0x0028 edma _ a_erh?edma_a error register (channels 63?32) reserved (edma_b) 32 r/w 0x0000_0000 21.3.2.14/21-31 0x002c edma _x _erl?edma error register (channels 31?00) 32 r/w 0x0000_0000 21.3.2.14/21-31 0x0030 edma _ a_hrsh?edma_a hardware request status register (channels 63?32) reserved (edma_b) 32 r/w 0x0000_0000 21.3.2.15/21-32 0x0034 edma _x _hrsl?edma hardware request status register (channels 31?00) 32 r/w 0x0000_0000 21.3.2.15/21-32 0x0038 edma_ x _gwrh?edma global write register high 32 r/w 0x0000_0000 21.3.2.16/21-33 0x003c edma_ x _gwrl?edma global write register low 32 r/w 0x0000_0000 21.3.2.16/21-33 0x0038?0x00ff reserved 0x0100 edma _x _cpr0?edma channel 0 priority register 8 r/w 0x00 21.3.2.17/21-33 0x0101 edma _x _cpr1?edma channel 1 priority register 8 r/w 0x01 21.3.2.17/21-33 0x0102 edma _x _cpr2?edma channel 2 priority register 8 r/w 0x02 21.3.2.17/21-33 0x0103 edma _x _cpr3?edma channel 3 priority register 8 r/w 0x03 21.3.2.17/21-33 0x0104 edma _x _cpr4?edma channel 4 priority register 8 r/w 0x04 21.3.2.17/21-33 0x0105 edma _x _cpr5?edma channel 5 priority register 8 r/w 0x05 21.3.2.17/21-33 0x0106 edma _x _cpr6?edma channel 6 priority register 8 r/w 0x06 21.3.2.17/21-33 0x0107 edma _x _cpr7?edma channel 7 priority register 8 r/w 0x07 21.3.2.17/21-33 0x0108 edma _x _cpr8?edma channel 8 priority register 8 r/w 0x08 21.3.2.17/21-33 0x0109 edma _x _cpr9?edma channel 9 priority register 8 r/w 0x09 21.3.2.17/21-33 0x010a edma _x _cpr10?edma channel 10 priority register 8 r/w 0x0a 21.3.2.17/21-33 0x010b edma _x _cpr11?edma channel 11 priority register 8 r/w 0x0b 21.3.2.17/21-33 0x010c edma _x _cpr12?edma channel 12 priority register 8 r/w 0x0c 21.3.2.17/21-33 0x010d edma _x _cpr13?edma channel 13 priority register 8 r/w 0x0d 21.3.2.17/21-33 0x010e edma _x _cpr14?edma channel 14 priority register 8 r/w 0x0e 21.3.2.17/21-33 0x010f edma _x _cpr15?edma channel 15 priority register 8 r/w 0x0f 21.3.2.17/21-33 table 21-1. edma memory map (continued) offset from edma _x _base register bits access reset value section/page
enhanced direct memory access controller (edma) 21-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x0110 edma _x _cpr16?edma channel 16 priority register 8 r/w 0x10 21.3.2.17/21-33 0x0111 edma _x _cpr17?edma channel 17 priority register 8 r/w 0x11 21.3.2.17/21-33 0x0112 edma _x _cpr18?edma channel 18 priority register 8 r/w 0x12 21.3.2.17/21-33 0x0113 edma _x _cpr19?edma channel 19 priority register 8 r/w 0x13 21.3.2.17/21-33 0x0114 edma _x _cpr20?edma channel 20 priority register 8 r/w 0x14 21.3.2.17/21-33 0x0115 edma _x _cpr21?edma channel 21 priority register 8 r/w 0x15 21.3.2.17/21-33 0x0116 edma _x _cpr22?edma channel 22 priority register 8 r/w 0x16 21.3.2.17/21-33 0x0117 edma _x _cpr23?edma channel 23 priority register 8 r/w 0x17 21.3.2.17/21-33 0x0118 edma _x _cpr24?edma channel 24 priority register 8 r/w 0x18 21.3.2.17/21-33 0x0119 edma _x _cpr25?edma channel 25 priority register 8 r/w 0x19 21.3.2.17/21-33 0x011a edma _x _cpr26?edma channel 26 priority register 8 r/w 0x1a 21.3.2.17/21-33 0x011b edma _x _cpr27?edma channel 27 priority register 8 r/w 0x1b 21.3.2.17/21-33 0x011c edma _x _cpr28?edma channel 28 priority register 8 r/w 0x1c 21.3.2.17/21-33 0x011d edma _x _cpr29?edma channel 29 priority register 8 r/w 0x1d 21.3.2.17/21-33 0x011e edma _x _cpr30?edma channel 30 priority register 8 r/w 0x1e 21.3.2.17/21-33 0x011f edma _x _cpr31?edma channel 31 priority register 8 r/w 0x1f 21.3.2.17/21-33 0x0120 edma_a_cpr32?edma channel 32 priority register 8 r/w 0x20 21.3.2.17/21-33 0x0121 edma_a_cpr33?edma channel 33 priority register 8 r/w 0x21 21.3.2.17/21-33 0x0122 edma_a_cpr34?edma channel 34 priority register 8 r/w 0x22 21.3.2.17/21-33 0x0123 edma_a_cpr35?edma channel 35 priority register 8 r/w 0x23 21.3.2.17/21-33 0x0124 edma_a_cpr36?edma channel 36 priority register 8 r/w 0x24 21.3.2.17/21-33 0x0125 edma_a_cpr37?edma channel 37 priority register 8 r/w 0x25 21.3.2.17/21-33 0x0126 edma_a_cpr38?edma channel 38 priority register 8 r/w 0x26 21.3.2.17/21-33 0x0127 edma_a_cpr39?edma channel 39 priority register 8 r/w 0x27 21.3.2.17/21-33 0x0128 edma_a_cpr40?edma channel 40 priority register 8 r/w 0x28 21.3.2.17/21-33 0x0129 edma_a_cpr41?edma channel 41 priority register 8 r/w 0x29 21.3.2.17/21-33 0x012a edma_a_cpr42?edma channel 42 priority register 8 r/w 0x2a 21.3.2.17/21-33 0x012b edma_a_cpr43?edma channel 43 priority register 8 r/w 0x2b 21.3.2.17/21-33 0x012c edma_a_cpr44?edma channel 44 priority register 8 r/w 0x2c 21.3.2.17/21-33 0x012d edma_a_cpr45?edma channel 45 priority register 8 r/w 0x2d 21.3.2.17/21-33 0x012e edma_a_cpr46?edma channel 46 priority register 8 r/w 0x2e 21.3.2.17/21-33 0x012f edma_a_cpr47?edma channel 47 priority register 8 r/w 0x2f 21.3.2.17/21-33 table 21-1. edma memory map (continued) offset from edma _x _base register bits access reset value section/page
enhanced direct memory access controller (edma) freescale semiconductor 21-7 pxr40 microcontroller reference manual, rev. 1 0x0130 edma_a_cpr48?edma channel 48 priority register 8 r/w 0x30 21.3.2.17/21-33 0x0131 edma_a_cpr49?edma channel 49 priority register 8 r/w 0x31 21.3.2.17/21-33 0x0132 edma_a_cpr50?edma channel 50 priority register 8 r/w 0x32 21.3.2.17/21-33 0x0133 edma_a_cpr51?edma channel 51 priority register 8 r/w 0x33 21.3.2.17/21-33 0x0134 edma_a_cpr52?edma channel 52 priority register 8 r/w 0x34 21.3.2.17/21-33 0x0135 edma_a_cpr53?edma channel 53 priority register 8 r/w 0x35 21.3.2.17/21-33 0x0136 edma_a_cpr54?edma channel 54 priority register 8 r/w 0x36 21.3.2.17/21-33 0x0137 edma_a_cpr55?edma channel 55 priority register 8 r/w 0x37 21.3.2.17/21-33 0x0138 edma_a_cpr56?edma channel 56 priority register 8 r/w 0x38 21.3.2.17/21-33 0x0139 edma_a_cpr57?edma channel 57 priority register 8 r/w 0x39 21.3.2.17/21-33 0x013a edma_a_cpr58?edma channel 58 priority register 8 r/w 0x3a 21.3.2.17/21-33 0x013b edma_a_cpr59?edma channel 59 priority register 8 r/w 0x3b 21.3.2.17/21-33 0x013c edma_a_cpr60?edma channel 60 priority register 8 r/w 0x3c 21.3.2.17/21-33 0x013d edma_a_cpr61?edma channel 61 priority register 8 r/w 0x3d 21.3.2.17/21-33 0x013e edma_a_cpr62?edma channel 62 priority register 8 r/w 0x3e 21.3.2.17/21-33 0x013f edma_a_cpr63?edma channel 63 priority register 8 r/w 0x3f 21.3.2.17/21-33 0x0140?0x0fff reserved 0x1000 edma _x _tcd00?edma transfer control descriptor 00 256 r/w ? 1 21.3.2.18/21-34 0x1020 edma _x _tcd01?edma transfer control descriptor 01 256 r/w ? 1 21.3.2.18/21-34 0x1040 edma _x _tcd02?edma transfer control descriptor 02 256 r/w ? 1 21.3.2.18/21-34 0x1060 edma _x _tcd03?edma transfer control descriptor 03 256 r/w ? 1 21.3.2.18/21-34 0x1080 edma _x _tcd04?edma transfer control descriptor 04 256 r/w ? 1 21.3.2.18/21-34 0x10a0 edma _x _tcd05?edma transfer control descriptor 05 256 r/w ? 1 21.3.2.18/21-34 0x10c0 edma _x _tcd06?edma transfer control descriptor 06 256 r/w ? 1 21.3.2.18/21-34 0x10e0 edma _x _tcd07?edma transfer control descriptor 07 256 r/w ? 1 21.3.2.18/21-34 0x1100 edma _x _tcd08?edma transfer control descriptor 08 256 r/w ? 1 21.3.2.18/21-34 0x1120 edma _x _tcd09?edma transfer control descriptor 09 256 r/w ? 1 21.3.2.18/21-34 0x1140 edma _x _tcd10?edma transfer control descriptor 10 256 r/w ? 1 21.3.2.18/21-34 0x1160 edma _x _tcd11?edma transfer control descriptor 11 256 r/w ? 1 21.3.2.18/21-34 0x1180 edma _x _tcd12?edma transfer control descriptor 12 256 r/w ? 1 21.3.2.18/21-34 0x11a0 edma _x _tcd13?edma transfer control descriptor 13 256 r/w ? 1 21.3.2.18/21-34 0x11c0 edma _x _tcd14?edma transfer control descriptor 14 256 r/w ? 1 21.3.2.18/21-34 table 21-1. edma memory map (continued) offset from edma _x _base register bits access reset value section/page
enhanced direct memory access controller (edma) 21-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x11e0 edma _x _tcd15?edma transfer control descriptor 15 256 r/w ? 1 21.3.2.18/21-34 0x1200 edma _x _tcd16?edma transfer control descriptor 16 256 r/w ? 1 21.3.2.18/21-34 0x1220 edma _x _tcd17?edma transfer control descriptor 17 256 r/w ? 1 21.3.2.18/21-34 0x1240 edma _x _tcd18?edma transfer control descriptor 18 256 r/w ? 1 21.3.2.18/21-34 0x1260 edma _x _tcd19?edma transfer control descriptor 19 256 r/w ? 1 21.3.2.18/21-34 0x1280 edma _x _tcd20?edma transfer control descriptor 20 256 r/w ? 1 21.3.2.18/21-34 0x12a0 edma _x _tcd21?edma transfer control descriptor 21 256 r/w ? 1 21.3.2.18/21-34 0x12c0 edma _x _tcd22?edma transfer control descriptor 22 256 r/w ? 1 21.3.2.18/21-34 0x12e0 edma _x _tcd23?edma transfer control descriptor 23 256 r/w ? 1 21.3.2.18/21-34 0x1300 edma _x _tcd24?edma transfer control descriptor 24 256 r/w ? 1 21.3.2.18/21-34 0x1320 edma _x _tcd25?edma transfer control descriptor 25 256 r/w ? 1 21.3.2.18/21-34 0x1340 edma _x _tcd26?edma transfer control descriptor 26 256 r/w ? 1 21.3.2.18/21-34 0x1360 edma _x _tcd27?edma transfer control descriptor 27 256 r/w ? 1 21.3.2.18/21-34 0x1380 edma _x _tcd28?edma transfer control descriptor 28 256 r/w ? 1 21.3.2.18/21-34 0x13a0 edma _x _tcd29?edma transfer control descriptor 29 256 r/w ? 1 21.3.2.18/21-34 0x13c0 edma _x _tcd30?edma transfer control descriptor 30 256 r/w ? 1 21.3.2.18/21-34 0x13e0 edma _x _tcd31?edma transfer control descriptor 31 256 r/w ? 1 21.3.2.18/21-34 0x1400 edma_a_tcd32?edma transfer control descriptor 32 256 r/w ? 1 21.3.2.18/21-34 0x1420 edma_a_tcd33?edma transfer control descriptor 33 256 r/w ? 1 21.3.2.18/21-34 0x1440 edma_a_tcd34?edma transfer control descriptor 34 256 r/w ? 1 21.3.2.18/21-34 0x1460 edma_a_tcd35?edma transfer control descriptor 35 256 r/w ? 1 21.3.2.18/21-34 0x1480 edma_a_tcd36?edma transfer control descriptor 36 256 r/w ? 1 21.3.2.18/21-34 0x14a0 edma_a_tcd37?edma transfer control descriptor 37 256 r/w ? 1 21.3.2.18/21-34 0x14c0 edma_a_tcd38?edma transfer control descriptor 38 256 r/w ? 1 21.3.2.18/21-34 0x14e0 edma_a_tcd39?edma transfer control descriptor 39 256 r/w ? 1 21.3.2.18/21-34 0x1500 edma_a_tcd40?edma transfer control descriptor 40 256 r/w ? 1 21.3.2.18/21-34 0x1520 edma_a_tcd41?edma transfer control descriptor 41 256 r/w ? 1 21.3.2.18/21-34 0x1540 edma_a_tcd42?edma transfer control descriptor 42 256 r/w ? 1 21.3.2.18/21-34 0x1560 edma_a_tcd43?edma transfer control descriptor 43 256 r/w ? 1 21.3.2.18/21-34 0x1580 edma_a_tcd44?edma transfer control descriptor 44 256 r/w ? 1 21.3.2.18/21-34 0x15a0 edma_a_tcd45?edma transfer control descriptor 45 256 r/w ? 1 21.3.2.18/21-34 0x15c0 edma_a_tcd46?edma transfer control descriptor 46 256 r/w ? 1 21.3.2.18/21-34 table 21-1. edma memory map (continued) offset from edma _x _base register bits access reset value section/page
enhanced direct memory access controller (edma) freescale semiconductor 21-9 pxr40 microcontroller reference manual, rev. 1 0x15e0 edma_a_tcd47?edma transfer control descriptor 47 256 r/w ? 1 21.3.2.18/21-34 0x1600 edma_a_tcd48?edma transfer control descriptor 48 256 r/w ? 1 21.3.2.18/21-34 0x1620 edma_a_tcd49?edma transfer control descriptor 49 256 r/w ? 1 21.3.2.18/21-34 0x1640 edma_a_tcd50?edma transfer control descriptor 50 256 r/w ? 1 21.3.2.18/21-34 0x1660 edma_a_tcd51?edma transfer control descriptor 51 256 r/w ? 1 21.3.2.18/21-34 0x1680 edma_a_tcd52?edma transfer control descriptor 52 256 r/w ? 1 21.3.2.18/21-34 0x16a0 edma_a_tcd53?edma transfer control descriptor 53 256 r/w ? 1 21.3.2.18/21-34 0x16c0 edma_a_tcd54?edma transfer control descriptor 54 256 r/w ? 1 21.3.2.18/21-34 0x16e0 edma_a_tcd55?edma transfer control descriptor 55 256 r/w ? 1 21.3.2.18/21-34 0x1700 edma_a_tcd56?edma transfer control descriptor 56 256 r/w ? 1 21.3.2.18/21-34 0x1720 edma_a_tcd57?edma transfer control descriptor 57 256 r/w ? 1 21.3.2.18/21-34 0x1740 edma_a_tcd58?edma transfer control descriptor 58 256 r/w ? 1 21.3.2.18/21-34 0x1760 edma_a_tcd59?edma transfer control descriptor 59 256 r/w ? 1 21.3.2.18/21-34 0x1780 edma_a_tcd60?edma transfer control descriptor 60 256 r/w ? 1 21.3.2.18/21-34 0x17a0 edma_a_tcd61?edma transfer control descriptor 61 256 r/w ? 1 21.3.2.18/21-34 0x17c0 edma_a_tcd62?edma transfer control descriptor 62 256 r/w ? 1 21.3.2.18/21-34 0x17e0 edma_a_tcd63?edma transfer control descriptor 63 256 r/w ? 1 21.3.2.18/21-34 1 see specific register description. table 21-2. edma_a 32-bit memory map?graphical view address register 0xfff4_4000 edma control register (edma_a_cr) 0xfff4_4004 edma error status (edma_a_esr) 0xfff4_4008 edma enable request register high (edma_a_erqrh) 0xfff4_400c edma enable request register low (edma_a_erqrl) 0xfff4_4010 edma enable error interrupt register high (edma_a_eeirh) 0xfff4_4014 edma enable error interrupt register low (edma_a_eeirl) 0xfff4_4018 edma set enable request (edma_a_serqr) edma clear enable request (edma_a_cerqr) edma set enable error interrupt (edma_a_seeir) edma clear enable error interrupt (edma_a_ceeir) 0xfff4_401c edma clear interrupt request (edma_a_cirqr) edma clear error (edma_a_cer) edma set start bit, activate channel (edma_a_ssbr) edma clear done status bit (edma_a_cdsbr) table 21-1. edma memory map (continued) offset from edma _x _base register bits access reset value section/page
enhanced direct memory access controller (edma) 21-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0xfff4_4020 edma interrupt request high (edma_a_irqrh channels 63?48) edma interrupt request high (edma_a_irqrh, channels 47?32) 0xfff4_4024 edma interrupt request low (edma_a_irqrl, channels 31?16) edma interrupt request low (edma_a_irqrl, channels 15?00) 0xfff4_4028 edma error high (edma_a_erl, channels 63?48) edma error high (edma_a_erl, channels 47?32) 0xfff4_402c edma error low (edma_a_erl, channels 31?16) edma error low (edma_a_erl, channels 15?00) 0xfff4_4030 edma hardware request status high (edma_a_hrsl, channels 63?48) edma hardware request status high (edma_a_hrsl, channels 47?32) 0xfff4_4034 edma hardware request status low (edma_a_hrsl, channels 31?16) edma hardware request status low (edma_a_hrsl, channels 15?00) 0xfff4_4038 ? 0xfff4_40fc reserved 0xfff4_4100 edma channel 0 priority (edma_a_cpr0) edma channel 1 priority (edma_a_cpr1) edma channel 2 priority (edma_a_cpr2) edma channel 3 priority (edma_a_cpr3) 0xfff4_4104 edma channel 4 priority (edma_a_cpr4) edma channel 5 priority (edma_a_cpr5) edma channel 6 priority (edma_a_cpr6) edma channel 7 priority edma_a_cpr7) 0xfff4_4108 edma channel 8 priority (edma_a_cpr8) edma channel 9 priority (edma_a_cpr9) edma channel 10 priority (edma_a_cpr10) edma channel 11 priority (edma_a_cpr11) 0xfff4_410c edma channel 12 priority (edma_a_cpr12) edma channel 13 priority (edma_a_cpr13) edma channel 14 priority (edma_a_cpr14) edma channel 15 priority (edma_a_cpr15) 0xfff4_4110 edma channel 16 priority (edma_a_cpr16) edma channel 17 priority (edma_a_cpr17) edma channel 18 priority (edma_a_cpr18) edma channel 19 priority (edma_a_cpr19) 0xfff4_4114 edma channel 20 priority (edma_a_cpr20) edma channel 21 priority (edma_a_cpr21) edma channel 22 priority (edma_a_cpr22) edma channel 23 priority (edma_a_cpr23) 0xfff4_4118 edma channel 24 priority (edma_a_cpr24) edma channel 25 priority (edma_a_cpr25) edma channel 26 priority (edma_a_cpr26) edma channel 27 priority (edma_a_cpr27) 0xfff4_411c edma channel 28 priority (edma_a_cpr28) edma channel 29 priority (edma_a_cpr29) edma channel 30 priority (edma_a_cpr30) edma channel 31 priority (edma_a_cpr31) 0xfff4_4120 edma channel 32 priority (edma_a_cpr32) edma channel 33 priority (edma_a_cpr33) edma channel 34 priority (edma_a_cpr34) edma channel 35 priority (edma_a_cpr35) table 21-2. edma_a 32-bit memory map?graphical view (continued) address register
enhanced direct memory access controller (edma) freescale semiconductor 21-11 pxr40 microcontroller reference manual, rev. 1 0xfff4_4124 edma channel 36 priority (edma_a_cpr36) edma channel 37 priority (edma_a_cpr37) edma channel 38 priority (edma_a_cpr38) edma channel 39 priority edma_a_cpr39) 0xfff4_4128 edma channel 40 priority (edma_a_cpr40) edma channel 41 priority (edma_a_cpr41) edma channel 42 priority (edma_a_cpr42) edma channel 43 priority (edma_a_cpr43) 0xfff4_412c edma channel 44 priority (edma_a_cpr44) edma channel 45 priority (edma_a_cpr45) edma channel 46 priority (edma_a_cpr46) edma channel 47 priority (edma_a_cpr47) 0xfff4_4130 edma channel 48 priority (edma_a_cpr48) edma channel 49 priority (edma_a_cpr49) edma channel 50 priority (edma_a_cpr50) edma channel 51 priority (edma_a_cpr51) 0xfff4_4134 edma channel 52 priority (edma_a_cpr52) edma channel 53 priority (edma_a_cpr53) edma channel 54 priority (edma_a_cpr54) edma channel 55 priority (edma_a_cpr55) 0xfff4_4138 edma channel 56 priority (edma_a_cpr56) edma channel 57 priority (edma_a_cpr57) edma channel 58 priority (edma_a_cpr58) edma channel 59 priority (edma_a_cpr59) 0xfff4_413c edma channel 60 priority (edma_a_cpr60) edma channel 61 priority (edma_a_cpr61) edma channel 62 priority (edma_a_cpr62) edma channel 63 priority (edma_a_cpr63) 0xfff4_4140 ? 0xfff4_4fff reserved 0xfff4_5000 ? 0xfff4_51fc edma_a_tcd00?edma_a_tcd15 0xfff4_5200 ? 0xfff4_53fc edma_a_tcd16?edma_a_tcd31 0xfff4_5400 ? 0xfff4_55fc edma_a_tcd32?edma_a_tcd47 0xfff4_5600 ? 0xfff4_57fc edma_a_tcd48?edma_a_tcd63 0xfff4_5800 reserved table 21-3. edma_b 32-bit memory map?graphical view address register 0xfff5_4000 edma control register (edma_b_cr) 0xfff5_4004 edma error status (edma_b_esr) 0xfff5_4008 reserved 0xfff5_400c edma enable request (edma_b_erqrl, channels 31?16) edma enable request (edma_b_erqrl, channels 15?00) 0xfff5_4010 reserved table 21-2. edma_a 32-bit memory map?graphical view (continued) address register
enhanced direct memory access controller (edma) 21-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0xfff5_4014 edma enable error interrupt low (edma_b_eeirl, channels 31?16) edma enable error interrupt low (edma_b_eeirl, channels 15?00) 0xfff5_4018 edma set enable request (edma_b_serqr) edma clear enable request (edma_b_cerqr) edma set enable error interrupt (edma_b_seeir) edma clear enable error interrupt (edma_b_ceeir) 0xfff5_401c edma clear interrupt request (edma_b_cirqr) edma clear error (edma_b_cer) edma set start bit, activate channel (edma_b_ssbr) edma clear done status bit (edma_b_cdsbr) 0xfff5_4020 reserved 0xfff5_4024 edma interrupt request (edma_b_irqrl, channels 31?16) edma interrupt request (edma_b_irqrl, channels 15?00) 0xfff5_4028 reserved 0xfff5_402c edma error (edma_b_erl, channels 31?16) edma error (edma_b_erl, channels 15?00) 0xfff5_4030 reserved 0xfff5_4034 edma hardware request status (edma_b_hrsl, channels 31?16) edma hardware request status (edma_b_hrsl, channels 15?00) 0xfff5_4038 ? 0xfff5_40fc reserved 0xfff5_4100 edma channel 0 priority (edma_b_cpr0) edma channel 1 priority (edma_b_cpr1) edma channel 2 priority (edma_b_cpr2) edma channel 3 priority (edma_b_cpr3) 0xfff5_4104 edma channel 4 priority (edma_b_cpr4) edma channel 5 priority (edma_b_cpr5) edma channel 6 priority (edma_b_cpr6) edma channel 7 priority edma_b_cpr7) 0xfff5_4108 edma channel 8 priority (edma_b_cpr8) edma channel 9 priority (edma_b_cpr9) edma channel 10 priority (edma_b_cpr10) edma channel 11 priority (edma_b_cpr11) 0xfff5_410c edma channel 12 priority (edma_b_cpr12) edma channel 13 priority (edma_b_cpr13) edma channel 14 priority (edma_b_cpr14) edma channel 15 priority (edma_b_cpr15) 0xfff5_4110 edma channel 16 priority (edma_b_cpr16) edma channel 17 priority (edma_b_cpr17) edma channel 18 priority (edma_b_cpr18) edma channel 19 priority (edma_b_cpr19) 0xfff5_4114 edma channel 20 priority (edma_b_cpr20) edma channel 21 priority (edma_b_cpr21) edma channel 22 priority (edma_b_cpr22) edma channel 23 priority (edma_b_cpr23) 0xfff5_4118 edma channel 24 priority (edma_b_cpr24) edma channel 25 priority (edma_b_cpr25) edma channel 26 priority (edma_b_cpr26) edma channel 27 priority (edma_b_cpr27) table 21-3. edma_b 32-bit memory map?graphical view (continued) address register
enhanced direct memory access controller (edma) freescale semiconductor 21-13 pxr40 microcontroller reference manual, rev. 1 21.3.2 register descriptions note any reference to edma_a _[register_name] should be ignored when using edma_b. that register does not exist in edma_b. registers that exist in both edma_a and edma_b are indicated with a register name of format edma_ x _[register_name]. this section lists the edma regist ers in address order and describes the registers and their bit fields. reading reserved bits in a register re turns the value of zero. writes to rese rved bits in a register are ignored. reading or writing to a reserved me mory location generates a bus error. many of the control registers have a bit width that matches the number of channels implemented in the module: ? 64 bits for edma_a (made up of two 32- bit registers: high and low?for example edma_a_erqrh has upper 32 channels of edma_a) ? 32 bits for edma_b 21.3.2.1 edma control register (edma_ x _mcr) the 32-bit edma_ x _mcr defines the basic operati ng configuration of the edma. the edma arbitrates channe l service requests in two (edma_b) or four (edma_ a) groups (0, 1, 2, 3) of 16 channels each: ? group 0 contains channels 0?15 ? group 1 contains channels 16?31 ? group 2 contains cha nnels 32-47 (edma_a only) ? group 3 contains cha nnels 48-63 (edma_a only) arbitration within a group can be c onfigured to use a fixed priority or a round robin. in fixed-priority arbitration, the highest priority ch annel requesting service is selected to execute. the priorities are 0xfff5_411c edma channel 28 priority (edma_b_cpr28) edma channel 29 priority (edma_b_cpr29) edma channel 30 priority (edma_b_cpr30) edma channel 31 priority (edma_b_cpr31) 0xfff5_4120 ? 0xfff5_4fff reserved 0xfff5_5000 ? 0xfff5_51fc edma_b_tcd00?edma_b_tcd15 0xfff5_5200 ? 0xfff5_53fc edma_b_tcd16?edma_b_tcd31 0xfff5_5300 reserved table 21-3. edma_b 32-bit memory map?graphical view (continued) address register
enhanced direct memory access controller (edma) 21-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 assigned by the channel priority registers. see section 21.3.2.17, edma channel n priority registers (edma_x_cprn). in round-robin arbitration m ode, the channel priorities ar e ignored and the channels within each group are cycled through, from channel 15 down to channel 0,without regard to priority. the group priorities operate in a si milar fashion. in group fi xed-priority arbitrati on mode, channel service requests in the highest priority grou p are executed first wh ere priority level 3 (e dma_a) or 1 (edma_b) is the highest and priori ty level 0 is the lowest. the group priorities are assigned in the grp n pri fields of the edma control register (edma_ x _mcr). all group priori ties must have unique values prior to any channel service requests occur, othe rwise a configuration er ror is reported. in gr oup round-robin mode, the group priorities are ignored and the groups are cycl ed through, from group 3 (edma_a) or 1 (edma_b) down to group 0, without regard to priority. minor loop offsets are address offset values added to the final source addre ss (saddr) or destination address (daddr) upon minor loop completion. when mi nor loop offsets are enabled, the minor loop offset (mloff) is added to the final source addr ess (saddr) or to the fi nal destination address (daddr) or to both addresses prior to the addresses being written back into the tcd. if the major loop is complete, the minor loop offset is ignored and the major loop address offsets (slast and dlast_sga) are used to compute the next edma _x _tcd.saddr and edma _x _tcd.daddr values. when minor loop mapping is enabled (edma_ x _mcr[emlm] = 1), tcd n word2 is redefined. a portion of tcd n word2 is used to specify multiple fields: a source enable bit (smloe) to specify that the minor loop offset should be applied to the s ource address (saddr) upon minor loop completion, a destination enable bit (dmloe) to specify the minor loop offset should be applied to the destination address (daddr) upon minor loop comp letion, and the sign extended minor loop offset value (mloff). the same offset value (mloff) is used for both source and destinat ion minor loop offsets. when either of the minor loop offset s is enabled (smloe is set or dmloe is set) , the nbytes field is reduced to 10 bits. when bot h minor loop offsets are disabled (smloe is cleared and dmloe is cleared), the nbytes field becomes a 30-bit vector. when minor loop mapping is disabled (edma_ x _mcr[emlm] = 0), all 32 bits of tcd n word2 are assigned to the nbytes field. see section 21.3.2.18, transfer control descriptor (tcd), for more details.
enhanced direct memory access controller (edma) freescale semiconductor 21-15 pxr40 microcontroller reference manual, rev. 1 offset: edma _a _base + 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000 0 000 0 0 cxfr ecx w reset00000000 0 000 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r grp3pri grp2pri grp1pri grp0pri emlm clm halt hoe erga erca edbg 0 w reset11100100 0 000 0 0 0 0 figure 21-2. edma control register (edma _a _cr) offset: edma _b _base + 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000 0 000 0 0 cxfr ecx w reset00000000 0 000 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 grp1 pri 0 grp0 pri emlm clm halt hoe erga erca edbg 0 w reset00000100 0 000 0 0 0 0 figure 21-3. edma control register (edma _b _cr) table 21-4. edma_ a _mcr field descriptions field description 0?13 reserved 14 cxfr cancel transfer. 0 normal operation. 1 cancel the remaining data transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the cxfr bit clears itself after the cancel has been honored. this cancel retires the channel normally as if the minor loop was completed. 15 ecx error cancel transfer. 0 normal operation. 1 cancel the remaining data transfer in the same fashion as the cxfr cancel transfer. stop the executing channel and force the minor loop to be fini shed. the cancel takes effect after the last write of the current read/write sequence. the ecx bit cl ears itself after the cancel has been honored. in addition to cancelling the transfer, the ecx treats the cancel as an error condition; thus updating the edma _x _esr register and generating an optional error interrupt. see section 21.3.2.2, edma error status register (edma_x_esr).
enhanced direct memory access controller (edma) 21-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16?17 grp3pri channel group 3 priority. group 3 priority level when fixed priority group arbitration is enabled. 18?19 grp2pri channel group 2 priority. group 2 priority level when fixed priority group arbitration is enabled. 20?21 grp1pri channel group 1 priority. group 1 priority level when fixed priority group arbitration is enabled. 22?23 grp0pri channel group 0 priority. group 0 priority level when fixed priority group arbitration is enabled. 24 emlm enable minor loop mapping. 0 minor loop mapping disabled. tcd word 2 is defined as a 32-bit nbytes field. 1 minor loop mapping enabled. when set, tcd n word 2 is redefined to include individual enable fields, an offset field and the nbytes field. the individu al enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. the nbytes field is reduced when either offset is enabled. 25 clm continuous link mode. 0 a minor loop channel link made to itself goes th rough channel arbitration before being activated again. 1 a minor loop channel link made to itself does not go through channel arbitration before being activated again. upon minor loop completion, the channel is ac tive again if that channel has a minor loop channel link enabled and the link channel is itself. this ef fectively applies the minor loop offsets and restarts the next minor loop. 26 halt halt dma operations. 0 normal operation. 1 stall the start of any new channels. executing channels are allowed to complete. channel execution resumes when the halt bit is cleared. 27 hoe halt on error. 0 normal operation. 1 any error causes the halt bit to be set. subsequen tly, all service requests are ignored until the halt bit is cleared. 28 erga enable round-robin group arbitration. 0 fixed-priority arbitration is used for selection among the groups. 1 round-robin arbitration is used for selection among the groups. 29 erca enable round-robin channel arbitration. 0 fixed-priority arbitration is used for channel selection within each group. 1 round-robin arbitration is used for channel selection within each group. 30 edbg enable debug. 0 the assertion of the system debug control input is ignored. 1 the assertion of the system debug control input causes the edma to stall the start of a new channel. executing channels are allowed to complete. ch annel execution resumes when either the system debug control input is negated or the edbg bit is cleared. 31 reserved table 21-4. edma_ a _mcr field descript ions (continued) field description
enhanced direct memory access controller (edma) freescale semiconductor 21-17 pxr40 microcontroller reference manual, rev. 1 21.3.2.2 edma error status register (edma _x _esr) the edma_ x _esr provides information about the last reco rded channel error. channel errors can be caused by a configuration error (an illegal setting in th e transfer control descriptor or an illegal priority register setting in fixed-arbitrati on mode) or an error termination to a bus master read or write cycle. a configuration error is caused when the starting source or destinati on address, source or destination offsets, minor loop byte count, and th e transfer size represent an inc onsistent state. the addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destinat ion transfer sizes. all source read s and destination writes must be configured to the natural boundary of th e programmed transfer size respectively. in fixed-arbitration mode, a configur ation error is generated when any tw o channel priority levels are equal and any channel is activated. the errchn field is undefi ned for this type of error. all channel priority levels must be unique before any service requests are made. if a scatter-gather operation is en abled on channel completion, a configuration error is reported if the scatter-gather address (dlast_s ga) is not aligned on a 32-byte bounda ry. if minor loop channel linking is enabled on channel completion, a c onfiguration error is reported when the link is attempted if the edma _x _tcd.citer.e_link bit is not equal to the edma _x _tcd.biter.e_link bit. all configuration error conditions except scatter-gather and mino r loop link error are reported as the channel is activated and assert an error interrupt request if enabled. when properly enabled, a scatter-gather configuration error is reported when the scatter-gather operation begins at major loop completion. a minor loop channel link configuration error is reported wh en the link operation is serviced at minor loop completion. if a system bus read or wr ite is terminated with an error, the data transfer is immediately stopped and the appropriate bus error flag is set. in this case, the state of the channe l?s transfer control descriptor is updated by the dma engine with the current s ource address, destination address, and minor loop byte count at the point of the fault. if a bus error oc curs on the last read prior to beginning the write sequence, the write is executed using the data capt ured during the bus error. if a bus error occurs on the last write prior to switching to the next read sequence, the read sequence is executed before the channel is terminated due to the destination bus error. a transfer may be cancelled by software via the edma_ x _mcr[cx] bit. when a can cel transfer request is recognized, the edma engine stops processing the ch annel. the current read-w rite sequence is allowed to finish. if the cancel occurs on the last read-write seque nce of a major or minor loop, the cancel request is discarded and the channel retires normally. the error cancel transfer is the sa me as a cancel transfer except the dmaes register is updated with the cancelled channel number and error cancel bit is set. the tcd of a cancelled channel has the source address and destination address of the last transfer saved in the tcd. it is the responsibility of the user to initialize the tcd again should the channel need to be restarted because the aforementioned fields have been modified by the edma engine and no longer represent the original parameters. when a transfer is cancelled via the error cancel tran sfer mechanism (setting the edma_ x _mcr[ecx]), the channel number is loaded into the edma_ x _esr[errchn] field and the edma_ x _esr[ecx] and edma_ x _esr[vld] bits are set. in addition, an error in terrupt may be generated if enabled. refer to section 21.3.2.14, edma error regist ers (edma_x_erh, edma_x_erl).
enhanced direct memory access controller (edma) 21-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the occurrence of any type of erro r causes the dma engine to stop the active channel and the appropriate channel bit in the edma error register to be asserte d. at the same time, the details of the error condition are loaded into the edma_ x _esr. the major loop complete indicators, setting the transfer control descriptor done flag and the possible a ssertion of an interrupt request, are not affected when an error is detected. after the error status has been updated, th e dma engine continues to operate by servicing the next appropriate channel. a channel that experiences an error condition is not automatically disabled. if a channel is terminated by an error a nd then issues another service request before the error is fixed, that channel will execute and terminat e with the same error condition. offset: edma _x _base + 0x0004 access: user read-only 0123456789101112131415 rvld00000000000000ecx w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpe cpe errchn sae soe dae doe nce sge sbe dbe w reset0000000000000000 figure 21-4. edma error status register (edma _x _esr) table 21-5. edma _x _esr field descriptions field description 0 vld valid bit. logical or of all edma _x _erl status bits. 0no edma _x _er bits are set. 1 at least one edma _x _er bit is set indicating a valid error exists that has not been cleared. 1?14 reserved 15 ecx transfer canceled. 0 no canceled transfers. 1 the last recorded entry was a canceled transfer via the error cancel transfer input. 16 gpe group-priority error. 0 no group-priority error. 1 the last recorded error was a configuration error among the group priorities indicating not all group priorities are unique. 17 cpe channel-priority error. 0 no channel-priority error. 1 the last recorded error was a configuration error in the channel priorities within a group, indicating not all channel priorities within a group are unique. 18?23 errchn error channel number or canceled channel number. channel number of the last recorded error (excluding gpe and cpe errors) or last recorded transfer that was error cancelled. note: do not rely on the number in the errchn field group for channel-priority errors. group- and channel-priority errors must be resolved by ins pection. the application code must interrogate the priority registers to find groups or channels with duplicate priority level.
enhanced direct memory access controller (edma) freescale semiconductor 21-19 pxr40 microcontroller reference manual, rev. 1 21.3.2.3 edma enable request registers (edma_a_erqrh, edma_ x _erqrl) note any reference to edma_a _[register_name] should be ignored when using edma_b. that register does not exist in edma_b. registers that exist in both edma_a and edma_b are indicated with a register name of format edma_ x _[register_name]. the edma_a_erqrh and edma_ x _erqrl provide a bit map for the 32 (or 64 for edma_a) channels to enable the request signal for each channel. edma _ a_erqrh supports channels 63?32, while edma _x _erqrl covers channels 31?0. 24 sae source address error. 0 no source address configuration error. 1 the last recorded error was a configuration error detected in the edma _x _tcd.saddr field, indicating edma _x _tcd.saddr is inconsistent with edma _x _tcd.ssize. 25 soe source offset error. 0 no source offset configuration error. 1 the last recorded error was a config uration error detected in the edma _x _tcd.soff field, indicating edma _x _tcd.soff is inconsistent with edma _x _tcd.ssize. 26 dae destination address error. 0 no destination address configuration error. 1 the last recorded error was a configuration error detected in the edma _x _tcd.daddr field, indicating edma _x _tcd.daddr is inconsistent with edma _x _tcd.dsize. 27 doe destination offset error. 0 no destination offset configuration error. 1 the last recorded error was a configuration error detected in the edma _x _tcd.doff field, indicating edma _x _tcd.doff is inconsistent with edma _x _tcd.dsize. 28 nce nbytes/citer configuration error. 0 no nbytes/citer co nfiguration error. 1 the last recorded error was a configuration error detected in the edma _x _tcd.nbytes or edma _x _tcd.citer fields, indicating the following conditions exist: ?edma _x _tcd.nbytes is not a multiple of edma _x _tcd.ssize and edma _x _tcd.dsize, or ?edma _x _tcd.citer is equal to zero, or ?edma _x _tcd.citer.e_link is not equal to edma _x _tcd.biter.e_link. 29 sge scatter-gather configuration error. 0 no scatter-gather configuration error. 1 the last recorded error was a configuration error detected in the edma _x _tcd.dlast_sga field, indicating edma _x _tcd.dlast_sga is not on a 32-byte boundary. this field is checked at the beginning of a scatter-gather operation after major loop completion if edma _x _tcd.e_sg is enabled. 30 sbe source bus error. 0 no source bus error. 1 the last recorded error was a bus error on a source read. 31 dbe destination bus error. 0 no destination bus error. 1 the last recorded error was a bus error on a destination write. table 21-5. edma _x _esr field descriptions (continued) field description
enhanced direct memory access controller (edma) 21-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the state of any given channel enable is directly affe cted by writes to these registers; the state is also affected by writes to the edma _x _serqr and edma_ x _cerqr. the edma_a x _cerqr and edma_ x _serqr are provided so that the request enable for a single channel can be modified without performing a read-modify-w rite sequence to the ed ma_a_erqrh and edma_ x _erqrl. both the edma request input signal and this enable request flag must be asse rted before a channel?s hardware service request is accepted. the state of the edma enable request flag does not effect a channel service request made through software or a linked channel request. as a given channel completes processing its major iterat ion count, there is a flag in the transfer control descriptor that may affect the ending state of the edma _x _erqr bit for that channel. if the address: edma_a_base + 0x0008 access: user r/w 0123456789101112131415 r erq 63 erq 62 erq 61 erq 60 erq 59 erq 58 erq 57 erq 56 erq 55 erq 54 erq 53 erq 52 erq 51 erq 50 erq 49 erq 48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq 47 erq 46 erq 45 erq 44 erq 43 erq 42 erq 41 erq 40 erq 39 erq 38 erq 37 erq 36 erq 35 erq 34 erq 33 erq 32 w reset0000000000000000 figure 21-5. edma enable reques t high register (edma_a_erqrh) offset: edma _x _base + 0x000c access: user read/write 0123456789101112131415 r erq 31 erq 30 erq 29 erq 28 erq 27 erq 26 erq 25 erq 24 erq 23 erq 22 erq 21 erq 20 erq 19 erq 18 erq 17 erq 16 w reset0000000000000000 16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq 15 erq 14 erq 13 erq 12 erq 11 erq 10 erq 09 erq 08 erq 07 erq 06 erq 05 erq 04 erq 03 erq 02 erq 01 erq 00 w reset0000000000000000 figure 21-6. edma enable request register (edma _x _erqrl) table 21-6. edma _x _erqrl field descriptions field description 0?31 erq n enable edma hardware service request n. 0 the edma request signal for channel n is disabled. 1 the edma request signal for channel n is enabled.
enhanced direct memory access controller (edma) freescale semiconductor 21-21 pxr40 microcontroller reference manual, rev. 1 edma _x _tcd.d_req bit is set, then the corresponding edma _x _erqr bit is cleared after the major loop is complete, disabling the edma hardware request . otherwise if the d_req bit is cleared, the state of the edma_ x _erqr bit is unaffected. 21.3.2.4 edma enable error interr upt registers (edma_a_eeirh, edma _x _eeirl) note any reference to edma_a _[register_name] should be ignored when using edma_b. that register does not exist in edma_b. registers that exist in both edma_a and edma_b are indicated with a register name of format edma _x _[register_name]. the edma_a_eeirh and edma_ x _eeirl provide a bit map for the 32 (or 64 fo r edma_a) channels to enable the error interrupt signal for each ch annel. edma_a_eeirh s upports channels 63?32, while edma _x _eeirl covers channels 31?0. the state of any given channel?s error interrupt enable is directly affected by writes to these registers; it is also affected by writes to the edma _x _seeir and edma _x _ceeir. the edma _x _seeir and edma _x _ceeir are provided so that the error interrupt enable for a single channel can be modified without the performing a read -modify-write seque nce to the edma_a _eeirh and edma _x _eeirl. both the edma error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a gi ven channel is asserted. address: edma_a_base + 0x0010 access: user read/write 0123456789101112131415 r eei 63 eei 62 eei 61 eei 60 eei 59 eei 58 eei 57 eei 56 eei 55 eei 54 eei 53 eei 52 eei 51 eei 50 eei 49 eei 48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei 47 eei 46 eei 45 eei 44 eei 43 eei 42 eei 41 eei 40 eei 39 eei 38 eei 37 eei 36 eei 35 eei 34 eei 33 eei 32 w reset0000000000000000 figure 21-7. edma enable error interrupt high register (edma_a_eeirh)
enhanced direct memory access controller (edma) 21-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 address: edma _x _base + 0x0014 access: user r/w 0123456789101112131415 r eei 31 eei 30 eei 29 eei 28 eei 27 eei 26 eei 25 eei 24 eei 23 eei 22 eei 21 eei 20 eei 19 eei 18 eei 17 eei 16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei 15 eei 14 eei 13 eei 12 eei 11 eei 10 eei 09 eei 08 eei 07 eei 06 eei 05 eei 04 eei 03 eei 02 eei 01 eei 00 w reset0000000000000000 figure 21-8. edma enable error interrupt low register (edma _x _eeirl) table 21-7. edma _x _eeirl field descriptions field description 0?31 eei n enable error interrupt n. 0 the error signal for channel n does not generate an error interrupt. 1 the assertion of the error signal for channel n generate an error interrupt request.
enhanced direct memory access controller (edma) freescale semiconductor 21-23 pxr40 microcontroller reference manual, rev. 1 21.3.2.5 edma set enable request register (edma _x _serqr) note any reference to edma_a _[register_name] should be ignored when using edma_b. that register does not exist in edma_b. registers that exist in both edma_a and edma_b are indicated with a register name of format edma _x _[register_name]. the edma _x _serqr provides a simple memory-mappe d mechanism to set a given bit in the edma_a_erqrh or edma _x _erqrl to enable the edma request for a given channel. the data value on a register write cau ses the corresponding bit in th e edma_a_erqrh or edma_ x _erqrl to be set. setting bit 1 (serq[0]) provides a globa l set function, forcing th e entire contents of edma_a_erqrh and edma_ x _erqrl to be asserted. reads of this register return all zeroes. if bit 0 is set, the serq command is ignored. this allows mu ltiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. offset: edma _x _base + 0x0018 access: user write-only 01234567 r00000000 w nop serq[0:6] reset00000000 figure 21-9. edma set enable request register (edma _x _serqr) table 21-8. edma _x _serqr field descriptions field descriptions 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1?7. 1?7 serq set enable request. 0?31 (63 for edma_a) set corresponding bit in edma_a_erqrh or edma _x _erqrl. 64?127 set all bits in edma_a_erqrh and edma _x _erqrl. bit 2 (serqr[1]) is not used on edma_b.
enhanced direct memory access controller (edma) 21-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.3.2.6 edma clear enable request register (edma _x _cerqr) note any reference to edma_a _[register_name] should be ignored when using edma_b. that register does not exist in edma_b. registers that exist in both edma_a and edma_b are indicated with a register name of format edma _x _[register_name]. the edma _x _cerqr provides a simple memory-mapped mechanism to clear a given bit in the edma_a_erqrh or edma _x _erqrl to disable the dma request fo r a given channel. the data value on a register write causes the corres ponding bit in the edma_a_erqrh or edma _x _erqrl to be cleared. setting bit 1 (cerq[0]) provides a global clear function, fo rcing the entire contents of edma_a_erqrh and edma _x _erqrl to be zero ed, disabling all ed ma request inputs. reads of this register return all zeroes. if bit 0 is set, the cerq command is ignored. this allows multiple byte registers to be wr itten as a 32-bit word. reads of this register return all zeroes. offset: edma _x _base + 0x0019 access: user write-only 01234567 r00000000 w nop cerq[0:6] reset00000000 figure 21-10. edma clear enable request register (edma _x _cerqr) table 21-9. edma _x _cerqr field descriptions field description 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1?7. 1?7 cerq clear enable request. 0?31 (63 for edma_a) clear corresponding bit in edma_a_erqrh or edma _x _erqrl. 64?127 clear all bits in edma_a_erqrh and edma _x _erqrl. bit 2 (cerqr[1]) is not used on edma_b.
enhanced direct memory access controller (edma) freescale semiconductor 21-25 pxr40 microcontroller reference manual, rev. 1 21.3.2.7 edma set enable erro r interrupt register (edma _x _seeir) note any reference to edma_a _[register_name] should be ignored when using edma_b. that register does not exist in edma_b. registers that exist in both edma_a and edma_b are indicated with a register name of format edma _x _[register_name]. the edma_ x _seeir provides a memory-mapped mechanism to set a given bit in the edma_a_eeirh or edma _x _eeirl to enable the error inte rrupt for a given channel. the data value on a register write causes the corresponding bit in the edma_a_eeirh or edma_ x _eeirl to be set. setting bit 1 (seei[0]) provides a global set function, forcing the entire co ntents of edma_a_eeirh or edma_ x _eeirl to be asserted. reads of this register return all zeroes. if bit 0 is set, the seei command is ignored. this al lows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. offset: edma _x _base + 0x001a access: user write-only 01234567 r00000000 w nop seei[0:6] reset00000000 figure 21-11. edma set enable error interrupt register (edma _x _seeir) table 21-10. edma _x _seeir field descriptions field description 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1?7. 1?7 seei[0:6] set enable error interrupt. 0?31 (63 for edma_a) set corresponding bit in edma_a_eirrh or edma _x _eirrl. 64?127 set all bits in edma_a_eirrh or edma _x _eeirl. bit 2(seeir[1]) is not used on edma_b.
enhanced direct memory access controller (edma) 21-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.3.2.8 edma clear enable erro r interrupt register (edma _x _ceeir) the edma _x _ceeir provides a memory-mapped mechan ism to clear a given bit in the edma_a_eeirh or edma _x _eeirl to disable the error interrupt for a given channel. the data value on a register write causes the corres ponding bit in the edma_a_eeirh or edma _x _eeirl to be cleared. setting bit 1 (ceei[0]) provides a global cl ear function, forcing the entire contents of the edma_a_eeirh or edma_ x _eeirl to be zeroed, disabling error interrupts for all ch annels. reads of this register return all zeroes. if bit 0 is set, the ceei command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. offset: edma _x _base + 0x001b access: user write-only 01234567 r00000000 w nop ceei[0:6] reset00000000 figure 21-12. edma clear enable error interrupt register (edma _x _ceeir) table 21-11. edma _x _ceeir field descriptions field description 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1-7. 1?7 ceei clear enable error interrupt. 0?31 (63 for edma_a) clear corresponding bit in edma_a_eeirh or edma _x _eeirl. 64?127 clear all bits in edma_a_eeirh or edma _x _eeirl. bit 2 (ceeir[1]) is not used on edma_b.
enhanced direct memory access controller (edma) freescale semiconductor 21-27 pxr40 microcontroller reference manual, rev. 1 21.3.2.9 edma clear interrupt request register (edma _x _cirqr) the edma _x _cirqr provides a memory-mapped mech anism to clear a given bit in the edma_a_irqrh or edma_ x _irqrl to disable the interrupt reque st for a given channel. the given value on a register write causes the corr esponding bit in the edma_a_irqrh or edma_ x _irqrl to be cleared. setting bit 1 (cint[0]) provides a global clear function, forc ing the entire contents of the edma_a_irqrh or edma_ x _irqrl to be zeroed, disabling all edma interrupt requests. reads of this register return all zeroes. if bit 0 is set, the cint command is ignored. this al lows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. 21.3.2.10 edma clear er ror register (edma _x _cer) the edma _x _cer provides a memory-mapped mechanism to clear a given bit in the edma_a_erh or edma _x _erl to disable the error condi tion flag for a given channel. the given value on a register write causes the corresponding bit in the edma_a_erh or edma _x _erl to be cleared. setting bit 1 (cerr[0]) provides a global clear function, forcing the entire cont ents of the edma_a_erh or edma _x _erl to be zeroed, clearing all ch annel error indicators. reads of th is register return all zeroes. if bit 0 is set, the cerr command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. offset: edma _x _base + 0x001c access: user write-only 01234567 r00000000 w nop cint[0:6] reset00000000 figure 21-13. edma clear interrupt request (edma _x _cirqr) table 21-12. edma _x _cirqr field descriptions field description 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1-7. 1?7 cint clear interrupt request. 0?31 (63 for edma_a) clear corresponding bit in edma_a_irqrh or edma _x _irqrl. 64?127 clear all bits in edma_a_irqrh or edma _x _irqrl. bit 2 (cirqr[1]) is not used on edma_b.
enhanced direct memory access controller (edma) 21-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.3.2.11 edma set start bit register (edma _x _ssbr) the edma _x _ssbr provides a memory-mapped mechanism to set the start bit in the tcd of the given channel. the data value on a register write causes the start bit in the corresponding transfer control descriptor to be set. sett ing bit 1 (ssb[0]) provides a global set function, forcing all start bits to be set. reads of this register return all zeroes. if bit 0 is set, the ssb command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. offset: edma _x _base + 0x001d access: user write-only 01234567 r00000000 w nop cerr[0:6] reset00000000 figure 21-14. edma clear error register (edma _x _cer) table 21-13. edma _x _cer field descriptions field description 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1?7. 1?7 cerr clear error indicator. 0?31 (63 for edma_a) clear corresponding bit in edma_a_erh or edma _x _erl. 64?127 clear all bits in edma_a_erh or edma _x _erl. bit 2 (cer[1]) is not used on edma_b. offset: edma _x _base + 0x001e access: user write-only 01234567 r00000000 w nop ssb[0:6] reset00000000 figure 21-15. edma set start bit register (edma _x _ssbr)
enhanced direct memory access controller (edma) freescale semiconductor 21-29 pxr40 microcontroller reference manual, rev. 1 21.3.2.12 edma clear done st atus bit register (edma _x _cdsbr) the edma_ x _cdsbr provides a memory-mappe d mechanism to clear the done bit in the tcd of the given channel. the data value on a re gister write causes the done bit in the corres ponding transfer control descriptor to be cleare d. setting bit 1 (cdsb[0]) provides a globa l clear function, forcing all done bits to be cleared. if bit 0 is set, the cdsb command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. table 21-14. edma _x _ssbr field descriptions field description 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1?7. 1?7 ssb set start bit (channel service request). 0?31 (63 for edma_a) set the corresponding channel?s tcd start bit. 64?127 set all tcd start bits. bit 2 (ssbr[1]) is not used on edma_b. offset: edma _x _base + 0x001f access: user write-only 01234567 r00000000 w nop cdsb[0:6] reset00000000 figure 21-16. edma clear done status bit register (edma _x _cdsbr) table 21-15. edma _x _cdsbr field descriptions field description 0 nop no operation. 0 normal operation. 1 no operation, ignore bits 1?7. 1?7 cdsb clear done status bit. 0?31 (63 for edma_a) clear the corresponding channel?s done bit. 64?127 clear all tcd done bits. bit 2 (cdsbr[1]) is not used on edma_b.
enhanced direct memory access controller (edma) 21-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.3.2.13 edma interrupt request registers (edma_a_irqrh, edma _x _irqrl) the edma_a_irqrh and edma _x _irqrl provide a bit map for the 32 channels signaling the presence of an interrupt request for each ch annel. edma_a_irqrh maps to channels 63?32 and edma _x _irqrl maps to channels 31?0. the dma engine signals the occurrence of a program med interrupt on the completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in this register. the outputs of this register are directly routed to the interrupt controller (intc). during the execution of the interrupt service routine associated with any given channel, so ftware must clear the appr opriate bit, negating the interrupt request. typically, a write to the edma _x _cirqr in the interrupt service routine is used for this purpose. the state of any given channel?s interr upt request is directly affected by wr ites to this register; it is also affected by writes to the edma _x _cirqr. on writes to th e edma_a_irqrh or edma _x _irqrl, a 1 in any bit position clears the corresponding channel? s interrupt request. a 0 in any bit position has no effect on the corresponding channel?s current interrupt status. the edma _x _cirqr is provided so the interrupt request for a single channel can be cleared. address: edma_a_base + 0x0020 access: user r/w 0123456789101112131415 r int 63 int 62 int 61 int 60 int 59 int 58 int 57 int 56 int 55 int 54 int 53 int 52 int 51 int 50 int 49 int 48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r int 47 int 46 int 45 int 44 int 43 int 42 int 41 int 40 int 39 int 38 int 37 int 36 int 35 int 34 int 33 int 32 w reset0000000000000000 figure 21-17. edma interrupt request high register (edma_a_irqrh) address: edma _x _base + 0x0024 access: user read/write 0123456789101112131415 r int 31 int 30 int 29 int 28 int 27 int 26 int 25 int 24 int 23 int 22 int 21 int 20 int 19 int 18 int 17 int 16 w reset0000000000000000 16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31 r int 15 int 14 int 13 int 12 int 11 int 10 int 09 int 08 int 07 int 06 int 05 int 04 int 03 int 02 int 01 int 00 w reset0000000000000000 figure 21-18. edma interrupt request register (edma _x _irqrl)
enhanced direct memory access controller (edma) freescale semiconductor 21-31 pxr40 microcontroller reference manual, rev. 1 21.3.2.14 edma error registers (edma_ x _erh, edma _x _erl) the edma_a_erh and edma _x _erl provides a bit map for the 32 channels signa ling the presence of an error for each channel. edma_a_erh supports channels 63?32 (for edma_a) and edma _x _erl maps to channels 31-0. the dma engine signals the occurren ce of a error condition by setting the appropriate bit in this register. the outputs of this register are enabled by the contents of the edma _x _eeir, then logically summed across across 32 (64 for edma_a) channels to form an error interrupt request, which is then routed to the interrupt controller. during the execution of the interr upt service routine associated with any edma errors, it is software?s responsibility to clear the appropriate bit, negating the error interrupt request. typically, a write to the edma _x _cer in the interrupt service routine is used for this purpose. the normal edma channel completion indicators , setting the transfer cont rol descriptor done flag and the possible assertion of an interrupt request, are not aff ected when an error is detected. the contents of this register can also be polled a nd a non-zero value indicates th e presence of a channel error, regardless of the state of the edma _x _eeir. the edma _x _esr[vld] bit is a logical or of all bits in this register and it provi des a single bit indication of any erro rs. the state of any given channel?s error indicators is affected by wr ites to this register; it is al so affected by writes to the edma _x _cer. on writes to edma_a_erh or edma _x _erl, a 1 in any bit position cl ears the corresponding channel?s error status. a 0 in any bit positi on has no effect on the corresponding channel?s current error status. the edma_ x _cer is provided so the error indica tor for a single channel can be cleared. table 21-16. edma _x _irqrl field descriptions field description 0?31 int n edma interrupt request n. 0 the interrupt request for channel n is cleared. 1 the interrupt request for channel n is active. address: edma_a_base + 0x0028 access: user r/w 0123456789101112131415 r err 63 err 62 err 61 err 60 err 59 err 58 err 57 err 56 err 55 err 54 err 53 err 52 err 51 err 50 err 49 err 48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err 47 err 46 err 45 err 44 err 43 err 42 err 41 err 40 err 39 err 38 err 37 err 36 err 35 err 34 err 33 err 32 w reset0000000000000000 figure 21-19. edma error high register (edma_a_erh)
enhanced direct memory access controller (edma) 21-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.3.2.15 dma hardware request status (edma_a_hrsh, edma _x _hrsl) the edma_a_hrsl and edma _x _hrsl registers provide a bit map map for the implemented channels (32 or 64) to show the current hardware request status fo r each channel. edma_a_hrsh maps to channels 64?32 and edma _x _hrsl maps to channels 31-00. figure 21-21. edma hardware request st atus register high (edma_a_hrsh) address: edma _x _base + 0x002c access: user read/write 0123456789101112131415 r err 31 err 30 err 29 err 28 err 27 err 26 err 25 err 24 err 23 err 22 err 21 err 20 err 19 err 18 err 17 err 16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err 15 err 14 err 13 err 12 err 11 err 10 err 09 err 08 err 07 err 06 err 05 err 04 err 03 err 02 err 01 err 00 w reset0000000000000000 figure 21-20. edma error register (edma _x _erl) table 21-17. edma _x _erl field descriptions field description 0?31 err n edma error n. 0 an error in channel n has not occurred. 1 an error in channel n has occurred. address: edma_a_base + 0x0030 access: user r/w 0123456789101112131415 r hrs 63 hrs 62 hrs 61 hrs 60 hrs 59 hrs 58 hrs 57 hrs 56 hrs 55 hrs 54 hrs 53 hrs 52 hrs 51 hrs 50 hrs 49 hrs 48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs 47 hrs 46 hrs 45 hrs 44 hrs 43 hrs 42 hrs 41 hrs 40 hrs 39 hrs 38 hrs 37 hrs 36 hrs 35 hrs 34 hrs 33 hrs 32 w reset0000000000000000
enhanced direct memory access controller (edma) freescale semiconductor 21-33 pxr40 microcontroller reference manual, rev. 1 figure 21-22. edma hardware request status register low (edma _x _hrsl) 21.3.2.16 edma global write registers (edma_ x _gwrh and edma_ x _gwrl) the edma_x_gwrh and edma_x_gwrl registers provide coherenc y controls to the cache coherency unit (ccu). the ed ma_x_gwrh and edma_x_gwrl regi sters provide a bit map to enable the ccu to snoop da ta writes from any enabled channel. when the global write enable (gwen) bit for a channel is set, the edma will signal th e ccu whenever that channel performs a write. the edma_x_gwrh and edma_x_gwrl registers perform no func tions within the edma. 21.3.2.17 edma channel n priority registers (edma _x _cpr n ) when the fixed-priority channel ar bitration mode is enabled (edma_ x _mcr[erca] = 0), the contents of these registers define the unique priorities associated with each channel. the channel priorities are evaluated by numeric value; th at is, 0 is the lowest priority, 1 is th e next higher priority, then 2, 3, etc. if software modifies channel priority va lues, then the software must ensure that the channel priorities contain unique values. otherwise, a configura tion error is reported. the range of th e priority value is limited to the values of 0 through 15. when read, the grppri bits of the edma_ x _cpr n register reflect the current priority level of the group of channels in which th e corresponding channel reside s. grppri bits are not affected by writes to the edma_ x _cpr n registers. the group priority is assigned in the edma_ x _mcr. see figure 21-2 and table 21-4 for the edma_ x _mcr definition. channel preemption is enabled on a per-channe l basis by setting the ecp bit in the edma _x _cpr n register. channel preemption allows the executing channel?s data transfer s to be temporarily suspended in favor of starting a higher priority channel. after the pr eempting channel has comp leted all its minor loop address: edma _x _base + 0x0034 access: user read/write 0123456789101112131415 r hrs 31 hrs 30 hrs 29 hrs 28 hrs 27 hrs 26 hrs 25 hrs 24 hrs 23 hrs 22 hrs 21 hrs 20 hrs 19 hrs 18 hrs 17 hrs 16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs 15 hrs 14 hrs 13 hrs 12 hrs 11 hrs 10 hrs 09 hrs 08 hrs 07 hrs 06 hrs 05 hrs 04 hrs 03 hrs 02 hrs 01 hrs 00 w reset0000000000000000 table 21-18. edma _x _hrsl field descriptions field description 0?31 hrs n dma hardware request status 0 a hardware service request for channel n is not present. 1 a hardware service request for channel n is present. note: the hardware request status reflec ts the state of the request as seen by the arbitration logic. therefore, this status is affected by the edma _x _erqrl[erq n ] bit.
enhanced direct memory access controller (edma) 21-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 data transfers, the preempted ch annel is restored and resumes ex ecution. after the restored channel completes one read/write se quence, it is again eligible for pree mption. if any higher priority channel requests service, the restored channel is suspended and the higher priority cha nnel is serviced. nested preemption (attempting to preempt a preempting channel) is not su pported. after a preempting channel begins execution, it cannot be preempt ed. preemption is available only when fixed arbitration is selected for both group and channel arbitration modes. a channel?s ability to pre-empt another channel can be disa bled by setting edma _x _cpr[dpa]. when a channel?s pre-empt ability is disabl ed, that channel cannot suspend a lowe r priority channel?s data transfer; regardless of the lower priority channel?s ecp settin g. this allows for a pool of low priority, large data moving channels to be defined. these low priority channels can be config ured to not preempt each other, thus preventing a low priority channel from consum ing the preempt slot norma lly available a true, high priority channel. 21.3.2.18 transfer control descriptor (tcd) each channel requires a 32-byte tr ansfer control descriptor for de fining the desired data movement operation. the channel de scriptors are stored in the local memory in sequential order: channel 0, channel address: edma _x _ base + 0x0100 + n access: user read/write 01234567 r ecp dpa grppri chpri w reset0000 ? 1 1 the reset value for the channel prio rity field, chpri [0?3], is equal to the corresponding channel number for each priority register; that is, edma _x _cpri0[chpri] = 0b0000 and edma _x _cpr15[chpri] = 0b1111. figure 21-23. edma channel n priority register (edma _x _cpr n ) table 21-19. edma_ x _cprn field descriptions field description 0 ecp enable channel preemption. 0 channel n cannot be suspended by a higher priority channel?s service request. 1 channel n can be temporarily suspended by the service request of a higher priority channel. 1 dpa disable preempt ability. 0 channel n can suspend a lower priority channel. 1 channel n cannot suspend any channel, regardless of channel priority. 2?3 grppri channel n current group priority. group priority assigned to this channel group when fixed-priority arbitration is enabled. these two bits are read-onl y; writes are ignored. the reset value for the group priority fields, is equal to the corresponding channel number for each priority register; that is, edma _x _cpr31[grppri] = 0b01. 4?7 chpri channel n arbitration priority. channel priority when fixe d-priority arbitration is enabled. the reset value for the channel priority fields chpri[0?3], is equal to the corresponding channel number for each priority register; that is, edma _x _cpr31[chpri] = 0b1111.
enhanced direct memory access controller (edma) freescale semiconductor 21-35 pxr40 microcontroller reference manual, rev. 1 1,... channel 31 (63 for edma_a). th e definitions of the tcd are pr esented as eight 32-bit values. table 21-20 is a field list of the basic tcd structure. figure 21-24 and table 21-21 define the fields of the tcd n structure. table 21-20. tcd n 32-bit memory structure edma offset tcd n field 0x1000+(32 x n )+0x0000 source address (saddr) 0x1000+(32 x n )+0x0004 transfer attributes signed source address offset (soff) 0x1000+(32 x n )+0x0008 inner minor byte count (nbytes) 0x1000+(32 x n )+0x000c last source address adjustment (slast) 0x1000+(32 x n )+0x0010 destination address (daddr) 0x1000+(32 x n )+0x0014 current major iteration count (cit er) signed destination address offset (doff) 0x1000 (32 x n ) 0x0018 last destination address adjustment / scatter-gather address (dlast_sga) 0x1000+(32 x n )+0x001c beginning major iteration count (biter) channel control/status word offset 012345678910111213141516171819202122232425262728293031 0x0000 saddr 0x0004 smod ssize dmod dsize soff 0x0008 nbytes 1 1 the fields implemented in word 2 depend on whether edma_ x _mcr(emlm) is set to 0 or 1. refer to table 21-4 . 0x0008 smloe 1 dmloe 1 mloff or nbytes 1 nbytes 1 0x000c slast 0x0010 daddr 0x0014 citer.e_ link citer or citer.linkch citer doff 0x0018 dlast_sga 0x001c biter.e_ link biter or biter.linkch biter bwc major linkch done active major.e_link e_sg d_req int_half int_maj start 012345678910111213141516171819202122232425262728293031 figure 21-24. tcd structure
enhanced direct memory access controller (edma) 21-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the tcd structures for the edma channels shown in figure 21-24 are implemented in internal sram. these stru ctures are not initialized at reset; therefore, all channel tcd parameters must be initialized by the application code before activating that channel. table 21-21. tcdn field descriptions field description 0?31 / 0x0 [0:31] saddr source address. memory address pointing to the source data. word 0x0, bits 0?31. 32?36 / 0x4 [0:4] smod source address modulo. 0 source address modulo feature is disabled. non-0 this value defines a specific address r ange that is specified to be the value after saddr + soff calculation is performed or the original register value. the setting of this field provides the ability to easily im plement a circular data queue. for data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the smod field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. the value programmed into this field specifies the number of lower address bits that are allowed to change. for this circular queue application, the soff is typically set to the transfer size to implement post-increment addressing with the smod function constraining the addresses to a 0-modulo-size range. 37?39 / 0x4 [5:7] ssize source data transfer size. 000 8-bit 001 16-bit 010 32-bit 011 64-bit 100 reserved 101 32-byte (64-bit, 4 beat, wrap4 burst) 110 reserved 111 reserved the attempted specification of a reserved encoding causes a configuration error. 40?44 / 0x4 [8:12] dmod destination address modulo. see the smod[0:5] definition. 45?47 / 0x4 [13:15] dsize destination data transfer size. see the ssize[0:2] definition. 48?63 / 0x4 [16:31] soff source address signed offset. sign-extended offset applied to the current source address to form the next-state value as each source read is completed. 64 0x8 [0] smloe 1 source minor loop offset enable this flag selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 the minor loop offset is not applied to the saddr. 1 the minor loop offset is applied to the saddr.
enhanced direct memory access controller (edma) freescale semiconductor 21-37 pxr40 microcontroller reference manual, rev. 1 65 0x8 [1] dmloe 1 destination minor loop offset enable this flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 the minor loop offset is not applied to the daddr. 1 the minor loop offset is applied to the daddr. 66?85 0x8 [2-21] mloff or nbytes 1 inner ?minor? byte transfer count or minor loop offset if both smloe and dmloe are cleared, this field is part of the byte transfer count. if either smloe or dmloe are set, this field r epresents a sign-extended offset applied to the source or destination address to form the next -state value after the minor loop is completed. 86?95 / 0x8 [22:31] nbytes 1 inner ?minor? byte transfer count. number of bytes to be transferred in each service request of the channel. as a channel is activated, the contents of the appropriate tcd is loaded into the edma engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. this is an in divisible operation and cannot be stalled or halted. once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major it eration count is decrem ented and restored to the local memory. if the major iteration count is completed, additional processing is performed. note: the nbytes value of 0x0000_0000 is interp reted as 0x1_0000_0000, thus specifying a 4 gb transfer. 96?127 / 0xc [0:31] slast last source address adjustment. adjustment value added to the source address at the completion of the outer major iteration count. this value can be applied to ?restore? the source address to the initial value, or adjust the address to reference t he next data structure. 128?159 / 0x10 [0:31] daddr destination address. memory address pointing to the destination data. 160 / 0x14 [0] citer.e_link enable channel-to-channel linking on minor loop completion. as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by citer.linkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the edma _x _tcd.start bit of the specified channel. if channel linking is disabled, the citer value is extended to 15 bits in place of a link channel number. if the major loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. note: this bit must be equal to the biter.e_link bit. otherwise, a configuration error is reported. 161?166 / 0x14 [1:6] citer or citer.linkch current major iteration count or link channel number. if channel-to-channel linking is disabled (edma _x _tcd.citer.e_link = 0), then ? no channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. tcd bits [161:175] are us ed to form a 15-bit citer field. otherwise, ? after the minor loop is exhausted, the dma engine initiates a channel service request at the channel defined by citer.linkch[0:5] by setting that channel?s edma _x _tcd.start bit. table 21-21. tcdn field descriptions (continued) field description
enhanced direct memory access controller (edma) 21-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 167?175 / 0x14 [7:15] citer current major iteration count. this 9 or 15-bit count represents the current major loop count for the channel. it is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. after the ma jor iteration count is exhausted, the channel performs a number of operations (for example, final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the citer field from the beginning iteration count (biter) field. note: when the citer field is initially loaded by software, it must be set to the same value as that contained in the biter field. note: if the channel is configured to execute a si ngle service request, the initial values of biter and citer should be 0x0001. 176?191 / 0x14 [16:31] doff destination address signed offset. sign-extende d offset applied to th e current destination address to form the next-state value as each destination write is completed. 192?223 / 0x18 [0:31] dlast_sga last destination address adjustment or the me mory address for the next transfer control descriptor to be loaded into this channel (scatter-gather). if scatter-gather processing for the channel is disabled (edma _x _tcd.e_sg = 0) then ? adjustment value added to the destination address at the completion of the outer major iteration count. this value can be applied to restore the destinat ion address to the initial value, or adjust the address to reference t he next data structure. otherwise, ? this address points to the beginning of a 0-modulo-32 byte region containing the next transfer control descriptor to be loaded into this channel. this channel reload is performed as the major iteration count completes. the scatter-gather address must be 0-modulo-32 byte, otherwise a configuration error is reported. 224 / 0x1c [0] biter.e_link enables channel-to-channel linking on minor loop complete. as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by biter.linkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the edma _x _tcd.start bit of the specified channel. if channel linking is disabled, the biter value is extended to 15 bits in place of a link channel number. if the major loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. note: when the tcd is first loaded by software, this field must be set equal to the corresponding citer field. otherwise, a conf iguration error is reported. as the major iteration count is exhausted, the contents of this field is reloaded into the citer field. 225?230 / 0x1c [1:6] biter or biter.linkch starting major iteration count or link channel number. if channel-to-channel linking is disabled (edma _x _tcd.biter.e_link = 0), then ? no channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. tcd bits [225:239] are us ed to form a 15-bit biter field. otherwise, ? after the minor loop is exhausted, the dma engine initiates a channel service request at the channel, defined by biter.linkch[ 0:5], by setting that channel?s edma _x _tcd.start bit. note: when the tcd is first loaded by software, this field must be set equal to the corresponding citer field. otherwise, a conf iguration error is reported. as the major iteration count is exhausted, the contents of this field is reloaded into the citer field. table 21-21. tcdn field descriptions (continued) field description
enhanced direct memory access controller (edma) freescale semiconductor 21-39 pxr40 microcontroller reference manual, rev. 1 231?239 / 0x1c [7:15] biter starting major iteration count. as the transfer control descriptor is first loaded by software, this field must be equal to the value in the citer fiel d. as the major iteration count is exhausted, the contents of this field are reloaded into the citer field. note: if the channel is configured to execute a si ngle service request, the initial values of biter and citer should be 0x0001. 240?241 / 0x1c [16:17] bwc bandwidth control. this two-bit field provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the edma. in general, as the edma processes the inner minor loop, it continuously generates read/write sequenc es until the minor count is exhausted. this field forces the edma to stall after the completi on of each read/write access to control the bus request bandwidth seen by the system bus crossbar switch (xbar). 00 no dma engine stalls 01 reserved 10 dma engine stalls for 4 cycles after each r/w 11 dma engine stalls for 8 cycles after each r/w 242?247 / 0x1c [18:23] major.linkch link channel number. if channel-to-channel linking on major loop complete is disabled (edma _x _tcd.major.e_link = 0) then, ? no channel-to-channel linking (or chaining) is performed after the outer major loop counter is exhausted. otherwise ? after the major loop counter is exhausted, the dma engine initiates a channel service request at the channel defined by major. linkch[0:5] by setti ng that channel?s edma _x _tcd.start bit. 248 / 0x1c [24] done channel done. this flag indicates the edma has completed the outer major loop. it is set by the dma engine as the citer coun t reaches zero; it is cleared by software or hardware when the channel is activated (when the dma engine has begun processing the channel, not when the first data transfer occurs). note: this bit must be cleared to writ e the major.e_link or e_sg bits. 249 / 0x1c [25] active channel active. this flag signals the channel is currently in execution. it is set when channel service begins, and is cleared by the dma engine as the inner minor loop completes or if any error condition is detected. 250 / 0x1c [26] major.e_link enable channel-to-channel linking on major loop completion. as the channel completes the outer major loop, this flag enables the linking to another channel, defined by major.linkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the edma _x _tcd.start bit of the specified channel. note: to support the dynamic linking coherency mode l, this field is fo rced to zero when written to while the edma _x _tcd.done bit is set. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. 251 / 0x1c [27] e_sg enable scatter-gather processing. as the channel completes the outer major loop, this flag enables scatter-gather processing in the current channel. if enabled, the dma engine uses dlast_sga as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control descriptor into the local memory. note: to support the dynamic scatter-gather coher ency model, this field is forced to zero when written to while the edma _x _tcd.done bit is set. 0 the current channel?s tcd is normal format. 1 the current channel?s tcd specifies a sca tter gather format. the dlast_sga field provides a memory pointer to the next tcd to be loaded into this channel after the outer major loop completes its execution. table 21-21. tcdn field descriptions (continued) field description
enhanced direct memory access controller (edma) 21-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.4 functional description this section provides an overview of the microarchitectur e and functional operati on of the edma block. the edma module is partitioned into two major mo dules: the dma engine and the transfer control descriptor local memory. the dma e ngine is further partitioned into four submodules, which are detailed below. ? dma engine ? address path: this module implements registered versions of two cha nnel transfer control descriptors: channel x and channel y, and is responsible for all the master bus address calculations. all the implemente d channels provide the same functionality. this hardware structure allows the data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel service request is asserted while the first channel is active. after a channel is activated, it runs until the minor loop is completed unless preempted by a higher prio rity channel. this capability provides a mechanism (optionally enabled by edma _x _cpr n [ecp]) where a large data move operation can be preempted to minimize the time a nother channel is bloc ked from execution. ? when another channel is activated, the contents of its transfer control de scriptor is read from the local memory and loaded into the register s of the other address path channel{x,y}. after the inner minor loop completes ex ecution, the address path hardware writes the new values for 252 / 0x1c [28] d_req disable hardware request. if this flag is set, the edma hardware automatically clears the corresponding edma_a_erqh or edma _x _erql bit when the current major iteration count reaches zero. 0 the channel?s edma_a_erqh or edma _x _erql bit is not affected. 1 the channel?s edma_a_erqh or edma _x _erql bit is cleared when the outer major loop is complete. 253 / 0x1c [29] int_half enable an interrupt when major counter is hal f complete. if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the edma_a_erqh or edma _x _erql when the current major iterat ion count reaches the halfway point. specifically, the comparison performed by the ed ma engine is (citer == (biter >> 1)). this halfway point interrupt request is provided to support double-buffered (aka ping-pong) schemes, or other types of data movement wher e the processor needs an early indication of the transfer?s progress. cite r = biter = 1 with int_half enabled will generate an interrupt as it satisfies the equation (citer == (biter >> 1)) after a single activation. 0 the half-point interrupt is disabled. 1 the half-point interrupt is enabled. 254 / 0x1c [30] int_maj enable an interrupt when major iteration count completes. if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the edma_a_erqh or edma _x _erql when the current major iteration count reaches zero. 0 the end-of-major loop interrupt is disabled. 1 the end-of-major loop interrupt is enabled. 255 / 0x1c [31] start channel start. if this flag is set the channel is requesting service. the edma hardware automatically clears this flag after the channel begins execution. 0 the channel is not explicitly started. 1 the channel is explicitly started via a software initiated service request. table 21-21. tcdn field descriptions (continued) field description
enhanced direct memory access controller (edma) freescale semiconductor 21-41 pxr40 microcontroller reference manual, rev. 1 the tcd n .{saddr, daddr, citer} back into the lo cal memory. if the major iteration count is exhausted, additional processing is performed, includi ng the final address pointer updates, reloading the tcdn .citer field, and a possibl e fetch of the next tcd n from memory as part of a scatter-gather operation. ? data path: this module implements the actual bu s master read/write da tapath. it includes 32 bytes of register storage (match ing the maximum transfer size) and the necessary mux logic to support any required data alignment. the system read data bus is the primary input, and the system write data bus is the primary output. ? the address and data path m odules directly support the two-st age pipelined system bus. the address path module represents th e 1st stage of the bus pipeline (the address phase), while the data path module implements the second st age of the pipeline (the data phase). ? program model/channel ar bitration: this module implements the first section of edma?s programming model and also the channel arbitr ation logic. the programming model registers are connected to the slave bus (not shown). the edma peripheral re quest inputs and edma interrupt request outputs are also connected to this module (via the control logic). ? control: this module provides all the control f unctions for the dma engi ne. for data transfers where the source and destination sizes are equal, the dma engine performs a series of source read, destination write operations until the number of bytes speci fied in the inner minor loop byte count has been moved. a minor loop interaction is defined as the number of bytes to transfer ( n bytes) divided by the transfer size. transfer size is defined as: if (ssize < dsize) transfer size = destination tr ansfer size (# of bytes) else transfer size = source transfer size (# of bytes) minor loop tcd variables are soff, smod , doff, dmod, nbytes, saddr, daddr, bwc, active, and start. major loop tc d variables are dlast, slast, citer, biter, done, d_req, int_maj, major_lnkch, and int_half. for descriptors where the sizes are not equal, multiple access of the smaller size data are required for each reference of the larger size. fo r example, if the source size references 16-bit data and the destination is 32-bit data, tw o reads are performed, then one 32-bit write. ? tcd local memory ? memory controller: this logi c implements the required dual-ported controller, handling accesses from both the dma engine as well as re ferences from the slave bus. as noted earlier, in the event of simultaneous accesses, the dma engine is given priority and the slave transaction is stalled. ? memory array: the tcd is implemented us ing a single-ported, sy nchronous compiled ram memory array.
enhanced direct memory access controller (edma) 21-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.4.1 edma basic data flow the edma transfers data based on a two-deep, nested flow. the basic fl ow of a data transfer can be partitioned into three segments. as shown in figure 21-25 , the first segment involves the channel service request. in the diagram, this example uses the assert ion of the edma peripheral request signal to request service for channel n . channel service request vi a software and the tcdn.start bit follows the same basic flow as an edma peripheral request. the edma peripheral request input signal is registered internally and then routed through the dma engine , first through the control module, then into the program model/channel arbitr ation module. in the next cycle, the channel arbitration is performed using the fixed-priority or round-robin algo rithm. after the arbitrat ion is complete, the activated channel number is sent through the address path a nd converted into the required addres s to access the tcd local memory. next, the tcd memory is accessed and the required de scriptor read from the local memory and loaded into the dma engine address path channel {x,y} registers. the tcd memo ry is organized 64-bits in width to minimize the time needed to fe tch the activated channel? s descriptor and load it into the edma engine address path channel {x,y} registers. figure 21-25. edma operation, part 1 in the second part of the basic data flow as shown in figure 21-26 , the modules associated with the data transfer (address path, da ta path, and control) sequence through th e required source reads and destination writes to perform the actual data movement. the source reads are in itiated and the fetched data is slave interface edma edma peripheral request system bus data path control address program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1* edma interrupt request bus read data channel arbitration edma done handshake path sram transfer control descriptor ( tcd ) sram * n = 32 (64 for edma_a) channels
enhanced direct memory access controller (edma) freescale semiconductor 21-43 pxr40 microcontroller reference manual, rev. 1 temporarily stored in the da ta path module until it is gated onto the system bus during the destination write. this source read/destination write processing cont inues until the inner mi nor byte count has been transferred. the edma done handshake signal is asserted at the end of the minor byte count transfer. figure 21-26. edma operation, part 2 after the inner minor byte count has been moved, the fi nal phase of the basic data flow is performed. in this segment, the address path logic performs the requ ired updates to certain fiel ds in the channel?s tcd; for example, saddr, daddr, citer. if the outer major iteration count is exhausted, then there are additional operations performed. thes e include the final address adjust ments and reloading of the biter field into the citer. additiona lly, assertion of an optional interrupt request occurs at th is time, as does a possible fetch of a new tcd from memory using the scatter-gather address pointer included in the descriptor. the updates to the tcd memory and the assertion of an interrupt request are shown in figure 21-27 . slave interface edma edma interrupt request system bus program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n? 1* edma peripheral bus read data channel arbitration request sram transfer control descriptor (tcd) sram data path control address path edma done handshake * n = 32 (64 for edma_a) channels
enhanced direct memory access controller (edma) 21-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 21-27. edma operation, part 3 21.5 initialization / application information 21.5.1 edma initialization a typical initialization of the edma has the following sequence: 1. write the edma_ x _mcr if a configuration other than the default is desired. 2. write the channel priority levels into the edma _x _cpr n registers if a conf iguration other than the default is desired. 3. enable error interrupts in the edma _x _eeirl and/or edma _x _eeirh registers if desired. 4. write the 32-byte tcd for each ch annel that may request service. 5. enable any hardware service requests via the edma _x _erqrh and/or edma _x _erqrl registers. 6. request channel service by software (setting the edma _x _tcd.start bit) or by hardware (slave device asserting its dm a peripheral request signal). slave interface edma edma done system bus slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n? 1* edma peripheral bus read data request sram transfer control descriptor (tcd) sram data path address path control program model/ channel arbitration * n = 32 (64 for edma_a) channels
enhanced direct memory access controller (edma) freescale semiconductor 21-45 pxr40 microcontroller reference manual, rev. 1 after any channel requests service, a channel is select ed for execution based on th e arbitration and priority levels written into the programmer' s model. the dma engine reads the entire tcd, including the primary transfer control parameter shown in table 21-22 , for the selected channel into its internal address path module. as the tcd is being read, th e first transfer is initiated on th e system bus unle ss a configuration error is detected. transfers from the sour ce (as defined by the source address, edma _x _tcd.saddr) to the destination (as defined by the destination address, edma _x _tcd.daddr) continue until the specified number of bytes (edma _x _tcd.nbytes) have been transfer red. when the transfer is complete, the dma engine's local edma _x _tcd.saddr, edma _x _tcd.daddr, and edma _x _tcd.citer are written back to the main tcd memory and a ny minor loop channel linking is performed, if enabled. if the major loop is exhauste d, further post processing is executed; for example, interrupts, major loop channel linking, and scatter-gather opera tions, if enabled. figure 21-28 shows how each dma request initiates one minor loop transf er (iteration) without cpu intervention. dma arbitration can occur after e ach minor loop, and one level of minor loop dma preemption is allowed. the number of minor loops in a major loop is specified by the beginning iteration count (biter). table 21-22. tcd primary control and status fields tcd field name description start control bit to start channel when using a software initiated dma service (automatically cleared by hardware) active status bit indicating the channel is currently in execution done status bit indicating major loop completion (cleared by software when using a software initiated dma service) d_req control bit to disable dma request at end of major loop completion when using a hardware-initiated dma service bwc control bits for throttling bandwidth control of a channel e_sg control bit to enable scatter-gather feature int_half control bit to enable interrupt when major loop is half complete int_maj control bit to enable interrupt when major loop completes
enhanced direct memory access controller (edma) 21-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 21-28. example of multiple loop iterations figure 21-29 lists the memory array terms and how the tcd settings interrelate. figure 21-29. memory array terms dma request minor loop 3 current major loop iteration count (citer) example memory array ? ? ? dma request minor loop 2 ? ? ? dma request minor loop 1 ? ? ? major loop xaddr: (starting address) xsize: (size of one data minor loop (nbytes in minor loop, often the same value as xsize) offset (xoff): number of bytes added to current address after each transfer (often the same value as xsize) ? minor loop each dma source (s) and destination (d) has its own: ? address (xaddr) ? size (xsize) ? offset (xoff) xlast: number of bytes added to current address peripheral queues typically have size and offset equal to nbytes ? ? after major loop (typically used to loop back) transfer) ? ? ? ? ? ? last minor loop ? modulo (xmod) ? last address adjustment (xlast) where x = s or d ? ? ?
enhanced direct memory access controller (edma) freescale semiconductor 21-47 pxr40 microcontroller reference manual, rev. 1 21.5.2 dma programming errors the dma performs various tests on the transfer control descriptor to veri fy consistency in the descriptor data. most programming errors are reported on a per-channel basis w ith the exception of two errors: group-priority error and channe l-priority error, or edma _x _esr[gpe] and edma _x _esr[cpe], respectively. for all error types other than group- or channel-priority errors, the channel number causing the error is recorded in the edma _x _esr. if the error source is not removed be fore the next activation of the problem channel, the error is detected and recorded again. channel-priority errors are identif ied within a group after that group ha s been selected as the active group. for the example, all of the channel priorities in group 1 are unique, but so me of the channel priorities in group 0 are the same: 1. the dma is configured for fixed-gr oup and fixed-channel arbitration modes. 2. group 1 is the highest priority and all channels are unique in that group. 3. group 0 is the next highest priority and has two channels with the same priority level. 4. if group 1 has any service reque sts, those requests are executed. 5. after all of group 1 requests have comp leted, group 0 becomes the next active group. 6. if group 0 has a service request, then an unde fined channel in group 0 is selected and a channel-priority error will occur. 7. this repeats until the all of group 0 requests have been removed or a higher priority group 1 request comes in. in this sequence, for item 2, the dma acknowledge lines asse rt only if the selected channel is requesting service via the dma peripheral request signal. if inte rrupts are enabled for all ch annels, the user receives an error interrupt, but the channel number for the edma _x _er and the error interrupt request line are undetermined because they reflect th e undefined channel. a group-priority error is global and any request in any group causes a group-priority error. if priority levels are not unique, the highest (channel/group) priority th at has an active re quest is selected, but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the dma engine. the hardware service request handshake signals, error interrupts, and error reporting are associated with the selected channel.
enhanced direct memory access controller (edma) 21-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.5.3 dma request assignments the assignments between the dma requests from the modules to the channels of the two edmas are shown in table 21-24 and table 21-24 . the source column is written in c language s yntax. the syntax is module_instance.register[bit]. table 21-23. dma request summary for edma_a dma request channel source description eqadc_a_fisr0_cfff0 0 eqadc_a.fisr0[cf ff0] eqadc_a command fifo 0 fill flag eqadc_a_fisr0_rfdf0 1 eqadc_a.fisr0[rfdf 0] eqadc_a receive fifo 0 drain flag eqadc_a_fisr1_cfff1 2 eqadc_a.fisr1[cf ff1] eqadc_a command fifo 1 fill flag eqadc_a_fisr1_rfdf1 3 eqadc_a.fisr1[rfdf 1] eqadc_a receive fifo 1 drain flag eqadc_a_fisr2_cfff2 4 eqadc_a.fisr2[cf ff2] eqadc_a command fifo 2 fill flag eqadc_a_fisr2_rfdf2 5 eqadc_a.fisr2[rfdf 2] eqadc_a receive fifo 2 drain flag eqadc_a_fisr3_cfff3 6 eqadc_a.fisr3[cf ff3] eqadc_a command fifo 3 fill flag eqadc_a_fisr3_rfdf3 7 eqadc_a.fisr3[rfdf 3] eqadc_a receive fifo 3 drain flag eqadc_a_fisr4_cfff4 8 eqadc_a.fisr4[cf ff4] eqadc_a command fifo 4 fill flag eqadc_a_fisr4_rfdf4 9 eqadc_a.fisr4[rfdf 4] eqadc_a receive fifo 4 drain flag eqadc_a_fisr5_cfff5 10 eqadc_a.fisr5[cf ff5] eqadc_a command fifo 5 fill flag eqadc_a_fisr5_rfdf5 11 eqadc_a.fisr5[rfdf 5] eqadc_a receive fifo 5 drain flag dspib_sr_tfff 12 dspib.sr[tfff] d spib transmit fifo fill flag dspib_sr_rfdf 13 dspib.sr[rfdf] dspib receive fifo drain flag dspic_sr_tfff 14 dspic.sr[tfff] d spic transmit fifo fill flag dspic_sr_rfdf 15 dspic.sr[rfdf] d spic receive fifo drain flag dspid_sr_tfff 16 dspid.sr[tfff] d spid transmit fifo fill flag dspid_sr_rfdf 17 dspid.sr[rfdf] d spid receive fifo drain flag escia_combtx 18 escia.sr[tdre] || escia.sr[tc] || escia.sr[txrdy] escia combined dma request of the transmit data register empty, transmit complete, and lin transmit data ready dma requests escia_combrx 19 escia.sr[rdrf] || escia.sr[rxrdy] escia combined dma request of the receive data register full and lin receive data ready dma requests emios_gfr_f0 20 emios.gfr[f0] emios channel 0 flag emios_gfr_f1 21 emios.gfr[f1] emios channel 1 flag emios_gfr_f2 22 emios.gfr[f2] emios channel 2 flag emios_gfr_f3 23 emios.gfr[f3] emios channel 3 flag emios_gfr_f4 24 emios.gfr[f4] emios channel 4 flag
enhanced direct memory access controller (edma) freescale semiconductor 21-49 pxr40 microcontroller reference manual, rev. 1 emios_gfr_f8 25 emios.gfr[f8] emios channel 8 flag emios_gfr_f9 26 emios.gfr[f9] emios channel 9 flag etpu_cdtrsr_a_dtrs0 27 etpu.cdtrsr_a[dtrs0] etpua channel 0 data transfer request status etpu_cdtrsr_a_dtrs1 28 etpu.cdtrsr_a[dtrs1] etpua channel 1 data transfer request status etpu_cdtrsr_a_dtrs2 29 etpu.cdtrsr_a[dtrs2] etpua channel 2 data transfer request status etpu_cdtrsr_a_dtrs14 30 etpu.cdtrsr_a[dtrs14] etp ua channel 14 data transfer request status etpu_cdtrsr_a_dtrs15 31 etpu.cdtrsr_a[dtrs15] etp ua channel 15 data transfer request status dspia_sr_tfff 32 dspiaisr[tfff] d spia transmit fifo fill flag dspia_sr_rfdf 33 dspia.sr[rfdf] d spia receive fifo drain flag escib_combtx 34 escib.sr[tdre] || escib.sr[tc] || escib.sr[txrdy] escib combined dma request of the transmit data register empty, transmit complete, and lin transmit data ready dma requests escib_combrx 35 escib.sr[rdrf] || escib.sr[rxrdy] escib combined dma request of the receive data register full and lin receive data ready dma requests emios_gfr_f6 36 emios.gfr[f6] emios channel 6 flag emios_gfr_f7 37 emios.gfr[f7] emios channel 7 flag emios_gfr_f10 38 emios.gfr[f10] emios channel 10 flag emios_gfr_f11 39 emios.gfr[f11] emios channel 11 flag emios_gfr_f16 40 emios.gfr[f16] emios channel 16 flag emios_gfr_f17 41 emios.gfr[f17] emios channel 17 flag emios_gfr_f18 42 emios.gfr[f18] emios channel 18 flag emios_gfr_f19 43 emios.gfr[f19] emios channel 19 flag etpu_cdtrsr_a_dtrs12 44 etpu.cdtrsr_a[dtrs12] etp ua channel 12 data transfer request status etpu_cdtrsr_a_dtrs13 45 etpu.cdtrsr_a[dtrs13] etp ua channel 13 data transfer request status etpu_cdtrsr_a_dtrs28 46 etpu.cdtrsr_a[dtrs28] etp ua channel 28 data transfer request status etpu_cdtrsr_a_dtrs29 47 etpu.cdtrsr_a[dtrs29] etp ua channel 29 data transfer request status siu_eisr_eif0 48 siu.siu_eisr[eif0] siu external interrupt flag 0 siu_eisr_eif1 49 siu.siu_eisr[eif1] siu external interrupt flag 1 siu_eisr_eif2 50 siu.siu_eisr[eif2] siu external interrupt flag 2 siu_eisr_eif3 51 siu.siu_eisr[eif3] siu external interrupt flag 3 etpu_cdtrsr_b_dtrs0 52 etpu.cdtrsr_b[dtrs0] etpub channel 0 data transfer request status etpu_cdtrsr_b_dtrs1 53 etpu.cdtrsr_b[dtrs1] etpub channel 1 data transfer request status etpu_cdtrsr_b_dtrs2 54 etpu.cdtrsr_b[dtrs2] etpub channel 2 data transfer request status table 21-23. dma request summary for edma_a (continued) dma request channel source description
enhanced direct memory access controller (edma) 21-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 etpu_cdtrsr_b_dtrs3 55 etpu.cdtrsr_b[dtrs3] etpub channel 3 data transfer request status etpu_cdtrsr_b_dtrs12 56 etpu.cdtrsr_b[dtrs12] etp ub channel 12 data transfer request status etpu_cdtrsr_b_dtrs13 57 etpu.cdtrsr_b[dtrs13] etp ub channel 13 data transfer request status etpu_cdtrsr_b_dtrs14 58 etpu.cdtrsr_b[dtrs14] etp ub channel 14 data transfer request status etpu_cdtrsr_b_dtrs15 59 etpu.cdtrsr_b[dtrs15] etp ub channel 15 data transfer request status etpu_cdtrsr_b_dtrs28 60 etpu.cdtrsr_b[dtrs28] etp ub channel 28 data transfer request status etpu_cdtrsr_b_dtrs29 61 etpu.cdtrsr_b[dtrs29] etp ub channel 29 data transfer request status etpu_cdtrsr_b_dtrs30 62 etpu.cdtrsr_b[dtrs30] etp ub channel 30 data transfer request status etpu_cdtrsr_b_dtrs31 63 etpu.cdtrsr_b[dtrs31] etp ub channel 31 data transfer request status table 21-24. dma request summary for edma_b dma request channel source description eqadc_b_fisr0_cfff0 0 eqadc_ b.fisr0[cfff0] eqadc_b command fifo 0 fill flag eqadc_b_fisr0_rf df0 1 eqadc_b.fisr0[rfdf0] eqadc_b receive fifo 0 drain flag eqadc_b_fisr1_cfff1 2 eqadc_ b.fisr1[cfff1] eqadc_b command fifo 1 fill flag eqadc_b_fisr1_rf df1 3 eqadc_b.fisr1[rfdf1] eqadc_b receive fifo 1 drain flag eqadc_b_fisr2_cfff2 4 eqadc_ b.fisr2[cfff2] eqadc_b command fifo 2 fill flag eqadc_b_fisr2_rf df2 5 eqadc_b.fisr2[rfdf2] eqadc_b receive fifo 2 drain flag eqadc_b_fisr3_cfff3 6 eqadc_ b.fisr3[cfff3] eqadc_b command fifo 3 fill flag eqadc_b_fisr3_rf df3 7 eqadc_b.fisr3[rfdf3] eqadc_b receive fifo 3 drain flag eqadc_b_fisr4_cfff4 8 eqadc_ b.fisr4[cfff4] eqadc_b command fifo 4 fill flag eqadc_b_fisr4_rf df3 9 eqadc_b.fisr4[rfdf4] eqadc_b receive fifo 4 drain flag eqadc_b_fisr5_cfff5 10 eqa dc_b.fisr5[cfff5] eqadc_b command fifo 5 fill flag eqadc_b_fisr5_rfdf5 11 eqadc_b.fisr5[rfdf5] eqadc_b receive fifo 5 drain flag decfiltera_ib 12 decfiltera.ib decimati on filter a input buffer fill flag decfiltera_ob 13 decfiltera.ob decimation filter a output buffer drain flag decfilterb_ib 14 decfilterb.ib decimati on filter b input buffer fill flag decfilterb_ob 15 decfilterb.ob decimation filter b output buffer drain flag decfilterc_ib 16 decfilterc.ib decimati on filter cinput buffer fill flag decfilterc_ob 17 decfilterc.ob decimation filter c output buffer drain flag decfilterd_ib 18 decfilterd.ib decimati on filter d input buffer fill flag decfilterd_ob 19 decfilterd.ob decimation filter d output buffer drain flag decfiltere_ib 20 decfiltere.ib decimati on filter e input buffer fill flag table 21-23. dma request summary for edma_a (continued) dma request channel source description
enhanced direct memory access controller (edma) freescale semiconductor 21-51 pxr40 microcontroller reference manual, rev. 1 decfiltere_ob 21 decfiltere.ob decimation filter e output buffer drain flag decfilterf_ib 22 decfilterf.ib decimati on filter f input buffer fill flag decfilterf_ob 23 decfilterf.ob decimation filter f output buffer drain flag decfilterg_ib 24 decfilterg.ib decimati on filter g input buffer fill flag decfilterg_ob 25 decfilterg.ob decimation filter g output buffer drain flag decfilterh_ib 26 decfilterh.ib decimati on filter h input buffer fill flag decfilterh_ob 27 decfilterh.ob decimation filter h output buffer drain flag no request 28?31 ? ? table 21-24. dma request summary for edma_b (continued) dma request channel source description
enhanced direct memory access controller (edma) 21-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 21.5.4 dma arbitration mode considerations 21.5.4.1 fixed-group arbitration, fixed-channel arbitration in this mode, the channel service re quest from the highest pr iority channel in the hi ghest priority group is selected to execute. if the edma is programmed so the channels within one group use fixe d priorities, and that group is assigned the highest fixe d priority of all groups, it is possi ble for that group to take all the bandwidth of the edma controller. th at is, no other groups can be serviced if there is always at least one dma request pending on a channel in the highest priori ty group when the controller arbitrates the next dma request. the advantage of this sc enario is that latency can be sma ll for channels that need to be serviced quickly. preem ption is available in this scenario only. 21.5.4.2 round-robin group arbitration, fixed-channel arbitration when one or more dma requests arri ve from one or more groups, the channel with the highest priority from a specific group is serv iced first. groups are serviced starting with the highest group number with a service request and rotating through to the lo west group number contai ning a service request. after the channel request is serv iced, the group round robi n algorithm selects the highest pending request from the next group in the round-robin sequence. se rvicing continues round robi n, always servicing the highest priority channel in the ne xt group in the sequence, or skippi ng a group if it ha s no pending requests. if a channel requests service at a ra te that equals or exceeds the round ro bin service rate, then that channel is always serviced before lower priority channels in the same group, and the lo wer priority channels are never serviced. the advantage of th is scenario is that no one group can consume all the edma bandwidth. the highest priority channel selecti on latency is potentially greater than fixed/fixed arbi tration. excessive request rates on high-priority channels can prevent the servicing of lower priority channels in the same group. 21.5.4.3 round-robin group arbitration, round-robin channel arbitration groups are serviced as described in section 21.5.4.2, round-robin group ar bitration, fixed-channel arbitration, but this time channels are serviced in channe l number order. one channe l only is serviced from each requesting group for each r ound robin pass through the groups. within each group, channels are serv iced starting with the highest ch annel number and rotating through to the lowest channel number without re gard to channel priority levels. because channels are serviced in round-robin manner, any channel that generates dma requests faster than a combination of the group round-robin service ra te and the channel servi ce rate for its group does not prevent the servicing of other ch annels in its group. any dma requests that are not serviced are simply lost, but at least one channel gets serviced. this scenario ensures that all channe ls are guaranteed service at some poi nt, regardless of the request rates. however, the potential latency could be high. all channels are treated equally. priority levels are not used in round-robin/round-robin mode.
enhanced direct memory access controller (edma) freescale semiconductor 21-53 pxr40 microcontroller reference manual, rev. 1 21.5.4.4 fixed-group arbitration, round-robin channel arbitration the highest priority group with a re quest is serviced. lower priority groups are serviced if no pending requests exist in the higher priority groups. within each group, channels are serv iced starting with the highest ch annel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. this scenario could cause the same bandwid th consumption problem as indicated in section 21.5.4.1, fixed-group arbitration, fi xed-channel arbitration, but all the channels in th e highest priority group get serviced. service latency is short on the highest prio rity group, but coul d potentially get longer and longer as the group priority decreases. 21.5.5 dma transfer 21.5.5.1 single request to perform a simple transfer of n bytes of data with one activation, set the major loop to 1 (edma _x _tcd.citer = edma _x _tcd.biter = 1). the data transfer begins after the channel service request is acknowledged and the channe l is selected to execute. afte r the transfer is complete, the edma _x _tcd.done bit is set and an interrupt is generated if properly enabled. for example, the following tcd entry is configured to transfer 16 bytes of data. the edma is programmed for one iterati on of the major loop transferring 16 byt es per iteration. the source memory has a byte wide memory port located at 0x1000. the dest ination memory has a word wide port located at 0x2000. the address offsets ar e programmed in increments to match the size of the transfer; one byte for the source and four bytes for the de stination. the final source and destin ation addresses are adjusted to return to their beginning values. edma _x _tcd.citer = edma _x _tcd.biter = 1 edma _x _tcd.nbytes = 16 edma _x _tcd.saddr = 0x1000 edma _x _tcd.soff = 1 edma _x _tcd.ssize = 0 edma _x _tcd.slast = ?16 edma _x _tcd.daddr = 0x2000 edma _x _tcd.doff = 4 edma _x _tcd.dsize = 2 edma _x _tcd.dlast_sga = ?16 edma _x _tcd.int_maj = 1 edma _x _tcd.start = 1 (must be written last after all other fields have been initialized) all other tcd fields = 0 this would generate the fo llowing sequence of events: 1. slave write to the edma _x _tcd.start bit requests channel service.
enhanced direct memory access controller (edma) 21-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 2. the channel is selected by arbitration for servicing. 3. edma engine writes: edma _x _tcd.done = 0, edma _x _tcd.start = 0, edma _x _tcd.active = 1. 4. edma engine reads: channel tcd data from local memory to internal register file. 5. the source to destination transfers are executed as follows: a) read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b) write_word(0x2000) ? first iteration of the minor loop c) read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d) write_word(0x2004) ? second iteration of the minor loop e) read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f) write_word(0x2008) ? third iteration of the minor loop g) read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h) write_word(0x200c) ? last iteration of the minor loop ? major loop complete 6. edma engine writes: edma _x _tcd.saddr = 0x1000, edma _x _tcd.daddr = 0x2000, edma _x _tcd.citer = 1 (edma _x _tcd.biter). 7. edma engine writes: edma _x _tcd.active = 0, edma _x _tcd.done = 1, edma _x _irqr n =1. 8. the channel retires. the edma goes idle or se rvices the next channel. 21.5.5.2 multiple requests the next example is the same as previous, excepting transferring 32 bytes via tw o hardware requests. the only fields that change are the ma jor loop iteration count and the fina l address offsets. the edma is programmed for two iterations of the major loop tran sferring 16 bytes per itera tion. after the channel?s hardware requests are enabled in the edma_ x _erqr, channel service request s are initiated by the slave device (erqr should be set af ter tcd). note that edma _x _tcd.start = 0. edma _x _tcd.citer = edma _x _tcd.biter = 2 edma _x _tcd.nbytes = 16 edma _x _tcd.saddr = 0x1000 edma _x _tcd.soff = 1 edma _x _tcd.ssize = 0 edma _x _tcd.slast = ?32 edma _x _tcd.daddr = 0x2000 edma _x _tcd.doff = 4 edma _x _tcd.dsize = 2 edma _x _tcd.dlast_sga = ?32 edma _x _tcd.int_maj = 1 edma _x _tcd.start = 0 (must be written last after all other fields have been initialized)
enhanced direct memory access controller (edma) freescale semiconductor 21-55 pxr40 microcontroller reference manual, rev. 1 all other tcd fields = 0 this generates the following sequence of events: 1. first hardware (edma peripheral re quest) request for channel service. 2. the channel is selected by arbitration for servicing. 3. edma engine writes: edma _x _tcd.done = 0, edma _x _tcd.start = 0, edma _x _tcd.active = 1. 4. edma engine reads: channel tcd data from local memory to internal register file. 5. the source to destination transfers are executed as follows: a) read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b) write_word(0x2000) ? first iteration of the minor loop c) read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d) write_word(0x2004) ? second iteration of the minor loop e) read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f) write_word(0x2008) ? third iteration of the minor loop g) read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h) write_word(0x200c) ? last iteration of the minor loop 6. edma engine writes: edma _x _tcd.saddr = 0x1010, edma _x _tcd.daddr = 0x2010, edma _x _tcd.citer = 1. 7. edma engine writes: edma _x _tcd.active = 0. 8. the channel retires ? one iteration of the major loop. the edma goes idle or se rvices the next channel. 9. second hardware (edma peripheral request) requests channel service. 10. the channel is selected by arbitration for servicing. 11. edma engine writes: edma _x _tcd.done = 0, edma _x _tcd.start = 0, edma _x _tcd.active = 1. 12. edma engine reads: channel tcd data from local memory to internal register file. 13. the source to destination transfers are executed as follows: a) read_byte(0x1010), r ead_byte(0x1011), rea d_byte(0x1012), read_byte(0x1013) b) write_word(0x2010) ? first iteration of the minor loop c) read_byte(0x1014), rea d_byte(0x1015), read_byte( 0x1016), read_byte(0x1017) d) write_word(0x2014) ? second iteration of the minor loop e) read_byte(0x1018), rea d_byte(0x1019), read_byte(0 x101a), read_byte(0x101b) f) write_word(0x2018) ? third iteration of the minor loop g) read_byte(0x101c), r ead_byte(0x101d), read_byte (0x101e), read_byte(0x101f) h) write_word(0x201c) ? last iteration of the minor loop ? major loop complete 14. edma engine writes: edma _x _tcd.saddr = 0x1000, edma _x _tcd.daddr = 0x2000, edma _x _tcd.citer = 2 (edma _x _tcd.biter).
enhanced direct memory access controller (edma) 21-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 15. edma engine writes: edma _x _tcd.active = 0, edma _x _tcd.done = 1, edma_ x _irqr n =1. 16. the channel retires ? major loop complete. the edma goes idle or se rvices the next channel. 21.5.5.3 modulo feature the modulo feature of the ed ma provides the ability to implement a ci rcular data queue in which the size of the queue is a power of two. mod is a 5-bit bitfield for both the s ource and destination in the tcd and specifies which lower address bits are allowed to increment from their original value after the address + offset calculation. all upper addr ess bits remain the same as in the original value. a setting of 0 for this field disables the modulo feature. table 21-25 shows how the transfer addresses are specified based on the setting of the mod field. here a circular buffer is cr eated where the address wraps to the origin al value while the 28 upper address bits (0x1234567x) retain their original value. in this example the source address is set to 0x12345670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 2 4 byte (16-byte) size queue. 21.5.6 tcd status 21.5.6.1 minor loop complete there are two methods to test for minor loop completion when using soft ware initiated service requests. the first method is to read the edma _x _tcd.citer field and test fo r a change. another method may be extracted from the sequence below. the second method is to test the edma _x _tcd.start bit and the edma _x _tcd.active bit. the minor loop complete c ondition is indicated by both bits reading zero after the edma _x _tcd.start was written to a 1. polling the edma _x _tcd.active bit may be inconclusive because the active status may be miss ed if the channel execution is short in duration. the tcd status bits execute the following sequence for a software activated channel: 1. edma _x _tcd.start = 1, edma _x _tcd.active = 0, edma _x _tcd.done = 0 (channel service request via software). table 21-25. modulo feature example transfer number address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567c 5 0x12345670 6 0x12345674
enhanced direct memory access controller (edma) freescale semiconductor 21-57 pxr40 microcontroller reference manual, rev. 1 2. edma _x _tcd.start = 0, edma _x _tcd.active = 1, edma _x _tcd.done = 0 (channel is executing). 3. edma _x _tcd.start = 0, edma _x _tcd.active = 0, edma _x _tcd.done = 0 (channel has completed the minor loop and is idle), or 4. edma _x _tcd.start = 0, edma _x _tcd.active = 0, edma _x _tcd.done = 1 (channel has completed the major loop and is idle). the best method to test for minor loop completion wh en using hardware initiate d service requests is to read the edma _x _tcd.citer field and test for a change . the hardware reque st and acknowledge handshakes signals are not visi ble in the programmer?s model. the tcd status bits execute the following sequence for a hardware activated channel: 1. edma peripheral request asserts (c hannel service request via hardware). 2. edma _x _tcd.start = 0, edma _x _tcd.active = 1, edma _x _tcd.done = 0 (channel is executing). 3. edma _x _tcd.start = 0, edma _x _tcd.active = 0, edma _x _tcd.done = 0 (channel has completed the minor loop and is idle), or 4. edma _x _tcd.start = 0, edma _x _tcd.active = 0, edma _x _tcd.done = 1 (channel has completed the major loop and is idle). for both activation types, the major loop comple te status is explicitly indicated via the edma _x _tcd.done bit. the edma _x _tcd.start bit is cleared auto matically when the channel begi ns execution, regardless of how the channel was activated. 21.5.6.2 active channel tcd reads the edma will read back the true edma _x _tcd.saddr, edma _x _tcd.daddr, and edma _x _tcd.nbytes values if read while a channel is executing. the true values of the saddr, daddr, and nbytes are the values the edma engine is currently using in its inte rnal register file and not the values in the tcd local memory for that channel. the addresse s (saddr and daddr) and nbytes (decrements to zero as the transfer progre sses) can give an indicati on of the progress of the transfer. all other values are read back from the tcd local memory. 21.5.6.3 preemption status preemption is available only when fi xed arbitration is selected for both group- and channel-arbitration modes. a preempt-able situ ation is one in which a preempt-ena bled channel is running and a higher priority request beco mes active. when the edma engine is not operating in fixed group, fixed-channel arbitration mode, the determination of the relative priority of the actively running and the outstanding requests become undefined. channel and group priorities are tr eated as equal (or more exactly, constantly rotating) when round-robin arbi tration mode is selected. the edma _x _tcd.active bit for the preempted channel remains asserted throughout the preemption. the preempted channel is temporaril y suspended while the preempting ch annel executes one iteration of
enhanced direct memory access controller (edma) 21-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the major loop. two edma _x _tcd.active bits set at the same ti me in the overall tcd map indicates a higher priority channel is actively preempting a lower priority channel. 21.5.7 channel linking channel linking (or chaining) is a mechan ism in which one channel sets the edma _x _tcd.start bit of another channel (or itself), thus initiating a service request for that channel. this operation is automatically performed by the edma engine at the conclusion of the major or minor loop when properly enabled. the minor loop channel linking occurs at the completio n of the minor loop (or one iteration of the major loop). the edma _x _tcd.citer.e_link field are used to determine whether a minor loop link is requested. when enabled, the channel li nk is made after each it eration of the minor loop except for the last. when the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. for exam ple, with the initial fields of: edma _x _tcd.citer.e_link = 1 edma _x _tcd.citer.linkch = 0xc edma _x _tcd.citer value = 0x4 edma _x _tcd.major.e_link = 1 edma _x _tcd.major.linkch = 0x7 will execute as: 1. minor loop done ? set channel 12 edma _x _tcd.start bit 2. minor loop done ? set channel 12 edma _x _tcd.start bit 3. minor loop done ? set channel 12 edma _x _tcd.start bit 4. minor loop done, major loop done ? set channel 7 edma _x _tcd.start bit when minor loop linking is enabled (edma _x _tcd.citer.e_link = 1), the edma _x _tcd.citer field uses a nine bit vector to form the current iteration count. when minor loop linking is disabled (edma _x _tcd.citer.e_link = 0), the edma _x _tcd.citer field uses a 15-bit vector to fo rm the current iteration count. the bits associated with the edma _x _tcd.citer.linkch field are con catenated onto the citer value to increase the range of the citer. note after configuration, the edma _x _tcd.citer.e_link bit and the edma _x _tcd.biter.e_link bit must be equal or a configuration error is reported. the citer and biter vector widths must be equal to calculate the major loop, halfway done interrupt point. table 21-26 summarizes how a dma channel can link to another dma channel, i.e, use another channel?s tcd, at the end of a loop.
enhanced direct memory access controller (edma) freescale semiconductor 21-59 pxr40 microcontroller reference manual, rev. 1 21.5.8 dynamic programming this section provides recommended methods to cha nge the programming model during channel execution. 21.5.8.1 dynamic channel linking and dynamic scatter-gather operation dynamic channel linking and dynamic scatter-gath er operation is the process of changing the edma _x _tcd.major.e_link or edma _x _tcd.e_sg bits during channel execution. these bits are read from the tcd local memory at the end of channel execution thus al lowing the user to enable either feature during channel execution. because the user is allowed to change the configur ation during execution, a c oherency model is needed. consider a scenario where the user attempts to execute a dynamic channel link by enabling the edma _x _tcd.major.e_link bit at the same time the edma engine is retiring the channel. the edma _x _tcd.major.e_link would be se t in the programmer?s model, but it would be unclear whether the actual link was made before the channel retired. the following coherency model is recommended when executing a dynamic channel link or dynamic scatter-gather request: 1. set the edma _x _tcd.major.e_link bit. 2. read back the edma _x _tcd.major.e_link bit 3. test the edma _x _tcd.major.e_link request status: a) if the bit is set, the dynamic link attempt was successful. b) if the bit is cleared, the attempted dynami c link did not succeed, the channel was already retiring. this same coherency model is true for dynamic scatter-ga ther operations. for bot h dynamic requests, the tcd local memory controller forces the edma _x _tcd.major.e_link and edma _x _tcd.e_sg bits to zero on any writes to a cha nnel?s tcd after that channel?s edma _x _tcd.done bit is set indicating the major loop is complete. table 21-26. channel linking parameters desired link behavior tcd control field name description link at end of minor loop citer.e_link enable channel-to-channel linking on minor loop completion (current iteration). citer.linkch link channel number when linking at end of minor loop (current iteration). link at end of major loop major.e_link enable channel-to-channel linking on major loop completion. major.linkch link channel number when linking at end of major loop.
enhanced direct memory access controller (edma) 21-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the user must clear the edma _x _tcd.done bit before writing the edma _x _tcd.major.e_link or edma _x _tcd.e_sg bits. the edma _x _tcd.done bit is cleared automa tically by the edma engine after a channel begins execution.
freescale semiconductor 22-1 pxr40 microcontroller reference manual, rev. 1 chapter 22 flexray communication controller (flexray) 22.1 introduction 22.1.1 reference the following documents are referenced. ? flexray communications system prot ocol specification, version 2.1 rev a ? flexray communications system electrical physical layer specification, version 2.1 rev a 22.1.2 glossary this section provides a list of terms used in the description of the controller. table 22-1. list of terms term definition bcu buffer control unit. handles message buffer access. bmif bus master interface. provides ma ster access to flexray memory block. cc communication controller cdc clock domain crosser chi controller host interface cycle length in ? t the actual length of a cycle in ? t for the ideal controller (+/- 0 ppm) ebi external bus interface flexray memory memory window to store message buffer payload, header, status, and synchronization frame related tables. system memory memory that is contains the flexray memory system bus bus that connects t he controller and system memory fss frame start sequence hif host interface. provides host access to controller. host the flexray cc host mcu lut look up table. stores message buffer header index value. mb message buffer mbidx message buffer index: the position of a header field entry within the header area. if the header area is accessed as an array, this is the same as the array index of the entry. mbnum message buffer number: position of message buff er configuration registers within the register map. for example, message buffer number 5 corresponds to the mbccs5 register. mcu microcontroller unit ? tmicrotick mt macrotick
flexray communication controller (flexray) 22-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.1.3 color coding throughout this chapter types of items are highlight ed through the use of an italicized color font. flexray protocol parameters, constant s and variables are highlighted with blue italics . an example is the parameter gdactionpointoffset . flexray protocol states are highlighted in green italics . an example is the state poc:normal active . 22.1.4 overview the controller is a flexray communicat ion controller that implements the flexray communications system protocol specifi cation, version 2.1 rev a. the controller has three main components: ? controller host interface (chi) ? protocol engine (pe) ? clock domain crossing unit (cdc) a block diagram of the controller wi th its surrounding modules is given in figure 22-1 . mts media access test symbol nit network idle time pe protocol engine poc protocol operation control. each state of the poc is denoted by poc:state rx reception seq sequencer engine tcu time control unit tx transmission sync frame null frame or message frame with sync frame indicator set to 1 startup frame null frame or message frame with both sync frame indicator and startup frame indicator set to 1 normal frame null frame or message frame with both sync frame indicator and startup frame indicator set to 0 null frame frame with null frame indicator set to 0 message frame frame with null frame indicator set to 1 table 22-1. list of terms (continued) term definition
flexray communication controller (flexray) freescale semiconductor 22-3 pxr40 microcontroller reference manual, rev. 1 figure 22-1. flexray block diagram the protocol engine has two tran smitter units txa and txb and two receiver units rxa and rxb for sending and receiving frames thr ough the two flexray channels. the time control unit (tcu) is responsible for maintaini ng global clock synchronization to the fl exray network. the overall activity of the pe is controlled by the sequencer engine (seq). the controller host interface provi des host access to the module?s c onfiguration, control, and status registers, as well as to the message buffer configuration, control, and st atus registers. the message buffers themselves, which contain the frame h eader and payload data received or to be transmitted, and the slot status information, are stor ed in the flexray memory. the clock domain crossing unit implements signal crossing from th e chi clock domain to the pe clock domain and vice versa, to allow for asynchronous pe and chi clock domains. the controller stores the frame header and payload data of frames receive d or of frames to be transmitted in the flexray memory. the application accesses the flex ray memory to retrieve an d provide the frames to be processed by the controller. in addition to the frame header and payload data, the controller stores the synchronization frame related tables in the flexray memory for application processing. the flexray memory is located in the system memory of the mcu. the controller has access to the flexray memory via its bus master interface (bmif). the host provides the start address of the flexray memory window within the system memory by programming the system memory base address register (symbadr) . all flexray memory related offsets are stored in offset registers. the physical address pointer into the flexray memory window of the mcu syst em memory is calculated using the offset values the flexray memory base address. clock domain crossing pe txa rxa tcu config seq chi hif search lut bcu fr_a_rx fr_b_rx fr_dbg[0] fr_a_tx fr_a_tx_en fr_b_tx fr_b_tx_en fr_dbg[1] fr_dbg[2] fr_dbg[3] flexray peripheral bridge b system memory bmif system bus
flexray communication controller (flexray) 22-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the controller does not provide a memo ry protection scheme for the flexray memory. 22.1.5 features the controller provides the following features: ? flexray communications system prot ocol specification, version 2.1 rev a compliant protocol implementation ? flexray communications system electrical physical layer specification, version 2.1 rev a compliant bus driver interface ? single channel support ? flexray port a can be configured to be conne cted either to physical flexray channel a or physical flexray channel b. ? flexray bus data rates of 10 mbit/s, 8 mbit/s, 5 mbit/s, and 2.5 mbit/s supported ? 128 configurable message buffers with ? individual frame id filtering ? individual channel id filtering ? individual cycle counter filtering ? message buffer header, status and payload data stored in dedicated flexray memory ? allows for flexible and efficient message buffer implementation ? consistent data access ensured by means of buffer locking scheme ? application can lock multiple buffers at the same time ? size of message buffer payload data se ction configurable from 0 up to 254 bytes ? two independent message buffer segments with configurable size of payload data section ? each segment can contain message buffers assigned to the stat ic segment and message buffers assigned to the dynamic segment at the same time ? zero padding for transmit messa ge buffers in static segment ? applied when the frame payloa d length exceeds the size of th e message buffer data section ? transmit message buffers configurable with state/event semantics ? message buffers can be configured as ? receive message buffer ? single buffered transmit message buffer ? double buffered transmit message buffer (com bines two single buffered message buffer) ? individual message buffer r econfiguration supported ? means provided to safely disa ble individual message buffers ? disabled message buffers can be reconfigured ? two independent receive fifos ? one receive fifo per channel ? up to 255 entries for each fifo
flexray communication controller (flexray) freescale semiconductor 22-5 pxr40 microcontroller reference manual, rev. 1 ? global frame id filtering, based on both value/mask filter s and range filters ? global channel id filtering ? global message id filtering for the dynamic segment ? 4 configurable slot error counters ? 4 dedicated slot status indicators ? used to observe slots without using receive message buffers ? measured value indicators for the clock synchronization ? internal synchronizatio n frame id and synchronization fr ame measurement tables can be copied into the flexray memory ? fractional macroticks are supported for clock correction ? maskable interrupt sources provided via individual and combined interrupt lines ? 1 absolute timer ? 1 timer that can be configured to absolute or relative 22.1.6 modes of operation this section describes the basic opera tional power modes of the controller. 22.1.6.1 disabled mode the controller enters the disabled mode during hard reset. the controller i ndicates that it is in the disabled mode by negating the module enable bit men in the module configuration register (mcr) . no communication is performed on the flexray bus. all registers with the write access conditions any time and disabled mode can be accessed for writing as stated in section 22.5.2, register descriptions . the application configures the c ontroller by accessing the configur ation bits and fields in the module configuration register (mcr) . 22.1.6.1.1 leave disabled mode the controller leaves the disabled mode and enters the normal mode , when the application writes 1 to the module enable bit men in the module configuration register (mcr) note when the controller was enabled, it cannot be disabled the later on. 22.1.6.2 normal mode in this mode the controller is fully functional. the controller indicates that it is in normal mode by asserting the module enable bit men in the module configuration register (mcr) .
flexray communication controller (flexray) 22-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.1.6.2.1 enter normal mode this mode is entered when the application requests the controller to leave th e disabled mode. if the normal mode was entered by leavi ng the disabled mode, th e application has to perform the protocol initialization described in section 22.7.1.2, protocol initialization , to achieve full flexray functionality. depending on the values of the sc m, cha, and chb bits in the module configurati on register (mcr) , the corresponding flexray bus driver ports are enabled and driven. 22.2 external signal description this section lists and describes the controller signa ls, connected to external pins. these signals are summarized in table 22-2 and described in detail in section 22.2.1, detailed signal descriptions . note the off chip signals fr_a_rx, fr_a_tx, and fr_a_tx_en are available on each package option. the availability of the other off chip signals depends on the package option. 22.2.1 detailed signal descriptions this section provides a detailed de scription of the controller signa ls, connected to external pins. 22.2.1.1 fr_a_rx ? rece ive data channel a the fr_a_rx signal carries the receive data for ch annel a from the corresponding flexray bus driver. 22.2.1.2 fr_a_tx ? transmit data channel a the fr_a_tx signal carries the tran smit data for channel a to the corresponding flexray bus driver. table 22-2. external signal properties name direction active reset function fr_a_rx input ? ? receive data channel a fr_a_tx output ? 1 transmit data channel a fr_a_tx_en output low 1 transmit enable channel a fr_b_rx input ? ? receive data channel b fr_b_tx output ? 1 transmit data channel b fr_b_tx_en output low 1 transmit enable channel b fr_dbg[0] output ? 0 debug strobe signal 0 fr_dbg[1] output ? 0 debug strobe signal 1 fr_dbg[2] output ? 0 debug strobe signal 2 fr_dbg[3] output ? 0 debug strobe signal 3
flexray communication controller (flexray) freescale semiconductor 22-7 pxr40 microcontroller reference manual, rev. 1 22.2.1.3 fr_a_tx_en ? transmit enable channel a the fr_a_tx_en signal indicates to the flexra y bus driver that the controll er is attempting to transmit data on channel a. 22.2.1.4 fr_b_rx ? rece ive data channel b the fr_b_rx signal carries the receive data for ch annel b from the corresponding flexray bus driver. 22.2.1.5 fr_b_tx ? transmit data channel b the fr_b_tx signal carries the tran smit data for channel b to th e corresponding flexray bus driver 22.2.1.6 fr_b_tx_en ? transmit enable channel b the fr_b_tx_en signal indicates to the flexray bus driver th at the controller is attempting to transmit data on channel b. 22.2.1.7 fr_dbg[3], fr_dbg [2], fr_dbg[1], fr_dbg [0] ? strobe signals these signals provide the selected debug strobe signals. for details on the debug strobe signal selection refer to section 22.6.16, strobe signal support . 22.3 controller host interface clocking the clock for the chi is derived fro m the system bus clock and has the same phase and frequency as the system bus clock. since the flexray protocol requires data delivery at fixed points in time, the memory read cycles from the flex ray memory must be finished after a fi xed amount of time. to ensure this, a minimum frequency f chi of the chi clock is required, which is given in equation 22-1 . eqn. 22-1 additional requirements for the mini mum frequency of the chi clock re sult from the number of message buffers. these requirements are provided in section 22.7.3, number of us able message buffers . 22.4 protocol engine clocking the clock for the protocol engine can be generated by two sources. the first source is the internal crystal oscillator and the sec ond source is an internal pl l. the clock source to be us ed is selected by the clock source select bit clksel in the module configurati on register (mcr) . 22.4.1 oscillator clocking if the protocol engine is clocked by the internal crystal oscillator , an 40 mhz crystal or cmos compatible clock must be connected to the osci llator pins. the crystal or clock mu st fulfill the requirements given by the flexray communications system prot ocol specification, version 2.1 rev a. f chi 32mhz ?
flexray communication controller (flexray) 22-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.4.2 pll clocking if the protocol engine is clocked by the internal pll, the frequency of the pe clock source is system clock / 3. the system cloc k frequency has to be 120 mhz. 22.5 memory map and register description the controller occupies 1280 bytes of address space starting at the contro ller?s base address defined by the memory map of the mcu. 22.5.1 memory map the complete memory map of the controller is shown in table 22-3 . the addresses presented here are the offsets relative to the contro ller base address which is defined by the mcu address map. table 22-3. flexray memory map offset register access module configuration and control 0x0000 module version register (mvr) r 0x0002 module configuration register (mcr) r/w 0x0004 system memory ba se address high register (symbadhr) r/w 0x0006 system memory base addre ss low register (symbadlr) r/w 0x0008 strobe signal control register (stbscr) r/w 0x000a reserved r 0x000c message buffer data size register (mbdsr) r/w 0x000e message buffer segment size an d utilization register (mbssutr) r/w test registers 0x0010 reserved r 0x0012 reserved r interrupt and error handling 0x0014 protocol operation co ntrol register (pocr) r/w 0x0016 global interrupt flag and enable register (gifer) r/w 0x0018 protocol interrupt flag register 0 (pifr0) r/w 0x001a protocol interrupt flag register 1 (pifr1) r/w 0x001c protocol interrupt enable register 0 (pier0) r/w 0x001e protocol interrupt enable register 1 (pier1) r/w 0x0020 chi error flag register (chierfr) r/w 0x0022 message buffer interrupt vector register (mbivec) r 0x0024 channel a status error counter register (casercr) r 0x0026 channel b status error counter register (cbsercr) r protocol status 0x0028 protocol status register 0 (psr0) r 0x002a protocol status register 1 (psr1) r 0x002c protocol status register 2 (psr2) r
flexray communication controller (flexray) freescale semiconductor 22-9 pxr40 microcontroller reference manual, rev. 1 0x002e protocol status register 3 (psr3) r/w 0x0030 macrotick counter register (mtctr) r 0x0032 cycle counter register (cyctr) r 0x0034 slot counter channel a register (sltctar) r 0x0036 slot counter channel b register (sltctbr) r 0x0038 rate correction value register (rtcorvr) r 0x003a offset correction value register (ofcorvr) r 0x003c combined interrupt flag register (cifrr) r 0x003e system memory access time-out register (symator) r/w sync frame counter and tables 0x0040 sync frame counter register (sfcntr) r 0x0042 sync frame table offset register (sftor) r/w 0x0044 sync frame table configuration, control, status register (sftccsr) r/w sync frame filter 0x0046 sync frame id rejection filter register (sfidrfr) r/w 0x0048 sync frame id acceptance filt er value register (sfidafvr) r/w 0x004a sync frame id acceptance fi lter mask register (sfidafmr) r/w network management vector 0x004c network management vector register 0 (nmvr0) r 0x004e network management vector register 1 (nmvr1) r 0x0050 network management vector register 2 (nmvr2) r 0x0052 network management vector register 3 (nmvr3) r 0x0054 network management vector register 4 (nmvr4) r 0x0056 network management vector register 5 (nmvr5) r 0x0058 network management vector length register (nmvlr) r/w timer configuration 0x005a timer configuration and control register (ticcr) r/w 0x005c timer 1 cycle set register (ti1cysr) r/w 0x005e timer 1 macrotick offse t register (ti1mtor) r/w 0x0060 timer 2 configuration register 0 (ti2cr0) r/w 0x0062 timer 2 configuration register 1 (ti2cr1) r/w slot status configuration 0x0064 slot status selection register (sssr) r/w 0x0066 slot status counter condition register (ssccr) r/w slot status 0x0068 slot status register 0 (ssr0) r 0x006a slot status register 1 (ssr1) r 0x006c slot status register 2 (ssr2) r 0x006e slot status register 3 (ssr3) r 0x0070 slot status register 4 (ssr4) r 0x0072 slot status register 5 (ssr5) r table 22-3. flexray memory map (continued) offset register access
flexray communication controller (flexray) 22-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x0074 slot status register 6 (ssr6) r 0x0076 slot status register 7 (ssr7) r 0x0078 slot status counter register 0 (sscr0) r 0x007a slot status counter register 1 (sscr1) r 0x007c slot status counter register 2 (sscr2) r 0x007e slot status counter register 3 (sscr3) r mts generation 0x0080 mts a configuration register (mtsacfr) r/w 0x0082 mts b configuration register (mtsbcfr) r/w shadow buffer configuration 0x0084 receive shadow buffer index register (rsbir) r/w receive fifo ? configuration 0x0086 receive fifo watermark and selection register (rfwmsr) r/w 0x0088 receive fifo start index register (rfsir) r/w 0x008a receive fifo depth and size register (rfdsr) r/w receive fifo - control 0x008c receive fifo a read index register (rfarir) r 0x008e receive fifo b read index register (rfbrir) r receive fifo - filter 0x0090 receive fifo message id acceptance filter value register (rfmidafvr) r/w 0x0092 receive fifo message id acceptance filter mask register (rfmiafmr) r/w 0x0094 receive fifo frame id rejection f ilter value register (rffidrfvr) r/w 0x0096 receive fifo frame id rejection filter mask register (rffidrfmr) r/w 0x0098 receive fifo range filter configuration register (rfrfcfr) r/w 0x009a receive fifo range filter control register (rfrfctr) r/w dynamic segment status 0x009c last dynamic transmit slot channel a register (ldtxslar) r 0x009e last dynamic transmit slot channel b register (ldtxslbr) r protocol configuration 0x00a0 ... 0x00dc protocol configuratio n register 0 (pcr0) ... protocol configuration register 30 (pcr30) r/w ? r/w 0x00de ... 0x00e6 reserved r receive fifo ? configuration (cont.) 0x00e8 receive fifo system me mory base address high register (rfsymbadhr) r/w 0x00ea receive fifo system memory base address low register (rfsymbadlr) r/w 0x00ec receive fifo periodic timer register (rfptr) r/w receive fifo - control (cont.) 0x00ee receive fifo fill level and pop count register (rfflpcr) r/w table 22-3. flexray memory map (continued) offset register access
flexray communication controller (flexray) freescale semiconductor 22-11 pxr40 microcontroller reference manual, rev. 1 22.5.2 register descriptions this section provides detailed descriptions of all re gisters in ascending address order, presented as 16-bit wide entities table 22-4 provides a key for the register figures and register tables. 22.5.2.1 register reset all registers except the message buffer cycle counte r filter registers (mbccfrn) , message buffer frame id registers (mbfidrn) , and message buffer index registers (mbidxrn) are reset to their reset value on system reset. the registers mentioned above are located in physical memory blocks and, thus, they are not affected by reset. for some register fields, additional rese t conditions exist. these additional 0x00f0 ... 0x00fe reserved r message buffers configuration, control, status 0x0100 message buffer configuration, cont rol, status register 0 (mbccsr0) r/w 0x0102 message buffer cycle counter filter register 0 (mbccfr0) r/w 0x0104 message buffer frame id register 0 (mbfidr0) r/w 0x0106 message buffer index register 0 (mbidxr0) r/w ... ... ... 0x04f8 message buffer configuration, cont rol, status register 127 (mbccsr127) r/w 0x04fa message buffer cycle counter filter register 127 (mbccfr127) r/w 0x04fc message buffer frame id register 127 (mbfidr127) r/w 0x04fe message buffer index register 127 (mbidxr127) r/w table 22-4. register access conventions convention description depending on its placement in the read or write row, in dicates that the bit is not readable or not writeable. r* reserved bit or field, will not be changed. application must not write any value different from the reset value. fieldname identifies the field. its presen ce in the read or write row indicate s that it can be read or written. register field types rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. w1c write one to clear. a flag bit that can be read, is cleared by writing a one, writing 0 has no effect. reset value 0 resets to zero. 1 resets to one. ? not defined after reset and not affected by reset. table 22-3. flexray memory map (continued) offset register access
flexray communication controller (flexray) 22-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 reset conditions are mentioned in the detailed descri ption of the register. the additional reset conditions are explained in table 22-5 . 22.5.2.2 register write access this section describes the write access restri ction terms that apply to all registers. 22.5.2.2.1 register write access restriction for each register bit and register fi eld, the write access conditions are sp ecified in the detailed register description. a description of the wr ite access conditions is given in table 22-6 . if, for a specific register bit or field, none of the given write access conditions is fulfilled, any writ e attempt to this register bit or field is ignored without a ny notification. the values of the bits or fields are not changed. the condition term [a or b] indicates that the register or field can be written to if at least one of the conditions is fulfilled. 22.5.2.2.2 register write access requirements all registers can be accessed with 8-bit, 16-bit and 32- bit wide operations. for some of the registers, at least a 16-bit wide write access is required to ensure correct operation. this write access requirement is stated in the detailed register de scription for each register affected 22.5.2.2.3 internal register access the following memory mapped registers are us ed to access multiple internal registers. ? strobe signal control register (stbscr) ? slot status selection register (sssr) ? slot status counter co ndition register (ssccr) ? receive shadow buffer index register (rsbir) table 22-5. additional re gister reset conditions condition description protocol run command the register field is reset when the application writes to run command ?0101? to the poccmd field in the protocol operation control register (pocr) . message buffer disable the register field is reset when the application has disabled the message buffer. this happens when the application writes 1 to the message buffer disable trigger bit mbccsrn[edt] while the message buffer is enabled (mbccsn[eds] = 1) and the controller grants the disable to the applic ation by clearing the mbccsrn[eds] bit. table 22-6. register write access restrictions condition indication description any time ? no write access restriction. disabled mode mcr[men] = 0 write access only when the controller is in disabled mode. normal mode mcr[men] = 1 write access only when the controller is in normal mode. poc:config psr0[protstate] = poc:config write access only when the protocol is in the poc:config state. mb_dis mbccsr[eds] = 0 write access only when the related message buffer is disabled. mb_lck mbccsrn[lcks] = 1 write access only when the related message buffer is locked.
flexray communication controller (flexray) freescale semiconductor 22-13 pxr40 microcontroller reference manual, rev. 1 each of these memory mapped registers provides a se l field and a wmd bit. the sel field is used to select the internal register. the wmd bit controls th e write mode. if the wmd bit is set to 0 during the write access, all fields of the inte rnal register are updated. if the wmd bit set to 1, only the sel field is changed. all other fields of the inte rnal register remain unc hanged. this allows for r eading back the values of the selected internal regist er in a subsequent read access. 22.5.2.3 module version register (mvr) this register provides the controller version number. the module version number is derived from the chi version number and the pe version number. 22.5.2.4 module configur ation register (mcr) this register defines the global configuration of the controller. base + 0x0000 0123456789101112131415 r chiver pever w reset1001110101100110 figure 22-2. module version register (mvr) table 22-7. mvr field descriptions field description chiver chi version number ? this field provides the version nu mber of the controller host interface. pever pe version number ? this field provides the versio n number of the protocol engine. base + 0x0002 write: men, sbf f, scm, chb, cha, fum, fam, clksel, bitrate: disabled mode sffe: disabled mode or poc:config 0123456789101112131415 r men sbff scm chb cha sffe 0 r* fum fam 0 clk sel bitrate 0 w reset0000000000000000 figure 22-3. module configuration register (mcr)
flexray communication controller (flexray) 22-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 22-8. mcr field descriptions field description men module enable ? this bit indicates whether or not the contro ller is in the disabled mode. the application requests the controller to leave the disabled mode by wr iting 1 to this bit before leaving the disabled mode, the application must configure the scm, sbff, chb, cha, tmode, bitrate values. for details see section 22.1.6, modes of operation . 0 write: ignored, controller disable not possible read: controller disabled 1 write: enable controller read: controller enabled note: if the controller is enabled it can not be disabled. sbff system bus failure freeze ? this bit controls the beha vior of the controller in case of a system bus failure. 0 continue normal operation 1 transition to freeze mode scm single channel device mode ? this control bit defines the channel device mode of the controller as described in section 22.6.10, channel device modes . 0 controller works in dual channel device mode 1 controller works in single channel device mode chb cha channel enable ? protocol related parameter: pchannels the semantic of these contro l bits depends on the channel device mode controlled by the scm bit and is given ta b l e 2 2 - 9 . sffe synchronization frame filter enable ? this bit controls the filtering for received synchronization frames. for details see section 22.6.15, sync frame filtering . 0 synchronization frame filtering disabled 1 synchronization frame filtering enabled r* reserved ? this bit is reserved. it is read as 0. application must not write 1 to this bit. fum fifo update mode ? this bit controls the fifo update behavior when the interrupt flags gifer[fafaif] and difer[fafbif] are written by the application (see section 22.6.9.8, fifo update ). 0 fifoa (fifob) is updated on writing 1 to gifer[fafaif] (gifer[fafbif]) 1 fifoa (fifob) is not updated on writing 1 to gife r[fafaif] (gifer[fafbif]) fam fifo address mode ? this bit controls the location of the system memory base address for the fifos. (see section 22.6.9.2, fi fo configuration ). 0 fifo base address located in system memory base address register (symbadr) 1 fifo base address located in receive fifo system memory base address register (rfsymbadr) clksel protocol engine clock source select ? this bit is used to select the clock source for the protocol engine. 0 pe clock source is generated by on-chip crystal oscillator. 1 pe clock source is generated by on-chip pll. bitrate flexray bus bit rate ? this bit field defines the flexray bus bit rate.00010.0 mbit/sec 001 5.0 mbit/sec 010 2.5 mbit/sec 011 8.0 mbit/sec 100 reserved 101 reserved 110 reserved 111 reserved
flexray communication controller (flexray) freescale semiconductor 22-15 pxr40 microcontroller reference manual, rev. 1 22.5.2.5 system memory base address register (symbadr) note the system memory base address must be set before the controller is enabled. the system memory base address re gisters define the base address of the flexray memory within the system memory. the base address is used by the bmif to calculat e the physical memory address for system memory accesses. table 22-9. flexray channel selection scm chb cha description dual channel device modes 0 00 ports fr_a_rx, fr_a_tx, and fr_a_tx_en not driven by controller ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by controller 01 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by controller - connected to flexray channel a ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by controller 10 ports fr_a_rx, fr_a_tx, and fr_a_tx_en not driven by controller ports fr_b_rx, fr_b_tx, and fr_a_tx_en driven by controller - connected to flexray channel b 11 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by controller - connected to flexray channel a ports fr_b_rx, fr_b_tx, and fr_a_tx_en driven by controller - connected to flexray channel b single channel device mode 1 00 ports fr_a_rx, fr_a_tx, and fr_a_tx_en not driven by controller ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by controller 01 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by controller - connected to flexray channel a ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by controller 10 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by controller - connected to flexray channel b ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by controller 11reserved base + 0x0004 write: disabled mode 0123456789101112131415 r smba[31:16] w reset0000000000000000 figure 22-4. system me mory base address high register (symbadhr) base + 0x0006 write: disabled mode 0123456789101112131415 r smba[15:4] 0000 w reset0000000000000000 figure 22-5. system memory base address low register (symbadlr)
flexray communication controller (flexray) 22-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.6 strobe signal control register (stbscr) this register is used to assign the individual protocol timing related strobe signals given in table 22-12 to the external strobe ports. each strobe signal can be as signed to at most one strobe port. each write access to registers overwrites the previ ously written enb and stbpsel values for the signal indicated by sel. if more than one strobe signal is as signed to one strobe port, the curren t values of the strobe signals are combined with a binary or and presented at the strobe port. if no strobe signal is assigned to a strobe port, the strobe port carries logic 0. for more detailed and timing in formation refer to section 22.6.16, strobe signal support . note in single channel device mode, cha nnel b related strobe signals are undefined and should not be as signed to the strobe ports. table 22-10. symbadr field descriptions field description smba system memory base address ? this is the value of the system memory base address for the individual message buffers and sync frame table. this is the value of the system memory base address for the receive fifo if the fifo address mode bit mcr[fam] is set to 1. it is defines as a byte address. base + 0x0008 16-bit write access required write: anytime 0123456789101112131415 r0000 sel 000 enb 00 stbpsel wwmd reset0000000000000000 figure 22-6. strobe signal control register (stbscr) table 22-11. stbscr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel strobe signal select ? this control field selects one of the strobe signals given in table 22-12 to be enabled or disabled and assigned to one of the four strobe ports given in table 22-12 . enb strobe signal enable ? the control bit is used to enable and to disable the strobe signal selected by stbssel. 0 strobe signal is disabled and not assigned to any strobe port. 1 strobe signal is e nabled and assigne d to the strobe port selected by stbpsel. stbpsel strobe port select ? this field selects the strobe port that the strobe signal selected by the sel is assigned to. all strobe signals that are enabled and assigned to the same strobe port are combined with a binary or operation. 00 assign selected signal to fr_dbg[0] 01 assign selected signal to fr_dbg[1] 10 assign selected signal to fr_dbg[2] 11 assign selected signal to fr_dbg[3]
flexray communication controller (flexray) freescale semiconductor 22-17 pxr40 microcontroller reference manual, rev. 1 .; 22.5.2.7 message buffer data size register (mbdsr) this register defines the size of the message buffer data section for th e two message buffer segments in a number of two-byte entities. the controller provides two indepe ndent segments for the individua l message buffers. all individual message buffers within one segment ha ve to have the same size for the message buf fer data section. this size can be different for the two message buffer segments. table 22-12. strobe signal mapping sel description channel type offset 1 1 given in pe clock cycles reference dec hex 0 0x0 arm - value +1 mt start 1 0x1 mt - value +1 mt start 2 0x2 cycle start - pulse 0 mt start 3 0x3 minislot start - pulse 0 mt start 4 0x4 slot start a pulse 0 mt start 5 0x5 b 6 0x6 receive data afte r glitch filtering a value +4 fr_a_rx 7 0x7 b fr_b_rx 8 0x8 channel idle indicator a level +5 fr_a_rx 9 0x9 b fr_b_rx 10 0xa syntax error detected a pulse +4 fr_a_rx 11 0xb b fr_b_rx 12 0xc content error detected a level +4 fr_a_rx 13 0xd b fr_b_rx 14 0xe receive fifo almost-full interrupt flag a value n.a. fafaif 15 0xf b fafbif base + 0x000c write: poc:config 0123456789101112131415 r0 mbseg2ds 0 mbseg1ds w reset0000000000000000 figure 22-7. message buffer data size register (mbdsr) table 22-13. mbdsr field descriptions field description mbseg2ds message buffer segment 2 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the second message buffer segment. mbseg1ds message buffer segment 1 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the first message buffer segment.
flexray communication controller (flexray) 22-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.8 message buffer segment size and utilization register (mbssutr) this register is used to define the last individual message buffer that belongs to the first message buffer segment and the number of the last used individual message buffer. 22.5.2.9 protocol operation control register (pocr) the application uses th is register to issue ? protocol control commands ? external clock correction commands protocol control commands are issu ed by writing to the po ccmd field. for more in formation on protocol control commands, see section 22.7.4, protocol control command execution . external clock correction commands are issued by wr iting to the eoc_ap and erc_ap fields. for more information on external clock correction, refer to section 22.6.11, external clock synchronization . base + 0x000e write: poc:config 0123456789101112131415 r0 last_mb_seg1 0 last_mb_util w reset0111111101111111 figure 22-8. message buffer segment size and utilization register (mbssutr) table 22-14. mbssutr field descriptions field description last_mb_seg1 last message buffer in segment 1 ? this field defines the message buffer number of the last individual message buffer that is assigned to the first message buffer segment. the individual message buffers in the first segment correspond to the message buffer control registers mbccsrn, mbccfrn, mbfidrn, mbidxrn with n <= last_mb_seg1. the first mess age buffer segment contains last_mb_seg1+1 individual message buffers. note: the first message buffer segment contains at least one individual message buffer. the individual message buffers in the second message buffer segment correspond to the message buffer control registers mbccsrn, mbccfrn, mbfi drn, mbidxrn with last_mb_seg1 < n < 128. note: if last_mb_seg1 = 127 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. last_mb_util last message buffer utilized ? this field defines the message buff er number of last utilized individual message buffer. the message buffer search engine examines all individual message buffer with a message buffer number n <= last_mb_util. note: if last_mb_util=last_mb_seg1 all individu al message buffers belong to the first message buffer segment and the second message buffer segment is empty. base + 0x0014 write: normal mode 0123456789101112131415 r0000 eoc_ap erc_ap bsy 0 0 0 poccmd wwme wmc reset0000000000000000 figure 22-9. protocol operation control register (pocr)
flexray communication controller (flexray) freescale semiconductor 22-19 pxr40 microcontroller reference manual, rev. 1 table 22-15. pocr field descriptions field description wme write mode external correction ? this bit controls the write mode of the eoc_ap and erc_ap fields. 0 write to eoc_ap and erc_ap fields on register write. 1 no write to eoc_ap and erc_ap fields on register write. eoc_ap external offset corr ection application ? this field is used to trigger the application of the external offset correction value defined in the protocol configuration register 29 (pcr29) . 00 do not apply external offset correction value 01 reserved 10 subtract external offset correction value 11 add external offset correction value erc_ap external rate correction application ? this field is used to trigger application of the external rate correction value defined in the protocol configuration register 21 (pcr21) 00 do not apply external rate correction value 01 reserved 10 subtract external rate correction value 11 add external rate correction value bsy wmc protocol control command write busy ? this status bit indicates the a cceptance of the protocol control command issued by the application via the poccmd field. t he controller sets this st atus bit when the application has issued a protocol control command via the poccmd field. the controller clears this status bit when protocol control command was accepted by the pe.when the applic ation issues a protocol control command while the bsy bit is asserted, the controller ignores this comm and, sets the protocol command ignored error flag pcmi_ef in the chi error flag register (chierfr) , and will not change the value of the poccmd field. 0 command write idle, command accepted an d ready to receive new protocol command. 1 command write busy, command not yet accepted, not ready to receive new protocol command. write mode command ? this bit controls the write mode of the poccmd field. 0 write to poccmd field on register write. 1 do not write to poccmd field on register write. poccmd protocol control command ? the application writes to this field to issue a protocol control command to the pe. the controller sends the protocol command to the pe immediately. while the transfer is running, the bsy bit is set. 0000 allow_coldstart ? immediately activate capa bility of node to cold start cluster. 0001 all_slots ? delayed 1 transition to the all slots transmission mode. 0010 config ? immediately transition to the poc:config state. 0011 freeze ? immediately transition to the poc:halt state. 0100 ready, config_complete ? i mmediately transition to the poc:ready state. 0101 run ? immediately transition to the poc:startup start state. 0110 default_config ? immediately transition to the poc:default config state. 0111 halt ? delayed transition to the poc:halt state 1000 wakeup ? immediately initiate the wakeup procedure. 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 1 delayed means on completion of current communication cycle.
flexray communication controller (flexray) 22-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.10 global interrupt flag and enable register (gifer) this register provides the means to control some of the interrupt request lines and provides the corresponding interrupt flags. the interrupt flags mif, prif, chif, rbif, and tbif are the outcome of a binary or of the related individual interrupt flags and interrupt enable s. the generation scheme for these flags is depicted in figure 22-150 . for more details on in terrupt generation, see section 22.6.20, interrupt support . these flags are cleared automati cally when all of the correspondi ng interrupt flags or interrupt enables in the related interrupt flag and en able registers are cleared by the application. base + 0x0016 write: normal mode 0123456789101112131415 r mif prif chif wup if fafb if fafa if rbif tbif mie prie chie wup ie fafb ie fafa ie rbie tbie w w1c w1c w1c reset0000000000000000 figure 22-10. global interrupt flag and enable register (gifer) table 22-16. gifer field descriptions field description mif module interrupt flag ? this flag is set if at least one of the other interrupt flags is in this register is asserted and the related interrupt enable is asserted, too. the controller generates the module interrupt request if mie is asserted. 0 no interrupt flag is asserted or no interrupt enable is set 1 at least one of the other interrupt flags in this register is asserted and the related interrupt bit is asserted, too prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag register 0 (pifr0) and protocol interrupt flag register 1 (pifr1) is asserted and the related interrupt enable flag is asserted, too. the controller generates the combined protocol interrupt request if the prie flag is asserted. 0 all individual protocol interrupt flags are equ al to 0 or no interrupt enable bit is set. 1 at least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1. chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (chierfr) is asserted and the chi error interrupt enable gifer [chie] is asserted. the controller generates the combined chi error interrupt if the chie flag is asserted, too. 0 all chi error flags are equal to 0 or the chi error interrupt is disabled 1 at least one chi error flag is asserted and chi error interrupt is enabled wupif wakeup interrupt flag ? this flag is set when the controller has received a wakeup symbol on the flexray bus. the application can determine on which channel the wakeup symbol was received by reading the related wakeup flags wub and wua in the protocol status r egister 3 (psr3). the controller generates the wakeup interrupt request if the wupie flag is asserted. 0 no wakeup condition or interrupt disabled 1 wakeup symbol received on flexray bus and interrupt enabled fafbif receive fifo channel b almost full interrupt flag ? this flag is set when one of the following events occurs a) the current number of fifo b entries is equal to or greater than the watermark defined by the wm field in the receive fifo watermark and selection register (rfwmsr) , and the controller writes a received message into the fifo b, or b) the current number of fifo b entries is at least 1 and the periodic timer as defined by receive fifo periodic timer register (rfptr) expires. 0 no such event 1 fifo b almost full event has occurred
flexray communication controller (flexray) freescale semiconductor 22-21 pxr40 microcontroller reference manual, rev. 1 fafaif receive fifo channel a almost full interrupt flag ? this flag is set when one of the following events occurs a) the current number of fifo a entries is equal to or greater than the watermark defined by the wm field in the receive fifo watermark and selection register (rfwmsr) , and the controller writes a received message into the fifo a, or b) the current number of fifo b entries is at least 1 and the periodic timer as defined by receive fifo periodic timer register (rfptr) expires. 0 no such event 1 fifo a almost full event has occurred rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (mbccsn[mtd] = 0) both the interrupt flag mbif and the interrupt enable bit mbie in the corresponding message buffer configuration, cont rol, status registers (mbccsrn) are asserted. the application can not clear this rbif flag directly. this flag is cleared by th e controller when all of the interrupt flags mbif of the individual receive message buffers are cleared by the appl ication or if the application has cleared the interrupt enables bit mbie. 0 none of the individual receive message bu ffers has the mbif and mbie flag asserted. 1 at least one individual receive message buffer has the mbif and mbie flag asserted. tbif transmit buffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (mbccsn[mtd] = 0) both the interrupt fl ag mbif and the interrupt enable bit mbie in the corresponding message buffer configuration, cont rol, status registers (mbccsrn) are equal to 1. the application can not clear this tbif flag directly. this fl ag is cleared by the controller when either all of the individual interrupt flags mbif of the individual transm it message buffers are cleared by the application or the host has cleared the interrupt enables bit mbie. 0 none of the individual transmit message buffers has the mbif and mbie flag asserted. 1 at least one individual transmit message buffer has the mbif and mbie flag asserted. mie module interrupt enable ? this flag controls if the module interr upt line is asserted when the mif flag is set. 0 disable interrupt line 1 enable interrupt line prie protocol interrupt enable ? this flag controls if the protocol interr upt line is asserted when the prif flag is set. 0 disable interrupt line 1 enable interrupt line chie chi interrupt enable ? this flag controls if the chi interrupt line is asserted when the chif flag is set. 0 disable interrupt line 1 enable interrupt line wupie wakeup interrupt enable ? this flag controls if the wakeup inte rrupt line is asserted when the wupif flag is set. 0 disable interrupt line 1 enable interrupt line fafbie receive fifo channel b almo st full interrupt enable ? this flag controls if the fifo b interrupt line is asserted when the fafbif flag is set. 0 disable interrupt line 1 enable interrupt line fafaie receive fifo channel a almo st full interrupt enable ? this flag controls if the fifo a interrupt line is asserted when the fafaif flag is set. 0 disable interrupt line 1 enable interrupt line table 22-16. gifer field descriptions (continued) field description
flexray communication controller (flexray) 22-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.11 protocol interrupt flag register 0 (pifr0) the register holds one set of the prot ocol-related individual interrupt flags. rbie receive buffer interrupt enable ? this flag controls if the receive buffer interrupt line is asserted when the rbif flag is set. 0 disable interrupt line 1 enable interrupt line tbie transmit interrupt enable ? this flag controls if the transmit buff er interrupt line is asserted when the tbif flag is set. 0 disable interrupt line 1 enable interrupt line base + 0x0018 write: normal mode 0123456789101112131415 rfatl _if intl _if ilcf _if csa _if mrc _if moc _if ccl _if mxs _if mtx _if lt x b _if lt x a _if tbvb _if tbva _if ti2 _if ti1 _if cys _if w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 22-11. protocol interrupt flag register 0 (pifr0) table 22-17. pifr0 field descriptions field description fatl_if fatal protocol error interrupt flag ? this flag is set when the protocol engine has detected a fatal protocol error. in this case, the protocol engine goes into the poc:halt state immediately. the fatal protocol errors are: 1) platesttx violation, as described in the mac process of the flexray protocol 2) transmission across slot boundary violation, as described in the fsp process of the flexray protocol 0 no such event. 1 fatal protocol error detected. intl_if internal protocol error interrupt flag ? this flag is set when the protocol engine has detected an internal protocol error. in this case, th e protocol engine goes into the poc:halt state immediately. an internal protocol error occurs when the protocol engine has not finished a calculation and a new calculation is requested. this can be caused by a hardware error. 0 no such event. 1 internal protocol error detected. ilcf_if illegal protocol configuration interrupt flag ? this flag is set when the protocol engine has detected an illegal protocol configuration parameter setting. in this case, the protocol engine goes into the poc:halt state immediately. the protocol engine checks the listen_timeout value programmed into the protocol configuration register 14 (pcr14) and protocol configuratio n register 15 (pcr15) when the config_complete command was sent by the application via the protocol operation control register (pocr) . if the value of listen_timeout is equal to zero, the protocol co nfiguration setting is considered as illegal. 0 no such event. 1 illegal protocol configuration detected. table 22-16. gifer field descriptions (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-23 pxr40 microcontroller reference manual, rev. 1 csa_if cold start abort interrupt flag ? this flag is set when the configured number of allowed cold start attempts is reached and none of these attempts was successful. the nu mber of allowed cold start attempts is configured by the coldstart_attempts field in the protocol configuratio n register 3 (pcr3) . 0 no such event. 1 cold start aborted and no more coldstart attempts allowed. mrc_if missing rate correction interrupt flag ? this flag is set when an insufficient number of measurements is available for rate correction at the end of the communication cycle. 0 no such event 1 insufficient number of measurements for rate correction detected moc_if missing offset corr ection interrupt flag ? this flag is set when an insufficient number of measurements is available for offset correction. this is related to the missing_term event in the csp process for offset correction in the flexray protocol. 0 no such event. 1 insufficient number of measurements for offset correction detected. ccl_if clock correction limit reached interrupt flag ? this flag is set when the internal calculated offset or rate calculation values have reached or exceeded its configured thresholds as given by the offset_coorection_out field in the protocol configuratio n register 9 (pcr9) and the rate_correction_out field in the protocol configuration register 14 (pcr14) . 0 no such event. 1 offset or rate correction limit reached. mxs_if max sync frames detected interrupt flag ? this flag is set when the number of synchronization frames detected in the current communicat ion cycle exceeds the value of the node_sync_max field in the protocol configuration register 30 (pcr30) . 0 no such event. 1 more than node_sync_max sync frames detected. note: only synchronization frames that have passed the syn chronization frame acceptance and rejection filters are taken into account. mtx_if media access test symbol received interrupt flag ? this flag is set when the mts symbol was received on channel a or channel b. 0 no such event. 1 mts symbol received. ltxb_if platesttx violation on channel b interrupt flag ? this flag is set when the frame transmission on channel b in the dynamic segment exceeds the dynamic segment boundary. this is related to the platesttx violation, as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel b. ltxa_if platesttx violation on channel a interrupt flag ? this flag is set when the frame transmission on channel a in the dynamic segment exceeds the dynamic segment boundary. this is related to the platesttx violation as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel a. tbvb_if transmission across boundary on channel b interrupt flag ? this flag is set when the frame transmission on channel b crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel b. table 22-17. pifr0 field descriptions (continued) field description
flexray communication controller (flexray) 22-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.12 protocol interrupt flag register 1 (pifr1) the register holds one set of the prot ocol-related individual interrupt flags. tbva_if transmission across boundary on channel a interrupt flag ? this flag is set when the frame transmission on channel a crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel a. ti2_if timer 2 expired interrupt flag ? this flag is set whenever timer 2 expires. 0 no such event. 1 timer 2 has reached its time limit. ti1_if timer 1 expired interrupt flag ? this flag is set whenever timer 1 expires. 0 no such event 1 timer 1 has reached its time limit cys_if cycle start interrupt flag ? this flag is set when a communication cycle starts. 0 no such event 1 communication cycle started. base + 0x001a write: normal mode 0123456789101112131415 remc _if ipc _if pecf _if psc _if ssi3 _if ssi2 _if ssi1 _if ssi0 _if 00 evt _if odt _if 0000 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 22-12. protocol interrupt flag register 1 (pifr1) table 22-18. pifr1 field descriptions field description emc_if error mode changed interrupt flag ? this flag is set when the valu e of the errmode bit field in the protocol status register 0 (psr0) is changed by the controller. 0 no such event. 1 errmode field changed. ipc_if illegal protocol control command interrupt flag ? this flag is set when the pe tries to execute a protocol control command, which was issued via the poccmd field of the protocol operation control register (pocr) , and detects that this protocol contro l command is not allowed in the current protocol state. in this case the command is not executed. for more details, see section 22.7.4, protocol control command execution . 0 no such event. 1 illegal protocol control command detected. pecf_if protocol engine communication failure interrupt flag ? this flag is set if th e controller has detected a communication failure between the protocol engine and the controller host interface 0 no such event. 1 protocol engine communication failure detected. psc_if protocol state changed interrupt flag ? this flag is set when the protocol state in the protstate field in the protocol status register 0 (psr0) has changed. 0 no such event. 1 protocol state changed. table 22-17. pifr0 field descriptions (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-25 pxr40 microcontroller reference manual, rev. 1 22.5.2.13 protocol interrupt enable register 0 (pier0) this register defines whether or not the individual interrupt flags defined in the protocol interrupt flag register 0 (pifr0) can generate a protocol interrupt request. ssi3_if ssi2_if ssi1_if ssi0_if slot status counter incr emented interrupt flag ? each of these flags is set when the slotstatuscnt field in the corresponding slot status counter registers (sscr0?sscr3) is incremented . 0 no such event. 1 the corresponding slot status counter has incremented. evt_if even cycle table written interrupt flag ? this flag is set if the controller has written the sync frame measurement / id tables into the flexray memory for the even cycle. 0 no such event. 1 sync frame measurement table written odt_if odd cycle table written interrupt flag ? this flag is set if the controller has written the sync frame measurement / id tables into the flexray memory for the odd cycle. 0 no such event. 1 sync frame measurement table written base + 0x001c write: anytime 0123456789101112131415 r fatl _ie intl _ie ilcf _ie csa _ie mrc _ie moc _ie ccl _ie mxs _ie mtx _ie lt x b _ie lt x a _ie tbvb _ie tbva _ie ti2 _ie ti1 _ie cys _ie w reset0000000000000000 figure 22-13. protocol interrupt enable register 0 (pier0) table 22-19. pier0 field descriptions field description fatl_ie fatal protocol error interrupt enable ? this bit controls fatl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled intl_ie internal protocol error interrupt enable ? this bit controls intl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ilcf_ie illegal protocol configuration interrupt enable ? this bit controls ilcf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled csa_ie cold start abort interrupt enable ? this bit controls csa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mrc_ie missing rate correction interrupt enable ? this bit controls mrc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled moc_ie missing offset correct ion interrupt enable ? this bit controls moc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled table 22-18. pifr1 field descriptions (continued) field description
flexray communication controller (flexray) 22-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.14 protocol interrupt enable register 1 (pier1) this register defines whether or not th e individual interrupt flags defined in protocol interrupt flag register 1 (pifr1) can generate a protocol interrupt request. ccl_ie clock correction limit reached interrupt enable ? this bit controls ccl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mxs_ie max sync frames detected interrupt enable ? this bit controls mxs_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mtx_ie media access test symbol received interrupt enable ? this bit controls mt x_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ltxb_ie platesttx violation on channel b interrupt enable ? this bit controls ltxb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ltxa_ie platesttx violation on channel a interrupt enable ? this bit controls ltxa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled tbvb_ie transmission across boundary on channel b interrupt enable ? this bit controls t bvb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled tbva_ie transmission across boundary on channel a interrupt enable ? this bit controls tbva_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ti2_ie timer 2 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ti1_ie timer 1 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled cys_ie cycle start interrupt enable ? this bit controls cyc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled base + 0x001e write: anytime 0123456789101112131415 r emc _ie ipc _ie pecf _ie psc _ie ssi3 _ie ssi2 _ie ssi1 _ie ssi0 _ie 00 evt _ie odt _ie 0000 w reset0000000000000000 figure 22-14. protocol interrupt enable register 1 (pier1) table 22-19. pier0 field descriptions (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-27 pxr40 microcontroller reference manual, rev. 1 22.5.2.15 chi error flag register (chierfr) this register holds the chi related error flags. the interrupt generation for each of these error flags is controlled by the chi interrupt enable bit chie in the global interrupt flag and enable register (gifer) . table 22-20. pier1 field descriptions field description emc_ie error mode changed interrupt enable ? this bit controls emc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ipc_ie illegal protocol control command interrupt enable ? this bit controls ipc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled pecf_ie protocol engine communication failure interrupt enable ? this bit controls pecf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled psc_ie protocol state changed interrupt enable ? this bit controls psc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ssi3_ie ssi2_ie ssi1_ie ssi0_ie slot status counter incr emented interrupt enable ? this bit controls ssi[3:0]_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled evt_ie even cycle table written interrupt enable ? this bit controls evt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled odt_ie odd cycle table written interrupt enable ? this bit controls odt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled base + 0x0020 write: normal mode 0123456789101112131415 rfrlb _ef frla _ef pcmi _ef fovb _ef fova _ef mbs _ef mbu _ef lck _ef dbl _ef sbcf _ef fid _ef dpl _ef spl _ef nml _ef nmf _ef ilsa _ef w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 22-15. chi error flag register (chierfr)
flexray communication controller (flexray) 22-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 22-21. chierfr field descriptions field description frlb_ef frame lost channel b error flag ? this flag is set if a complete frame was received on channel b but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. in this case, the frame and the related slot status information are lost. 0 no such event 1 frame lost on channel b detected frla_ef frame lost channel a error flag ? this flag is set if a complete frame was received on channel a but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. in this case, the frame and the related slot status information are lost. 0 no such error 1 frame lost on channel a detected pcmi_ef protocol command ignored error flag ? this flag is set if the application has issued a poc command by writing to the poccmd field in the protocol operation control register (pocr) while the bsy flag is equal to 1. in this case the command is ignored by the controller and is lost. 0 no such error 1 poc command ignored fovb_ef receive fifo overrun channel b error flag ? this flag is set when an overrun of the fifo for channel b occurred. this error occurs if a semantically valid fram e was received on channel b and matches the all criteria to be appended to the fifo for channel b but the fifo is full. in this case, th e received frame and its related slot status information is lost. 0 no such error 1 fifo overrun on channel b has been detected fova_ef receive fifo overrun channel a error flag ? this flag is set when an overrun of the fifo for channel a occurred. this error occurs if a semantically valid fram e was received on channel a and matches the all criteria to be appended to the fifo for channel a but the fifo is full. in this case, th e received frame and its related slot status information is lost. 0 no such error 1 fifo overrun on channel b has been detected msb_ef message buffer search error flag ? this flag is set if the message buffer search engine is still running while the next search cycle must be started due to the flexray protocol timing. in this case, not all message buffers are considered while searching. 0 no such event 1 search engine active while search start appears mbu_ef message buffer utilization error flag ? this flag is asserted if the application writes to a message buffer control field that is beyond the number of utilized message buffers programmed in the message buffer segment size and utilizati on register (mbssutr) . if the application writes to a mbccsrn register with n > last_m b_util, the controller i gnores the write attempt and asserts the message buffer utilization error flag mbu_ef in the chi error flag register (chierfr) . 0 no such event 1 non-utilized message buffer enabled lck_ef lock error flag ? this flag is set if the application tries to lock a message buffer that is already locked by the controller due to internal operations. in that case, the controller does not grant the lock to the application. the application must issue the lock request again. 0 no such error 1 lock error detected dbl_ef double transmit message buffer lock error flag ? this flag is set if the application tries to lock the transmit side of a double transmit message buffer. in this case, the c ontroller does not grant the lock to the transmit side of a double transmit message buffer. 0 no such event 1 double transmit buffer lock error occurred
flexray communication controller (flexray) freescale semiconductor 22-29 pxr40 microcontroller reference manual, rev. 1 22.5.2.16 message buffer interrupt vector register (mbivec) sbcf_ef system bus communication failure error flag ? this flag is set if a system bus access was not finished within the required amount of time (see section 22.6.19.2, syst em bus access timeout ). 0 no such event 1 system bus access not finished in time fid_ef frame id error flag ? this flag is set if the frame id stored in the message buffer header area differs from the frame id stored in the message buffer control register. 0 no such error occurred 1 frame id error occurred dpl_ef dynamic payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the dynamic segment is greater than the maximum payload length for the dynamic segment as it is configured in the correspond ing protocol configuration register field max_payload_length_dynamic in the protocol configuration register 24 (pcr24) . 0 no such error occurred 1 dynamic payload length error occurred spl_ef static payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assig ned to the static segment is different from the payload length for the static segment as it is configured in the corresponding protocol c onfiguration register field payload_length_static in the protocol configuration register 19 (pcr19) . 0 no such error occurred 1 static payload length error occurred nml_ef network management length error flag ? this flag is set if the payload length written into the header structure of a receive message buffer assigned to the st atic segment is less than t he configured length of the network management vector as configured in the network management vector length register (nmvlr) . in this case the received part of the network managemen t vector will be used to update the network management vector. 0 no such error occurred 1 network management length error occurred nmf_ef network management frame error flag ? this flag is set if a received message in the static segment with a preamble indicator flag pp asserted has its null frame indi cator flag nf asserted as well. in this case, the global network management registers (see network management vector registers (nmvr0?nmvr5) ) are not updated. 0 no such error occurred 1 network management frame error occurred ilsa_ef illegal system bus address error flag ? this flag is set if the extern al system bus subsystem has detected an access to an illegal system bus ad dress from the c ontroller (see section 22.6.19.1, s ystem bus illegal address access ). 0 no such event 1 illegal system bus address accessed base + 0x0022 0123456789101112131415 r 0 tbivec 0 rbivec w reset0000000000000000 figure 22-16. message buffer interrupt vector register (mbivec) table 22-21. chierfr field descriptions (continued) field description
flexray communication controller (flexray) 22-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 this register indicates the lowest numbered receive message buffer and the lo west numbered transmit message buffer that have their interr upt status flag mbif and interrupt enable mbie bits asserted. this means that message buffers with lower me ssage buffer numbers have higher priority. 22.5.2.17 channel a status erro r counter register (casercr) this register provides the channel st atus error counter for channel a. th e protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, a nd the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror, vss!cont enterror, vss!bviolation , and vss!txconflict . the controller increments the status error counter by 1 if, for a slot or segment, at least one error indicator bit is set to 1. the counter wrap s around after it has reached the maximum value. for more information on slot status monitoring, see section 22.6.18, slot status monitoring . 22.5.2.18 channel b status erro r counter register (cbsercr) table 22-22. mbivec field descriptions field description tbivec transmit buffer interrupt vector ? this field provides the number of the lowest numbered enabled transmit message buffer that has its interrupt stat us flag mbif and its interrupt enable bit mbie set. if there is no transmit message buffer with the interrupt status flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. rbivec receive buffer interrupt vector ? this field provides the message buffer number of the lowest numbered receive message buffer which has its interrupt flag mbif and its interrupt enable bit mbie asserted. if there is no receive message buffer with the interrupt status flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. base + 0x0024 a dditional reset: run command 0123456789101112131415 r status_err_cnt w reset0000000000000000 figure 22-17. channel a status er ror counter register (casercr) table 22-23. casercr field descriptions field description status_err_cnt channel status error counter ? this field provides the current va lue channel status error counter. the counter value is updated within the first ma crotick of the following slot or segment. base + 0x0026 additional reset: run command 0123456789101112131415 r status_err_cnt w reset0000000000000000 figure 22-18. channel b status er ror counter register (cbsercr)
flexray communication controller (flexray) freescale semiconductor 22-31 pxr40 microcontroller reference manual, rev. 1 this register provides the channel st atus error counter for channel b. th e protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, a nd the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror , vss!contenterror , vss!bviolation , and vss!txconflict . the controller increments the status error counter by 1 if, for a slot or segment, at least one error indicator bit is set to 1. the counter wrap s around after it has reached the maximum value. for more information on slot status monitoring see section 22.6.18, slot status monitoring . 22.5.2.19 protocol status register 0 (psr0) this register provides information about the current protocol status. table 22-24. cbsercr field descriptions field description status_err_cnt channel status error counter ? this field provides the current cha nnel status error count. the counter value is updated within the first macrot ick of the following slot or segment. base + 0x0028 0123456789101112131415 r errmode slotmode 0 protstate startupstate 0 wakeupstatus w reset0000000000000000 figure 22-19. protocol status register 0 (psr0) table 22-25. psr0 field descriptions field description errmode error mode ? protocol related variable: vpoc!errormode . this field indicates the error mode of the protocol. 00 active 01 passive 10 comm_halt 11 reserved slotmode slot mode ? protocol related variable: vpoc!slotmode . this field indicates the slot mode of the protocol. 00 single 01 all_pending 10 all 11 reserved protstate protocol state ? protocol related variable: vpoc!state. this field indicates t he state of the protocol. 000 poc:default config 001 poc:config 010 poc:wakeup 011 poc:ready 100 poc:normal passive 101 poc:normal active 110 poc:halt 111 poc:startup
flexray communication controller (flexray) 22-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.20 protocol status register 1 (psr1) startup state startup state ? protocol related variable: vpoc!startupstate. this field indicates the current sub-state of the startup procedure. 0000 reserved 0001 reserved 0010 poc:coldstart collision resolution 0011 poc:coldstart listen 0100 poc:integration consistency check 0101 poc:integrationi listen 0110 reserved 0111 poc:initialize schedule 1000 reserved 1001 reserved 1010 poc:coldstart consistency check 1011 reserved 1100 reserved 1101 poc:integration coldstart check 1110 poc:coldstart gap 1111 poc:coldstart join wakeup status wakeup status ? protocol related variable: vpoc!wakeupstatus . this field provides the outcome of the execution of the wakeup mechanism. 000 undefined 001 received_header 010 received_wup 011 collision_header 100 collision_wup 101 collision_unknown 110 transmitted 111 reserved base + 0x002a additional re set: csaa, csp, cpn: run command write: normal mode 0123456789101112131415 r csaa csp 0 remcsat cpn hhr frz aptac ww1c reset0000000000000000 figure 22-20. protocol status register 1 (psr1) table 22-26. psr1 field descriptions field description csaa cold start attempt aborted flag ? protocol related event: ?set coldstart abort indicator in chi? this flag is set when the controller has aborted a cold start attempt. 0 no such event 1 cold start attempt aborted csp leading cold start path ? this status bit is set when the controller has reached the poc:normal active state via the leading cold start path. this indicates that this node has started the network 0 no such event 1 poc:normal active reached from poc:startup state via leading cold start path table 22-25. psr0 field descriptions (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-33 pxr40 microcontroller reference manual, rev. 1 22.5.2.21 protocol status register 2 (psr2) this register provides a snapshot of status inform ation about the network idle time nit, the symbol window and the clock synchronizati on. the nit related status bits nbvb, nseb, nbva, and nsea are updated by the controller after the e nd of the nit and before the end of the first slot of the next communication cycle. the symbol wi ndow related status bits stcb , sbvb, sseb, mtb, stca, sbva, sseb, and mta are updated by the cont roller after the end of the symb ol window and before the end of the current communication cycle. if no symbol window is configured, the symbol window related status bits remain in their reset state. the clock sync hronization related clkcorrf ailcnt is updated by the controller after the end of the static segment and before the end of the cu rrent communication cycle. remcsat remaining coldstart attempts ? protocol related variable: vremainingcoldstartattempts this field provides the number of remaining cold start attempts that th e controller will execute. cpn leading cold start path noise ? protocol related variable: vpoc!coldstartnoise this status bit is set if t he controller has reached the poc:normal active state via the leading cold start path under noise conditions. this indicates there was some activity on the flexray bus while the controller was starting up the cluster. 0 no such event 1 poc:normal active state was reached from poc:startup state via noisy leading cold start path hhr host halt request pending ? protocol related variable: vpoc!chihaltrequest this status bit is set when controller receives the halt command from the application via the protocol operation control register (pocr) . the controller clears this st atus bit after a hard reset cond ition or when the protocol is in the poc:default config state. 0 no such event 1 halt command received frz freeze occurred ? protocol related variable: vpoc!freeze this status bit is set when the controller has reached the poc:halt state due to the host freeze command or due to an internal error condition requiring immediate halt. the controller clears this status bit after a hard reset condition or when the protocol is in the poc:default config state. 0 no such event 1 immediate halt due to freeze or internal error condition aptac allow passive to active counter ? protocol related variable: vpoc!vallowpassivetoactive this field provides the number of consecutive even/odd communication cycle pairs that have passed with valid rate and offset correction terms, but the protocol is still in the poc:normal passive state due to an application configured delay to enter poc:normal active state. this delay is defined by the allow_passive_to_active field in the protocol configuration register 12 (pcr12) . base + 0x002c additional reset: run command 0123456789101112131415 r nbvb nseb stcb sbvb sseb mtb nbva nsea stca sbva ssea mta clkcorrfailcnt w reset0000000000000000 figure 22-21. protocol status register 2 (psr2) table 22-26. psr1 field descriptions (continued) field description
flexray communication controller (flexray) 22-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 22-27. psr2 field descriptions field description nbvb nit boundary violation on channel b ? protocol related variable: vss!bviolation for nit on channel b this status bit is set when there was some media activi ty on the flexray bus channel b at the end of the nit. 0 no such event 1 media activity at boundaries detected nseb nit syntax error on channel b ? protocol related variable: vss!syntaxerror for nit on channel b this status bit is set when a syntax error was detected during nit on channel b. 0 no such event 1 syntax error detected stcb symbol window transmit conflict on channel b ? protocol related variable: vss!txconflict for symbol window on channel b this status bit is set if there was a transmissi on conflict during the symbol window on channel b. 0 no such event 1 transmission conflict detected sbvb symbol window boundary violation on channel b ? protocol related variable: vss!bviolation for symbol window on channel b this status bit is set if there was some media activity on the flexray bus channel b at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected sseb symbol window syntax error on channel b ? protocol related variable: vss!syntaxerror for symbol window on channel b this status bit is set when a syntax error was detected during the symbol window on channel b. 0 no such event 1 syntax error detected mtb media access test symbol mts received on channel b ? protocol related variable: vss!validmts for symbol window on channel b this status bit is set if the media access test sy mbol mts was received in the symbol window on channel b. 0 no such event 1 mts symbol received nbva nit boundary violation on channel a ? protocol related variable: vss!bviolation for nit on channel a this status bit is set when there was some media activi ty on the flexray bus channel a at the end of the nit. 0 no such event 1 media activity at boundaries detected nsea nit syntax error on channel a ? protocol related variable: vss!syntaxerror for nit on channel a this status bit is set when a syntax error was detected during nit on channel a. 0 no such event 1 syntax error detected stca symbol window transmit conflict on channel a ? protocol related variable: vss!txconflict for symbol window on channel a this status bit is set if there was a transmission conflicts during the symbol window on channel a. 0 no such event 1 transmission conflict detected sbva symbol window boundary violation on channel a ? protocol related variable: vss!bviolation for symbol window on channel a this status bit is set if there was some media activity on the flexray bus channel a at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected
flexray communication controller (flexray) freescale semiconductor 22-35 pxr40 microcontroller reference manual, rev. 1 22.5.2.22 protocol status register 3 (psr3) this register provides aggregated ch annel status information as an accrued status of channel activity for all communication slots, re gardless of whether they are assigne d for transmission or subscribed for reception. it provides accrued information for the symbol window, the nit, and the wakeup status. ssea symbol window syntax error on channel a ? protocol related variable: vss!syntaxerror for symbol window on channel a this status bit is set when a syntax error wa s detected during the symbol window on channel a. 0 no such event 1 syntax error detected mta media access test symbol mts received on channel a ? protocol related variable: vss!validmts for symbol window on channel a this status bit is set if the media access test sy mbol mts was received in the symbol window on channel a. 1 mts symbol received 0 no such event clkcorr- failcnt clock correction failed counter ? protocol related variable: vclockcorrectionfailed this field provides the number of consecutive even /odd communication cycle pairs that have passed without clock synchronization having performed an offset or a rate correction due to lack of synchronization frames. it is not incremented when it has reached the configured value of either max_without_clock_correction_fatal or max_without_clock_correction_passive as defined in the protocol configuration register 8 (pcr8) . the controller resets this counter on a hard rese t condition, when the protocol enters the poc:normal active state, or when both the rate and offset correctio n terms have been calculated successfully. base + 0x002e additional reset: run command write: normal mode 0123456789101112131415 r 0 0 wub abvb aacb aceb aseb avfb 0 0 wua abva aaca acea asea avfa w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 22-22. protocol status register 3 (psr3) table 22-28. psr3 field descriptions field description wub wakeup symbol received on channel b ? this flag is set when a wakeup symbol was received on channel b. 0 no wakeup symbol received 1 wakeup symbol received abvb aggregated boundary violation on channel b ? this flag is set when a boundary violation has been detected on channel b. boundary violations are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected aacb aggregated additional co mmunication on channel b ? this flag is set when at least one valid frame was received on channel b in a slot that also contained an additional communication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected table 22-27. psr2 field descriptions (continued) field description
flexray communication controller (flexray) 22-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.23 macrotick counter register (mtctr) aceb aggregated content error on channel b ? this flag is set when a content error has been detected on channel b. content errors are detected in the communication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected aseb aggregated syntax error on channel b ? this flag is set when a synta x error has been detected on channel b. syntax errors are detected in the co mmunication slots, the symbol window and the nit. 0 no syntax error detected 1 syntax errors detected avfb aggregated valid frame on channel b ? this flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel b. 1 at least one syntactically valid frame received 0 no syntactically valid frames received wua wakeup symbol received on channel a ? this flag is set when a wakeup symbol was received on channel a. 0 no wakeup symbol received 1 wakeup symbol received abva aggregated boundary violation on channel a ? this flag is set when a boundary violation has been detected on channel a. boundary violat ions are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected aaca aggregated additional co mmunication on channel a ? this flag is set when a valid frame was received in a slot on channel a that also contained an additional co mmunication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected acea aggregated content error on channel a ? this flag is set when a content error has been detected on channel a. content errors are detected in the co mmunication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected asea aggregated syntax error on channel a ? this flag is set when a syntax error has been detected on channel a. syntax errors are detected in the comm unication slots, the symbol window, and the nit. 0 no syntax error detected 1 syntax errors detected avfa aggregated valid frame on channel a ? this flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel a. 0 no syntactically valid frames received 1 at least one syntactically valid frame received base + 0x0030 0123456789101112131415 r0 0 mtct w reset0000000000000000 figure 22-23. macrotick counter register (mtctr) table 22-28. psr3 field descriptions (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-37 pxr40 microcontroller reference manual, rev. 1 this register provides the macrotick c ount of the current communication cycle. 22.5.2.24 cycle counter register (cyctr) this register provides the number of the current communication cycle. 22.5.2.25 slot counter chan nel a register (sltctar) this register provides the number of the current slot in the curren t communication cycle for channel a. table 22-29. mtctr field descriptions field description mtct macrotick counter ? protocol related variable: vmacrotick this field provides the macrotick count of the current communication cycle. base + 0x0032 0123456789101112131415 r0000000000 cy ccnt w reset0000000000000000 figure 22-24. cycle counter register (cyctr) table 22-30. cyctr field descriptions field description cyccnt cycle counter ? protocol related variable: vcyclecounter this field provides the numb er of the current communication cycle. if the counter reaches the maximum value of 63, the counter wraps and starts from zero again. base + 0x0034 0123456789101112131415 r00000 slotcnta w reset0000000000000000 figure 22-25. slot counter channel a register (sltctar) table 22-31. sltctar field descriptions field description slotcnta slot counter value for channel a ? protocol related variable: vslotcounter for channel a this field provides the number of the curr ent slot in the current communication cycle.
flexray communication controller (flexray) 22-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.26 slot counter chan nel b register (sltctbr) this register provides the number of the current slot in the curren t communication cycle for channel b. 22.5.2.27 rate correction value register (rtcorvr) this register provides the sign extende d rate correction value in microticks as it was calculated by the clock synchronization algorithm. the controller updates th is register during the nit of each odd numbered communication cycle. base + 0x0036 0123456789101112131415 r00000 slotcntb w reset0000000000000000 figure 22-26. slot counter channel b register (sltctbr) table 22-32. sltctbr field descriptions field description slotcnta slot counter value for channel b ? protocol related variable: vslotcounter for channel b this field provides the number of the curr ent slot in the current communication cycle. base + 0x0038 additional reset: run command 0123456789101112131415 rratecorr w reset0000000000000000 figure 22-27. rate correction value register (rtcorvr) table 22-33. rtcorvr field descriptions field description ratecorr rate correction value ? protocol related variable: vratecorrection (before value limitation and external rate correction) this field provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the applicat ion of the external rate correction. if the magnitude of the internally calculated rate correction value exceeds the limit given by rate_correction_out in the protocol configuration register 13 (pcr13) , the clock correction reached limit interrupt flag ccl_if is set in the protocol interrupt flag register 0 (pifr0) . note: if the controller was not able to calculate a new ra te correction term due to a lack of synchronization frames, the ratecorr value is not updated.
flexray communication controller (flexray) freescale semiconductor 22-39 pxr40 microcontroller reference manual, rev. 1 22.5.2.28 offset correction value register (ofcorvr) this register provides the sign extend ed offset correction value in micro ticks as it was calculated by the clock synchronization algorithm. the controll er updates this register during the nit. 22.5.2.29 combined interrupt flag register (cifrr) this register provides five combined interrupt flag s and a copy of three individual interrupt flags. the combined interrupt flags are the result of a binary or of the values of other interrupt flags regardless of the state of the interrupt enable bits . the generation scheme for the combin ed interrupt flags is depicted in figure 22-152 . the individual interrupt flags wupif, fafb if, and fafaif are copies of corresponding flags in the global interrupt flag and enable register (gifer) and are provided here to simplify the application interrupt flag check. to clear the indivi dual interrupt flags, the application must use the global interrupt flag and enable register (gifer) . note the meanings of the combined status bits mif, prif, chif, rbif, and tbif are different from those mentioned in the global interrupt flag and enable register (gifer) . base + 0x003a additional reset: run command 0123456789101112131415 r offsetcorr w reset0000000000000000 figure 22-28. offset correction value register (ofcorvr) table 22-34. ofcorvr field descriptions field description offset- corr offset correction value ? protocol related variable: voffsetcorrection (before value limitation and external offset correction) this field provides the sign extended offset correction value in microticks as it wa s calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the application of the external offset correction. if the magnitude of the internally calculated rate correction value exceeds the limit giv en by offset_correction_out field in the protocol configuration register 29 (pcr29) , the clock correction reached limit in terrupt flag ccl_if is set in the protocol interrupt flag register 0 (pifr0) . note: if the controller was not able to calculate an new offs et correction term due to a lack of synchronization frames, the offsetcorr value is not updated. base + 0x003c 0123456789101112131415 r 00000000mifprifchif wup if fafb if fafa if rbif tbif w reset0000000000000000 figure 22-29. combined interrupt flag register (cifrr)
flexray communication controller (flexray) 22-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.30 system memo ry access time-out register (symator) table 22-35. cifrr field descriptions field description mif module interrupt flag ? this flag is set if there is at least one interrupt source that has its interrupt flag asserted. 0 no interrupt source has its interrupt flag asserted 1 at least one interrupt source has its interrupt flag asserted prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag register 0 (pifr0) or protocol interrupt flag register 1 (pifr1) is equal to 1. 0 all individual protocol interrupt flags are equal to 0 1 at least one of the individual protocol interrupt flags is equal to 1 chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (chierfr) is equal to 1. 0 all chi error flags are equal to 0 1 at least one chi error flag is equal to 1 wupif wakeup interrupt flag ? provides the same value as gifer[wupif] fafbif receive fifo channel b almost full interrupt flag ? provides the same value as gifer[fafbif] fafaif receive fifo channel a almost full interrupt flag ? provides the same value as gifer[fafaif] rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (mbccsrn[mtd] = 0) the inte rrupt flag mbif in the corresponding message buffer configuration, control, status registers (mbccsrn) is equal to 1. 0 none of the individual receive message buffers has the mbif flag asserted. 1 at least one individual receive message buffers has the mbif flag asserted. tbif transmit message buffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (mbccsrn[mtd] = 1) the interrupt flag mbif in the corresponding message buffer configuration, control, status registers (mbccsrn) is equal to 1. 0 none of the individual transmit message buffers has the mbif flag asserted. 1 at least one individual transmit message buffers has the mbif flag asserted. base + 0x003e write: disabled mode 0123456789101112131415 r00000000 timeout w reset0000000000000100 figure 22-30. system memory access time-out register (symator) table 22-36. symator field descriptions field description timeout system memory access time-out ? this value defines the maximum amou nt of time to finish a system bus access in order to ensure correct frame transmission and reception (see section 22.6.19.2, s ystem bus access timeout ).
flexray communication controller (flexray) freescale semiconductor 22-41 pxr40 microcontroller reference manual, rev. 1 22.5.2.31 sync frame counter register (sfcntr) this register provides the number of synchronization fram es that are used for cl ock synchronization in the last even and in the last odd numbere d communication cycle. this register is updated after the start of the nit and before 10 mt afte r offset correction start. note if the application has locked the even synchronization table at the end of the static segment of an even communica tion cycle, the c ontroller will not update the fields sfevb and sfeva. if the application has locked the odd sy nchronization table at the end of the static segment of an odd communication cycle, the controll er will not update the values sfodb and sfoda. 22.5.2.32 sync frame table offset register (sftor) this register defines the flexray memory related of fset for sync frame tables . for more details, see section 22.6.12, sync frame id and sync frame deviation tables . base + 0x0040 additional reset: run command 0123456789101112131415 r sfevb sfeva sfodb sfoda w reset0000000000000000 figure 22-31. sync frame counter register (sfcntr) table 22-37. sfcntr field descriptions field description sfevb sync frames channel b, even cycle ? protocol related variable: size of ( vssyncidlistb for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfevb sync frames channel a, even cycle ? protocol related variable: size of ( vssyncidlista for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfodb sync frames channel b, odd cycle ? protocol related variable: size of ( vssyncidlistb for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfoda sync frames channel a, odd cycle ? protocol related variable: size of ( vssyncidlista for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. base + 0x0042 write: poc:config 0123456789101112131415 r sft_offset[15:1] 0 w reset0000000000000000 figure 22-32. sync frame table offset register (sftor)
flexray communication controller (flexray) 22-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.33 sync frame table configuratio n, control, status register (sftccsr) this register provides configurati on, control, and status information related to the generation and access of the clock sync id tables a nd clock sync measurement tables. for a detailed description, see section 22.6.12, sync frame id and sync frame deviation tables . table 22-38. sftor field description field description sftor sync frame table offset ? the offset of the sync frame tables in t he flexray memory. this offset is required to be 16-bit aligned. thus stf_offset[0] is always 0. base + 0x0044 write: normal mode 0123456789101112131415 r 0 0 cycnum elks olks eval oval 0 0 sdv en sid en w elkt olkt opt reset0000000000000000 figure 22-33. sync frame table configurat ion, control, status register (sftccsr) table 22-39. sftccsr field descriptions field description elkt even cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the even cycle tables. 0no effect 1 triggers lock/unlock of the even cycle tables. olkt odd cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the odd cycle tables. 0no effect 1 triggers lock/unlock of the odd cycle tables. cycnum cycle number ? this field provides the number of the cycle in which the curr ently locked table was recorded. if none or both tables are locked, this value is related to the even cycle table. elks even cycle tables lock status ? this status bit indicates whether the application has locked the even cycle tables. 0 application has not locked the even cycle tables. 1 application has locked the even cycle tables. olks odd cycle tables lock status ? this status bit indica tes whether the applicatio n has locked the odd cycle tables. 0 application has not locked the odd cycle tables. 1 application has locked the odd cycle tables. eval even cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the even cycle are valid. the controller clears th is status bit when it star ts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent). oval odd cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the odd cycle are valid. the controller clears this st atus bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent).
flexray communication controller (flexray) freescale semiconductor 22-43 pxr40 microcontroller reference manual, rev. 1 22.5.2.34 sync frame id rejectio n filter register (sfidrfr) this register defines the s ync frame rejection filter id. the application must upda te this register outside of the static segment. if the applic ation updates this register in the stat ic segment, it can appear that the controller accepts the sync frame in the current cycle. opt one pair trigger ? this trigger bit controls whether the contro ller writes continuously or only one pair of sync frame tables into the flexray memory. if this trigger is set to 1 while sdven or siden is set to 1, the controller writes only one pair of the enabled sync frame tables corresponding to the next even-odd-cycle pair into the flexray memory. in this case, the controller clears the sdven or siden bits immediately. if this trigger is set to 0 while sdven or siden is set to 1, the controller writes continuously the enabled sync frame tables into the flexray memory. 0 write continuously pairs of enabled sync frame tables into flexray memory. 1 write only one pair of enabled sync frame tables into flexray memory. sdven sync frame deviation table enable ? this bit controls the generation of the sync frame deviation tables. the application must set this bit to r equest the controller to write the sy nc frame deviation tables into the flexray memory. 0 do not write sync frame deviation tables 1 write sync frame deviation tables into flexray memory note: if sdven is set to 1, then siden must also be set to 1. siden sync frame id table enable ? this bit controls the generation of the sync frame id tables. the application must set this bit to 1 to request the controll er to write the sync frame id tables into the flexray memory. 0 do not write sync frame id tables 1 write sync frame id ta bles into flexray memory base + 0x0046 16-bit write access required write: normal mode 0123456789101112131415 r000000 synfrid w reset0000000000000000 figure 22-34. sync frame id rej ection filter register (sfidrfr) table 22-40. sfidrfr field descriptions field description synfrid sync frame rejection id ? this field defines the frame id of a frame that must not be used for clock synchronization. for details see section 22.6.15.2, sync frame rejection filtering . table 22-39. sftccsr field descriptions (continued) field description
flexray communication controller (flexray) 22-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.35 sync frame id acceptance filter value register (sfidafvr) this register defines the sync frame acceptanc e filter value. for details on filtering, see section 22.6.15, sync frame filtering . 22.5.2.36 sync frame id acceptance filter mask register (sfidafmr) this register defines the sync frame acceptance filter mas k. for details on filtering see section 22.6.15.1, sync frame acceptance filtering . 22.5.2.37 network management vector registers (nmvr0?nmvr5) base + 0x0048 write: poc:config 0123456789101112131415 r000000 fval w reset0000000000000000 figure 22-35. sync frame id acceptance filter value register (sfidafvr) table 22-41. sfidafvr field descriptions field description fval filter value ? this field defines the value for the sync frame acceptance filtering. base + 0x004a write: poc:config 0123456789101112131415 r000000 fmsk w reset0000000000000000 figure 22-36. sync frame id acceptance filter mask register (sfidafmr) table 22-42. sfidafmr field descriptions field description fmsk filter mask ? this field defines the mask for the sync frame acceptance filtering. base + 0x004c (nmvr0) base + 0x004e (nmvr1) base + 0x0050 (nmvr2) base + 0x0052 (nmvr3) base + 0x0054 (nmvr4) base + 0x0056 (nmvr5) 0123456789101112131415 r nmvp[15:8] nmvp[7:0] w reset0000000000000000 figure 22-37. network management vector registers (nmvr0?nmvr5)
flexray communication controller (flexray) freescale semiconductor 22-45 pxr40 microcontroller reference manual, rev. 1 each of these six registers holds one part of the network management vector. the length of the network management vector is configured in the network management vector length register (nmvlr) . if nmvlr is programmed with a valu e that is less than 12 bytes, the remaining bytes of the network management vector registers (nmvr0?nmvr5) , which are not used for the network management vector accumulating, will remain 0. the nmvr provides accrued information over all recei ved nmvs in the last communication cycle. all nmvs received in one cycle are ored into the nmvr. the nmvr is updated at the end of the communication cycle. 22.5.2.38 network management vector length register (nmvlr) this register defines the length of th e network management vector in bytes. table 22-43. nmvr[0:5] field descriptions field description nmvp network management vector part ? the mapping between the network management vector registers (nmvr0?nmvr5) and the receive message buffer payload bytes in nmv[0:11] is depicted in table 22-44 . table 22-44. mapping of nmvrn to the received payload bytes nmvn nmvrn register nmvn received payload nmvr0[nmvp[15:8]] nmv0 nmvr0[nmvp[7:0]] nmv1 nmvr1[nmvp[15:8]] nmv2 nmvr1[nmvp[7:0]] nmv3 ... nmvr5[nmvp[15:8]] nmv10 nmvr5[nmvp[7:0]] nmv11 base + 0x0058 write: poc:config 0123456789101112131415 r000000000000 nmvl w reset0000000000000000 figure 22-38. network management vector length register (nmvlr) table 22-45. nmvlr field descriptions field description nmvl network management vector length ? protocol related variable: gnetworkmanagementvectorlength this field defines the length of th e network management vector in byte s. legal values are between 0 and 12.
flexray communication controller (flexray) 22-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.39 timer configuration a nd control register (ticcr) this register is used to configure and control the two timers t1 and t2. for timer details, see section 22.6.17, timer support . the timer t1 is an absolute timer. the timer t2 can be configured as an absolute or relative timer. note both timers are deactivated immediatel y when the protocol enters a state different from poc:normal active or poc:normal passive . base + 0x005a write: t2_cfg: poc:config t2_rep, t1_rep, t1sp, t2sp, t1tr, t2tr: normal mode 0123456789101112131415 r0 0 t2_ cfg t2_ rep 000t2st000 t1_ rep 000t1st w t2sp t2tr t1sp t1tr reset0000000000000000 figure 22-39. timer configuration and control register (ticcr) table 22-46. ticcr field descriptions field description t2_cfg timer t2 configuration ? this bit configures the timebase mode of timer t2. 0 t2 is absolute timer. 1 t2 is relative timer. t2_rep timer t2 repetitive mode ? this bit configures the repetition mode of timer t2. 0 t2 is non repetitive 1 t2 is repetitive t2sp timer t2 stop ? this trigger bit is used to stop timer t2. 0 no effect 1 stop timer t2 t2tr timer t2 trigger ? this trigger bit is used to start timer t2. 0 no effect 1 start timer t2 t2st timer t2 state ? this status bit provides the current state of timer t2. 0 timer t2 is idle 1 timer t2 is running t1_rep timer t1 repetitive mode ? this bit configures the repetition mode of timer t1. 0 t1 is non repetitive 1 t1 is repetitive t1sp timer t1 stop ? this trigger bit is used to stop timer t1. 0 no effect 1 stop timer t1 t1tr timer t1 trigger ? this trigger bit is used to start timer t1. 0 no effect 1 start timer t1 t1st timer t1 state ? this status bit provides the current state of timer t1. 0 timer t1 is idle 1 timer t1 is running
flexray communication controller (flexray) freescale semiconductor 22-47 pxr40 microcontroller reference manual, rev. 1 22.5.2.40 timer 1 cycle set register (ti1cysr) this register defines the cycle filter value and the cycle filter mask for timer t1. for a detailed description of timer t1, refer to section 22.6.17.1, absolute timer t1 . note if the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer t1 will expire according to the changed value. 22.5.2.41 timer 1 macrotick offset register (ti1mtor) this register holds the macrotick offs et value for timer t1. for a detailed description of timer t1, refer to section 22.6.17.1, absolute timer t1 . note if the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer t1 will expire according to the changed value. base + 0x005c write: anytime 0123456789101112131415 r0 0 t1_cyc_val 00 t1_cyc_msk w reset0000000000000000 figure 22-40. timer 1 cycle set register (ti1cysr) table 22-47. ti1cysr field descriptions field description t1_cyc_val timer t1 cycle filter value ? this field defines the cycle filter value for timer t1. t1_cyc_msk timer t1 cycle filter mask ? this field defines the cycle filter mask for timer t1. base + 0x005e write: anytime 0123456789101112131415 r0 0 t1_mtoffset w reset0000000000000000 figure 22-41. timer 1 macrotick offset register (ti1mtor) table 22-48. ti1mtor field descriptions field description t1_mtoffset timer 1 macrotick offset ? this field defines the macrotick offset value for timer 1.
flexray communication controller (flexray) 22-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.42 timer 2 configuration register 0 (ti2cr0) the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (ticcr) . for a detailed description of timer t2, refer to section 22.6.17.2, absolute / relative timer t2 . note if timer t2 is configured as an absolute timer and the appl ication modifies the values in this register while th e timer is running, the change becomes effective immediately and timer t2 will expire according to the changed values. if timer t2 is configured as a relative timer and the app lication changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. 22.5.2.43 timer 2 configuration register 1 (ti2cr1) base + 0x0060 write: anytime 0123456789101112131415 r r* t2_cyc_val r* t2_cyc_msk w r t2_mtcnt[31:16] w reset0000000000000000 figure 22-42. timer 2 configur ation register 0 (ti2cr0) table 22-49. ti2cr0 field descriptions field description fields for absolute timer t2 (ticcr[t2_cfg] = 0) t2_cyc_val timer t2 cycle filter value ? this field defines the cycl e filter value for timer t2. t2_cyc_msk timer t2 cycle filter mask ? this field defines the cycle filter mask for timer t2. fields for relative timer t2 (ticcr[t2_cfg = 1) t2_mtcnt[31:16] timer t2 macrotick high word ? this field defines the high word of the macrotick count for timer t2. base + 0x0062 write: anytime 0123456789101112131415 r r* t2_mtoffset w r t2_mtcnt[15:0] w reset0000000000000000 figure 22-43. timer 2 configur ation register 1 (ti2cr1)
flexray communication controller (flexray) freescale semiconductor 22-49 pxr40 microcontroller reference manual, rev. 1 the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (ticcr) . for a detailed description of timer t2, refer to section 22.6.17.2, absolute / relative timer t2 . note if timer t2 is configured as an absolute timer and the appl ication modifies the values in this register while th e timer is running, the change becomes effective immediately and th e timer t2 will expire according to the changed values. if timer t2 is configured as a relative timer and the app lication changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. 22.5.2.44 slot status selection register (sssr) this register is used to access th e four internal non memo ry-mapped slot status selection registers sssr0 to sssr3. each internal registers sel ects a slot, or symbol window/nit, whose status vector will be saved in the corresponding slot status registers (ssr0?ssr7) according to table 22-52 . for a detailed description of slot status monitoring, refer to section 22.6.18, slot status monitoring . table 22-50. ti2cr1 field descriptions field description fields for absolute timer t2 (ticcr[t2_cfg] = 0) t2_mtoffset timer t2 macrotick offset ? this field holds the macrotick offset value for timer t2. fields for relative timer t2 (ticcr[t2_cfg] = 1) t2_mtcnt[15:0] timer t2 macrotick low word ? this field defines the low word of the macrotick value for timer t2. base + 0x0064 16-bit write access required write: anytime 0123456789101112131415 r0 0 sel 0 slotnumber wwmd reset0000000000000000 figure 22-44. slot status selection register (sssr) table 22-51. sssr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access.
flexray communication controller (flexray) 22-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.45 slot status counter condition register (ssccr) this register is used to access and program the f our internal non-memory mapped slot status counter condition registers ssccr0 to ssccr3. each of these four internal slot status counter condition registers defines the mode and the conditions for incrementing the counter in the corresponding slot status counter registers (sscr0?sscr3) . the correspondence is given in table 22-54 . for a detailed description of slot stat us counters, refer to section 22.6.18.4, slot status counter registers . sel selector ? this field selects one of the four internal slot status selection registers for access. 00 select sssr0. 01 select sssr1. 10 select sssr2. 11 select sssr3. slotnumber slot number ? this field specifies the number of the slot whose status will be saved in the corresponding slot status registers. note: if this value is set to 0, the related slot status re gister provides the status of the symbol window after the nit start, and provides the status of the nit after the cycle start. table 22-52. mapping between sssrn and ssrn internal slot status selection register write the slot status of the slot selected by sssrn for each even communication cycle odd communication cycle for channel b to for channel a to for channel b to for channel a to sssr0 ssr0[15:8] ssr0[7: 0] ssr1[15:8 ] ssr1[7:0] sssr1 ssr2[15:8] ssr2[7: 0] ssr3[15:8 ] ssr3[7:0] sssr2 ssr4[15:8] ssr4[7: 0] ssr5[15:8 ] ssr5[7:0] sssr3 ssr6[15:8] ssr6[7: 0] ssr7[15:8 ] ssr7[7:0] base + 0x0066 16-bit write access required write: anytime 0123456789101112131415 r0 0 sel 0 cntcfg mcy vfr syf nuf suf statusmask[3:0] wwmd reset0000000000000000 figure 22-45. slot status counter condition register (ssccr) table 22-51. sssr field descriptions field description
flexray communication controller (flexray) freescale semiconductor 22-51 pxr40 microcontroller reference manual, rev. 1 table 22-53. ssccr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel selector ? this field selects one of the four internal slot counter conditio n registers for access. 00 select ssccr0. 01 select ssccr1. 10 select ssccr2. 11 select ssccr3. cntcfg counter configuration ? these bit field controls the channel relat ed incrementing of the slot status counter. 00 increment by 1 if condition is fulfilled on channel a. 01 increment by 1 if condition is fulfilled on channel b. 10 increment by 1 if condition is fulfilled on at least one channel. 11 increment by 2 if condition is fulfilled on both channels channel. increment by 1 if condition is fulfilled on only one channel. mcy multi cycle selection ? this bit defines whether the slot status counter accumulates over multiple communication cycles or provides information for the previ ous communication cycle only. 0 the slot status counter prov ides information for the previous communication cycle only. 1 the slot status counter accumulate s over multiple communication cycles. vfr valid frame restriction ? this bit is used to restrict the counter to received valid frames. 0 the counter is not restricted to valid frames only. 1 the counter is restricted to valid frames only. syf sync frame restriction ? this bit is used to restrict the counter to received frames with the sync frame indicator bit set to 1. 0 the counter is not restricted with re spect to the sync frame indicator bit. 1 the counter is restricted to frames with the sync frame indicator bit set to 1. nuf null frame restriction ? this bit is used to restrict the coun ter to received frames with the null frame indicator bit set to 0. 0 the counter is not restricted with respect to the null frame indicator bit. 1 the counter is restricted to frames with the null frame indicator bit set to 0. suf startup frame restriction ? this bit is used to restrict the counter to received frames with the startup frame indicator bit set to 1. 0 the counter is not restricted with respect to the startup frame indicator bit. 1 the counter is restricted to received frames with the startup frame indicator bit set to 1. status mask[3:0] slot status mask ? this bit field is used to enable the counte r with respect to the four slot status error indicator bits. statusmask[3] ? this bit enables the counting for slots with the syntax error indicator bit set to 1. statusmask[2] ? this bit enables the counting for slots with the content error indicator bit set to 1. statusmask[1] ? this bit enables the counting for slots with the boundary violation indicator bit set to 1. statusmask[0] ? this bit enables the counting for slots with the transmission conflict indicator bit set to 1. table 22-54. mapping betwee n internal ssccrn and sscrn condition register condition defined for register ssccr0 sscr0 ssccr1 sscr1 ssccr2 sscr2 ssccr3 sscr3
flexray communication controller (flexray) 22-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.46 slot status registers (ssr0?ssr7) each of these eight register s holds the status vector of the slot sp ecified in the corresponding internal slot status selection register, whic h can be programmed using the slot status selection register (sssr) . each register is updated afte r the end of the corres ponding slot as shown in figure 22-148 . the register bits are directly related to the pr otocol variables and described in more detail in section 22.6.18, slot status monitoring . base + 0x0068 (ssr0) base + 0x006a (ssr1) base + 0x006c (ssr2) base + 0x006e (ssr3) base + 0x0070 (ssr4) base + 0x0072 (ssr5) base + 0x0074 (ssr6) base + 0x0076 (ssr7) 0123456789101112131415 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca w reset0000000000000000 figure 22-46. slot status registers (ssr0?ssr7) table 22-55. ssr0?ssr7 field descriptions field description vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = 0 1 vss!txconflict = 1
flexray communication controller (flexray) freescale semiconductor 22-53 pxr40 microcontroller reference manual, rev. 1 22.5.2.47 slot status counter registers (sscr0?sscr3) each of these four registers provide s the slot status counter value for the previous communication cycle(s) and is updated at the cycle start. th e provided value depends on the contro l bits and fields in the related internal slot status counter condition register ssccrn, which can be programmed by using the slot status counter condition re gister (ssccr) . for more details, see section 22.6.18.4, slot status counter registers . vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = 0 1 vss!txconflict = 1 base + 0x0078 (sscr0) base + 0x007a (sscr1) base + 0x007c (sscr2) base + 0x007e (sscr3) additional reset: run command 0123456789101112131415 r slotstatuscnt w reset0000000000000000 figure 22-47. slot status counter registers (sscr0?sscr3) table 22-55. ssr0?ssr7 field descriptions (continued) field description
flexray communication controller (flexray) 22-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note if the counter has reached its ma ximum value 0xffff and is in the multicycle mode, i.e. ssccrn[mcy] = 1, the counter is not reset to 0x0000. the application can reset the counter by clearing the ssccrn[mcy] bit and waiti ng for the next cycle start, when the controller clears the counter. subseque ntly, the counter can be set into the multicycle mode again. 22.5.2.48 mts a configurat ion register (mtsacfr) this register controls the transmission of the me dia access test symbol mts on channel a. for more details, see section 22.6.13, mts generation . 22.5.2.49 mts b configurat ion register (mtsbcfr) this register controls the transmission of the me dia access test symbol mts on channel b. for more details, see section 22.6.13, mts generation . table 22-56. sscr0?sscr3 field descriptions field description slotstatuscnt slot status counter ? this field provides the current value of the slot status counter. base + 0x0080 write: mte: anytime cyccntmsk,cyccntval: poc:config 0123456789101112131415 r mte 0 cyccntmsk 00 cyccntval w reset0000000000000000 figure 22-48. mts a configuration register (mtsacfr) table 22-57. mtsacfr field descriptions field description mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled cyccntmsk cycle counter mask ? this field provides the filter mask for the mts cycle count filter. cyccntval cycle counter value ? this field provides the filter value for the mts cycle count filter. base + 0x0082 write: mte: anytime cyccntmsk,cyccntval: poc:config 0123456789101112131415 r mte 0 cyccntmsk 00 cyccntval w reset0000000000000000 figure 22-49. mts b configur ation register (mtsbcfr)
flexray communication controller (flexray) freescale semiconductor 22-55 pxr40 microcontroller reference manual, rev. 1 22.5.2.50 receive shadow buffer index register (rsbir) this register is used to provide and retrieve the indices of the message buffer header fields currently associated with the receive shadow buffers. for more details on the receive shadow buffer concept, refer to section 22.6.6.3.5, receive shadow buffers concept . 22.5.2.51 receive fifo system memory base address register (rfsymbadr) table 22-58. mtsbcfr field descriptions field description mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled cyccntmsk cycle counter mask ? this field provides the filter mask for the mts cycle count filter. cyccntval cycle counter value ? this field provides the filter value for the mts cycle count filter. base + 0x0084 16-bit write access required write: wmd, sel: any time rsbidx: poc:config 0123456789101112131415 r0 0 sel 0000 rsbidx wwmd reset0000000000000000 figure 22-50. receive shadow buffer index register (rsbir) table 22-59. rsbir field descriptions field description wmd write mode ? this bit controls the write mode for this register. 0 update sel and rsbidx field on register write 1 update only sel field on register write sel selector ? this field is used to select the internal receive shadow buffer index register for access. 00 rsbir_a1 ? receive shadow buffer index register for channel a, segment 1 01 rsbir_a2 ? receive shadow buffer index register for channel a, segment 2 10 rsbir_b1 ? receive shadow buffer index register for channel b, segment 1 11 rsbir_b2 ? receive shadow buffer index register for channel b, segment 2 rsbidx receive shadow buffer index ? this field contains the current index of the message buffer header field of the receive shadow message buffer selected by the sel field. the controller uses this index to determine the physical location of the shadow buffer header field in the flexray memory. the controller will update this field during receive operation.the application provides initial message buffer header index value in the configuration phase. controller: updates the message buffer header index after successful reception. application: provides initial message buffer header index.
flexray communication controller (flexray) 22-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 these registers define the system me mory base address for the receive fi fo if the fifo address mode bit mcr[fam] is set to 1. the system memory base a ddress is used by the bmif to calculate the physical memory address for system me mory accesses for the fifos. 22.5.2.52 receive fifo periodi c timer register (rfptr) this register holds periodic timer duration for the periodic fifo timer. the periodic timer applies to both fifos (see section 22.6.9.3, fifo periodic timer ). base + 0x00e8 write: disabled mode 0123456789101112131415 r smba[31:16] w reset0000000000000000 figure 22-51. receive fifo system memory base address high register (rfsymbadhr) base + 0x00ea write: disabled mode 0123456789101112131415 r smba[15:4] 0000 w reset0000000000000000 figure 22-52. receive fifo system memory base address low register (rfsymbadlr) table 22-60. rfsymbadr field descriptions field description smba system memory base address ? this is the value of the system me mory base address for the receive fifo if the fifo address mode bit mcr[fam] is se t to 1. it is defines as a byte address. base + 0x00ec write: poc:config 0123456789101112131415 r0 0 ptd w reset0000000000000000 figure 22-53. receive fifo peri odic timer register (rfptr) table 22-61. rfptir field descriptions field description ptd periodic time r duration ? this value defines the periodic timer duration in terms of macroticks. 0000 timer stays expired 3fff timer never expires other timer expires after specified number of macroticks, expires an d is restarted at each cycle start
flexray communication controller (flexray) freescale semiconductor 22-57 pxr40 microcontroller reference manual, rev. 1 22.5.2.53 receive fifo watermark and selection register (rfwmsr) this register is used to ? select a receiver fifo for subsequent programming access through the receiver fifo configuration registers summarized in table 22-62 . ? to define the watermark for the selected fifo. 22.5.2.54 receive fifo start index register (rfsir) this register defines the message buffer header index of the firs t message buffer of the selected fifo. base + 0x0086 write: wm a /wm b : poc:config, sel: anytime 0123456789101112131415 r wm a/ /wm b 0000000 sel w reset0000000000000000 figure 22-54. receive fifo watermark and selection register (rfwmsr) table 22-62. sel controlled receiver fifo registers register receive fifo start index register (rfsir) receive fifo depth and size register (rfdsr) receive fifo message id acceptance filter value register (rfmidafvr) receive fifo message id acceptance filter mask register (rfmiafmr) receive fifo frame id rejection f ilter value register (rffidrfvr) receive fifo frame id rejection filter mask register (rffidrfmr) receive fifo range filter configuration register (rfrfcfr) receive fifo range filter control register (rfrfctr) table 22-63. rfsr field descriptions field description wm a wm b watermark ? this field defines the watermark value for the selected fifo. this value is used to control the generation of the almost full interrupt flags. sel select ? this control bit selects the receiver fifo for subsequent programming. 0 receiver fifo for channel a selected 1 receiver fifo for channel b selected base + 0x0088 write: poc:config 0123456789101112131415 r000000 sidx a /sidx b w reset0000000000000000 figure 22-55. receive fifo start index register (rfsir)
flexray communication controller (flexray) 22-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.55 receive fifo depth and size register (rfdsr) this register defines the st ructure of the selected fifo , i.e. the number of entries and the size of each entry. 22.5.2.56 receive fifo a read index register (rfarir) this register provides the message buffer header in dex of the next available fifo a entry that the application can read. table 22-64. rfsir field descriptions field description sidx a sidx b start index ? this field defines the number of the message buff er header field of the first message buffer of the selected fifo. the controller uses the value of the sidx field to determine the physical location of the receiver fifo?s first message buffer header field. base + 0x008a write: poc:config 0123456789101112131415 r fifo_depth a /fifo_depth b 0 entry_size a /entry_size b w reset0000000000000000 figure 22-56. receive fifo dept h and size register (rfdsr) table 22-65. rfdsr field descriptions field description fifo_depth a fifo_depth b fifo depth ? this field defines the depth of the se lected fifo, i.e. the number of entries. entry_size a entry_size b entry size ? this field defines the size of the frame data se ctions for the selected fifo in 2 byte entities. base + 0x008c 0123456789101112131415 r000000 rdidx w reset0000000000000000 figure 22-57. receive fifo a read index register (rfarir) table 22-66. rfarir field descriptions field description rdidx read index ? this field provides the message buffer header i ndex of the next available fifo message buffer that the application can read. if the old style fifo mode is confi gured (mcr.fimd=0), the controller updates this index by 1 entry, when the application writes to the fafaif flag in the global interrupt flag and enable register (gifer) . if the new style fifo mode is configured (mcr.fimd=1), the controller updates this index by pca entries, when the application writes to the receive fifo fill level and pop count register (rfflpcr) .
flexray communication controller (flexray) freescale semiconductor 22-59 pxr40 microcontroller reference manual, rev. 1 note if the fifo is empty, the rdidx fiel d points to an physical message buffer with invalid content. 22.5.2.57 receive fifo b read index register (rfbrir) this register provides the message buffer header in dex of the next available fifo b entry that the application can read. note if the fifo is empty, the rdidx fiel d points to an physical message buffer with invalid content. 22.5.2.58 receive fifo fill level and pop count register (rfflpcr) this register provides the current fi ll level of the two recei ver fifos and is used to pop a number of entries from the fifos. base + 0x008e 0123456789101112131415 r000000 rdidx w reset0000000000000000 figure 22-58. receive fifo b read index register (rfbrir) table 22-67. rfbrir field descriptions field description rdidx read index ? this field provides the message buffer header i ndex of the next available fifo message buffer that the application can read. base + 0x00ee 0123456789101112131415 rflb fla wpcb pca reset0000000000000000 figure 22-59. receive fifo fill level and pop count register (rfflpcr) table 22-68. rfflpcr field descriptions field description flb fill level fifo b ? this field provides the current number of entries in the fifo b. fla fill level fifo a ? this field provides the current number of entries in the fifo a. pcb pop count fifo b ? this field defines the number of entries to be removed from fifo b. pca pop count fifo a ? this field defines the number of entries to be removed from fifo a.
flexray communication controller (flexray) 22-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note if the pop count value pca/pcb is greater than the current fifo fill level flb/fla, than the fifo is empty afte r the update. no notification is given that not the required number of entries was removed. 22.5.2.59 receive fifo m essage id acceptance filter value register (rfmidafvr) this register defines the fi lter value for the message id acceptance filter of the selected fifo. for details on message id filtering see section 22.6.9.9, fifo filtering . 22.5.2.60 receive fifo mess age id acceptance filter mask register (rfmiafmr) this register defines the filter mask for the message id acceptance filter of the selected fifo. for details on message id filtering see section 22.6.9.9, fifo filtering . base + 0x0090 write: poc:config 0123456789101112131415 r midafval a /midafval b w reset0000000000000000 figure 22-60. receive fifo message id acceptance filter value register (rfmidafvr) table 22-69. rfmidafvr field descriptions field description midafval a midafval b message id acceptance filter value ? filter value for the message id acceptance filter. base + 0x0092 write: poc:config 0123456789101112131415 r midafmsk a /midafmsk b w reset0000000000000000 figure 22-61. receive fifo message id acceptance filter mask register (rfmiafmr) table 22-70. rfmiafmr field descriptions field description midafmsk a midafmsk b message id acceptance filter mask ? filter mask for the messa ge id acceptance filter.
flexray communication controller (flexray) freescale semiconductor 22-61 pxr40 microcontroller reference manual, rev. 1 22.5.2.61 receive fifo fram e id rejection filter value register (rffidrfvr) this register defines the fi lter value for the frame id rejection filter of the se lected fifo. for details on frame id filtering see section 22.6.9.9, fifo filtering . 22.5.2.62 receive fifo fram e id rejection filter m ask register (rffidrfmr) this register defines the filter mask for the frame id rejection filter of the selected fifo. for details on frame id filtering see section 22.6.9.9, fifo filtering . 22.5.2.63 receive fifo range filter configuration regi ster (rfrfcfr) this register provides access to the four internal fram e id range filter boundary registers of the selected fifo. for details on frame id range filter see section 22.6.9.9, fifo filtering . base + 0x0094 write: poc:config 0123456789101112131415 r00000 fidrfval a /fidrfval b w reset0000000000000000 figure 22-62. receive fifo frame id rejection filter value register (rffidrfvr) table 22-71. rffidrfvr field descriptions field description fidrfval a fidrfval b frame id rejection filter value ? filter value for the frame id rejection filter. base + 0x0096 write: poc:config 0123456789101112131415 r00000 fidrfmsk a /fidrfmsk b w reset0000000000000000 figure 22-63. receive fifo frame id rejection filter mask register (rffidrfmr) table 22-72. rffidrfmr field descriptions field description fidrfmsk frame id rejection filter mask ? filter mask for the frame id rejection filter. base + 0x0098 16-bit write access required write: wmd, ibd, sel: any time sid: poc:config 0123456789101112131415 r0 ibd sel 0 sid a /sid b wwmd reset0000000000000000 figure 22-64. receive fifo range filt er configuration register (rfrfcfr)
flexray communication controller (flexray) 22-62 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.64 receive fifo range filt er control regi ster (rfrfctr) this register is used to enable a nd disable each frame id range filter and to define whether it is running as acceptance or rejection filter. table 22-73. rfrfcfr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel and ibd field only on write access. ibd interval boundary ? this control bit selects the interval boundary to be programmed with the sid value. 0 program lower interval boundary 1 program upper interval boundary sel filter selector ? this control field selects the frame id range filter to be accessed. 00 select frame id range filter 0. 01 select frame id range filter 1. 10 select frame id range filter 2. 11 select frame id range filter 3. sid a sid b slot id ? defines the ibd-selected frame id boundary value for the sel-selected range filter. base + 0x009a write: anytime 0123456789101112131415 r0000 f3md f2md f1md f0md 0000 f3en f2en f1en f0en w reset0000000000000000 figure 22-65. receive fifo range filter control register (rfrfctr) table 22-74. rfrfctr field descriptions field description f3md range filter 3 mode ? this control bit defines the filter mode of the frame id range filter 3. 0 range filter 3 runs as acceptance filter 1 range filter 3 runs as rejection filter f2md range filter 2 mode ? this control bit defines the filter mode of the frame id range filter 2. 0 range filter 2 runs as acceptance filter 1 range filter 2 runs as rejection filter f1md range filter 1 mode ? this control bit defines the filter mode of the frame id range filter 1. 0 range filter 1 runs as acceptance filter 1 range filter 1 runs as rejection filter f0md range filter 0 mode ? this control bit defines the filter mode of the frame id range filter 0. 0 range filter 0 runs as acceptance filter 1 range filter 0 runs as rejection filter f3en range filter 3 enable ? this control bit is used to enable and disable the frame id range filter 3. 0 range filter 3 disabled 1 range filter 3 enabled f2en range filter 2 enable ? this control bit is used to enable and disable the frame id range filter 2. 0 range filter 2 disabled 1 range filter 2 enabled
flexray communication controller (flexray) freescale semiconductor 22-63 pxr40 microcontroller reference manual, rev. 1 22.5.2.65 last dynamic transmit sl ot channel a register (ldtxslar) this register provides the number of the last transmission slot in the dynamic segment for channel a. this register is updated after the end of the dynamic segment and before th e start of the next communication cycle. 22.5.2.66 last dynamic transmit sl ot channel b register (ldtxslbr) this register provides the number of the last transmission slot in the dy namic segment for channel b. this register is updated after the end of the dynamic segment and before th e start of the next communication cycle. f1en range filter 1 enable ? this control bit is used to enable and disable the frame id range filter 1. 0 range filter 1 disabled 1 range filter 1 enabled f0en range filter 0 enable ? this control bit is used to enable and disable the frame id range filter 0. 0 range filter 0 disabled 1 range filter 0 enabled base + 0x009c 0123456789101112131415 r00000 lastdyntxslota w reset0000000000000000 figure 22-66. last dynamic slot channel a register (ldtxslar) table 22-75. ldtxslar field descriptions field description lastdyntx slota last dynamic transmission slot channel a ? protocol related variable: zlastdyntxslot channel a number of the last transmission slot in the dynamic se gment for channel a. if no frame was transmitted during the dynamic segment on channel a, the value of this field is set to 0. base + 0x009e 0123456789101112131415 r00000 lastdyntxslotb w reset0000000000000000 figure 22-67. last dynamic slot channel b register (ldtxslbr) table 22-76. ldtxslbr field descriptions field description lastdyntx slotb last dynamic transmission slot channel b ? protocol related variable: zlastdyntxslot channel b number of the last transmission slot in the dynamic segm ent for channel b. if no frame was transmitted during the dynamic segment on channel b the value of this field is set to 0. table 22-74. rfrfctr field descriptions (continued) field description
flexray communication controller (flexray) 22-64 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.67 protocol configuration registers the following configurati on registers provide the necessary confi guration information to the protocol engine. the individual values in the registers are described in table 22-77 . for more details about the flexray related configuration parameters and the allowed parameter ranges, see flexray communications system protocol specification, version 2.1 rev a . table 22-77. protocol configuration register fields name description 1 min max unit pcr coldstart_attempts gcoldstartattempts number 3 action_point_offset gdactionpointoffset - 1 mt 0 cas_rx_low_max gdcasrxlowmax - 1 gdbit 4 dynamic_slot_idle_phase gddynamicslotidlephase minislot 28 minislot_action_point_offset gdminislotactionpointoffset - 1 mt 3 minislot_after_action_point gdminislot - gdminislotactionpointoffset - 1 mt 2 static_slot_length gdstaticslot mt 0 static_slot_after_action_point gdstaticslot - gdactionpointoffset - 1 mt 13 symbol_window_exists gdsymbolwindow !=0 0 1 bool 9 symbol_window_after_action_point gdsymbolwindow - gdactionpointoffset - 1 mt 6 tss_transmitter gdtsstransmitter gdbit 5 wakeup_symbol_rx_idle gdwakeupsymbolrxidle gdbit 5 wakeup_symbol_rx_low gdwakeupsymbolrxlow gdbit 3 wakeup_symbol_rx_window gdwakeupsymbolrxwindow gdbit 4 wakeup_symbol_tx_idle gdwakeupsymboltxidle gdbit 8 wakeup_symbol_tx_low gdwakeupsymboltxlow gdbit 5 noise_listen_timeout ( glistennoise * pdlistentimeout ) - 1 ? t 16/17 macro_initial_offset_a pmacroinitialoffset[a] mt 6 macro_initial_offset_b pmacroinitialoffset[b] mt 16 macro_per_cycle gmacropercycle mt 10 macro_after_first_static_slot gmacropercycle - gdstaticslot mt 1 macro_after_offset_correction gmacropercycle - goffsetcorrectionstart mt 28 max_without_clock_correction_fatal gmaxwithoutclockcorrectionfatal cyclepairs 8 max_without_clock_ correction_passive gmaxwithoutclockcorrectionpassive cyclepairs 8 minislot_exists gnumberofminislots !=0 0 1 bool 9 minislots_max gnumberofminislots - 1 minislot 29 number_of_static_slots gnumberofstaticslots static slot 2 offset_correction_start goffsetcorrectionstart mt 11 payload_length_static gpayloadlengthstatic 2-bytes 19 max_payload_length_dynamic ppayloadlengthdynmax 2-bytes 24 first_minislot_action_point_offset max( gdactionpointoffset , gdminislotactionpointoffset ) - 1 mt 13 allow_halt_due_to_clock pallowhaltduetoclock bool 26 allow_passive_to_active pallowpassivetoactive cyclepairs 12
flexray communication controller (flexray) freescale semiconductor 22-65 pxr40 microcontroller reference manual, rev. 1 cluster_drift_damping pclusterdriftdamping ? t24 comp_accepted_startup_range_a pdacceptedstartuprange - pdelaycompensation[a] ? t22 comp_accepted_startup_range_b pdacceptedstartuprange - pdelaycompensation[b] ? t26 listen_timeout pdlistentimeout - 1 ? t 14/15 key_slot_id pkeyslotid number 18 key_slot_used_for_startup pkeyslotusedforstartup bool 11 key_slot_used_for_sync pkeyslotusedforsync bool 11 latest_tx gnumberofminislots - platesttx minislot 21 sync_node_max gsyncnodemax number 30 micro_initial_offset_a pmicroinitialoffset[a] ? t20 micro_initial_offset_b pmicroinitialoffset[b] ? t20 micro_per_cycle pmicropercycle ? t 22/23 micro_per_cycle_min pmicropercycle - pdmaxdrift ? t 24/25 micro_per_cycle_max pmicropercycle + pdmaxdrift ? t 26/27 micro_per_macro_nom_half round( pmicropermacronom / 2) ? t7 offset_correction_out poffsetcorrectionout ? t9 rate_correction_out pratecorrectionout ? t14 single_slot_enabled psingleslotenabled bool 10 wakeup_channel pwakeupchannel see table 22-78 10 wakeup_pattern pwakeuppattern number 18 decoding_correction_a pdecodingcorrection + pdelaycompensation[a] + 2 ? t19 decoding_correction_b pdecodingcorrection + pdelaycompensation[b] + 2 ? t7 key_slot_header_crc header crc for key slot 0x000 0x7ff number 12 extern_offset_correction pexternoffse tcorrection ? t29 extern_rate_correction pexternratecorrection ? t21 1 see flexray communications system protocol specification, version 2.1 rev a for detailed protocol parameter definitions table 22-78. wakeup channel selection wakeup_channel wakeup channel 0a 1b table 22-77. protocol configurati on register fields (continued) name description 1 min max unit pcr
flexray communication controller (flexray) 22-66 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.67.1 protocol configur ation register 0 (pcr0) 22.5.2.67.2 protocol configur ation register 1 (pcr1) 22.5.2.67.3 protocol configur ation register 2 (pcr2) 22.5.2.67.4 protocol configur ation register 3 (pcr3) 22.5.2.67.5 protocol configur ation register 4 (pcr4) base + 0x00a0 write: poc:config 0123456789101112131415 r action_point_offset st atic_slot_length w reset0000000000000000 figure 22-68. protocol confi guration register 0 (pcr0) base + 0x00a2 write: poc:config 0123456789101112131415 r0 0 macro_after_first_static_slot w reset0000000000000000 figure 22-69. protocol confi guration register 1 (pcr1) base + 0x00a4 write: poc:config 0123456789101112131415 r minislot_after_action_point number_of_static_slots w reset0000000000000000 figure 22-70. protocol confi guration register 2 (pcr2) base + 0x00a6 write: poc:config 0123456789101112131415 r wakeup_symbol_rx_low minislot_action_point_offset[4:0] coldstart_attempts w reset0000000000000000 figure 22-71. protocol confi guration register 3 (pcr3) base + 0x00a8 write: poc:config 0123456789101112131415 r cas_rx_low_max wakeup_symbol_rx_window w reset0000000000000000 figure 22-72. protocol confi guration register 4 (pcr4)
flexray communication controller (flexray) freescale semiconductor 22-67 pxr40 microcontroller reference manual, rev. 1 22.5.2.67.6 protocol configur ation register 5 (pcr5) 22.5.2.67.7 protocol configur ation register 6 (pcr6) 22.5.2.67.8 protocol configur ation register 7 (pcr7) 22.5.2.67.9 protocol configur ation register 8 (pcr8) 22.5.2.67.10 protocol configur ation register 9 (pcr9) base + 0x00aa write: poc:config 0123456789101112131415 r tss_transmitter wakeup_symbol_tx_low wakeup_symbol_rx_idle w reset0000000000000000 figure 22-73. protocol confi guration register 5 (pcr5) base + 0x00ac write: poc:config 0123456789101112131415 r0 symbol_window_after_action_point macro_initial_offset_a w reset0000000000000000 figure 22-74. protocol confi guration register 6 (pcr6) base + 0x00ae write: poc:config 0123456789101112131415 r decoding_correction_b micro_per_macro_nom_half w reset0000000000000000 figure 22-75. protocol confi guration register 7 (pcr7) base + 0x00b0 write: poc:config 0123456789101112131415 r max_without_clock_ correction_fatal max_without_clock_ correction_passive wakeup_symbol_tx_idle w reset0000000000000000 figure 22-76. protocol confi guration register 8 (pcr8) base + 0x00b2 write: poc:config 0123456789101112131415 r mini slot_ exists sym bol_ win dow_ exists offset_correction_out w reset0000000000000000 figure 22-77. protocol confi guration register 9 (pcr9)
flexray communication controller (flexray) 22-68 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.67.11 protocol configur ation register 10 (pcr10) 22.5.2.67.12 protocol configur ation register 11 (pcr11) 22.5.2.67.13 protocol configur ation register 12 (pcr12) 22.5.2.67.14 protocol configur ation register 13 (pcr13) base + 0x00b4 write: poc:config 0123456789101112131415 r single _slot _en abled wake up_ chan nel macro_per_cycle w reset0000000000000000 figure 22-78. protocol configuration register 10 (pcr10) base + 0x00b6 write: poc:config 0123456789101112131415 rkey_ slot_ used_ for_ start up key_ slot_ used_ for_ sync offset_correction_start w reset0000000000000000 figure 22-79. protocol configuration register 11 (pcr11) base + 0x00b8 write: poc:config 0123456789101112131415 r allow_passive_to_active key_slot_header_crc w reset0000000000000000 figure 22-80. protocol configuration register 12 (pcr12) base + 0x00ba write: poc:config 0123456789101112131415 r first_minislot_action_point_offset static_slot_after_action_point w reset0000000000000000 figure 22-81. protocol configuration register 13 (pcr13)
flexray communication controller (flexray) freescale semiconductor 22-69 pxr40 microcontroller reference manual, rev. 1 22.5.2.67.15 protocol configur ation register 14 (pcr14) 22.5.2.67.16 protocol configur ation register 15 (pcr15) 22.5.2.67.17 protocol configur ation register 16 (pcr16) 22.5.2.67.18 protocol configur ation register 17 (pcr17) 22.5.2.67.19 protocol configur ation register 18 (pcr18) base + 0x00bc write: poc:config 0123456789101112131415 r rate_correction_out listen_timeout[20:16] w reset0000000000000000 figure 22-82. protocol configuration register 14 (pcr14) base + 0x00be write: poc:config 0123456789101112131415 r listen_timeout[15:0] w reset0000000000000000 figure 22-83. protocol configuration register 15 (pcr15) base + 0x00c0 write: poc:config 0123456789101112131415 r macro_initial_offset_b no ise_listen_tim eout[24:16] w reset0000000000000000 figure 22-84. protocol configuration register 16 (pcr16) base + 0x00c2 write: poc:config 0123456789101112131415 r noise_listen_timeout[15:0] w reset0000000000000000 figure 22-85. protocol configuration register 17 (pcr17) base + 0x00c4 write: poc:config 0123456789101112131415 r wakeup_pattern key_slot_id w reset0000000000000000 figure 22-86. protocol configuration register 18 (pcr18)
flexray communication controller (flexray) 22-70 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.67.20 protocol configur ation register 19 (pcr19) 22.5.2.67.21 protocol configur ation register 20 (pcr20) 22.5.2.67.22 protocol configur ation register 21 (pcr21) 22.5.2.67.23 protocol configur ation register 22 (pcr22) 22.5.2.67.24 protocol configur ation register 23 (pcr23) base + 0x00c6 write: poc:config 0123456789101112131415 r decoding_correction_a payload_length_static w reset0000000000000000 figure 22-87. protocol configuration register 19 (pcr19) base + 0x00c8 write: poc:config 0123456789101112131415 r micro_initial_offset_b micro_initial_offset_a w reset0000000000000000 figure 22-88. protocol configuration register 20 (pcr20) base + 0x00ca write: poc:config 0123456789101112131415 r extern_rate_ correction latest_tx w reset0000000000000000 figure 22-89. protocol configuration register 21 (pcr21) base + 0x00cc write: poc:config 0123456789101112131415 r r* comp_accepted_startup_range_a micro_per_cycle[19:16 w reset0000000000000000 figure 22-90. protocol configuration register 22 (pcr22) base + 0x00ce write: poc:config 0123456789101112131415 r micro_per_cycle[15:0] w reset0000000000000000 figure 22-91. protocol configuration register 23 (pcr23)
flexray communication controller (flexray) freescale semiconductor 22-71 pxr40 microcontroller reference manual, rev. 1 22.5.2.67.25 protocol configur ation register 24 (pcr24) 22.5.2.67.26 protocol configur ation register 25 (pcr25) 22.5.2.67.27 protocol configur ation register 26 (pcr26) 22.5.2.67.28 protocol configur ation register 27 (pcr27) 22.5.2.67.29 protocol configur ation register 28 (pcr28) base + 0x00d0 write: poc:config 0123456789101112131415 r cluster_drift_damping max_payload_length_dynamic micro_per_cycle_min [19:16] w reset0000000000000000 figure 22-92. protocol configuration register 24 (pcr24) base + 0x00d2 write: poc:config 0123456789101112131415 r micro_per_cycle_min[15:0] w reset0000000000000000 figure 22-93. protocol configuration register 25 (pcr25) base + 0x00d4 write: poc:config 0123456789101112131415 r allow _halt_ due _to_ clock comp_accepted_startup_range_b micro_per_cycle_max [19:16] w reset0000000000000000 figure 22-94. protocol configuration register 26 (pcr26) base + 0x00d6 write: poc:config 0123456789101112131415 r micro_per_cycle_max[15:0] w reset0000000000000000 figure 22-95. protocol configuration register 27 (pcr27) base + 0x00d8 write: poc:config 0123456789101112131415 r dynamic_slot _idle_phase macro_after_offset_correction w reset0000000000000000 figure 22-96. protocol configuration register 28 (pcr28)
flexray communication controller (flexray) 22-72 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.67.30 protocol configur ation register 29 (pcr29) 22.5.2.67.31 protocol configur ation register 30 (pcr30) 22.5.2.68 message buffer configuration, control, status registers (mbccsrn) the content of these registers comprises message buf fer configuration data, me ssage buffer control data, message buffer status information, and message buffer in terrupt flags. a detailed description of all flags can be found in section 22.6.6, individual message buffer func tional description if the application writes 1 to the edt bit, no writ e access to the other regi ster bits is performed. if the application writes 0 to the edt bit and 1 to th e lckt bit, no write acce ss to the other bits is performed. base + 0x00da write: poc:config 0123456789101112131415 r extern_offset_ correction minislots_max w reset0000000000000000 figure 22-97. protocol configuration register 29 (pcr29) base + 0x00dc write: poc:config 0123456789101112131415 r000000000000 sync_node_max w reset0000000000000000 figure 22-98. protocol configuration register 30 (pcr30) base + 0x0100 (mbccsr0) base + 0x0108 (mbccsr1) ... base + 0x04f8 (mbccsr127) write: mcm, mbt, mtd: poc:config or mb_dis cmt: mb_lck or mb_dis edt, lckt, mbie, mbif: normal mode additional reset: cmt, dup, dval, mbif: message buffer disable 0123456789101112131415 r0 mcm mbt mtd cmt 0 0 mbie 0 0 0 dup dval eds lcks mbif w rwm edt lckt w1c reset0000000000000000 figure 22-99. message buffer configuration, control, status registers (mbccsrn)
flexray communication controller (flexray) freescale semiconductor 22-73 pxr40 microcontroller reference manual, rev. 1 table 22-79. mbccsrn field descriptions field description message buffer configuration mcm message buffer commit mode ? this bit configures the commit mode of a double buffered message buffer. 0 streaming commit mode 1 immediate commit mode mbt message buffer type ? this bit configures the buffering type of a transmit message buffer. 0 single buffered message buffer 1 double buffered message buffer mtd message buffer transfer direction ? this bit configures the transfer direction of a message buffer. 0 receive message buffer 1 transmit message buffer message buffer control cmt commit for transmission ? this bit indicates if the transmit message buffer data are ready for transmission. 0 message buffer data not ready for transmission 1 message buffer data ready for transmission edt enable/disable trigger ? if the application writes 1 to this bit, a message buffer enable or disable is triggered, depending on the current value eds status bit is 0. 0 no effect 1 message buffer enable or disable is triggered lckt lock/unlock trigger ? if the application writes 1 to this bit, a message buffer lock or unlock is triggered, depending on the current value of the lcks status bit. 0 no effect 1 message buffer lock or unlock is triggered mbie message buffer interrupt enable ? this control bit defines whether the message buffer will generate an interrupt request when its mbif flag is set. 0 interrupt request generation disabled 1 interrupt request generation enabled message buffer status dup data updated ? this status bit indicates whether the frame header in the message buffer header field and the data in the message buffer data field were updated after a frame reception. 0 frame header and message buffer data field not updated 1 frame header and message buffer data field updated dval data valid ? for receive message buffers this status bit indicates whether the message buffer data field contains valid frame data. for transmit message buffers the status bit indicates if a message is transferred again due to the state transmission mode of the message buffer. 0 receive message buffer contains no valid frame data / message is transmitted for the first time 1 receive message buffer contains valid frame data / message will be transferred again eds enable/disable status ? this status bit indicates whether the message buffer is enabled or disabled. 0 message buffer is disabled. 1 message buffer is enabled. lcks lock status ? this status bit indicates the current lock status of the message buffer. 0 message buffer is not locked by the application. 1 message buffer is locked by the application. mbif message buffer interrupt flag ? this flag is set when the slot status field of the message buffer was updated after frame transmission or reception, or when a transmi t message buffer was just enabled by the application. 0 no such event 1 slot status field updated or transmit message buffer just enabled
flexray communication controller (flexray) 22-74 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.5.2.69 message buffer cycle counter filter registers (mbccfrn) this register contains message buffer configurat ion data for the transm ission mode, the channel assignment, and for the cycle counter filtering. for detailed information on cycle c ounter filtering, refer to section 22.6.7.1, message buffer cycle counter filtering . . base + 0x0102 (mbccfr0) base + 0x010a (mbccfr1) ... base + 0x04fa (mbccfr127) write: poc:config or mb_dis 0123456789101112131415 r mtm cha chb ccfe ccfmsk ccfval w reset---------------- figure 22-100. message buffer cycle counter filter registers (mbccfrn) table 22-80. mbccfrn field descriptions field description mtm message buffer transmission mode ? this control bit applies only to transmit message buffers and defines the transmission mode. 0 event transmission mode 1 state transmission mode cha chb channel assignment ? these control bits define the channel assignment and control the receive and transmit behavior of the message buffer according to table 22-81 . ccfe cycle counter filtering enable ? this control bit is used to enable and disable the cycle counter filtering. 0 cycle counter filtering disabled 1 cycle counter filtering enabled ccfmsk cycle counter filtering mask ? this field defines the filter mask for the cycle counter filtering. ccfval cycle counter filtering value ? this field defines the filter value for the cycle counter f iltering. table 22-81. channel assignment description cha chb transmit message buffer receive message buffer static segment dynamic segment static segment dynamic segment 1 1 transmit on both channel a and channel b transmit on channel a only store first valid frame received on either channel a or channel b store first valid frame received on channel a, ignore channel b 0 1 transmit on channel b transmit on channel b store first valid frame received on channel b store first valid frame received on channel b 1 0 transmit on channel a transmit on channel a store first valid frame received on channel a store first valid frame received on channel a 0 0 no frame transmission no frame transmission no frame stored no frame stored
flexray communication controller (flexray) freescale semiconductor 22-75 pxr40 microcontroller reference manual, rev. 1 note if at least one message buffer assigned to a certain slot is assigned to both channels, then all message buffers assigne d to this slot have to be assigned to both channels. otherwis e, the message buffer configuration is illegal and the result of the message buf fer search is not defined. 22.5.2.70 message buffer frame id registers (mbfidrn) 22.5.2.71 message buffer index registers (mbidxrn) base + 0x0104 (mbfidr0) base + 0x010c (mbfidr1) ... base + 0x04fc (mbfidr127) write: poc:config or mb_dis 0123456789101112131415 r00000 fid w reset00000 ----------- figure 22-101. message buffer frame id registers (mbfidrn) table 22-82. mbfidrn field descriptions field description fid frame id ? the semantic of this field depends on the message buffer transfer type. ? receive message buffer: this field is used as a filter value to de termine if the message buffer is used for reception of a message received in a slot with the slot id equal to fid. ? transmit message buffer: this field is used to determine the slot in which the message in this message buffer should be transmitted. base + 0x0106 (mbidxr0) base + 0x010e (mbidxr1) ... base + 0x04fe (mbidxr127) write: poc:config or mb_dis 0123456789101112131415 r00000000 mbidx w reset00000000 - ------- figure 22-102. message buffer index registers (mbidxrn) table 22-83. mbidxrn field descriptions field description mbidx message buffer index ? this field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer. the application writes the index of the initially associated message buffer header field into this register. the controller updates this register af ter frame reception or transmission.
flexray communication controller (flexray) 22-76 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6 functional description this section provides a detailed description of the functionality implemented in the controller. 22.6.1 message buffer concept the controller uses a data structure called message buffer to store frame data, c onfiguration, control, and status data. each message buffe r consists of two parts, the message buffer control data and the physical message buffer. the message buffer control data are located in dedicated registers. the structure of the message buffer control data depends on the message buffer type and is described in section 22.6.3, message buffer types . the physical message buffer is located in the flexray memory and is described in section 22.6.2, physical message buffer . 22.6.2 physical message buffer all flexray messages and related fram e and slot status information of r eceived frames and of frames to be transmitted to the flexray bus ar e stored in data structures called physical message buffers . the physical message buffers are located in the flexray memory.the structur e of a physical message buffer is depicted in figure 22-103 . a physical message buffer cons ists of two fields, the message buffer header field and the message buffer data field . the message buffer header field contains the frame header , the data field offset , and the slot status .the message buffer data field contains the frame data . the connection between the two fields is established by the data field offset . figure 22-103. physical message buffer structure 22.6.2.1 message buffer header field the message buffer header field is a contiguous region in the flexray me mory and occupies ten bytes. it contains the frame header, the da ta field offset, and the slot st atus. its structure is shown in figure 22-103 . the physical start address sadr_mbhf of the message buffer header field must be 16-bit aligned. 22.6.2.1.1 frame header the frame header occupies the first six bytes in the message buffer header field. it contains all flexray frame header related information according to the flexray communications system protocol data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory
flexray communication controller (flexray) freescale semiconductor 22-77 pxr40 microcontroller reference manual, rev. 1 specification, version 2.1 rev a . a detailed description of the usage and the content of the frame header is provided in section 22.6.5.2.1, frame h eader description . 22.6.2.1.2 data field offset the data field offset follows the fra me header in the message buffer data field and occupies two bytes. it contains the offset of the corres ponding message buffer data field with respect to the c ontroller flexray memory base address as provided by smba field in the system memory base address register (symbadr) . the data field offset is used to determine the start address sadr_mbdf of the corresponding message buffer data field in the flexray memory according to equation 22-2 . sadr_mbdf = [data field offset] + smba eqn. 22-2 22.6.2.1.3 slot status the slot status occupies the last two bytes of the me ssage buffer header field. it provides the slot and frame status related informat ion according to the flexray communications syst em protocol specification, version 2.1 rev a . a detailed description of the content and usage of the slot status is provided in section 22.6.5.2.3, slot status description . 22.6.2.2 message buffer data field the message buffer data fiel d is a contiguous area of 2- byte entities. this field c ontains the frame payload data, or a part of it, of the frame to be transmit ted to or received from th e flexray bus. the minimum length of this field depends on the specific message buf fer configuration and is specified in the message buffer descriptions given in section 22.6.3, message buffer types . 22.6.3 message buffer types the controller provides three diff erent types of message buffers. ? individual message buffers ? receive shadow buffers ? receive fifo buffers for each message buffer type the st ructure of the physical message buffe r is identical. the message buffer types differ only in the structure and content of message buffer contro l data, which control the related physical message buffer. the message buffer control data are descri bed in the following sections. 22.6.3.1 individual message buffers the individual message buffers are used for all t ypes of frame transmission and for dedicated frame reception based on individual filter se ttings for each message buffer. th e controller supports three types of individual messa ge buffers, which are described in section 22.6.6, individua l message buffer functional description .
flexray communication controller (flexray) 22-78 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 each individual message buffer consists of two parts, the phys ical message buffer, which is located in the flexray memory, and the message buffer control data , which are located in dedicated registers. the structure of an individual message buffer is given in figure 22-104 . each individual message buffer has a message buffe r number n assigned, which determines the set of message buffer control registers a ssociated to this individual messa ge buffer. the individual message buffer with message buffer number n is controlled by the regist ers mbccsrn, mbccfrn, mbfidrn, and mbidxrn. the connection between the message buffer control registers and the physical message buffer is established by the message buffe r index field mbidx in the message buffer index registers (mbidxrn) . the start address sadr_mbhf of the related messag e buffer header field in the flexray memory is determined according to equation 22-3 . sadr_mbhf = (mbidxrn[mbidx] * 10) + smba eqn. 22-3 figure 22-104. individual message buffer structure 22.6.3.1.1 individual m essage buffer segments the set of the individual message buffers can be sp lit up into two message buffer segments using the message buffer segment size and utilization register (mbssutr) . all individual message buffers with a message buffer number n <= mbssut r[last_mb_seg1] belong to the fi rst message buffer segment. all individual message buffers with a message buffer number n > mbssutr[last_mb_seg1] belong to the second message buffer segment. the following rules apply to the length of the message buffer data field: ? all physical message buffers associated to indi vidual message buffers that belong to the same message buffer segment must have message buffer data fields of the same length ? the minimum length of the message buffer data fi eld for individual messag e buffers in the first message buffer segment is 2 * mbdsr[mbseg1ds] bytes ? the minimum length of the messag e buffer data field fo r individual message buf fers assigned to the second segment is 2 * mbdsr[mbseg2ds] bytes. mbfidrn message buffer control registers mbccsrn mbccfrn mbidxrn (min) mbdsr[mbseg1ds] * 2 bytes / mbdsr[mbseg2ds] * 2 bytes data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory
flexray communication controller (flexray) freescale semiconductor 22-79 pxr40 microcontroller reference manual, rev. 1 22.6.3.2 receive shadow buffers the receive shadow buffers are required for the fram e reception process for individual message buffers. the controller provides four receive shadow buffe rs, one receive shadow buffer per channel and per message buffer segment. each receive shadow buffer consists of two parts, the physical message buffer located in the flexray memory and the receive shadow buffer control registers located in dedicat ed registers. the structure of a receive shadow buffer is shown in figure 22-105 . the four internal shadow bu ffer control registers can be accessed by the receive shadow buffer index register (rsbir) . the connection between the receive sh adow buffer control register and the physical message buffer for the selected receive shadow buffer is established by th e receive shadow buffer i ndex field rsbidx in the receive shadow buffer index register (rsbir) . the start address sadr_mbh f of the related message buffer header field in the flexray memory is determined according to equation 22-4 . sadr_mbhf = (rsbir[rsbidx] * 10) + smba eqn. 22-4 the length required for the message buffer data fiel d depends on the message buffer segment that the receive shadow buffer is assigned to. for the receiv e shadow buffers assigned to the first message buffer segment, the length must be the same as for the i ndividual message buffers assi gned to the first message buffer segment. for the receive sha dow buffers assigned to the second message buffe r segment, the length must be the same as for the indi vidual message buffers assigned to the second message buffer segment. the receive shadow buffer assignment is described in receive shadow buffer index register (rsbir) . figure 22-105. receive shadow buffer structure 22.6.3.3 receive fifo the receive fifo implements a fra me reception system based on the fifo concept. the controller provides two independent recei ve fifos, one per channel. rsbidx[3] rsbidx[2] rsbidx[1] rsbidx[0] receive shadow buffer control register (min) mbdsr[mbseg1ds] * 2 bytes / mbdsr[mbseg2ds] * 2 bytes data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory
flexray communication controller (flexray) 22-80 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 a receive fifo consists of a set of physical message buffers in the flexray memory and a set of receive fifo control registers located in dedicated registers. the structure of a receive fifo is given in figure 22-106 . the connection between the receive fifo control registers and the se t of physical message buffers is established by the receive fifo start i ndex register (rfsir) , the receive fifo depth and size register (rfdsr) , and the receive fifo a read i ndex register (rfarir) / receive fifo b read index register (rfbrir) . the system memory base address smba is defined by the system memory base address register selected by the fifo address mode bit mcr[fam]. the start byte address sadr_mbhf[1] of the first message buffer header field that belongs to the receive fifo in the flexray memory is determined according to equation 22-5 . sadr_mbhf[1] = (10 * rfsir[sidx]) + smba eqn. 22-5 the start byte address sadr_mbhf[n] of the last message buffer header field that belongs to the receive fifo in the flexray memory is determined according to equation 22-6 . sadr_mbhf[n] = (10 * (rfsir[sidx] + rfdsr[fifo_depth])) + smba eqn. 22-6 note all message buffer header fields assigned to a receive fifo must be a contiguous region.
flexray communication controller (flexray) freescale semiconductor 22-81 pxr40 microcontroller reference manual, rev. 1 figure 22-106. receive fifo structure 22.6.3.4 message buffer configuration and control data this section describes the configuration and control data for each message buffer type. 22.6.3.4.1 individual message buffer configuration data before an individual message buffer can be used for transmission or reception, it must be configured. there is a set of common configuratio n parameters that applies to all in dividual message buffers and a set of configuration parameters that applie s to each message buffer individually. common configuration data the set of common configurat ion data for indivi dual message buffers is located in the following registers. ? message buffer data size register (mbdsr) the mbseg2ds and mbseg1ds fields define the mini mum length of the message buffer data field with respect to the message buffer segment. ? message buffer segment size and utilization register (mbssutr) the last_mb_seg1 and last_mb_util fields define the segmentation of the individual rfbrir rfdsr[b] rfsir[b] rfarir rfdsr[a] rfsir[a] frame header[1] slot status[1] data field offset[1] receive fifo control register message buffer header fields message buffer data fields frame header[n] slot status[n] data field offset[n] (min) rfdsr[entry_size] * 2 bytes rfdsr[fifo_depth] + frame header[i] slot status[i] data field offset[i] frame data[n] sadr_mbdf[n] frame data[i] sadr_mbdf[i] frame data[1] sadr_mbdf[1] rfdsr[fifo_depth] sadr_mbhf[n] sadr_mbhf[i] sadr_mbhf[1] flexray memory
flexray communication controller (flexray) 22-82 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 message buffers and the number of individual message buffers that are used. for mo re details, see section 22.6.3.1.1, individual message buffer segments . specific configuration data the set of message buffer specific configuration data for individual me ssage buffers is located in the following registers. ? message buffer configuration, cont rol, status registers (mbccsrn) the mcm, mbt, mtd bits conf igure the message buffer type. ? message buffer cycle counter filter registers (mbccfrn) the mtm, cha, chb bits configure the transm ission mode and the channel assignment. the ccfe, ccfmsk, and ccfval bits and fiel ds configure the cycle counter filter. ? message buffer frame id registers (mbfidrn) for a transmit message buffer, the fid field is used to determine the slot in which the message in this message buffer will be transmitted. ? message buffer inde x registers (mbidxrn) this mbidx field provides the index of the mess age buffer header field of the physical message buffer that is currently associat ed with this message buffer. 22.6.3.5 individual messag e buffer control data during normal operation, each individua l message buffer can be controlled by the control and trigger bits cmt, lckt, edt, and mbie in the message buffer configuration, control, status registers (mbccsrn) . 22.6.3.6 receive shadow buffer configuration data before frame reception into the indi vidual message buffers can be perf ormed, the receive shadow buffers must be configured. the configur ation data are provided by the receive shadow buffer index register (rsbir) . for each receive shadow buffer, the application provides the mess age buffer header index. when the protocol is in the poc:normal active or poc:normal passive state, the receive shadow buffers are under full controller control. 22.6.3.7 receive fifo cont rol and configuration data this section describes the configuration a nd control data for the two receive fifos. 22.6.3.7.1 receive fifo configuration data the controller provides two functi onal independent receive fifos, one per channel. the fifos have a common subset of c onfiguration data: ? receive fifo system memory ba se address register (rfsymbadr) ? receive fifo periodic timer register (rfptr) each fifo has its own set of configuration data. th e configuration data are located in the following registers:
flexray communication controller (flexray) freescale semiconductor 22-83 pxr40 microcontroller reference manual, rev. 1 ? receive fifo watermark and selection register (rfwmsr) ? receive fifo start i ndex register (rfsir) ? receive fifo depth and size register (rfdsr) ? receive fifo message id acceptance filter valu e register (rfmidafvr) ? receive fifo message id acceptance filter mask register (rfmiafmr) ? receive fifo frame id rejection filter value register (rffidrfvr) ? receive fifo frame id rejection filter mask register (rffidrfmr) ? receive fifo range filter conf iguration register (rfrfcfr) 22.6.3.7.2 receive fifo control data the application can access the fifos at any time using the control bi ts in the following registers: ? global interrupt flag and enable register (gifer) ? receive fifo fill level and pop count register (rfflpcr) 22.6.3.7.3 receive fifo status data the current status of the receive fifo is provided in the following register: ? global interrupt flag and enable register (gifer) ? receive fifo a read index register (rfarir) ? receive fifo b read index register (rfbrir) ? receive fifo fill level and pop count register (rfflpcr) 22.6.4 flexray memory layout the controller supports a wide range of possible la youts for the flexray memory. two basic layout modes can be selected by the fifo address mode bit mcr[fam]. 22.6.4.1 flexray memory layout (mcr[fam] = 0) figure 22-107 shows an example layout for the fifo addr ess mode mcr[fam]=0. in this mode, the following set of rules applies to the layout of the flexray memory: ? the flexray memory is one contiguous region. ? the flexray memory size is maximum 64 kbytes. ? the flexray memory starts at a 16 byte boundary the flexray memory cont ains three areas: the message buffer header area , the message buffer data area , and the sync frame table area .
flexray communication controller (flexray) 22-84 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 22-107. example of flexray memory layout (mcr[fam] = 0) 22.6.4.2 flexray memory layout (mcr[fam] = 1) figure 22-108 shows an example layout for the fifo addr ess mode mcr[fam]=1. the following set of rules applies to the layout of the flexray memory: ? the flexray memory consists of two contiguous regions. ? the size of each region is maximum 64 kbytes. ? each region start at a 16 byte boundary. message buffer header area flexray memory message buffer data area sync frame table area data field offset frame header slot status data field offset frame header slot status message buffer header fields individual message buffers receive shadow buffers data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo a data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo b data field offset frame header slot status 10 bytes symbadr[smba] system memory
flexray communication controller (flexray) freescale semiconductor 22-85 pxr40 microcontroller reference manual, rev. 1 figure 22-108. example of flexray memory layout (mcr[fam] = 1) 22.6.4.3 message buffer header area (mcr[fam] = 0) the message buffer header area contains all message buffer header fields of th e physical message buffers for all message buffer types. the following rules apply to the message buffer header fields for the three type of message buffers. 1. the start byte address sadr_mbhf of each message buffer header field for individual message buffers and receive shadow buffers must fulfill equation 22-7 . sadr_mbhf = (i * 10) + symbadr[smba]; (0 <= i < 256) eqn. 22-7 2. the start byte address sadr_mbhf of each message buffer header field for the fifo must fulfill equation 22-8 . sadr_mbhf = (i * 10) + symdard[smba]; (0 <= i < 1024) eqn. 22-8 fifo header area fifo flexray memory data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo a data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo b rfsymbadr[smba] system memory message buffer header area flexray memory message buffer data area sync frame table area data field offset frame header slot status data field offset frame header slot status message buffer header fields individual message buffers receive shadow buffers data field offset frame header slot status 10 bytes symbadr[smba] fifo message buffer data area
flexray communication controller (flexray) 22-86 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 sadr_mbhf = (i * 10) + symbadr[smba]; (0 <= i < 1024) eqn. 22-9 3. the message buffer header fields for each fifo have to be a contiguous area. 22.6.4.4 message buffer header area (mcr[fam] = 1) the message buffer header area contains all message buffer header fields of th e physical message buffers for the individual message buffers and receiver shadow buffers. the following rules apply to the message buffer header fields for the two type of message buffers. 1. the start address sadr_mbhf of each message buffer header field for individual message buffers and receive shadow buffers must fulfill equation 22-10 . sadr_mbhf = (i * 10) + symbadr[smba]; (0 <= i < 256) eqn. 22-10 22.6.4.5 fifo message buffer header area (mcr[fam] = 1) the fifo message buffer header area contains all me ssage buffer header fields of the physical message buffers for the fifo. the following rules appl y to the fifo message buffer header fields. 1. the start byte address sadr_mbhf of each message buffer header field for the fifo must fulfill equation 22-11 . sadr_mbhf = (i * 10) + rfsymbadr[smba]; (0 <= i < 1024) eqn. 22-11 2. the message buffer header fields for each fifo have to be a contiguous area. 22.6.4.6 message buffer data area the message buffer data area contai ns all the message buffer data fiel ds of the physical message buffers. each message buffer data fiel d must start at a 16-bit boundary. 22.6.4.7 sync frame table area the sync frame table area is used to provide a copy of the internal s ync frame tables for application access. refer to section 22.6.12, sync frame id and sync frame deviation tables , for the description of the sync frame table area. 22.6.5 physical message buffer description this section provides a detailed de scription of the usage and the cont ent of the two parts of a physical message buffer, the message buffer header field and the message buffer data field. 22.6.5.1 message buffer prot ection and data consistency the physical message buffers are located in the fl exray memory. the contro ller provides no means to protect the flexray me mory from uncontrolled or ille gal host or other client writ e access. to ensure data consistency of the physical message buffers, the appli cation must follow the wr ite access scheme that is given in the description of each of the physical message buffer fields.
flexray communication controller (flexray) freescale semiconductor 22-87 pxr40 microcontroller reference manual, rev. 1 22.6.5.2 message buffer h eader field description this section provides a detailed desc ription of the usage and content of the message buffer header field. a description of the structure of the messa ge buffer header fields is given in section 22.6.2.1, message buffer header field . each message buffer header field consists of three sections: the frame header section, the data field offset, and the slot status section. for a detailed descri ption of the data field offset, see section 22.6.2.1.2, data field offset . 22.6.5.2.1 frame header description frame header content the semantic and content of the frame header section depends on the message buffer type. for individual receive message buffers and receive fifos, the frame header receives the frame header data of the first valid frame received on the assigned channels. for receive shadow buffers, the frame header receives the frame header data of the current frame received regardless of whether th e frame is valid or not. for transmit message buffers, the appl ication writes the frame header of the frame to be transmitted into this location. the frame header will be read out when the frame is transferred to the flexray bus. the structure of the frame header in the message buffer header field for receive message buffers and the receive fifo is given in figure 22-109 . a detailed description is given in table 22-85 . figure 22-109. frame header structure (receive message buffer and receive fifo) the structure of the frame header in the message buffer header field for transmit message buffers is given in figure 22-110 . a detailed description is given in table 22-86 . the checks that will be performed are described in frame header checks . figure 22-110. frame header structure (transmit message buffer) the structure of the frame header in the message buffer header fi eld for transmit message buffers assigned to key slot is given in figure 22-111 . 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x0 r ppi nuf syf suf fid 0x2 0 0 cyccnt 0 pldlen 0x400000 hdcrc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x0 r ppi nuf syf suf fid 0x2 cyccnt pldlen 0x4 hdcrc = not used = checked = checked if static slot
flexray communication controller (flexray) 22-88 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 22-111. frame header structure (transmit message buffer for key slot) frame header access the frame header is located in the flexray memory. to ensure data c onsistency, the application must follow the write access scheme described below. for receive message buffers, receive shadow buffers, a nd receive fifos, the application must not write to the frame header field. for transmit message buffers, the application must follow the write access restrictions given in table 22-84 . this table shows the condition under which the application can write to the frame header entries without corrupting the flexray message transmission. frame header checks as shown in figure 22-110 and figure 22-111 not all fields in the message buffer frame header are used for transmission. some fields in the message buffer frame header are ignored, some are used for transmission, and some of them are checked for corr ect values. all checks that will be performed are described below. for message buffers assigned to the key slot, no checks will be performed. the value of the fid field must be equal to the value of the corresponding message buffer frame id registers (mbfidrn) . if the controller detects a mismatch while tran smitting the frame h eader, it will set the frame id error flag fid_ef in the chi error flag register (chierfr) . the value of the fid field will be ignored and replaced by the value provided in the message buffer frame id registers (mbfidrn) . for transmit message buffers assigned to the static segment, the pldlen value must be equal to the value of the payload_length_static field in the protocol configurati on register 19 (pcr19) . if this is not fulfilled, the static payload length error flag spl_ef in the chi error flag register (chierfr) is set when the message buffer is under transmission. a syntacti cally and semantically co rrect frame is generated with payload_length_static pa yload words and the payloa d length field in the tran smitted frame header set to payload_length_static. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x0 r ppi nuf syf suf fid 0x2 cyccnt pldlen 0x4 hdcrc = not used table 22-84. frame header write access constraints (transmit message buffer) field single buffered double buffered static segment dynamic segment static segment dynamic segment commit side transmit side commit side transmit side fid poc:config or mb_dis ppi, pldlen, hdcrc poc:config or mb_dis or mb_lck mb_lck
flexray communication controller (flexray) freescale semiconductor 22-89 pxr40 microcontroller reference manual, rev. 1 for transmit message buffers assigned to the dynamic segment, the pldlen value must be less than or equal to the value of the max_pa yload_length_dynamic field in the protocol configuration register 24 (pcr24) . if this is not fulfilled, the dynamic payload length error flag dpl_ef in the chi error flag register (chierfr) is set when the message buffer is under transmission. a syntactically and semantically correct dynamic frame is generated wi th pldlen payload words and the payload length field in the frame header set to pldlen. table 22-85. frame header field descriptions (receive message buffer and receive ffo) field description r reserved bit ? this is the value of the reserved bit of the received frame stored in the message buffer ppi payload preamble indicator ? this is the value of the payload preamble indicator of the received frame stored in the message buffer. nuf null frame indicator ? this is the value of the null frame indicator of the received frame stored in the message buffer. syf sync frame indicator ? this is the value of the sync frame indicator of the received frame stored in the message buffer. suf startup frame indicator ? this is the value of the startup frame indicator of the received frame stored in the message buffer. fid frame id ? this is the value of the frame id field of the received frame stored in the message buffer. cyccnt cycle count ? this is the number of the communication cycle in which the frame stored in the message buffer was received. pldlen payload length ? this is the value of the payload length field of the received frame stored in the message buffer. hdcrc header crc ? this is the value of the header crc field of the received frame stored in the message buffer. table 22-86. frame header field descriptions (transmit message buffer) field description r reserved bit ? this bit is not used, the value of the reserved bit is generated internally according to flexray communications system protocol specification, version 2.1 rev a. ppi payload preamble indicator ? this bit provides the value of the payload preamble indicator for the frame transmitted from the message buffer. nuf null frame indicator ? this bit is not used, the value of the null frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a. syf sync frame indicator ? this bit is not used, the value of the sync frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a. suf startup frame indicator ? this bit is not used, the value of the startup frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a. fid frame id ? this field is checked as described in frame header checks . cyccnt cycle count ? this field is not used, the value of the transmitted cycle count field is taken from the internal communication cycle counter.
flexray communication controller (flexray) 22-90 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.5.2.2 data field offset description data field offset content for a detailed description of the data field offset, see section 22.6.2.1.2, data field offset . data field offset access the application shall program the da ta field offset when configuring the message buffers either in the poc:config state or when the message buffer is disabled. 22.6.5.2.3 slot status description the slot status is a read-only struct ure for the application and a write-on ly structure for the controller. the meaning and content of the slot status in the messa ge buffer header field de pends on the message buffer type. receive message buffer and receiv e fifo slot st atus description this section describes the slot st atus structure for the individual re ceive message buffers and receive fifos. the content of the slot st atus structure for receive message buffers depends on the message buffer type and on the channel assignment for indivi dual receive message buffers as given by table 22-87 . the meaning of the bits in the slot status structure is explained in table 22-88 . pldlen payload length ? this field is checked and used as described in frame header checks . hdcrc header crc ? this field provides the value of the header crc field for the frame transmitted from the message buffer. table 22-87. receive message buffer slot status content receive message buffer ty pe slot status content individual receive message buffer assigned to both channels mbccsrn[cha]=1 and mbccsrn[chb]=1 see figure 22-112 individual receive message buffer assigned to channel a mbccsrn[cha]=1 and mbccsrn[chb[=0 see figure 22-113 individual receive message buffer assigned to channel b mbccsrn[cha]=0 and mbccsrn[chb]=1 see figure 22-114 receive fifo channel a message buffer see figure 22-113 receive fifo channel b message buffer see figure 22-114 table 22-86. frame header field descripti ons (transmit message buffer) (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-91 pxr40 microcontroller reference manual, rev. 1 figure 22-112. receive message buffer slot status structure (chab) figure 22-113. receive message buffer slot status structure (cha) figure 22-114. receive message buffer slot status structure (chb) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb ch vfa sya nfa sua sea cea bva 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 vfa sya nfa sua sea cea bva 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb 1 0 0 0 0 0 0 0 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 22-88. receive message buffer slot status field descriptions field description common message buffer status bits vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indi cator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 ch channel first valid received ? this status bit applies only to receive message buffers assigned to the static segment and to both channels. it indica tes the channel that has received the first valid frame in the slot. this flag is set to 0 if no valid frame was received at all in the subscribed slot. 0 first valid frame received on channel a, or no valid frame received at all 0 first valid frame received on channel b vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1
flexray communication controller (flexray) 22-92 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 transmit message buffer slot status description this section describes the slot status structure for transmit message buffers. on ly the tca and tcb status bits are directly related to the tran smission process. all other status bits in this structure are related to a receive process that may have occu rred. the content of the slot stat us structure for transmit message buffers depends on the channel assignment as given by table 22-89 . the meaning of the bits in the slot status structure is described in table 22-88 . figure 22-115. transmit message buffer slot status structure (chab) sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indi cator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 table 22-89. transmit message buffer slot status content transmit message buffer type slot status content individual transmit message buffer assigned to both channels mbccsrn[cha]=1 and mbccsrn[chb]=1 see figure 22-115 individual transmit message buffer assigned to channel a mbccsrn[cha]=1 and mbccsrn[chb]=0 see figure 22-116 individual transmit message buffer assigned to channel b mbccsrn[cha]=0 and mbccsrn[chb]=1 see figure 22-117 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 22-88. receive message buffer slot status field descriptions (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-93 pxr40 microcontroller reference manual, rev. 1 figure 22-116. transmit message buffer slot status structure (cha) figure 22-117. transmit message buffer slot status structure (chb) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 vfa sya nfa sua sea cea bva tca reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb tcb 0 0 0 0 0 0 0 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 22-90. transmit message buffer slot status structure field descriptions field description vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = 0 1 vss!txconflict = 1 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1
flexray communication controller (flexray) 22-94 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.5.3 message buffer data field description the message buffer data field is used to store the fram e payload data, or a part of it, of the frame to be transmitted to or received from the flexray bus. the minimum required length of this field depends on the message buffer type that the physical mess age buffer is assigned to and is given in table 22-91 . the structure of the message buffer data field is given in figure 22-118 . note the controller will not a ccess any locations outside the message buffer data field boundaries given by table 22-91 . figure 22-118. message buffer data field structure the message buffer data fiel d is located in the flexray memory; thus , the controller has no means to control application write access to the field. to ensure data consistency, the a pplication must follow a write and read access scheme. sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = 0 1 vss!txconflict = 1 table 22-91. message buffer data field minimum length physical message buffer assigned to minimum length defined by individual message buffer in segment 1 mbdsr[mbseg1ds] receive shadow buffer in segment 1 mbdsr[mbseg1ds] individual message buffer in segment 2 mbdsr[mbseg2ds] receive shadow buffer in segment 2 mbdsr[mbseg2ds] receive fifo for channel a rfdsr[entry_size] (rfsr[sel] = 0) receive fifo for channel b rfdsr[entry_size] (rfsr[sel] = 1) 0123456789101112131415 0x0 data0 / mid0 / nmv0 data1 / mid1 / nmv1 0x2 data2 / nmv2 data3 / nmv3 ... ... ... 0xn-2 data n-2 data n-1 table 22-90. transmit message buffer slot status structure field descriptions (continued) field description
flexray communication controller (flexray) freescale semiconductor 22-95 pxr40 microcontroller reference manual, rev. 1 22.6.5.3.1 message buffer data field read access for transmit message buffers, the controller will not m odify the content of the me ssage buffer data field. thus the application can read ba ck the data at any time without any impact on data consistency. for receive message buffers the application must lock the related re ceive message buffer and retrieve the message buffer header index from the message buffer index registers (mbidxrn) . while the message buffer is locked, the controller will not update the message buffer data field. for receive fifos, the application can read the message buffer indicated by the receive fifo a read index register (rfarir) or the receive fifo b read index register (rfbrir) when the related fill levels in the receive fifo fill level and pop count register (rfflpcr) indicate an non-empty fifo. 22.6.5.3.2 message buffer data field write access for receive message buffers, receive shadow buffers, a nd receive fifos, the application must not write to the message buffer data field. for transmit message buffers, the application must follow the write access restrictions given in table 22-92 . 22.6.6 individual message bu ffer functional description the controller provides th ree basic types of indi vidual message buffers: 1. single transmit message buffers 2. double transmit message buffers 3. receive message buffers table 22-92. frame data write access constraints field single buffered double buffered commit side transmit side data, mid, nmv poc:config or mb_dis or mb_lck poc:config or mb_dis or mb_lck poc:config or mb_dis table 22-93. frame data field descriptions field description data 0, data 1, ... data n-1 message data ? provides the message data received or to be transmitted. for receive message buffer and receive fifos, this field provides the message data received for this message buffer. for transmit message buffers, the field provides the message data to be transmitted. mid 0, mid 1 message identifier ? if the payload preamble bit ppi is set in the message buffer frame header, the mid field holds the message id of a dynamic frame located in the message buffer. the re ceive fifo filter uses the received message id for message id filtering. nmv 0, nmv 1, ... nmv 11 network management vector ? if the payload preamble bit ppi is set in the message buffer frame header, the network management vector field holds the network managem ent vector of a static frame located in the message buffer. note: the mid and nmv bytes replace the corresponding data bytes.
flexray communication controller (flexray) 22-96 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 before an individual message buffer can be used, it must be configured by the appl ication. after the initial configuration, the message buffer can be reconfigured later. the set of the configuration data for individual message buffers is given in section 22.6.3.4.1, individual message buffer configuration data . 22.6.6.1 individual messag e buffer configuration the individual message buffer configur ation consists of two steps. the fi rst step is the allocation of the required amount of memory for the flexray memory. the second step is the pr ogramming of the message buffer configuration registers, whic h is described in this section. 22.6.6.1.1 common configuration data one part of the message buffer c onfiguration data is common to all individual message buffers and the receive shadow buffers. these data can onl y be set when the protocol is in the poc:config state. the application configures the num ber of utilized individual messag e buffers by writing the message buffer number of the last utilized message buffer into the last_mb_util field in the message buffer segment size and utilizat ion register (mbssutr) . the application configures the si ze of the two segments of individual message buffers by writing the message buffer number of the last me ssage buffer in the first segment into the last_mb_seg1 field in the message buffer segment size and utilization register (mbssutr) the application configures the length of the message buffer data fields for both of the message buffer segments by writing to the mbseg2ds and mbseg1ds fields in the message buffer data size register (mbdsr) . depending on the current rece ive functionality of the controller, the application must c onfigure the receive shadow buffers. for each se gment and for each channel with at least one indivi dual receive message buffer assigned, the application must configure th e related receive shadow buffer using the receive shadow buffer index register (rsbir) . 22.6.6.1.2 specific configuration data the second part of the message buffer configur ation data is specific for each message buffer. these data can be cha nged only when either ? the protocol is in the poc:config state or ? the message buffer is disa bled, i.e. mbccsrn[eds] = 0 the individual message buffer type is defined by the mtd and mbt bits in the message buffer configuration, control, st atus registers (mbccsrn) as given in table 22-94 . table 22-94. individual message buffer types mbccsrn[mtd] mbccsrn[mbt] individu al message buffer description 0 0 receive message buffer 01 reserved 1 0 single transmit message buffer 1 1 double transmit message buffer
flexray communication controller (flexray) freescale semiconductor 22-97 pxr40 microcontroller reference manual, rev. 1 the message buffer specific configuration data are 1. mcm, mbt, mtd bits in message buffer configuration, c ontrol, status registers (mbccsrn) 2. all fields and bits in message buffer cycle counter filter registers (mbccfrn) 3. all fields and bits in message buffer frame id registers (mbfidrn) 4. all fields and bits in message buffer inde x registers (mbidxrn) the meaning of the specific configurat ion data depends on the message buffe r type, as given in the detailed message buffer type descriptions section 22.6.6.2, single transmit message buffers , section 22.6.6.3, receive message buffers , and section 22.6.6.4, double transmit message buffer . 22.6.6.2 single transmit message buffers the section provides a detail ed description of the func tionality of single buffered transmit message buffers. a single transmit message buffer is us ed by the application to provide message data to the controller that will be transmitted over the flexray bus. the controller uses the transmit message buffers to provide information about the transmission pr ocess and status information about the slot in which message was transmitted. the individual message buffer with message buffer number n is configured to be a single transmit message buffer by the following settings: ? mbccsrn[mbt] = 0 (single buffered message buffer) ? mbccsrn[mtd] = 1 (transmit message buffer) 22.6.6.2.1 access regions to certain message buffer fields, both the application and the contro ller have access. to ensure data consistency, a message buffer locking scheme is implemented, which is used to control the access to the data, control, and status bits of a message buffer. the access regions for single transmit message buffers are depicted in figure 22-119 . a description of the regions is given in table 22-95 . if an region is active as indicated in table 22-96 , the access scheme given for that re gion applies to the message buffer.
flexray communication controller (flexray) 22-98 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 22-119. single transmit message buffer access regions the trigger bits mbccsrn[edt] and mbccsr n[lckt], and the interrupt enable bit mbccsrn[mbie] are not under access control and can be accessed from the app lication at any time. the status bits mbccsrn[eds] and mbccsrn[lcks] are not under access control and can be accessed from the controller at any time. the interrupt flag mbccsnr[mbif] is not under access control and can be accessed from the application and the controller at any time. contro ller clear access has higher priority. the controller restricts it s access to the regions depending on the cu rrent state of the message buffer. the application must adhere to these re strictions in order to ensure data consistency. the transmit message buffer states are given in figure 22-120 . a description of the states is given in table 22-96 , which also provides the access scheme for the access regions. the status bits mbccsrn[eds] and mbccsrn[lcks ] provide the application with the required message buffer status information. the internal stat us information is not visible to the application. 22.6.6.2.2 message buffer states this section describes the transmit message buffer states and provides a state diagram. table 22-95. single transmit message buffer access regions description region access from region used for application module cfg read/write - message buffer configuration msg read/write - message data and slot status access nf - read-only message header access for null frame transmission tx - read/write message transmission and slot status update cm - read-only message buffer validation sr - read-only message buffer search message buffer data field: data[0-n] message buffer header field: frame header mbccsrn[cmt] message buffer header field: slot status message buffer header field: data field offset mbccfrn[mtm/cha/chb/ccf*] mbfidrn[fid] mbidxrn[mbidx] mbccsrn[mbt/mtd] tx nf cmt sr cfg msg
flexray communication controller (flexray) freescale semiconductor 22-99 pxr40 microcontroller reference manual, rev. 1 figure 22-120. single transmit message buffer states table 22-96. single transmit message buffer state description state mbccsrn access region description eds lcks appl. module idle 1 0 ? cm, sr idle - message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. hdislck 0 1 cfg ? dis abled and l ock ed - message buffer under configuration. excluded from message buffer search. hlck 1 1 msg sr l ock ed - applications access to data, control, and status. included in message buffer search. ccsa 10?? s lot a ssigned - message buffer assigned to next static slot. ready for null frame transmission. hlckccsa 1 1 msg ? l ock ed and s lot a ssigned - applications access to data, control, and status.message buffer assigned to next static slot ccnf 1 0 ? nf n ull f rame transmission header is used for null frame transmission. hlckccnf 1 1 msg nf l ock ed and n ull f rame transmission - applications access to data, control, and status. header is used for null frame transmission. ccma 1 0 ? cm m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. hlckccma 1 1 msg ? l ock ed and m essage a vailable - applications access to data, control, and status. message buffer is assigned to next slot and cycle counter filter matches. cctx 10?tx message t ransmission - message buffer data transmit. payload data from buffer transmitted ccsu 1 0 ? tx s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. hdis reset_state hd he idle sa dss su ccsu ccsa cctx tx hlck hlckccsa ccnf hl hu ccma hl hu hlckccnf hlckccma sss sts he hl sts hu hl dss ma sss hdislck hd hu hl hu sts ma sss sa dss sts dss
flexray communication controller (flexray) 22-100 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.6.2.3 message buffer transitions application transitions the application transitions can be triggered by the a pplication using the commands described in table 22-97 . the application issues the commands by writing to the message buffer configuration, control, status registers (mbccsrn) . only one command can be issu ed with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands i ssued by writing 1 to the trigger bit mbccsrn[edt]. the transition that will be triggered by each of these comma nd depends on the current va lue of the status bit mbccsrn[eds]. if the command triggers the disable transition hd and the message buffer is in one of the states ccsa, hlckccsa, ccma, hlckccma, ccnf, hlckccnf, or cctx, th e disable transition has no effect (command is ignor ed) and the message buffer state is not ch anged. no notification is given to the application. message buffer lock and unlock the lock and unlock commands issued by writing 1 to the trigger bit mbccsr n[lckt]. the transition that will be triggered by each of these commands depends on the current value of the status bit mbccsrn[lcks]. if the comm and triggers the lock tr ansition hl and the message buffer is in the state cctx, the lock transition has no effect (command is i gnored) and message buffer state is not changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (chierfr) is set. module transitions the module transitions that can be triggered by the cont roller are described in table 22-98 . each transition will be triggered for certain message buffe rs when the related condition is fulfilled. table 22-97. single transmit message buffer application transitions transition command condition description he mbccsrn[edt]:= 1 mbccsrn[eds] = 0 application triggers message buffer enable. hd mbccsrn[eds] = 1 application triggers message buffer disable. hl mbccsrn[lckt]:= 1 mbccsrn[lcks] = 0 application triggers message buffer lock. hu mbccsrn[lcks] = 1 application triggers message buffer unlock. table 22-98. single transmit message buffer module transitions transition condition description sa slot match and static slot s lot a ssigned - message buffer is assigned to next static slot. ma slot match and cyclecounter match m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. tx slot start and mbccsrn[cmt] = 1 t ransmission slot start - slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. su status updated s tatus u pdated - slot status field and messa ge buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart - start of static slot.
flexray communication controller (flexray) freescale semiconductor 22-101 pxr40 microcontroller reference manual, rev. 1 transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 22-99 , the module transitions have a high er priority than the application transitions. for all states except the ccma state, both a lock/unlock tran sition hl/hd and a module transition can be executed at the same time. the resu lt state is reached by firs t applying the application transition and subsequently the module transition to the intermediately reached state. for example, if the message buffer is in the hlck state and the appli cation unlocks the message buffer by the hu transition and the module triggers the sl ot assigned transition sa, th e intermediate state is id le and the resulting state is ccsa. the priorities among the module transiti ons is given in the second part of table 22-99 . 22.6.6.2.4 transmit message setup to transmit a message over the flex ray bus, the application writes the message data into the message buffer data field and sets the commit bit cmt in the message buffer configuration, control, status registers (mbccsrn) . the physical access to the message bu ffer data field is described in section 22.6.3.1, individua l message buffers . as indicated by table 22-96 , the application shall write to the me ssage buffer data field and change the commit bit cmt only if the transmit message buffer is in one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma. the application can change the state of a message buffer if it issues the appropriate commands shown in table 22-97 . the state change is indicated through the mbccsrn[eds] and mbccsrn[lcks] status bits. if the transmit message buffer ente rs one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma the mbccsrn[dval] flag is negated. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart. - start of dynamic slot or symbol window or nit. sss slot start or symbol window start or nit start s lot or s egment s tart - start of static slot or dy namic slot or symbol window or nit. table 22-99. single transmit message buffer transition priorities state priorities description module vs. application idle, hlck sa > hd ma > hd slot assigned > message buffer disable message available > message buffer disable ccma tx > hl transmission start > message buffer lock module internal idle, hlck ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start table 22-98. single transmit message buffer module transitions (continued) transition condition description
flexray communication controller (flexray) 22-102 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.6.2.5 message transmission as a result of the message buffer search described in section 22.6.7, individual message buffer search , the controller triggers the message available transition ma for up to two transmit message buffers. this changes the message buffer state from idle to ccma and the message buffers can be used for message transmission in the next slot. the controller transmits a messag e from a message buffer if both of the following tw o conditions are fulfilled at the start of the transmission slot: 1. the message buffer is in th e message available state ccma 2. the message data are still valid, i.e. mbccsrn[cmt] = 1 in this case, the controller triggers the tx tran sition and changes the message buffer state to cctx. a transmit message buffer timing and state change diagram for message tran smission is given in figure 22-121 . in this example, the message buffer with message buffer number n is idle at the start of the search slot, matches the slot and cycle number of th e next slot, and message buffer data are valid, i.e. mbccsrn[cmt] = 1. figure 22-121. message transmission timing figure 22-122. message transmission from hlck state with unlock the amount of message data read from the flexra y memory and transferred to the flexray bus is determined by the following three items: ? the message buffer segment that the message buffer is assigned to, as defined by the message buffer segment size and util ization register (mbssutr) . ? the message buffer data field size, as defined by the related field of the message buffer data size register (mbdsr) ? the value of the pldlen field in the me ssage buffer header field, as described in section 22.6.5.2.1, frame header description search[s+1] mt start ma slot s tx su ccma cctx slot s+1 idle mt start idle slot s+2 slot start slot start slot start mt start message transmit sss ccsu search[s+1] mt st a rt m t s ta r t ma slot s tx sss hlckccma cctx slot s+1 hlck m t st a r t idle slot s+2 slot start slot start slot start hu ccma message transmit
flexray communication controller (flexray) freescale semiconductor 22-103 pxr40 microcontroller reference manual, rev. 1 if a message buffer is assigned to message buf fer segment 1, and pldlen > mbseg1ds, then 2 * mbseg1ds bytes will be read from the message buffer data field and zero padding is used for the remaining bytes for the flexray bus transfer. if pldlen <= mbseg1ds, the controller reads and transfers 2*pldlen bytes. the same holds for segment 2 and mbseg2ds. 22.6.6.2.6 null fr ame transmission a static slot with slot num ber s is assigned to the controller for cha nnel a, if at least one transmit message buffer is configured with the mbfidrn[fid] set to s and mbccfrn[cha] se t to 1. a null frame is transmitted in the static slot s on cha nnel a, if this slot is assigned to the controller for channel a, and all transmit message buffers with mbfidrn[fid] = s and mbccfrn[cha] = 1 are either not committed, i.e mbccsrn[cmt] = 0, or locked by the application, i.e. mbccsrn[lcks] = 1, or the cycle counter filter is enabled and does not match. additionally, the application can clear the commit bit of a message buf fer that is in the ccma state, which is called uncommit or transmit abort . this message buffer will be used for null frame transmission. as a result of the message buffer search described in section 22.6.7, individual message buffer search , the controller triggers the slot assi gned transition sa for up to two transm it message buffers if at least one of the conditions mentioned above is fulfilled for these message buffe rs. the transition sa changes the message buffer states from either id le to ccsa or from hlck to hlck ccsa. in each case, these message buffers will be used for null frame transmission in the next slot. a me ssage buffer timing and state change diagram for null frame transmission from idle state is given in figure 22-123 . figure 22-123. null frame transmission from idle state a message buffer timing and state ch ange diagram for null frame transm ission from hlck state is given in figure 22-124 . figure 22-124. null frame transmission from hlck state if a transmit message buffer is in the ccsa or hlckcc sa state at the start of the transmission slot, a null frame is transmitted in any case, even if the me ssage buffer is unlocked or committed before the transmission slot starts. a tran smit message buffer timing and stat e change diagra m for null frame transmission for this case is given in figure 22-125 . search[s+1] mt st a rt m t s ta r t sa slot s sts sss ccsa ccnf slot s+1 idle mt start idle slot s+2 slot start slot start slot start null frame transmit search[s+1] m t s tart m t s tart sa slot s sts sss hlckccsa hlckccnf slot s+1 hlck m t st a r t hlck slot s+2 slot start slot start slot start null frame transmit
flexray communication controller (flexray) 22-104 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 22-125. null frame transmission from hlck state with unlock since the null frame transmission will not use the messa ge buffer data, the appli cation can lock/unlock the message buffer during null frame tr ansmission. a transmit message buffer timing and state change diagram for null frame transmissi on for this case is given in figure 22-126 . figure 22-126. null frame transmission from idle state with locking 22.6.6.2.7 message buffer status update after the end of each slot, the pe generates the sl ot status vector. depending on the this status, the transmitted frame type, and the amount of transmitted data, the message buffer status is updated. message buffer status update a fter complete message transmission the term complete message transmissi on refers to the fact that all payload data stored in the message buffer were send to flexray bus. in this case, the cont roller updates the slot st atus field of the message buffer and triggers the stat us updated transition su. w ith the su transition, the c ontroller sets the message buffer interrupt flag mbccsn[mbif] to indica te the successful message transmission. depending on the transmission mode flag mbccfrn[mtm], the contro ller changes the commit flag mbccsrn[cmt] and the valid flag mbccsrn[dval]. if the mbccfrn [mtm] flag is negated, the message buffer is in the event transmission mode. in this case, each committed message is transmitted only once. the commit flag mbccsrn[cmt ] is cleared with the su trans ition. if the mbccfrn[mtm] flag is asserted, the message buffer is in the state transmission mode . in this case, each committed message is transmitted as long as the applicati on provides new data or locks the me ssage buffers. the controller will not clear the mbccsrn[cmt] flag at the end of transmission and will set the valid flag mbccsrn[dval] to indicate that the message will be transmitted again. search[s+1] m t s t ar t mt start sa slot s sts sss hlckccsa ccnf slot s+1 hlck mt s t art idle slot s+2 slot start slot start slot start hu ccsa null frame transmit search[s+1] m t s t ar t mt start sa slot s sts sss slot s+1 idle mt st a rt hlck slot s+2 slot start slot start slot start null frame transmit hl ccsa ccnf hlckccnf
flexray communication controller (flexray) freescale semiconductor 22-105 pxr40 microcontroller reference manual, rev. 1 message buffer status update a fter incomplete message transmission the term incomplete message transmission refers to the fact that not all payload data that should be transmitted were send to flexray bus. this may be caused by the following regular conditions in the dynamic segment: 1. the transmission slot starts in a minisl ot with a minislot number greater than platesttx . 2. the transmission slot did not ex ist in the dynamic segment at all. additionally, an incomplete message transmission can be caused by internal communication errors. if those error occur, the protocol engine communicati on failure interrupt flag pecf_if is set in the protocol interrupt flag register 1 (pifr1) . in any of these two cases, the status of the message buffer is not ch anged at all with th e su transition. the slot status field is not updated, the status and contro l flags are not changed, and th e interrupt flag is not set. message buffer status update after null frame transmission after the transmission of a null fram e, the status of the message buffe r that was used for the null frame transmission is not changed at all. the slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. 22.6.6.3 receive message buffers the section provides a detailed description of th e functionality of the receive message buffers. a receive message buffer is used to receive a message from the flex ray bus based on individual filter criteria. the controller uses the receive message buffe r to provide the following data to the application 1. message data received 2. information about the reception process 3. status information about the slot in which the message was received a individual message buffer with message buffer number n is configured as a receive message buffer by the following configuration settings ? mbccsrn[mbt] = 0 (single buffered message buffer) ? mbccsrn[mtd] = 0 (receive message buffer) to certain message buffer fields, both the application and the contro ller have access. to ensure data consistency, a message buffer locking scheme is implem ented that is used to c ontrol the access to the data, control, and status bits of a messa ge buffer. the access regions for rece ive message buffers are depicted in figure 22-127 . a description of the regions is given in table 22-100 . if an region is ac tive as indicated in table 22-101 , the access scheme given for that re gion applies to the message buffer.
flexray communication controller (flexray) 22-106 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 22-127. receive message buffer access regions the trigger bits mbccsrn[edt] a nd mbccsrn[lckt] and the interr upt enable bit mbccsrn[mbie] are not under access control and can be accessed from the application at any time. the status bits mbccsrn[eds] and mbccsrn[lcks] are not under access control and can be accessed from the controller at any time. the interrupt flag mbccsrn[mbif] is not under access control and can be accessed from the application and the controller at any time. cont roller set access has higher priority. the controller restricts it s access to the regions depending on the cu rrent state of the message buffer. the application must adhere to these re strictions in order to ensure data consistency. th e receive message buffer states are given in figure 22-128 . a description of the message buffer states is given in table 22-96 , which also provides the access scheme for the access regions. the status bits mbccsrn[e ds] and mbccsrn[lcks] provide the a pplication with the required status information. the internal status informat ion is not visible to the application. table 22-100. receive message buffer access region description region access from region used for application module cfg read/write - message buffer configuration, message data and status access msg read/write - message data, header, and status access rx - write-only message reception and status update sr - read-only message buffer search data message buffer data field: data[0-n] message buffer header field: frame header mbccsrn[dval/dup] message buffer header field: slot status message buffer header field: data field offset mbccfrn[cha/chb/ccf*] mbfidrn[fid] mbidxrn[mbidx] mbccsrn[mtd] rx sr cfg msg
flexray communication controller (flexray) freescale semiconductor 22-107 pxr40 microcontroller reference manual, rev. 1 figure 22-128. receive message buffer states 22.6.6.3.1 message buffer transitions application transitions the application transitions that ca n be triggered by the application using the commands described in table 22-102 . the application issues the commands by writing to the message buffer configuration, control, status registers (mbccsrn) . only one command can be issu ed with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable table 22-101. receive message buffer states and access state mbccsrn access from description eds lcks appl. module idle 10?sr idle - message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. hdislck 0 1 cfg ? dis abled and l ock ed - message buffer under configuration. excluded from message buffer search. hlck 1 1 msg ? l ock ed - applications access to data, control, and status. included in message buffer search. ccbs 10?? b uffer s ubscribed - message buffer subscribed for reception. filter matches next (slot, cycle, channel) tuple. hlckccbs 1 1 msg ? l ock ed and b uffer s ubscribed - applications access to data, control, and status. message buff er subscribed for reception. ccrx 10?? message r eceive - message data received into related shadow buffer. hlckccrx 1 1 msg ? l ock ed and message r eceive - applications access to data, control, and status. message data received into related shadow buffer. ccsu 1 0 ? rx s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. hdis reset_state hd he idle bs sns su ccsu ccbs ccrx hlck hlckccbs hlckccrx sss sls he hl hdislck hd hl hu bs sns hl hu hu hl hu sls sss
flexray communication controller (flexray) 22-108 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the enable and disable commands i ssued by writing 1 to the trigger bit mbccsrn[edt]. the transition that will be triggered by each of these comma nd depends on the current va lue of the status bit mbccsrn[eds]. if the command triggers the disable transition hd and the message buffer is in one of the states ccbs, hlckccbs, or ccrx, the disable tr ansition has no effect (com mand is ignored) and the message buffer state is not changed. no not ification is given to the application. message buffer lock and unlock the lock and unlock commands issued by writing 1 to the trigger bit mbccsr n[lckt]. the transition that will be triggered by each of these commands depends on the current value of the status bit mbccsrn[lcks]. if the command triggers the lock tran sition hl while the message buffer is in the state ccrx, the lock transition ha s no effect (command is ig nored) and message buffer st ate is not changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (chierfr) is set. module transitions the module transitions that can be trigge red by the controller are described in table 22-103 . each transition will be triggered for certain message buffers when the related condition is fulfilled. transition priorities the application can tr igger only one transition at a time. there is no need to sp ecify priorities among them. as shown in table 22-104 , the module transitions have a higher prio rity than the application transitions. for all states except the ccrx stat e, a module transition and the appli cation lock/unlock transition hl/hu and can be executed at the same ti me. the result state is reached by first applying the module transition and subsequently the application tran sition to the intermediately reached state. for example, if the message buffer is in the buffer subscribed state ccbs and the module triggers the slot st art transition sls at the table 22-102. receive message buffer application transitions transition host command condition description he mbccsrn[edt]:= 1 mbccsrn[eds] = 0 application triggers message buffer enable. hd mbccsrn[eds] = 1 application triggers message buffer disable. hl mbccsrn[lckt]:= 1 mbccsrn[lcks] = 0 application triggers message buffer lock. hu mbccsrn[lcks] = 1 application triggers message buffer unlock. table 22-103. receive message buffer module transitions transition condition description bs slot match and cyclecounter match b uffer s ubscribed - the message buffer filter matches next slot and cycle. sls slot start sl ot s tart - start of either static slot or dynamic slot. sns symbol window start or nit start s ymbol window or n it s tart - start of either symbol window or nit. sss slot start or symbol window start or nit start sl ot or s egment s tart - start of either static slot, dynamic slot, symbol window, or nit. su status updated s tatus u pdated - slot status field, message bu ffer status flags, header index updated. interrupt flag set.
flexray communication controller (flexray) freescale semiconductor 22-109 pxr40 microcontroller reference manual, rev. 1 same time as the applicat ion locks the message buffer by the hl transition, the in termediate state is ccrx and the resulting state is locked buffer subscribed state hlckccrx. 22.6.6.3.2 message reception as a result of the message buffer search, the contro ller changes the state of up to two enabled receive message buffers from either idle state idle or locked state hlck to the either subscribed state ccbs or locked buffer subscribed state hlckccbs by tr iggering the buffer subscribed transition bs. if the receive message buffers for the next slot are assigned to both channels, then at most one receive message buffer is changed to a buffer subscribed state . if more than one matching message buffers assigned to a certain channe l, then only the message buffer with the lowest message buffer number is in one of the states mentioned above. with the start of the next static or dynamic slot the module trigger th e slot start transition sls. this changes the state of the subscribed receive messa ge buffers from either ccbs to ccrx or from hlckccbs to hlckccrx, respectively. during the reception slot, the recei ved frame data are written into the shadow buffers. for details on receive shadow buffers, see section 22.6.6.3.5, receive sha dow buffers concept . the data and status of the receive message buffers that are the ccrx or hlckccrx are not modified in the reception slot. 22.6.6.3.3 message buffer update with the start of the next static or dynamic slot or with th e start of the symbol wi ndow or nit, the module triggers the slot or segment start transition sss. this transition change s the state of the receiving receive message buffers from either ccrx to ccs u or from hlckccrx to hlck, respectively. if a message buffer was in the locked state hlckccr x, no update will be perfor med. the received data are lost. this is indica ted by setting the frame lost channel a/ b error flag frla_e f/frlb_ef in the chi error flag register (chierfr) . if a message buffer was in th e ccrx state it is now in the ccsu state. after the evaluation of the slot status provided by the pe the message buffe r is updated. the message buffer upda te depends on the slot status bits and the segment the message buffer is assigned to. this is described in table 22-105 . table 22-104. receive message buffer transition priorities state priorities description module vs. application idle bs > hd buffer subscribed > message buffer disable hlck bs > hd buffer subscribed > message buffer disable ccrx sss > hl slot or segment start > message buffer lock
flexray communication controller (flexray) 22-110 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note if the number of the last slot in th e current communication cycle on a given channel is n , then all receive message buffers assigned to this channel with mbfidrn[fid] > n will not be updated at all. when the receive message buffer update has finished the status updated transition su is triggered, which changes the buffer state from ccsu to idle. an exam ple receive message buffer timing and state change diagram for a normal fram e reception is given in figure 22-129 . figure 22-129. message reception timing the amount of message data written into the message buffer data field of the receive shadow buffer is determined by the following two items: 1. the message buffer segment that the messag e buffer is assigned to, as defined by the message buffer segment size and util ization register (mbssutr) . table 22-105. receive message buffer update vss!validframe vrf!header!nfindicator update description 11 valid non-null frame received. - message buffer data field updated. - frame header field updated. - slot status field updated. - dup:= 1 - dval:= 1 - mbif:= 1 10 valid null frame received. - message buffer data field not updated. - frame header field not updated. - slot status field updated. - dup:= 0 - dval not changed - mbif:= 1 0x no valid frame received. - message buffer data field not updated. - frame header field not updated. - slot status field updated. - dup:= 0 - dval not changed. - mbif:= 1, if the slot was not an empty dynamic slot. note: an empty dynamic slot is indicated by the following frame and slot status bit values: vss!validframe = 0 and vss!syntaxerror = 0 and vss!contenterror = 0 and vss!bviolation = 0. search[s+1] m t star t bs slot s sls su ccbs ccrx slot s+1 idle m t st a r t idle slot s+2 slot start slot start m t star t message receive to receive shadow buffer sss ccsu slot start
flexray communication controller (flexray) freescale semiconductor 22-111 pxr40 microcontroller reference manual, rev. 1 2. the message buffer data field size, as defined by the related field of the message buffer data size register (mbdsr) 3. the number of bytes received over the flexray bus if the message buffer is assigned to the message buf fer segment 1, and the number of received bytes is greater than 2*mbdsr.mbseg1ds, the controller writes only 2*m bdsr.mbseg1ds bytes into the message buffer data field of the receive shadow buf fer. if the number of received bytes is less than 2*mbdsr.mbseg1ds, the controller wr ites only the received number of bytes and will not change the trailing bytes in the message buffer da ta field of the receive shadow buffe r. the same holds for the message buffer segment 2 with mbdsr.mbseg2ds. 22.6.6.3.4 received message access to access the message data received over the flexray bus, the application reads the message data stored in the message buffer data field of the corresponding receive message buffer. the access to the message buffer data field is described in section 22.6.3.1, individual message buffers . the application can read the message buffer data field if the receive me ssage buffer is one of the states hdis, hdislck, or hlck. if th e message buffer is in one of these stat es, the controller will not change the content of the message buffer. 22.6.6.3.5 receive shadow buffers concept the receive shadow buffer concept applies only to individua l receive message buffers. the intention of this concept is to ensure that only syntactically and se mantically valid received non-null frames are presented to the application in a receive message buffer. the basic structure of a receive shadow buffer is described in section 22.6.3.2, receive shadow buffers . the receive shadow buffers temporar ily store the received frame header and message data. after the slot boundary the slot status information is generated. if the slot status info rmation indicates the reception of the valid non-nu ll frame (see table 22-105 ), the controller writes the slot st atus into the slot status field of the receive shadow buffer and exchanges the content of the message buffer index registers (mbidxrn) with the content of the corresponding internal shadow buffer index register. in all other cases, the controller writes the slot status into the identified receive message buffer, depe nding on the slot status and the flexray segment the message buffer is assigned to. the shadow buffer concept, with its index exchange, re sults in the fact that the flexray memory located message buffer associated to an individual receive me ssage buffer changes after su ccessful reception of a valid frame. this means that the message buffer ar ea in the flexray memory accessed by the application for reading the received message is di fferent from the initial setting of the message buffer. therefore, the application must not rely on the index information written initially into the message buffer index registers (mbidxrn) . instead, the index of the message buffer header field must be fetched from the message buffer index registers (mbidxrn) . 22.6.6.4 double transmit message buffer the section provides a detailed description of the functionality of the double transmit message buffers.
flexray communication controller (flexray) 22-112 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 double transmit message buffers are used by the applic ation to provide the controller with the message data to be transmitted over the fl exray bus. the controller uses this message buffer to provide information to the application about the transmission process, and status information about the slot in which message data was transmitted. in contrast to the single transmit message buffers, the application can provide new transmis sion data while the transmission of the previously provided message data is running. this scheme is called double buffering and can be considered as a fifo of depth 2. double transmit message buffers are implemented by combining two indi vidual message buff ers that form the two sides of an double transmit me ssage buffer. one side is called the commit side and will be accessed by the application to provi de the message data. the other side is called the transmit side and is used by the controller to transmit the message data to the flexra y bus. the two sides are loca ted in adjace nt individual message buffers. the message buffer th at implements the commit side ha s an even message buffer number 2n. the transmit side message buffer follows the com mit side message buffer and has the message buffer number 2n+1. the basic structure and data flow of a double transmit message buffer is given in figure 22-130 . figure 22-130. double transmit buffer structure and data flow note both the commit and the transmit side must be configured with identical values except for the message buffer index registers (mbidxrn) . 22.6.6.4.1 access regions to certain message buffer fields, both the application and the contro ller have access. to ensure data consistency, a message buffer locki ng scheme is implemented, which cont rols the exclusive access to the data, control, and status bits of the message buffer. the access scheme for double transmit message buffers is depicted in figure 22-131 . the given regions represent fields that can be accesse d from both the application and the controller and, t hus, require access restrictions. a description of the regions is given in table 22-106 . commit side transmit side application flexray bus mb# 2n mb# 2n+1 internal message transfer message data message data message data
flexray communication controller (flexray) freescale semiconductor 22-113 pxr40 microcontroller reference manual, rev. 1 figure 22-131. double transmit message buffer access regions layout the trigger bits mbccsrn[edt] and mbccsr n[lckt], and the interrupt enable bit mbccsrn[mbie] are not under access control and can be accessed from the app lication at any time. the status bits mbccsrn[eds] and mbccsrn[lcks] are not under access control and can be accessed from the controller at any time. the interrupt flag mbccsnr.mbif is not under access control and ca n be accessed from the application and the controller at any time. cont roller set access has higher priority. the controller restricts its access to the regions, depending on the curren t state of the corresponding part of the double transmit message buffer. the application must adhere to thes e restrictions in order to ensure data consistency. the states fo r the commit side of a double transm it message buffer are given in figure 22-132 . a description of the states is given in table 22-108 . the states for the transmit side of a table 22-106. double transmit message buffer access regions description access description region type application module commit side cfg read/write - message buffer configuration msg read/write - message buffer data and control access itx - read/write internal message transfer. ss - write-only slot status update transmit side cfg read/write - message buffer configuration sr - read-only message buffer search tx - read-only internal message transfer, message transmission ss - write-only slot status update message buffer data field: data[0-n] message buffer header field: frame header mbccsr(2n)[cmt] message buffer header field: slot status message buffer header field: data field offset mbccfr(2n)[mtm/cha/chb/ccf*] mbfidr(2n)[fid] mbidxr(2n)[mbidx] mbccsr(2n)[mbt/mtd] message buffer data field: data[0-n] message buffer header field: frame header mbccsr(2n+1)[cmt] message buffer header field: slot status message buffer header field: data field offset mbccfr(2n+1)[mtm/cha/chb/ccf*] mbfidr(2n+1)[fid] mbidxr(2n+1)]mbidx] mbccsr(2n+1)[mbt/mtd] commit side transmit side cfg msg cfg itx ss ss sr tx
flexray communication controller (flexray) 22-114 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 double transmit message buffer are given in figure 22-133 . a description of the states is given in table 22-108 . the description tables also provide the access scheme for the access regions. the status bits mbccsrn[eds] and mbccsrn[lcks ] provide the application with the required message buffer status information. the internal stat us information is not visible to the application. 22.6.6.4.2 message buffer states this section describes the transmit message buffer states and provides a state diagram. figure 22-132. double transmit message buffer state diagram (commit side) a description of the states of the commit side of a double transm it message buffer is given in table 22-107 . table 22-107. double transmit message buffer state description (commit side) state mbccsr(2n) access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled - message buffer under configuration. commit side can not be used for internal message transfer. ccitx 1 0 ? itx i nternal message t ransfer - message buffer data transferred from commit side to transmit side. commit side specific states idle 1 0 ? itx, ss idle - message buffer commit side is idle. commit side can be used for internal message transfer. hdislck 0 1 cfg ss dis abled and l ock ed - message buffer under configuration. commit side can not be used for internal message transfer. hlck 1 1 msg ss l ock ed - applications access to data, control, and status. commit side can not be used for internal message transfer. hdis reset_state hd he idle is ie ccitx hlck he hl hu hdislck hu hd hl
flexray communication controller (flexray) freescale semiconductor 22-115 pxr40 microcontroller reference manual, rev. 1 figure 22-133. double transmit message buffer state diagram (transmit side) a description of the states of th e transmit side of a double tran smit message buffer is given in table 22-108 . table 22-108. double transmit message buffer state description (transmit side) state mbccsrn access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. ccitx 1 0 ? tx i nternal m essage t ransfer - message buffer data transferred from commit side to transmit side. transmit side specific states idle 1 0 ? sr idle - message buffer transmit side is idle. transmit side is included in message buffer search. ccsa 1 0 ? ? s lot a ssigned - message buffer assigned to next static slot. ready for null frame transmission. ccsaccitx 1 0 ? tx s lot a ssigned and i nternal m essage t ransfer - message buffer assigned to next static slot and message buffer data transferred from commit side to transmit side. ccnf 1 0 ? tx n ull f rame transmission header is used for null frame transmission. ccnfccitx 1 0 ? tx n ull f rame transmission and i nternal m essage t ransfer - header is used for null frame transmission and message buffer data transferred from commit side to transmit side. ccma 1 0 ? ? m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. ccmaccitx 1 0 ? ? m essage a vailable and i nternal m essage t ransfer - message buffer is assigned to next slot and cycle counter filter matches and message buffer data transferred from commit side to transmit side. hdis reset_state hd he idle sa dss su ccsu ccsa cctx tx ccitx ccsaccitx ccnf is ie ccma is ie ccnfccitx ccmaccitx sss sts is ie sts ie is dss ma sss
flexray communication controller (flexray) 22-116 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.6.4.3 message buffer transitions application transitions the application transitions that ca n be triggered by the application using the commands described in table 22-109 . the application issues the commands by writing to the message buffer configuration, control, status registers (mbccsrn) . only one command can be issu ed with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands can be issued on the transmit side onl y. any enable or disable command issued on the commit side will be ignored without not ification. the tr ansitions that will be triggered depends on the value of the eds bit. the enable and disable commands will affe ct both the commit side and the transmit side at the same time. if the a pplication triggers the disa ble transition hd while the transmit side is in one of the states ccsa, ccsaccitx, cc nf, ccnfccitx, ccma, ccmaccitx, cctx, or ccsu, the disable transition ha s no effect (command is ignored) an d the message buffer state is not changed. no notification is given to the application. message buffer lock and unlock the lock and unlock commands can be issued on th e commit side only. any lock or unlock command issued on the transmit side will be ignored and th e double transmit buffer lock error flag dbl_ef in the chi error flag register (chierfr) will be set. the transitions that will be triggered depends on the current value of the lcks bit. th e lock and unlock commands will onl y affect the commit side. if the application triggers the lock transi tion hl while the commit side is in the state ccitx, the message buffer state will not be changed and the message buffer lock error flag lck_ef in the chi error flag register (chierfr) will be set. cctx 1 0 ? tx message t ransmission - message buffer data transmit. payload data from buffer transmitted ccsu 1 0 ? ss s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. note: the slot status field of the comm it side is updated too, even if the application has locked the commit side. table 22-109. double transmit message buffer host transitions transition host command condition description he mbccsr(2n+1)[edt]:=1 mbccsr(2n+1)[eds] = 0 application triggers message buffer enable. hd mbccsr(2n+1)[eds] = 1 application triggers message buffer disable. hl mbccsr(2n)[lckt]:=1 mbccsr(2n)[lcks] = 0 application triggers message buffer lock. hu mbccsr(2n)[lcks] = 1 application triggers message buffer unlock. table 22-108. double transmit message buffer state description (transmit side) (continued) state mbccsrn access region description eds lcks appl. module
flexray communication controller (flexray) freescale semiconductor 22-117 pxr40 microcontroller reference manual, rev. 1 module transitions the module transitions that can be trigge red by the controller are described in table 22-110 . the transitions c1 and c2 apply to both sides of the mess age buffer and are applied at the same time. all other controller transitions apply to the transmit side only. transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 22-111 , the module transitions have a higher priority than the application transitions. the priorities among the controll er transitions and the rela ted states are given in the second part of table 22-111 . these priorities apply only to the transmit side. the internal message transmit start transition is has tho lowest priority. table 22-110. double transmit message buffer module transitions transition condition description common transitions is see section 22.6.6.4.5, internal message transfer i nternal message transfer s tart - start transfer of message data from commit side to transmit side. ie i nternal message transfer e nd - stop transfer of message data from commit side to transmit side. note: the internal message transfer is st opped before the slot or segment start. transmit side specific transitions sa slot match and static slot s lot a ssigned - message buffer is assigned to next static slot. ma slot match and cyclecounter match m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. tx slot start and mbccsr(2n+1)[cmt]=1 t ransmission slot start - slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. su status updated s tatus u pdated - slot status field and messa ge buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart - start of static slot. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart. - start of dynamic slot or symbol window or nit. sss slot start or symbol window start or nit start s lot or s egment s tart - start of static slot or dy namic slot or symbol window or nit. table 22-111. double transmit message buffer transition priorities state priority description module vs. application idle is > hd is > hl internal message transfer start > message buffer disable internal message transfer start > message buffer lock module internal idle ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start
flexray communication controller (flexray) 22-118 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.6.4.4 message preparation the application provides the message data through the commit side. the transmission itself is executed from the transmit side. the transfer of the message data from the commit side to th e transmit side is done by the internal message transfer , which is described in section 22.6.6.4.5, internal message transfer to transmit a message over the flex ray bus, the application writes the message data into the message buffer data field of the commit side and sets the commit bit cmt in the message buffer configuration, control, status registers (mbccsrn) . the physical access to the message buffer data field is described in section 22.6.3.1, individual message buffers . as indicated by table 22-107 , the application shall write to the me ssage buffer data field and change the commit bit cmt only if the transmit message buffer is in one of the st ates hdis, hdislck, or hlck. the application can change the state of a message buffe r if it issues the appropriate commands shown in table 22-109 . the state change is indicated through th e mbccsrn[eds] and m bccsrn[lcks] status bits. 22.6.6.4.5 internal message transfer the internal message transfer transf ers the message data from the commit side to the transmit side. the internal message transfer is implemented as the swapping of the content of the message buffer index registers (mbidxrn) of the commit side and the transmit si de. after the swapping, the commit side cmt bit is cleared, the commit side interrupt flag mbif is set, the transmit side cmt bit is set, and the transmit side dval bit is cleared. the conditions and the point in time when the internal message transfer is started are controlled by the message buffer commit mode bit mcm in the message buffer configuration, control, status registers (mbccsrn) . the mcm bit configures the me ssage buffer for either the st reaming commit mode or the immediate commit mode. a detail ed description is given in streaming commit mode and immediate commit mode . the internal message transfer is triggered wi th the transition is. both sides of the message buffer enter one of the ccitx states. the internal me ssage transfer is finished with the transition ie. streaming commit mode the intention of the streaming commit mode is to ensure that each committed message is transmitted at least once . the controller will not start th e internal message tr ansfer for a message buffer as long as the message data on the transmit side is not transmitted at least once. the streaming commit mode is conf igured by clearing the message buffer commit mode bit mcm in the message buffer configuration, cont rol, status registers (mbccsrn) . in this mode, the internal message tr ansfer from the commit side to the transmit side is started for a double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data are valid, i.e. mbccsr(2n)[cmt] = 1 3. the transmit side is in one of the states idle, ccsa, or ccma 4. the transmit side contains either no vali d message data, i.e. mbccsr(2n+1)[cmt] = 0 or the message data were tr ansmitted at least once, i.e. mbccsr(2n+1)[dval] = 1
flexray communication controller (flexray) freescale semiconductor 22-119 pxr40 microcontroller reference manual, rev. 1 an example of a streami ng commit mode state cha nge diagram is given in figure 22-134 . in this example, both the commit and the transmit si de do not contain valid message data and the application provides two messages. the message buffer does not match the next slot. figure 22-134. internal message transfer in streaming commit mode immediate commit mode the intention of the immediate co mmit mode is to transmit the latest data provided by the application. this implies that it is not guaranteed that each pr ovided message will be tr ansmitted at least once. the immediate commit mode is configured by setti ng the message buffer commit mode bit mcm in the message buffer configuration, cont rol, status registers (mbccsrn) . in this mode, the internal message transfer from the commit side to the transmit side is started for one double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data are valid, i.e. mbccsr(2n)[cmt] = 1 3. the transmit side is in one of the states idle, ccsa, or ccma it is not checked whether the transm it side contains no valid message data or valid message data were transmitted at least once. if message data are va lid and not transmitted, th ey may be overwritten. an example of a streami ng commit mode state cha nge diagram is given in figure 22-135 . in this example, both the commit and the tran smit side do not contain valid message data, and the applic ation provides two messages and the first message is gets overwritte n. the message buffer does not match the next slot. figure 22-135. internal message transfer in immediate commit mode idle commit transmit idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu ccitx idle is ccitx ie idle hl hlck hu idle idle no internal message transfer, until message transmitted idle commit transmit idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu ccitx idle is ccitx ie idle hl hlck hu idle ccitx idle is ccitx ie idle idle internal message transfer overwrites non-transmitted message
flexray communication controller (flexray) 22-120 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.6.4.6 message transmission for double transmit message buffers, the message buffer search checks only the transmit side part. the internal scheduling ensures, that the internal message transfer is stopped on the me ssage buffer search start. thus, the transmit side of message buffer, that is not in its transmis sion or status update slot, is always in the idle state. the message transmit behavior and transmission state changes of the transmit side of a double transmit message buffer are the same as for si ngle buffered transmit buffers, except that the transm it side of double buffers can not be locked by the application, i.e. the hu and hl transition do not ex ist. therefore, refer to section 22.6.6.2.5, message transmission. 22.6.6.4.7 message buffer status update the message buffer status u pdate behavior of the tran smit side of a double transm it message buffer is the same as for single transmit message buffers which is described in section 22.6.6.2.7, message buffer status update. additionally, the slot status field of the commit side is update after the update of the sl ot status field of the transmit side, even if the commit side is locked by th e application. this is implem ented to provide the slot status of the most r ecent transmission slot. 22.6.7 individual message buffer search this section provides a detailed descripti on of the message buffer search algorithm. the message buffer search determines for each enabled channel if a slot s in a communication cycle c is assigned for frame or null frame tran smission or if it is subscribed for frame reception on that channel. the message buffer search is a se quential algorithm which is invoked at the following protocol related events: 1. nit start 2. slot start in the static segment 3. minislot start in the dynamic segment the message buffer search within the nit searches fo r message buffers assigned or subscribed to slot 1. the message buffer search within slot n searches for message buffers a ssigned or subscribed to slot n+1 . in general, the message buffer search for the next slot n considers only message buffers which are 1. enabled, i.e. mbccsrn[eds] = 1, and 2. matches the next slot n , i.e. mbfidrn[fid] = n , and 3. are the transmit side buffer in ca se of a double transmit message buffer. on top of that, for the static se gment only those message buffers are considered, that match the condition of at least one row of table 22-112 . for the dynamic segment only those message buffers are considered, that match the condition of at least one row of table 22-113 . these message buf fers are called matching message buffers.
flexray communication controller (flexray) freescale semiconductor 22-121 pxr40 microcontroller reference manual, rev. 1 for each enabled channel the message buffer search may identify multiple matching message buffers. among all matching message buffers the message buffers with highest pr iority according to table 22-112 for the static segment and according to table 22-113 for the dynamic segment are selected. if there are multiple message buffer with highest pr iority, the message buffer with the lowest message buffer number is selected. all messa ge buffer which have the highest pr iority must have a consistent channel assignment as specified in section 22.6.7.2, message buffer ch annel assignment consistency . depending on the message buffer ch annel assignment the same messa ge buffer can be found for both channel a and channel b. in this case, this message buffer is used as described in section 22.6.3.1, individual message buffers . 22.6.7.1 message buffer cycle counter filtering the message buffer cycle counter filter is a valu e-mask filter defined by the ccfe, ccfmsk, and ccfval fields in the message buffer cycle counter filter registers (mbccfrn) . this filter determines a set of communication cycles in which the message buf fer is considered for message reception or message transmission. if the cycle c ounter filter is disabled, i.e. ccfe = 0, this set of cycles consists of all communication cycles. if the cycle counter filter of a message buffer does not match a certain communication cycle number, this message buffer is not considered for message transmi ssion or reception in that communication cycle. in case of a transmit message buffer as signed to a slot in the static segment, though, this buffer is added to the matching message buffers to i ndicate the slot assignment and to trigger the null frame transmission. table 22-112. message buffer search priority (static segment) priority mtd lcks cmt ccfm 1 1 cycle counter filter match, see section 22.6.7.1, message buff er cycle counter filtering. description transition (highest) 0 1011transmit buffer, matches cycle c ount, not locked and committed ma 1 1 - 0 1 transmit buffer, matches cycle count, not committed sa 1 1 - 1 transmit buffer, matches cycle count, locked sa 2 1 - - - transmit buffer sa 3 0 0 n/a 1 receive buffer, matches cycle count, not locked sb (lowest) 4 0 1 n/a 1 receive buffer, matches cycle count, locked sb table 22-113. message buffer search priority (dynamic segment) priority mtd lcks cmt ccfm 1 1 cycle counter filter match, see section 22.6.7.1, message buff er cycle counter filtering. description transition (highest) 0 1011transmit buffer, matches cycle c ount, not locked and committed ma 1 0 0 n/a 1 receive buffer, matches cycle count, not locked sb (lowest) 2 0 1 n/a 1 receive buffer, matches cycle count, locked sb
flexray communication controller (flexray) 22-122 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the cycle counter filter of a me ssage buffer matches the communicat ion cycle with the number cyccnt if at least one of the followi ng conditions evaluates to true: eqn. 22-12 eqn. 22-13 22.6.7.2 message buffer channel assignment consistency the message buffer channel assignment given by the cha and chb bits in the message buffer cycle counter filter re gisters (mbccfrn) defines the channels on which the message buffer will receive or transmit. the message buffer with number n transmits or receives on channel a if mbccfrn[cha] = 1 and transmits or receives on channel b if mbccfrn[chb] = 1. to ensure correct message buffer operation, all messag e buffers assigned to the same slot and with the same priority must have a consistent channel assignment. that means they must be either assigned to one channel only, or must be assigned to both channels. the behavior of the message buffer search is not defined, if both types of ch annel assignments occur for one slot a nd priority. an inconsistent channel assignment for message buffer 0 and message buffer 1 is depicted in figure 22-136 . figure 22-136. inconsistent channel assignment 22.6.7.3 node related slot multiplexing the term node related slot multiplexing applies to the dynamic segment only and refers to the functionality if there are transmit as well as receive message buffers are configured for the same slot. according to table 22-113 the transmit buffer is only found if the cycle counter filter matches, and the buffer is not locked and committed. in all other cases, the receive buffer will be found. t hus, if the block has no data to transmit in a dynamic slot, it is able to receive frames on that slot. 22.6.7.4 message buffer search error if the message buffer search is running while the ne xt message buffer search start event appears, the message buffer search is stopped and the message bu ffer search error flag msb_ef is set in the chi error flag register (chierfr) . this appears only if the chi freque ncy is too low to search through all message buffers within the nit or a minislot. the messa ge buffer result is not defined in this case. for more details see section 22.7.3, number of usable message buffers. 22.6.8 individual message buffer reconfiguration the initial configuration of each i ndividual message buffer can be changed even when the protocol is not in the poc:config state. this is referred to as individual message buffer reconfiguration . the configuration bits and fiel ds that can be changed ar e given in the section on specific configuration data . mbccfrn ccfe ?? 0 = cyccnt & mbccfrn ccfmsk ?? mbccfrn ccfval ?? & mbccfrn ccfmsk ? = mb0 mbccfr0[cha] = 1, mbccfr0[chb] = 0 mb1 dual channel assignment single channel assignment mbfidr0[fid] = 10 mbfidr1[fid] = 10 mbccfr1[cha] = 1, mbccfr1[chb] = 1
flexray communication controller (flexray) freescale semiconductor 22-123 pxr40 microcontroller reference manual, rev. 1 the common configuration data given in the section on specific configuration data can not be reconfigured when the protocol is out of the poc:config state. 22.6.8.1 reconfiguration schemes depending on the target and destinatio n basic state of the message buffer th at is to be reconfigured, there are three reconfiguration schemes. 22.6.8.1.1 basic type not changed (rc1) a reconfiguration will not change the basic type of the individual message buffer, if both the message buffer transfer direction bit mb ccsn[mtd] and the message buffer type bit mbccsn[mbt] are not changed. this type of reconfi guration is denoted by rc1 in figure 22-137 . single transmit and receive message buffers can be rc1-reconfigured when in th e hdis or hdislck state. double transmit message buffers can be rc1-reconfigured if both the transmit side and the commit side are in the hdis state. 22.6.8.1.2 buffer type not changed (rc2) a reconfiguration will not change the buffer type of the individual me ssage buffer if the message buffer buffer type bit mbccsrn[mbt] is not changed. this type of reconfiguration is denoted by rc2 in figure 22-137 . it applies only to single transmit and recei ve message buffers. singl e transmit and receive message buffers can be rc2-reconfigured when in the hdis or hdislck state. 22.6.8.1.3 buffer type changed (rc3) a reconfiguration will change the buffer type of th e individual message buffer if the message buffer type bit mbccsrn[mbt] is changed. this type of reconfiguration is denoted by rc3 in figure 22-137 . the rc3 reconfiguration splits one double buffer into two single buffers or combines two single buffer into one double buffer. in the la ter case, the two single message buffers must have consecutive message buffer numbers and the smaller one must be even. message bu ffers can be rc3 reconfigured if they are in the hdis state. figure 22-137. message buffer reconfiguration scheme 22.6.9 receive fifos this section provides the functional de scription of the two receive fifos. single rx single tx double tx (commit side) double tx (transmit side) rc1 rc1 rc1 rc2 rc3 rc3
flexray communication controller (flexray) 22-124 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.9.1 overview the two receive fifos implement the queue d message buffer concept defined by the flexray communications system protocol specification, version 2.1 rev a. one fifo is assigned to channel a, the other fifo is assigned to channel b. both fi fos work completely inde pendent from each other. the message buffer structure of each fifo is described in section 22.6.3.3, receive fifo. the area in the flexray memory for each of the two fifos is characterized by: ? the fifo system memory base address ? the index of the first fifo entry given by receive fifo start i ndex register (rfsir) ? the number of fifo entries and the le ngth of each fifo entry as given by receive fifo depth and size register (rfdsr) 22.6.9.2 fifo configuration the fifos can be configured for two different locations of the system memory ba se address via the fifo address mode bit fam in the module configuration register (mcr) . 22.6.9.2.1 single system memory base address mode this mode is configured, when th e fifo address mode flag mcr[fam] is set to 0. in this mode, the location of the system memory base address for the fifo buffers is system memory base address register (symbadr) . 22.6.9.2.2 dual system memory base address mode this mode is configured, when th e fifo address mode flag mcr[fam] is set to 1. in this mode, the location of the system memory base address for the fifo buffers is receive fifo system memory base address register (rfsymbadr) . the fifo control and confi guration data are given in section 22.6.3.7, receive fifo control and configuration data. the configuration of the fifo s consists of two steps. the first step is the allocation of the required am ount of flexray memory for the flexray window. this includes the allocation of the message buffer header area and the allocation of the message buffer data fields. for more details see section 22.6.4, flexray memory layout. the second step is the programming of the confi guration data register while the pe is in poc:config. the following steps configur e the layout of the fifo. ? configure the fifo update and address modes in module configuration register (mcr) ? configure the fifo system memory base address ? configure the receive fifo start index register (rfsir) with the first message buffer header index that belongs to the fifo ? configure the receive fifo depth and size register (rfdsr) with fifo entry size ? configure the receive fifo depth and size register (rfdsr) with fifo depth ? configure the fifo filters
flexray communication controller (flexray) freescale semiconductor 22-125 pxr40 microcontroller reference manual, rev. 1 22.6.9.3 fifo periodic timer the fifo periodic timer is used to generate an fifo almost-full interrupt at certain point in time, if the almost-full watermark is not reached, but the fifo is not empty. this can be used to prevent frames from get stuck in the fi fo for a long time. the fifo periodic timer is configured via the receive fifo periodic timer register (rfptr) . if the periodic timer duration rfpt ir[ptd] is configured to 0x0000, the periodic timer is continuously expired. if the periodic timer duration rfptir[ptd] is configur ed to 0x3fff, the periodic timer never expires. if the periodic timer is configured to a value ptd, greater than 0x0000 and smaller 0x3fff, the periodic timer expires and is restarted at the st art of every communication cycle, a nd expires and is restarted after ptd macroticks have been elapsed. 22.6.9.4 fifo reception the fifo reception is a controller internal operation. a message frame reception is dire cted into the fifo, if no indivi dual message buffer is assigned for transmission or subscribed for reception for the curren t slot. in this case the fifo filter path shown in figure 22-138 is activated. if the fifo filter path indicates that the received fr ame has to be appended to the fifo and the fifo is not full, the controller wr ites the received fram e header into the message buf fer header field indicated by the controller internal fifo write index. the fram e payload data are written into the corresponding message buffer data field. if the status of the received frame indicates a valid non-nul l frame, the slot status information is written into the message buffer header field and the controller internal fifo write index is updated by 1 and the fifo fill level fla (flb) in the receive fifo fill level and pop count register (rfflpcr) is incremented.if the status of the received frame indicates an invalid or null frame, the frame is not appended to the fifo. 22.6.9.5 fifo almost-full interrupt generation if the fifo fill level fla (flb) is updated after a frame reception and exceeds the fifo watermark level wm, i.e. fla>wm a (flb>wm b ), then the fifo almost-full interrupt flag gifer[fafaif] (gifer[fafbif]) is asserted.if the periodic timer expires, and fifoa (fifob) is not empty, i.e. fla>0 (flb>0), then the fifo almost-full interrupt flag gifer[fafaif] (gifer[fafbif]) is asserted. 22.6.9.6 fifo overflow error generation if the fifoa (fifob) is full, i.e. fla=fifo_depth a (flb=fifo_depth b ) and the conditions for a fifo reception as described in section 22.6.9.4, fifo reception , are fulfilled, then the fifo overflow error flag chierfr[fova_ef] (chier fr[fovb_ef]) is asserted. 22.6.9.7 fifo message access the fifoa (fifob) contains valid messages if the fi fo fill level fla (flb) is greater than 0. the receive fifo a read index register (rfarir) ( receive fifo b read index register (rfbrir) ) pointing to a message buffer with valid conten t and the oldest frames stored in the fifo.
flexray communication controller (flexray) 22-126 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if the fifo fill level fla (flb ) is 0, than the fifoa (fifob) c ontains no valid me ssages and the receive fifo a read index register (rfarir) ( receive fifo b read index register (rfbrir) ) pointing to a message buffer with invalid content. in this case th e application must not read data from the fifo. to access the oldest message in the fifoa (fifob), the application first reads the read index rdidx out of the receive fifo a read index register (rfarir) ( receive fifo b read index register (rfbrir) ). this read index points to the message buffer header field of the oldest message buffer that contains valid received message data. the application can access the message data as described in section 22.6.3.3, receive fifo. when the application has read the message buffe r data and status info rmation, it can update the fifo as described in section 22.6.9.8, fifo update . 22.6.9.8 fifo update the application updates the fifoa (fifob) by writing a pop count value pc different from 0 to the pca (pcb) field in the receive fifo fill level and pop count register (rfflpcr) . as a result of the this operation, the controller removes the oldest pc entries from fifoa (fifob). if the specified pop count value pc is greater than the current fill level fl provided in fla (fab) field, then only fl entries are removed from the fifoa (fifob), the remaining fl-pc requested pop operations are discarded without any notificati on. in this case fifoa (fifob) is empty after the update operation. the read index in the receive fifo a read index register (rfarir) ( receive fifo b read index register (rfbrir) ) is incremented by the number of removed items. if the read index reaches the top of the fifo, it wraps around to the fifo start index defined in receive fifo start i ndex register (rfsir) automatically. 22.6.9.8.1 fifo interrupt flag update th fifo interrupt flag update mode is configured , when the fifo update mode flag mcr[fum] is set to 0. in this mode fifoa (fifob) will be updated by 1 entry, when the interrupt flag gifer[fafaif] (gifer[fafbif]) is written with 1 by the application. if the fifo is empty, the update reque st is ignored without any notification. the read index in the receive fifo a read index register (rfarir) ( receive fifo b read index register (rfbrir) ) is incremented by 1, if the fifo was not em pty. if the read index reaches the top of the fifo, it wraps around to the fifo start index automatically. 22.6.9.9 fifo filtering the fifo filtering is activated after all enabled i ndividual receive message buffers have been searched without success for a message buffer to receive the current frame. the controller provides thr ee sets of fifo filters. the fifo filt ers are applied to valid non-null frames only. the fifo will not receive inva lid or null-frames. for each fifo f ilter, the pass criteria is specified in the related section given below. only frames that have passed all filters will be appended to the fifo. the fifo filter path is depicted in figure 22-138 .
flexray communication controller (flexray) freescale semiconductor 22-127 pxr40 microcontroller reference manual, rev. 1 figure 22-138. received frame fifo filter path valid frame received ( vrf ) individual null frame frame id value- frame id append to fifo ( vrf ) frame id no frame received fifo full set fifo overflow interrupt flag message buffer found ? no passed passed passed yes (vrf!header!nfindicator=0 ) ? mask rejection filter ? range rejection filter ? range acceptance filter ? in dynamic segment ? ? store into message buffer ( vrf ) yes no else ignore frame yes else else message id ( vrf!header!ppindicator=1 ) ? message id yes passed acceptance filter ? no yes no else
flexray communication controller (flexray) 22-128 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 a received frame passes the fifo filtering if it has passed all three type of filter. 22.6.9.9.1 rx fifo frame id value-mask rejection filter the frame id value-mask rejection filter is a value-mask filter and is defined by the fields in the receive fifo frame id rejection filt er value register (rffidrfvr) and the receive fifo frame id rejection filter mask register (rffidrfmr) . each received frame wi th a frame id fid that does not match the value-mask filter value passes th e filter, i.e. is not rejected. consequently, a received valid frame with the frame id fid passes the rx fifo frame id value-mask rejection filter if equation 22-14 is fulfilled. eqn. 22-14 the rx fifo frame id value-mask re jection filter can be c onfigured to pass all frames by the following settings. ? rffidrfvr[fidrfval]:= 0x000 and rffidrfmr[fidrfmsk]:= 0x7ff using the settings above, only the frame with frame id 0 will be rejecte d, which is an invalid frame. all other frames will pass. the rx fifo frame id value-mask rejection filter can be configured to reject all frames by the following settings. ? rffidrfmr[fidrfmsk]:= 0x000 using the settings above, equation 22-14 can never be fulfilled (0!= 0) a nd thus all frames are rejected; no frame will pass. this is the reset value for the rx fifo. 22.6.9.9.2 rx fifo frame id range rejection filter each of the four rx fifo frame id range filters can be configured as a rejection filter. the filters are configured by the receive fifo range filter conf iguration register (rfrfcfr) and controlled by the receive fifo range filter control register (rfrfctr) . the rx fifo frame id range filters apply to all received valid frames. a received frame with th e frame id fid passes the rx fifo frame id range rejection filters if either no rejection filter is enabled, or, for all of the enabled rx fi fo frame id range rejection filters, i.e. rfrfctr. fimd = 1 and rfrfctr.fien = 1, equation 22-15 is fulfilled. eqn. 22-15 consequently, all frames with a frame id that fulfills equation 22-16 for at least one of the enabled rejection filters will be re jected and thus not pass. eqn. 22-16 22.6.9.9.3 rx fifo frame id range acceptance filter each of the four rx fifo frame id range filter s can be configured as an ac ceptance filter. the filters are configured by the receive fifo range filter conf iguration register (rfrfcfr) and controlled by the receive fifo range filter control register (rfrfctr) . the rx fifo frame id range filters apply to all received valid frames. a received frame with th e frame id fid passes the rx fifo frame id range id & rffidrfmr fidrfmsk ?? rffidrfvr fidrfval ?? & rffidrfmr fidrfmsk ? ? ?? ?? or rfrfcfr sel sid ibd 1 = ?? fid ? ?? ?? fid rfrfcfr sel sid ibd 1 = ?? ??
flexray communication controller (flexray) freescale semiconductor 22-129 pxr40 microcontroller reference manual, rev. 1 acceptance filters if either no acceptance filter is enable d, or, for at least one of the enabled rx fifo frame id range acceptance filters, i.e. rf rfctr.fimd = 0 and rfrfctr.fien = 1, equation 22-17 is fulfilled. eqn. 22-17 22.6.9.9.4 rx fifo messa ge id acceptance filter the rx fifo message id acceptance filter is a value-mask filter and is defined by the receive fifo message id acceptance filter value register (rfmidafvr) and the receive fifo message id acceptance filter mask register (rfmiafmr) . this filter applies only to valid frames received in the dynamic segment with the payload preamb le indicator bit ppi set to 1. all ot her frames will pass this filter. a received valid frame in the dynamic segment with th e payload preamble indicator bit ppi set to 1 and with the message id mid (the first two bytes of the payload) will pass the rx fifo message id acceptance filter if equation 22-18 is fulfilled. eqn. 22-18 the rx fifo message id acceptance filter can be configured to accep t all frames by setting ? rfmidafmr[midafmsk]:= 0x000 using the settings above, equation 22-18 is always fulfilled and all frames will pass. 22.6.10 channel device modes this section describes the two flexray channel de vice modes that are supported by the controller. 22.6.10.1 dual channel device mode in the dual channel device mode, both flexray ports are connected to physical flexray bus lines. the flexray port consisting of fr_a _rx, fr_a_tx, and fr_a_tx_en is connected to the physical bus channel a and the flexray port consisting of fr_b_rx, fr_b_tx, and fr_b_tx_en is connected to the physical bus channel b. the dual channel system is shown in figure 22-139 . rfrfcfr sel sid ibd 0 = ?? fid rfrfcfr sel sid ibd 1 = ?? ?? ?? rfmidafmr midafval ?? & rfmidafmr midafmsk ? =
flexray communication controller (flexray) 22-130 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 22-139. dual channel device mode 22.6.10.2 single channel device mode the single channel device mode suppor ts devices that have only one flex ray port available. this flexray port consists of the signals fr _a_rx, fr_a_tx, and fr_a_tx_en and can be connect ed to either the physical bus channel a (shown in figure 22-140 ) or the physical bus channel b (shown in figure 22-141 ). if the device is configured as a single channel devi ce by setting mcr.scd to 1, only the internal channel a and the flexray port a is used. depending on the setting of mcr.cha and mcr.chb, the internal channel a behaves either as a flex ray channel a or flexray channel b. the bit mcr.cha must be set, if the flexray port a is connected to a flexray cha nnel a. the bit mcr.chb must be set if the flexray port a is connected to a flexray ch annel b. the two flexray channels di ffer only in the initial value for the frame crc ccrcinit . for a single channel device, the appli cation can access and configure only the registers related to internal channel a. chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel 0 channel 1 flexray channel a flexray bus driver channel a fr_a_rx fr_a_tx fr_a_tx_en flexray channel b flexray bus driver channel b fr_b_rx fr_b_tx fr_b_tx_en flexray
flexray communication controller (flexray) freescale semiconductor 22-131 pxr40 microcontroller reference manual, rev. 1 figure 22-140. single channel device mode (channel a) figure 22-141. single channel device mode (channel b) 22.6.11 external clock synchronization the application of the external rate and offset correct ion is triggered when the application writes to the eoc_ap and erc_ap fields in the protocol operation c ontrol register (pocr) . the pe applies the external correction values in the next even-odd cycle pair as shown in figure 22-142 and figure 22-143 . chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel a flexray bus driver channel a fr_a_rx fr_a_tx fr_a_tx_en fr_b_rx fr_b_tx fr_b_tx_en flexray chi pe cfg(a) reg(a) ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel b init value for frame crc is ccrcinit[b] ccrcinit[a] flexray bus driver channel a fr_a_rx fr_a_tx fr_a_tx_en fr_b_rx fr_b_tx fr_b_tx_en flexray
flexray communication controller (flexray) 22-132 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the values provided in the eoc_ap and erc_ap fields are the values that were written from the appl ication most recently. if these value were already applied, they will not be applied in the current cycle pair again. if the offset correction applied in the nit of cycle 2n +1 shall be affect by the external offset correction, the eoc_ap field must be written to after the start of cycle 2n and before the end of the static segment of cycle 2n+1. if this field is written to after the end of the st atic segment of cycle 2n+ 1, it is not guaranteed that the external correction value is applied in cycl e 2n+1. if the value is not applied in cycle 2n+1, then the value will be applied in the cycle 2n+3. refer to figure 22-142 for timing details. figure 22-142. external offset correction write and application timing if the rate correction for the cycle pair [2n+2, 2n+3] shall be affect by the external offset correction, the erc_ap field must be written to after the start of cy cle 2n and before the end of the static segment start of cycle 2n+1. if this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycle pair [2n+2, 2n+3]. if the valu e is not applied for cycle pair [2n+2, 2n+3], then the va lue will be applied for cycl e pair [2n+4, 2n+5]. refer to figure 22-143 for details. figure 22-143. external rate correction write and application timing 22.6.12 sync frame id and sync frame deviation tables the flexray protocol requires the pr ovision of a snapshot of the synchr onization frame id tables for the even and odd communication cycle for both channels. th e controller provides the means to write a copy of these internal tables into the flexray memory a nd ensures application access to consistent tables by means of table locking. once the application has lock ed the table successfully, the controller will not overwrite these tables and the applicat ion can read a consistent snapshot. note only synchronization frames that have passed the synchronization frame filters are considered for clock synchr onization and appear in the sync frame tables. static segment nit static segment nit eoc_ap write window eoc_ap application cycle 2n cycle 2n+1 static segment nit erc_ap write window erc_ap application cycle 2n static segment nit cycle 2n+1 static segment nit cycle 2n+2 static segment nit cycle 2n+3
flexray communication controller (flexray) freescale semiconductor 22-133 pxr40 microcontroller reference manual, rev. 1 22.6.12.1 sync frame id table content the sync frame id table is a snapshot of the protocol related variables vssyncidlista and vssyncidlistb for each even and odd communication cycle. this table provides a list of the frame ids of the synchronization frames received on the corresponding channel and cycle that are used for the clock synchronization. 22.6.12.2 sync frame deviation table content the sync frame deviation table is a snapshot of th e protocol related variable zsdev(id)(oe)(ch)!value. each sync frame deviation table entry provides the deviation value for the s ync frame, with the frame id presented in the corresponding en try in the sync frame id table. figure 22-144. sync table memory layout 22.6.12.3 sync frame id and sync frame deviation table setup the controller writes a copy of the internal synchronization fra me id and deviation ta bles into the flexray memory if requested by the application. the applicat ion must provide the appr opriate amount of flexray memory for the tables. the memory layout of the tables is given in figure 22-144 . each table occupies 120 16-bit entries. sftor sftor + 180 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 sftor + 60 sftor +120 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 offset + $00 offset + $02 offset + $04 offset + $06 offset + $08 offset + $0a offset + $0c offset + $0e offset + $10 offset + $12 offset + $14 offset + $16 offset + $18 offset + $1a offset + $1c sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 offset + $1e offset + $20 offset + $22 offset + $24 offset + $26 offset + $28 offset + $2a offset + $2c offset + $2e offset + $30 offset + $32 offset + $34 offset + $36 offset + $38 offset + $3a sfcntr sfeva sfevb sfcntr sfoda sfodb even odd even odd
flexray communication controller (flexray) 22-134 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 while the protocol is in poc:config state, the application must program the offsets for the tables into the sync frame table offset register (sftor) . 22.6.12.4 sync frame id and sync frame deviation table generation the application controls the genera tion process of the sync frame id and sync frame deviation tables into the flexray memory using the sync frame table configuration, cont rol, status register (sftccsr) . a summary of the copy modes is given in table 22-114 . the sync frame table generation pro cess is described in the following for the even cycle. the same sequence applies to the odd cycle. if the application has enabled the sync frame ta ble generation by setting sftccsr.siden to 1, the controller starts the update of the even cycle related tables after the start of the nit of the next even cycle. the controller checks if the appl ication has locked the tables by r eading the sftccsr.elks lock status bit. if this bit is set, the controller will not update the table in this cycle. if this bit is cl eared, the controller locks this table and starts the tabl e update. to indicate that these tables are currently updated and may contain inconsistent data, the controller clears the even table va lid status bit sftccs r[eval]. once all table entries related to the even cycl e have been transferred into the flex ray memory, the controller sets the even table valid bit sftccsr[eval] and the even cycle table written interrupt flag evt_if in the protocol interrupt flag register 1 (pifr1) . if the interrupt enable flag evt_ ie is set, an interrupt request is generated. to read the generated tables, the application must lo ck the tables to prevent the controller from updating these tables. the locking is initia ted by writing a 1 to the even tabl e lock trigger sftccsr.elkt. when the even table is not current ly updated by the controller, the lock is granted and the even table lock status bit sftccsr.elks is set. this indica tes that the application has successf ully locked the even sync tables and the corresponding status inform ation fields sfra, sfrb in the sync frame counter register (sfcntr) . the value in the sftccsr.cycnum field provid es the number of the cycle that this table is related to. the number of available table entries per chan nel is provided in the sfcntr.sfeva and sfcntr.sfevb fields. the application can now start to read the sync table data from the locations given in figure 22-144 . table 22-114. sync frame table generation modes sftccsr description opt sdven siden 0 0 0 no sync frame table copy 0 0 1 sync frame id tables will be copied continuously 010reserved 0 1 1 sync frame id tables and sync frame deviation tables will be copied continuously 1 0 0 no sync frame table copy 1 0 1 sync frame id tables for next even-odd-cycle pair will be copied 010reserved 1 1 1 sync frame id tables and sync frame deviat ion tables for next even-odd-cycle pair will be copied
flexray communication controller (flexray) freescale semiconductor 22-135 pxr40 microcontroller reference manual, rev. 1 after reading all the data from the locked tables, th e application must unlock the table by writing to the even table lock trigger sftccsr.e lkt again. the even table lock status bit sftccsr.elks is reset immediately. if the sync frame table generation is disabl ed, the table valid bits sftccsr[eval] and sftccsr[eval] are reset when the counter va lues in the sync frame counter register (sfcntr) are updated. this is done because the tables stored in th e flexray memory are no longer related to the values in the sync frame counter register (sfcntr) . figure 22-145. sync frame table trigger and generation timing 22.6.12.5 sync frame table access the sync frame tables will be tr ansferred into the flexray memory during the table write windows shown in figure 22-145 . during the table write, the application can not lock the table that is currently written. if the application locks the table outside of the tabl e write window, the lock is granted immediately. 22.6.12.5.1 sync frame tabl e locking and unlocking the application locks the even/odd s ync frame table by writing 1 to th e lock trigger bit elkt/olkt in the sync frame table configuration, cont rol, status register (sftccsr) . if the affected table is not currently written to the flexray memory, the lock is granted immediately, and the lock status bit elks/olks is set. if the affected ta ble is currently written to the flex ray memory, the lock is not granted. in this case, the application must issue the lock request again until the lock is granted. the application unlocks the even/odd sync frame tabl e by writing 1 to the lock trigger bit elkt/olkt. the lock status bit elks/olks is cleared immediately. 22.6.13 mts generation the controller provides a flexible means to request the transmission of the media access test symbol mts in the symbol window on channel a or channel b. the application can configure the se t of communication cycles in which the mts will be transmitted over the flexray bus by programming the cycc ntmsk and cyccntval fields in the mts a configuration regi ster (mtsacfr) and mts b configuration register (mtsbcfr) . the application enables or disables the generation of the mts on either channel by setting or clearing the mte control bit in the mts a configuration register (mtsacfr) or mts b configuration register (mtsbcfr) . if an mts is to be transmitted in a certai n communication cycle, the application must set the mte control bit during the static segm ent of the preceding communication cycle. the mts is transmitted over channel a in th e communication cycle with number cyccnt, if equation 22-20 , equation 22-21 , and equation 22-21 are fulfilled. sftccsr.[opt,siden,sdven] write window even table write static segment nit static segment nit static segment nit cycle 2n-1 cycle 2n cycle 2n+1 odd table write
flexray communication controller (flexray) 22-136 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 eqn. 22-19 eqn. 22-20 eqn. 22-21 the mts is transmitted over channel b in th e communication cycle with number cyccnt, if equation 22-19 , equation 22-22 , and equation 22-23 are fulfilled. eqn. 22-22 eqn. 22-23 22.6.14 key slot transmission 22.6.14.1 key slot assignment a key slot is assigned to the controll er if the key_slot_id field in the protocol configuration register 18 (pcr18) is configured with a value greater than 0 and less or equal to num ber_of_static_slots in protocol configuration re gister 2 (pcr2) , otherwise no key slot is assigned. 22.6.14.2 key slot transmission in poc:startup if a key slot is assigned an d the controller is in the poc:startup state, startup null frames will be transmitted as specified by flexray communications system protoc ol specification, version 2.1 rev a . 22.6.14.3 key slot transmission in poc:normal active if a key slot is assigned and the controller is in poc:normal active , a frame of the type as shown in table 22-115 is transmitted. if a transmit message buffer is configured for the key sl ot and a valid message is available, a message frame is transmitted (see section 22.6.6.2.5, messa ge transmission ). if no transmit message buffer is configured for the key slot or no valid message is avai lable, a null frame is transmitted (see section 22.6.6.2.6, null frame transmission ). 22.6.15 sync frame filtering each received synchronization frame must pass the sync frame acceptance filt er and the sync frame rejection filter before it is considered for clock synchronization. if the synchr onization frame filtering is table 22-115. key slot frame type pcr11[key_slot_used_for_sync] pcr11[key_slot_used_for_startup] key slot frame type 0 0 normal frame 0 1 normal frame 1 1 the frame transmitted has an semantically incorrect header and will be detected as an inva lid frame at the receiver. 1 0 sync frame 1 1 startup frame psr0 protstate ?? poc:normal active = mtsacrf mte ?? 1 = cyccnt & mtsacfr cyccntmsk ?? mtsacfr cyccntval ?? & mtsacfr cyccntmsk ? = mtsbcrf mte ?? 1 = yccnt & mtsbcfr cyccntmsk ?? mtsbcfr cyccntval ?? & mtsbcfr cyccntmsk ? =
flexray communication controller (flexray) freescale semiconductor 22-137 pxr40 microcontroller reference manual, rev. 1 globally disabled, i.e. the sffe control bit in the module configuration register (mcr) is cleared, all received synchronization frames are considered for cl ock synchronization. if a received synchronization frame did not pass at least one of the two filters, this frame is proc essed as a normal frame and is not considered for clock synchronization. 22.6.15.1 sync frame acceptance filtering the synchronization frame accep tance filter is implemente d as a value-mask filter. the value is configured in the sync frame id acceptance filt er value register (sfidafvr) and the mask is configured in the sync frame id acceptance filt er mask register (sfidafmr) . a received synchr onization frame with the frame id fid passes the sync frame acceptance filter, if equation 22-24 or equation 22-25 evaluates to true. eqn. 22-24 eqn. 22-25 note sync frames are transmitted in the static segment only. thus fid <= 1023. 22.6.15.2 sync frame rejection filtering the synchronization frame rejection filter is a comparator. the compare value is defined by the sync frame id rejection filte r register (sfidrfr) . a received synchronization fr ame with the frame id fid passes the sync frame rejection filter if equation 22-26 or equation 22-27 evaluates to true. eqn. 22-26 eqn. 22-27 note sync frames are transmitted in the static segment only. thus fid <= 1023. 22.6.16 strobe signal support the controller provides a number of strobe signals for observing internal protocol timing related signals in the protocol engine. the signa ls are listed and described in table 22-12 . 22.6.16.1 strobe signal assignment each of the strobe signals listed in table 22-12 can be assigned to one of th e four strobe ports using the strobe signal control register (stbscr) . to assign multiple strobe si gnals, the application must write multiple times to the strobe signal control register (stbscr) with appropriate settings. to read out the current settings for a strobe signal with number n, the application must execute the following sequence. 1. write to stbscr with wmd = 1 a nd sel = n. (updates sel field only) mcr sffe ?? 0 = id & sfidafmr fmsk ?? sfidafvr fval ?? & sfidafmr fmsk ? = mcr sffe ?? 0 = fid sfidrfr synfrid ?? ?
flexray communication controller (flexray) 22-138 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 2. read stbcsr. the sel field provides n and the enb and stbpse l fields provides the settings for signal n. 22.6.16.2 strobe signal timing this section provides detail ed timing information of the strobe signals with respect to th e protocol engine clock. the strobe signals display internal pe signals. due to the internal archit ecture of the pe, some signals are generated several pe clock cycles before the actual action is performe d on the flexray bus. these signals are listed in table 22-12 with a negative clock offset. an example waveform is given in figure 22-146 . figure 22-146. strobe signal timing (type = pulse, clk_offset = -2) other signals refer to events that occurred on the fl exray bus some cycles befo re the strobe signal is changed. these signals are listed in table 22-12 with a positive clock offset . an example waveform is given in figure 22-147 . figure 22-147. strobe signal timing (type = pulse, clk_offset = +4) 22.6.17 timer support the controller provides two timers, which run on the flexray time base. each timer generates a maskable interrupt when it reaches a configur ed point in time. timer t1 is an absolute timer. timer t2 can be configured to be an absolute or a relative timer . both timers can be configured to be repetitive. in the non-repetitive mode, timer stops if it expires. in repetitive mode, timer is restarted when it expires. both timers are active only when the protocol is in poc:normal active or poc:normal passive state. if the protocol is not in one of these modes, the timers are stopped. the application must restart the timers when the protocol has reached the poc:normal active or poc:normal passive state. pe clock strobe signal flexray bus event -2 pe clock strobe signal flexray bus event +4
flexray communication controller (flexray) freescale semiconductor 22-139 pxr40 microcontroller reference manual, rev. 1 22.6.17.1 absolute timer t1 the absolute timer t1 has the protoc ol cycle count and the macrotick c ount as the time base. the timer 1 interrupt flag ti1_if in the protocol interrupt flag register 0 (pifr0) is set at the macrotick start event, if equation and equation 22-29 are fulfilled eqn. 22-28 eqn. 22-29 if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (pier0) is asserted, an interrupt request is generated. the status bit t1st is set when the timer is tri ggered, and is cleared when the timer expires and is non-repetitive. if the timer expires but is repetitive, the t1st bit is not cleared and the t imer is restarted immediately. the t1st is cleared when the timer is stopped. 22.6.17.2 absolute / relative timer t2 the timer t2 can be configured to be an absolute or relative timer by setting the t2_cfg control bit in the timer configuration and control register (ticcr) . the status bit t2st is set when the timer is triggered, and is cleared when the timer expire s and is non-repetitive. if the timer expires but is repetitive, the t2st bit is not cleared and the timer is restarted immediat ely. the t2st is cleared when the timer is stopped. 22.6.17.2.1 absolute timer t2 if timer t2 is configured as an absolute timer, it has the same functionality ti mer t1 but the configuration from timer 2 configuration register 0 (ti2cr0) and timer 2 configuration register 1 (ti2cr1) is used. on expiration of timer t2, the interrupt flag ti2_if in the protocol interrupt flag register 0 (pifr0) is set. if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (pier0) is asserted, an interrupt request is generated. 22.6.17.2.2 relative timer t2 if the timer t2 is configured as a relati ve timer, the interrupt flag ti2_if in the protocol interrupt flag register 0 (pifr0) is set, when the programmed amount of macroticks mt[31:0], defined by timer 2 configuration regi ster 0 (ti2cr0) and timer 2 configuration register 1 (ti2cr1) , has expired since the trigger or restart of timer 2. the re lative timer is implemented as a dow n counter and expires when it has reached 0. at the macrotick start event, the value of mt[31:0] is checked and then decremented. thus, if the timer is started with mt [31:0] == 0, it expires at the next macrotick start. cyctr ctccnt ?? & ti1cysr t1_cyc_msk ?? ti1cysr t1_cyc_val ?? & ti1cysr t1_cyc_msk ?? = mtctr mtct ?? ti1mtor t1_mtoffset ?? =
flexray communication controller (flexray) 22-140 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.18 slot status monitoring the controller provides several means for slot status monitoring. all slot status monitors us e the same slot status vector provided by the pe. th e pe provides a slot status vector for each static slot, for each dynamic slot, for the symbol window, and for the nit, on a per ch annel base. the content of the slot status vector is described in table 22-116 . the pe provides the slot st atus vector within the first macrotick after the end of the related slot/window/nit, as shown in figure 22-148 . figure 22-148. slot status vector update note the slot status for the nit of cycle n is provided after the start of cycle n+1. cycle start slot start slot start symbol window start mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt
flexray communication controller (flexray) freescale semiconductor 22-141 pxr40 microcontroller reference manual, rev. 1 22.6.18.1 channel status error counter registers the two channel status error counter registers, channel a status error co unter register (casercr) and channel b status error co unter register (cbsercr) , incremented by one, if at least one of four slot status error bits, vss!syntaxerror , vss!contenterror , vss!bviolation , or vss!txconflict is set to 1. the status vectors for all slots in the static and dynami c segment, in the symbol window, and in the nit are taken into account. the counter s wrap round after they have reached the maximum value. table 22-116. slot status content status content static / dynamic slot slot related status vss!validframe - valid frame received vss!syntaxerror - syntax error occu rred while receiving vss!contenterror - content error occu rred while receiving vss!bviolation - boundary violation while receiving for slots in which th e module transmits: vss!txconflict - reception ongoing while transmission starts for slots in which the module does not transmit: vss!txconflict - reception ongoing while transmission starts first valid - channel that has received the first valid frame received frame related status extracted from a) header of valid frame, if vss!validframe = 1 b) last received header, if vss!validframe = 0 c) set to 0, if nothing was received vrf!header!nfindicator - null frame indicator (0 for null frame) vrf!header!sufindicator - startup frame indicator vrf!header!syfindicator - sync frame indicator symbol window window related status vss!validframe - always 0 vss!contenterror - content error occu rred while receiving vss!syntaxerror - syntax error occu rred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - reception ongoing while transmission starts received symbol related status vss!validmts - valid media test access symbol received received frame related status see static/dynamic slot nit nit related status vss!validframe - always 0 vss!contenterror - content error occu rred while receiving vss!syntaxerror - syntax error occu rred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - always 0 received frame related status see static/dynamic slot
flexray communication controller (flexray) 22-142 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.18.2 protocol status registers the protocol status register 2 (psr2) provides slot status information about the network idle time nit and the symbol window. the protocol status register 3 (psr3) provides aggregated slot status information. 22.6.18.3 slot status registers the eight slot status registers, slot status registers (ssr0?ssr7) , can be used to observe the status of static slots, dynamic slots, the symbol window, or the nit without individual message buffers. these registers provide all slot status related and received frame / symbol related status information, as given in table 22-116 , except of the first valid indicator for non-transmission slots. 22.6.18.4 slot status counter registers the controller provides four slot status error counter registers, slot status counter registers (sscr0?sscr3) . each of these slot status c ounter registers is updat ed with the value of an internal slot status counter at the start of a comm unication cycle. the internal slot st atus counter is incremented if its increment condition, defined by the slot status counter c ondition register (ssccr) , matches the status vector provided by the pe. all static slots, the sym bol window, and the nit status are taken into account. dynamic slots are excluded . the internal slot status count ing and update timing is shown in figure 22-149 . figure 22-149. slot status counting and sscrn update the pe provides the status of the nit in the first slot of the next cycle. due to these facts, the sscrn register reflects, in cycle n, the stat us of the nit of cycle n-2, and the status of all static slots and the symbol window of cycle n-1. the increment condition for each slot status counter c onsists of two parts, the frame related condition part and the slot related conditi on part. the internal slot status counter sscrn_int is increm ented if at least one of the conditions is fulfilled: 1. frame related condition: cycle start slot start slot start symbol window start mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt incr. sscrn_int on error incr. sscrn_int on error sscrn:= sscrn_int sscrn_int not updated sscrn:= sscrn_int
flexray communication controller (flexray) freescale semiconductor 22-143 pxr40 microcontroller reference manual, rev. 1 ? (ssccrn.vfr | ssccrn.syf | ssccrn.nuf | ssccrn.suf) // count on frame condition = 1; and ? ((~ssccrn.vfr | vss!validframe ) & // valid frame restriction (~ssccrn.syf | vrf!header!syfindicator ) & // sync frame indicator restriction (~ssccrn.nuf | ~ vrf!header!nfindicator ) & // null frame indicator restriction (~ssccrn.suf | vrf!header!sufindicator )) // startup frame indicator restriction = 1; note the indicator bits syf, nuf, and su f are valid only when a valid frame was received. thus it is required to set the vfr always, whenever count on frame condition is used. 2. slot related condition: ? ((ssccrn.statusmask[3] & vss!contenterror ) | // increment on content error (ssccrn.statusmask[2] & vss!syntaxerror ) | // increment on syntax error (ssccrn.statusmask[1] & vss!bviolation ) | // increment on boundary violation (ssccrn.statusmask[0] & vss!txconflict )) // increment on transmission conflict = 1; if the slot status counter is in single cycle mode, i.e. ssccrn.mcy = 0, the internal slot status counter sscrn_int is reset at each cycle start. if the slot status counter is in the multicycle mode, i.e. ssccrn.mcy = 1, the counter is not reset and in cremented, until the maximum value is reached. 22.6.18.5 message buffer slot status field each individual message buffer and each fifo message buffer provides a slot status field, which provides the information shown in table 22-116 for the static/dynamic slot. the upda te conditions for the slot status field depend on the message buffer type. refer to the message buffer update sections in section 22.6.6, individual message buffer functional description . 22.6.19 system bus access this section provides a description of the sy stem bus accesses performed by the controller. all flexray memory data located in the system me mory are accessed via the system bus. there are two types of failures that can occur dur ing the system bus access, the system bus illegal address access and the system bus access timeout. the behavior of the controller afte r the occurrence of a system bus fa ilure is defined by the sbff bit in the module configurati on register (mcr) .
flexray communication controller (flexray) 22-144 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.19.1 system bus illegal address access if the system bus detects an controller access to an illegal address, the controll er receives a notification from the system bus about this event and sets the ilsa_ef flag in the chi error flag register (chierfr) . 22.6.19.2 system bus access timeout the controller starts a timer when it has send an access request to the sy stem bus. this timer expires after 2 * symator.timeout + 2 system bus clock cycles. if the access is not finished within this amount of time, the sbcf_ef flag in the chi error flag register (chierfr) is set. 22.6.19.3 continue after system bus failure if the sbff bit in the module configuration register (mcr) is 0, the controller wi ll continue its operation after the occurrence of the system bus access failure but will not gene rate any system bus accesses until the start of the next communication cycle. if a frame is under transmission when the system bus failure occurs, a co rrect frame is generated with the remaining header and frame data are replaced by all ze ros. depending on the point in time this can affect the ppi bit, the header crc, the pa yload length in case of an dynamic slot, and the payload data. starting from the next slot in the current cycle, no frames wi ll be transmitted and recei ved, except for the key slot, where a sync or startup null-frame is tr ansmitted, if the ke y slot is assigned. if a frame is received when the sy stem bus failure occurs, the recepti on is aborted and the related receive message buffer is not updated. normal operation is resumed after th e start of next communication cycle. 22.6.19.4 freeze after system bus failure if the sbff bit in the module configuration register (mcr) is set to 1, the controller will go into the freeze mode immediately after the occurrence of one of the system bus access failures. 22.6.20 interrupt support the controller provides 172 indivi dual interrupt sources and five combined interrupt sources. 22.6.20.1 individual interrupt sources 22.6.20.1.1 message buffer interrupts the controller provides 128 messa ge buffer interrupt sources. each individual message buffer provides an interrupt flag mbccsn[mbif] and an interrupt enable bit mbccsn[mbie]. the controller sets the interrupt flag when the slot status of the message buffer was updated. if the interrupt enable bit is asse rted, an interrupt request is generated.
flexray communication controller (flexray) freescale semiconductor 22-145 pxr40 microcontroller reference manual, rev. 1 22.6.20.1.2 fifo interrupts the controller provides 2 fifo interrupt sources. each of the 2 fifo provides a receive fifo almost fu ll interrupt flag. the controller sets the receive fifo almost full interrupt flags (gifer.fafbif, gifer.fafaif) in the global interrupt flag and enable register (gifer) if the corresponding receive fifo fill level exceeds the defined watermark. 22.6.20.1.3 wakeup interrupt the controller provides one interr upt source related to the wakeup. the controller sets the wakeup interrupt flag gife r.wupif when it has received a wakeup symbol on the flexray bus. the controller generates an interrupt request if the interrupt enable bit gifer.wupie is asserted. 22.6.20.1.4 protocol interrupts the controller provides 25 interru pt sources for protocol rela ted events. for details, see protocol interrupt flag register 0 (pifr0) and protocol interrupt flag register 1 (pifr1) . each interrupt source has its own interrupt enable bit. 22.6.20.1.5 chi error interrupts the controller provides 16 interr upt sources for chi related e rror events. for details, see chi error flag register (chierfr) . there is one common interr upt enable bit gifer.chiie for all chi error interrupt sources. 22.6.20.2 combined interrupt sources each combined interrupt source generates an interrupt request only when at least one of the interrupt sources that is combined ge nerates an interrupt request. 22.6.20.2.1 receive message buffer interrupt the combined receive message buffe r interrupt request rbirq is generated when at least one of the individual receive message buffers generates an interr upt request mbxirq[n] and the interrupt enable bit gifer.rbie is set. 22.6.20.2.2 transmit message buffer interrupt the combined transmit message buffer interrupt reque st tbirq is generated when at least one of the individual transmit message buffers generates an interrupt request mb xirq[n] and the interrupt enable bit gifer.tbie is asserted. 22.6.20.2.3 protocol interrupt the combined protocol interrupt reque st prtirq is generated when at le ast one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit gifer.prie is set.
flexray communication controller (flexray) 22-146 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.6.20.2.4 chi error interrupt the combined chi error interrupt request chiirq is generated when at least one of the individual chi error interrupt sources generates an interrupt request and the interrupt enable bit gifer.chie is set. 22.6.20.2.5 module interrupt the combined module interrupt request mirq is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit gifer.mie is set.
flexray communication controller (flexray) freescale semiconductor 22-147 pxr40 microcontroller reference manual, rev. 1 figure 22-150. scheme of cascaded interrupt request interrupt sources interrupt signals mbccsr n [mbif] n chier[15:0] 16 pifr0[15:0] 16 pifr1[15:0] 16 rbirq chiirq prtirq gifer[fafaif] fafairq gifer[wupif] wupirq gifer[rbie] mbccsr n [mtd] receive tr a n s m i t gifer[prie] gifer[wupie] gifer[mie] mbccsr n [mbie] & pier0[15:0] pier1[15:0] or & & & gifer[chie] & & n & or tbirq gifer[tbie] & n or or & & gifer[fafaie] gifer[fafbif] fafbirq & gifer[fafbie] & & n = # message buffers or gifer[rbif] gifer[tbif] gifer[prif] gifer[chif] gifer[mif] mirq
flexray communication controller (flexray) 22-148 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 22-151. figure 22-152. scheme of combined interrupt flags 22.6.21 lower bit rate support the controller supports a number of lower bit rates on the flexray bus channels. the lower bit rates are implemented by modifying the duration of the microtick pdmicrotick , the number of samples per microtick psamplespermicrotick , the number of samples per bit csamplesperbit , and the strobe offset cstrobeoffset. the application configures the flexray channel bit rate by setting the bitrate field in the module configuration register (mcr) . the protocol values are set internally . the available bit rates, the related bitrate field configuration settings and relate d protocol parameter values are shown in table 22-117 . interrupt sources com bined interrupt flags mbccsr n [mbif] n chier[15:0] pifr0[15:0] pifr1[15:0] gifer[fafaif] gifer[wupif] cifr[tbif] cifr[chif] cifr[prif] mbccsr n [mtd] receive tr a n s m i t or & & or cifr[rbif] n or or gifer[fafbif] n = # message buffers n or cifr[mif] cifr[fafaif] cifr[wupif] cifr[fafbif]
flexray communication controller (flexray) freescale semiconductor 22-149 pxr40 microcontroller reference manual, rev. 1 note the bit rate of 8 mbit/ s is not defined by the flexray communications system protocol specifi cation, version 2.1 rev a. 22.7 application information 22.7.1 initialization sequence this section describes the required st eps to initialize the controller. the first subsection describes the steps required after a system rese t, the second section describes the step s required after pre ceding shutdown of the controller. 22.7.1.1 module initialization this section describes the module related initialization steps after a system reset. 1. configure controller. a) configure the control bits in the module configuratio n register (mcr) b) configure the system memory base address in system memory base address register (symbadr) 2. enable the controller. a) write 1 to the module enable bit men in the module configuration register (mcr) the controller now enters the normal mode. th e application can commence with the protocol initialization described in section 22.7.1.2, protocol initialization . table 22-117. flexray channel bit rate control flexray channel bit rate [mbit/s] mcr.bitrate pdmicrotick [ns] gdsampleclockperiod [ns] psamplespermicrotick csamplesperbit cstrobeoffset 10.0 000 25.0 12.5 2 8 5 8.0 011 25.0 12.5 2 10 6 5.0 001 25.0 25.0 1 8 5 2.5 010 50.0 50.0 1 8 5
flexray communication controller (flexray) 22-150 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.7.1.2 protocol initialization this section describes the protocol related initialization steps. 1. configure the protocol engine. a) issue config command via protocol operation control register (pocr) b) wait for poc:config in protocol status register 0 (psr0) c) configure the pcr0,..., pcr30 register s to set all protocol parameters 2. configure the message buffers and fifos. a) set the number of message buffers used a nd the message buffer segmentation in the message buffer segment size and util ization register (mbssutr) b) define the message buffer data size in the message buffer data size register (mbdsr) c) configure each message buffer by sett ing the configuration values in the message buffer configuration, control, status registers (mbccsrn) , message buffer cycle counter filter registers (mbccfrn) , message buffer frame id registers (mbfidrn) , message buffer index registers (mbidxrn) d) configure the fifos e) issue config_complete command via protocol operation control register (pocr) f) wait for poc:ready in protocol status register 0 (psr0) after this sequence, the c ontroller is configured as a flexray node and is ready to integrate into the flexray cluster. 22.7.2 shut down sequence this section describes a secure shut down sequence to stop the controller gracefully. the main targets of this sequence are ? finish all ongoing reception and transmission ? do not corrupt flexray bus and do not disturb ongoing flexray bus communication for a graceful shutdown the applicati on shall perform the following tasks: 1. disable all enabled message buffers. a) repeatedly write 1 to mbccsrn[edt] until mbccsrn[eds] == 0. 2. stop protocol engine. a) issue halt command via protocol operation control register (pocr) b) wait for poc:halt in protocol status register 0 (psr0) 22.7.3 number of usable message buffers this section describes the relationshi p between the number of message buffers that can be utilized and the required minimum chi clock frequenc y. additional constraints for the minimum chi clock frequency are given in section 22.3, controller ho st interface clocking .
flexray communication controller (flexray) freescale semiconductor 22-151 pxr40 microcontroller reference manual, rev. 1 the controller uses a sequential s earch algorithm to determine the i ndividual message buffer assigned or subscribed to the next slot. this search must be finished within one flexray slot. the shortest flexray slot is an empty dynamic slot. an empty dyna mic slot is a minisl ot and consists of gdminislot macroticks with a nominal duration of gdmacrotick . the minimum duration of a corrected macrotick is gdmacrotick min = 39 ? t. this results in a minimum slot length of eqn. 22-30 the search engine is located in the chi and runs on the chi clock. it evaluates one individual message buffer per chi clock cycle. for inte rnal status update and double buffer commit operations, and as a result of the clock domain crossing jitter, an additional amount of 10 chi cloc k cycles is required to ensure correct operation. for a given number of message buffers and for a given chi clock frequency f chi , this results in a search duration of eqn. 22-31 the message buffer search must be finish ed within one slot which requires that equation 22-32 must be fulfilled eqn. 22-32 this results in the formula given in equation 22-33 which determines the required minimum chi frequency for a given number of me ssage buffers that are utilized. eqn. 22-33 the minimum chi frequency for a selected set of relevant protocol parameters is given in table 22-118 . 22.7.4 protocol control command execution this section considers the issues of the protocol control command execution. the application issues any of the protocol co ntrol commands listed in the poccmd field of table 22-15 by writing the command to the poccmd field of the protocol operation control register (pocr) . as a result the controller sets the bs y bit while the command is transferred to the pe. when the pe has accepted the command, the bsy flag is clear ed. all commands are accepted by the pe. the pe maintains a protocol comma nd vector. for each command that wa s accepted by the pe, the pe sets the corresponding command bit in the protocol comm and vector. if a command is issued while the corresponding command bit is set, the command is not queued and is lost. table 22-118. minimum f chi [mhz] examples (128 message buffers) pdmicrotick [ns] gdminislot 234567 25.0 70.77 47.18 35.39 28.31 23.59 20.22 50.0 35.39 23.59 17.70 14.16 11.80 10.11 ? slotmin 39 pdmicrotick gdminislot ?? = ? search 1 f chi ------- - # messagebuffers 10 + ?? ? = ? search ? slotmin ? f chi # messagebuffers 10 + 39 pdmicrotick gdminislot ?? --------------------------------------------------------------------- - ?
flexray communication controller (flexray) 22-152 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if the command execution block of the pe is idle, it selects the next accepted protocol command with the highest priority from the current protocol command vector according to the protocol control command priorities given in table 22-119 . if the current protocol state does not allow the ex ecution of this protocol command (see poc state changes in flexray communications system pr otocol specification, version 2.1 rev a ) the controller asserts the illegal protoc ol command interrupt flag ipc_if in the protocol interrupt flag register 1 (pifr1) . the protocol command is not executed in this case. some protocol commands may be inte rrupted by other commands or the de tection of a fatal protocol error as indicated by table 22-119 . if the application issues the fr eeze or ready command, or if the pe detects a fatal protocol error, some commands already stored in the co mmand vector will be removed from this vector. 22.7.5 message buffer search on si mple message buffer configuration this sections describes the messag e buffer search behavior for a simp lified message buffer configuration. the fifo behavior is not c onsidered in this section. 22.7.5.1 simple message buffer configuration a simple message buffer conf iguration is a configurati on that has at most one tr ansmit message buffer and at most one receive messag e buffer assigned to a slot s . the simple configuration used in this section utilizes two message buff ers, one single buffered transmit message buffer and one receive message buffer. the transmit message buffer has the message buffer number t and has following configuration table 22-119. protocol control command priorities protocol command priority interrupted by cleared and terminated by freeze (highest) 1 none ready 2 config_complete 3 all_slots 4 freeze, ready, config_complet, fatal protocol error freeze, ready, config_complete, fatal protocol error allow_coldstart 5 run 6 freeze, fatal protocol error wakeup 7 freeze, fatal protocol error default_config 8 freeze, fatal protocol error config 9 halt (lowest) 10 freeze, ready, config_complete, fatal protocol error
flexray communication controller (flexray) freescale semiconductor 22-153 pxr40 microcontroller reference manual, rev. 1 the availability of data in the tr ansmit buffer is indicated by the comm it bit mbccsrt[cmt] and the lock bit mbccsrt[lcks]. the receive message buffer has the message buffer number r and has following configuration furthermore the assumption is that bot h message buffers are enabled (mbccsr t [eds] = 1 and mbccsr r [eds] = 1) note the cycle set {4n+2} = {2,6,10,...} is assigned to the receive buffer only. the cycle set {4n} = {0,4,8,12,...} is assigned to both buffers. table 22-120. transmit buffer configuration register field value description mbccsr t mcm - used only for double buffers mbt 0 single transmit buffer mtd 1 transmit buffer mbccfr t mtm 0 event transition mode cha 1 assigned to channel a chb 0 not assigned to channel b ccfe 1 cycle counter filter enabled ccfmsk 000011 cycle set = {4n} = {0,4,8,12,...} ccfval 000000 mbfidr t fid s assigned to slot s table 22-121. receive buffer configuration register field value description mbccsr r mcm - n/a mbt - n/a mtd 0 receive buffer mbccf r mtm - n/a cha 1 assigned to channel a chb 0 not assigned to channel b ccfe 1 cycle counter filter enabled ccfmsk 000001 cycle set = {2n} = {0,2,4,6,...} ccfval 000000 mbfidr r fid s subscribed slot
flexray communication controller (flexray) 22-154 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 22.7.5.2 behavior in static segment in this case, both message buffers are assigned to a slot s in the static segment. the configuration of a transm it buffer for a static slot s assigns this slot to the node as a transmit slot. the flexray protocol requires: ? when a slot occurs, if the slot is assigned to a node on a channel that node must transmit either a normal frame or a null frame on that channel. specifically, a null fram e will be sent if there is no data ready, or if there is no match on a transmit filt er (cycle counter f iltering, for example). regardless of the availability of data and the cycle counter fi lter, the node will transm it a frame in the static slot s. in any case, the result of the message buffe r search will be the tr ansmit message buffer t. the receive message buffer r will not be found, no reception is possible. 22.7.5.3 behavior in dynamic segment in this case, both message buf fers are assigned to a slot s in the dynamic segment. the flexray protocol requires: ? when a slot occurs, if a slot is assigned to a node on a channel that node onl y transmits a frame on that channel if there is data ready and there is a match on relevant transmit filters (no null frames are sent). the transmission of a frame in the dynamic segment is determined by the av ailability of data and the match of the cycle counter filter of the transmit message buffer. 22.7.5.3.1 transmit data not available if transmit data are not available , i.e. the transmit buffer is not committed mbccsr t [cmt]=0 and/or locked mbccsr t [lcks]=1, a) for the cycles in the set {4n}, which is assigned to both buffers, the receiv e buffer will be found and the node can receive data, and b) for the cycles in the set {4n+2}, which is assigne d to the receive buffer only, the receive buffer will be found and the node can receive data. the receive cycles are shown in figure 22-153 figure 22-153. transmit data not available 22.7.5.3.2 transmit data available if transmit data are available, i.e. the transmit buffer is committed mbccsr t [cmt]=1 and not locked mbccsr t [lcks]=0, a) for the cycles in the set {4n}, which is assigned to both buffers, the transm it buffer will be found and the node transmits data. 0 rx 1 2 rx 3 4 rx 5 6 rx 7 59 60 rx 61 62 rx 8 rx 63
flexray communication controller (flexray) freescale semiconductor 22-155 pxr40 microcontroller reference manual, rev. 1 b) for the cycles in the set {4n+2}, which is assigne d to the receive buffer only, the receive buffer will be found and the node can receive data. the receive and transmit cycles are shown in figure 22-153 figure 22-154. transmit data not available 0 tx 1 2 rx 3 4 tx 5 6 rx 7 59 60 tx 61 62 rx 8 tx 63
flexray communication controller (flexray) 22-156 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 23-1 pxr40 microcontroller reference manual, rev. 1 chapter 23 enhanced modular input/output subsystem (emios200) 23.1 introduction the emios200 provides functionality to generate or measure time events. the emios200 is implemented with its own configuration of time r channels to suit the target appl ications needs, while providing a consistent user interface with previous emios im plementations. the pxr40 has one emios200 module that implements 24-bitcounters.
enhanced modular input/output subsystem (emios200) 23-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.1.1 block diagram figure 23-1 shows the emios200 block diagram. figure 23-1. emios200 block diagram ? ? ? ? ? ? channel[7] channel[0] [b] emios[7] emios[0] [a] ? ? ? ? ? ? counter buses (time bases) all submodules internal counter clock enable iib emios channel flags global time base enable global time base bit (gtbe) output system clock biu ip interface clock prescaler output disable control bus channel[15] channel[8] [c] enhanced modular i/o system (emios200) emios[15] emios[8] ? ? ? ? ? ? channel[23] channel[16] [d] emios[23] emios[16] ? ? ? ? ? ? channel[31] channel[24] [e] emios[31] emios[24] redline former stac bus
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-3 pxr40 microcontroller reference manual, rev. 1 23.1.2 features ? 32 unified channels (uc) ? channel features: ? 24-bit registers for captured/match values ? 24-bit internal counter ? internal prescaler ? selectable time base ? can generate its own time base ? five 24-bit-wide counter buses ? counter bus a can be driven by unified channel 23or by the stac bus. ? counter buses b, c, d, and e are driven by unified channels 0, 8, 16, and 24, respectively ? counter bus a can be shared am ong all unified channels. ucs 0 to 7, 8 to 15, 16 to 23, and 24 to 31 can share counter buses b, c, d, and e, respectively ? one global prescaler ? the output signal from the module configurati on register?s global time base enable bit (emios_mcr[gtbe]) is wra pped back into the global timebase en able input so that the timebase of each channel can be started simultaneously. ? shared time bases through the counter buses ? shadow flag register ? state of emios200 can be frozen for debug purposes ? debug mode is supported 23.1.3 modes of operation there are three main operating m odes of emios200: run mode, modul e disable mode, and debug mode. these modes are briefly de scribed in this section. run mode is the normal operati on mode and is described in section 23.4, functional description. module disable mode is used for mcu power mana gement. the clock to the non-memory-mapped logic in the emios200 is stopped while in module disabl e mode. module disable m ode is entered when mdis = 1 in the emios_mcr. debug mode is individually programmed for each channel. when entering this m ode, the unified channel registers? contents are frozen, but remain availabl e for read and write acces s through the ip interface. 23.1.4 emios200 chan nel configurations table 23-1 lists the emios modes supported on the unified channels for th is device. all included modes are on all channels.
enhanced modular input/output subsystem (emios200) 23-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 23-1. emios modes description name section/page general purpose in put / output gpio 23.4.1.1.1/23-22 single action input capture saic 23.4.1.1.2/23-23 single action output compare saoc 23.4.1.1.3/23-24 input pulse-width measurement ipwm 23.4.1.1.4/23-26 input period measurement ipm 23.4.1.1.5/23-27 double action output compare daoc 23.4.1.1.6/23-29 pulse edge accumulation pea 23.4.1.1.7/23-31 pulse edge counting pec 23.4.1.1.8/23-33 quadrature decode qdec 23.4.1.1.9/23-35 windowed programmable time accumulation wpta 23.4.1.1.10/23-36 modulus counter mc 23.4.1.1.11/23-37 modulus counter buffered (up / down) mcb 23.4.1.1.12/23-39 output pulse width and frequency modulation opwfm 23.4.1.1.13/23-42 output pulse width and frequency modulation buffered opwfmb 23.4.1.1.14/23-43 center-aligned output pwm with dead time opwmc 23.4.1.1.15/23-48 center-aligned output pwm buffered with dead time opwmcb 23.4.1.1.16/23-51 output pulse width modulation opwm 23.4.1.1.18/23-58 output pulse width modulation buffered opwmb 23.4.1.1.18/23-58
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-5 pxr40 microcontroller reference manual, rev. 1 23.2 external signal description refer to section 2.2, external signal descripti ons, pin multiplexing, and attributes , and section 2.3, detailed signal description, for detailed signal descriptions. 23.2.1 emios[ n ] emios[ n ] are the emios channel pins. when used as an input, an emios[ n ] signal is available to be read by the mcu through the ucin bit in the emios_csr[ n ] register. when used as an output, the ucout bit of the emios_csr[ n ] register reflects the state of the output pin. note all emios channels support both input and output functions. when the emios function is the primary functi on of a pin, then both the input and output functions are supported. when th e emios function is not the primary function of the pin, then only th e output functions are supported. 23.2.2 output disable input ? emio s200 output disable input signal each output pin may be disabled by the assertion of a selected emios channel flag bit from the emios_gfr register described in 23.3.2.2/23-9 . the choice of flag is defined by the odis and odissl bit fields of the emios_ ccr[n] described in section 23.3.2.7/23-12
enhanced modular input/output subsystem (emios200) 23-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.3 memory map and register description this section provides a detailed de scription of all emios200 registers. 23.3.1 memory map the emios200 memory map is shown in table 23-2 . the address of each register is given as an offset to the emios200 base address. register s are listed in address order, identified by complete name and mnemonic, and lists the type of accesses allowed. table 23-2. emios200 memory map offset from emios_base (0xc3fa_0000) register bits access 1 reset value section/page global registers 0x0000 emios_mcr ? module configuration register 32 r/w 0x0000_0000 23.3.2.1/23-8 0x0004 emios_gfr ? global flag register 32 r 0x0000_0000 23.3.2.2/23-9 0x0008 emios_oudr ? output update disable register 32 r/w 0x0000_0000 23.3.2.3/23-10 0x000c?0x001f reserved unified channel 0 registers 0x0020 emios_cadr[0] ? channel a data register 32 r/w 0x0000_0000 23.3.2.4/23-10 0x0024 emios_cbdr[0] ? channel b data register 32 r/w 0x0000_0000 23.3.2.5/23-11 0x0028 emios_ccntr[0] ? channel counter register 32 r 0x0000_0000 23.3.2.6/23-12 0x002c emios_ccr[0] ? channel control register 32 r/w 0x0000_0000 23.3.2.7/23-12 0x0030 emios_csr[0] ? channel status register 32 r 0x0000_0000 23.3.2.8/23-18 0x0034 emios_alta[0] 2 ? alternate a register 32 r/w 0x0000_0000 23.3.2.9/23-19 0x0038?0x003f reserved unified channel 1 registers 0x0040 emios_cadr[1] ? a register 32 r/w 0x0000_0000 23.3.2.4/23-10 0x0044 emios_cbdr[1] ? b register 32 r/w 0x0000_0000 23.3.2.5/23-11 0x0048 emios_ccntr[1] ? counter register 32 r 0x0000_0000 23.3.2.6/23-12 0x004c emios_ccr[1] ? control register 32 r/w 0x0000_0000 23.3.2.7/23-12 0x0050 emios_csr[1] ? status register 32 r 0x0000_0000 23.3.2.8/23-18 0x0054 emios_alta[1] 2 ? alternate a register 32 r/w 0x0000_0000 23.3.2.9/23-19 0x0058?0x005f reserved unified channel 2 registers 0x0060 emios_cadr[2] ? a register 32 r/w 0x0000_0000 23.3.2.4/23-10 0x0064 emios_cbdr[2] ? b register 32 r/w 0x0000_0000 23.3.2.5/23-11
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-7 pxr40 microcontroller reference manual, rev. 1 0x0068 emios_ccntr[2] ? counter register 32 r 0x0000_0000 23.3.2.6/23-12 0x006c emios_ccr[2] ? control register 32 r/w 0x0000_0000 23.3.2.7/23-12 0x0070 emios_csr[2] ? status register 32 r 0x0000_0000 23.3.2.8/23-18 0x0074 emios_alta[2] 2 ? alternate a register 32 r/w 0x0000_0000 23.3.2.9/23-19 0x0078?0x007f reserved unified channel 3?31 registers 0x0080?0x041f same as other channel registers (e.g. emios_cadr[2], emio s_cbdr[2], etc.) 32 ? ? ? 0x0420?0x3fff reserved 1 note that r/w registers may contain some read-only or write-only bits. 2 the alternate address register provides and alternate read-only address to access a2 channel registers in pulse edge counting (pec) and windowed programmable time accumulation (wpta) modes. if emios_cadr[ n ] register is used with emios_alta[ n ], both a1 and a2 registers can be accessed in these modes. table 23-3. unified channel base offsets unified channel offset from emios_base (0xc3fa_0000) unified channel offset from emios_base (0xc3fa_0000)) unified channel 0 0x0020 unified channel 16 0x0220 unified channel 1 0x0040 unified channel 17 0x0240 unified channel 2 0x0060 unified channel 18 0x0260 unified channel 3 0x0080 unified channel 19 0x0280 unified channel 4 0x00a0 unified channel 20 0x02a0 unified channel 5 0x00c0 unified channel 21 0x02c0 unified channel 6 0x00e0 unified channel 22 0x02e0 unified channel 7 0x0100 unified channel 23 0x0300 unified channel 8 0x0120 unified channel 24 0x0320 unified channel 9 0x0140 unified channel 25 0x0340 unified channel 10 0x0160 unified channel 26 0x0360 unified channel 11 0x0180 unified channel 27 0x0380 unified channel 12 0x01a0 unified channel 28 0x03a0 unified channel 13 0x01c0 unified channel 29 0x03c0 unified channel 14 0x01e0 unified channel 30 0x03e0 unified channel 15 0x0200 unified channel 31 0x0400 table 23-2. emios200 memory map (continued) offset from emios_base (0xc3fa_0000) register bits access 1 reset value section/page
enhanced modular input/output subsystem (emios200) 23-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.3.2 register descriptions this section lists the emios200 regist ers in address order and describes the registers and their bit fields. 23.3.2.1 emios200 module config uration register (emios_mcr) the emios_mcr contains global c ontrol bits for the emios200 block. offset: emios_base + 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mdis frz gtbe etb gpren 000000 srv[0:3] w reset000 0 0 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpre[0:7] 00000000 w reset000 0 0 0 0000000000 figure 23-2. emios200 module configuration register (emios_mcr) table 23-4. emios_m cr field descriptions field description 0 reserved. note: writing to this bit updates the register value, and re ading it returns the last valu e written, but the bit has no other effect. 1 mdis module disable bit. puts the emios200 in low-power m ode. the mdis bit is used to stop the clock of the block, except the access to regi sters emios_mcr and emios_oudr. 0 clock is running. 1 enter low-power mode. 2 frz freeze bit. enables the emios200 to freeze the re gisters of the unified channels when debug mode is requested at mcu level. each unified channel must have fren bit set in order to enter freeze mode. while in freeze mode, the emios200 continues to operate to allow the mcu access to the unified channel registers. the unified channel remains frozen until the frz bit is wr itten to 0 or the mcu exit s debug mode or the unified channel fren bit is cleared. 0 exit freeze mode. 1 stops unified channel operation when in debug mode and the fren bit is set in the emios_ccr[ n ] register. 3 gtbe global time base enable bit. the gtbe bit is used to export a global time base enable from the module and provide a method to start time bases of several blocks simultaneously. 0 global time base enable out signal negated. 1 global time base enable out signal asserted. note: the global time base enable input pin controls the internal counters. when asserted, internal counters are enabled. when negated, inte rnal counters are disabled. 4 etb external time base bit. the etb bit selects the time base source that drives counter bus[a]. 0 counter bus[a] assigned to unified channel 23 1 stac drives counter bus [a] if etb is set to select stac as the counter bus[a] source, the gtbe must be set to enable the stac to counter bus[a]. see the stac bus configuration regi ster (etpu_redcr) section of the etpu chapter for more information about the stac.
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-9 pxr40 microcontroller reference manual, rev. 1 23.3.2.2 emios200 glo bal flag register (emios_gfr) 5 gpren global prescaler enable bit. the gpren bit enables the prescaler counter. 0 prescaler disabled and prescaler counter is cleared. 1 prescaler enabled. 6?11 reserved 12?15 srv server time slot. selects the address of a specific stac server to which the stac client submodule is assigned. see section 23.4.3, stac client submodule . 0000 etpu engine a, tcr1 0001 etpu engine b, tcr1 0010 etpu engine a, tcr2 0011 etpu engine b, tcr2 0100?1111 reserved 16?23 gpre global prescaler bits. the gpre bits select the clock divider value for the global prescaler. 24?31 reserved offset: emios_base + 0x000 4 access: user read-only 0123456789101112131415 rf31f30f29f28f27f26f25f24f23f22f21f20f19f18f17f16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rf15f14f13f12f11f10f9f8f7f6f5f4f3f2f1f0 w reset0000000000000000 figure 23-3. emios200 global flag register (emios_gfr) table 23-4. emios_mcr field descriptions (continued) field description gpre divide ratio 0000_0000 1 0000_0001 2 0000_0010 3 0000_0011 4 . . . . . . 1111_1110 255 1111_1111 256
enhanced modular input/output subsystem (emios200) 23-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.3.2.3 emios200 output update disable register (emios_oudr) 23.3.2.4 emios200 a re gister (emios_cadr[ n ]) depending on the mode of operation, in ternal registers a1 or a2, used for matches and captures, can be assigned to address emios_cadr[ n ]. a1 and a2 are cleared by reset. table 23-7 summarizes the emios_cadr[ n ] writing and reading accesses for all oper ation modes. for more information see section 23.4.1.1, unified channe l modes of operation. table 23-5. emios_gfr field descriptions field description 0?31 f n flag bits. the emios_gfr is a read-onl y register that groups the flag bits from all channels. these bits are mirrors of the flag bits of each channel register (emios_csr[ n ]). offset: emios_base + 0x0008 a ccess: user read/write 0123456789101112131415 r ou31 ou30 ou29 ou28 ou27 ou26 ou25 ou24 ou23 ou22 ou21 ou20 ou19 ou18 ou17 ou16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ou15 ou14 ou13 ou12 ou11 ou10 ou9 ou8 ou7 ou6 ou5 ou4 ou3 ou2 ou1 ou0 w reset0000000000000000 figure 23-4. emios200 ou tput update disable register (emios_oudr) table 23-6. emios_oudr field descriptions field description 0?31 ou n channel [ n ] output update disable bits. w hen running mc, mcb, or an output mode, values are written to registers a2 and b2. ou n bits are used to disable transfers from regist ers a2 to a1 and b2 to b1. each bit controls one channel. 0 transfer enabled. depending on the operation mode, tran sfer may occur immediately or in the next period. unless stated otherwise, transfer occurs immediately. 1 transfers disabled. offset: uc[ n ] base address + 0x0000 access: user read/write 0123456789101112131415 r00000000 a[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r a[0:23] w reset0000000000000000 figure 23-5. emios200 a register (emios_cadr[ n ])
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-11 pxr40 microcontroller reference manual, rev. 1 23.3.2.5 emios200 b re gister (emios_cbdr[ n ]) depending on the mode of operation, internal regi sters b1 or b2 can be assigned to address emios_cbdr[ n ]. both b1 and b2 are cleared by reset. table 23-7 summarizes the emios_cbdr writing and reading accesses fo r all operation modes. for mo re information see section section 23.4.1.1, unified channel modes of operation. depending on the channel configuration, it may have the emios_cbdr register or not. this means that if at least one mode that requires th e register is implemented, then the regi ster is present. otherwise, it is absent. pxr40 has register b (e mios_cbdr) in all channels. offset: uc[ n ] base address + 0x0004 access: user read/write 0123456789101112131415 r00000000 b[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r b[0:23] w reset0000000000000000 figure 23-6. emios200 b register (emios_cbdr[ n ]) table 23-7. emios_cadr[ n ], emios_cbdr[ n ], and emios_alta[ n ] values assignment operation mode register access write read write read alternate write alternate read gpio a1, a2 a1 b1, b2 b1 a2 a2 saic 1 ?a2b2b2 ? ? saoc 1 a2 a1 b2 b2 ? ? ipwm ? a2 ? b1 ? ? ipm ? a2 ? b1 ? ? daoc a2 a1 b2 b1 ? ? pea a1 a2 ? b1 ? ? pec 1 a1 a1 b1 b1 ? a2 qdec 1 a1 a1 b2 b2 ? ? wpta a1 a1 b1 b1 ? a2 mc 1 a2 a1 b2 b2 ? ? opwfm a2 a1 b2 b1 ? ? opwmc a2 a1 b2 b1 ? ? opwm a2 a1 b2 b1 ? ? mcb 1 a2 a1 b2 b2 ? ?
enhanced modular input/output subsystem (emios200) 23-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.3.2.6 emios200 counter register (emios_ccntr[ n ]) the emios_ccntr[ n ] register contains the value of th e internal counter for emios channel n . when gpio mode is selected or the ch annel is frozen, the emios_ccntr[ n ] register is read/w rite. for all other modes, the emios_ccntr[ n ] is a read-only register. when enteri ng some operation modes, this register is automatically cleared (refer to section 23.4.1.1, unified channel modes of operation, for details). depending on the channel configuration it may have an internal counter or not. it means that if at least one mode that requires the counter is implemented, then the counter is present, otherwise it is absent. 23.3.2.7 emios200 control register (emios_ccr[ n ]) opwfmb a2 a1 b2 b1 ? ? opwmcb a2 a1 b2 b1 ? ? opwmb a2 a1 b2 b1 ? ? 1 in these modes, the register emios_cbdr[ n ] is not used, but b2 can be accessed. offset: uc[ n ] base address + 0x0008 access: user read/write 0123456789101112131415 r00000000 c[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rc[0:23] w reset0000000000000000 1 in gpio mode or freeze action, this register is writable. figure 23-7. emios200 count er register (emios_ccntr[ n ]) offset: uc[ n ] base address + 0x000c access: user read/write 012 3 456789101112131415 r fren odis odissl ucpre uc pren dma 0 if fck fen 0 w reset000 0 000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 forc ma forc mb 0 bsl ed sel ed pol mode w reset000 0 000000000000 figure 23-8. emios200 control register (emios_ccr[ n ]) table 23-7. emios_cadr[ n ], emios_cbdr[ n ], and emios_alta[ n ] values assignment (continued) operation mode register access write read write read alternate write alternate read
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-13 pxr40 microcontroller reference manual, rev. 1 the control register gathers bits reflecting the status of the unified channel i nput/output signals and the overflow condition of the internal counter, as well as several read/write control bits. table 23-8. emios_ccr[ n ] field descriptions field description 0 fren freeze enable bit. the fren bit, if set and validated by frz bit in emios_mcr register, freezes all registers? values when in debug mode, allowing the mcu to perform debug functions. 0 normal operation. 1 freeze unified channel registers? values. 1 odis output disable bit. the odis bit allows disabling the output pin when running any of the output modes with the exception of gpio mode. 0 the output pin operates normally. 1 if the selected output disable input signal is asse rted, the output pin goes to edpol for opwfmb and opwmb modes and to the complement of edpol for other modes, but the unified channel continues to operate normally, i.e., it continues to produce flag and matches. when the selected output disable input signal is negated, the output pin operates normally. 2?3 odissl output disable select bits. the odissl bits select an emios channel flag to disable an output when the flag asserts. 4?5 ucpre prescaler bits. the ucpre bits select the clock divider value for the internal prescaler of unified channel. 6 ucpren prescaler enable bit. the ucpren bit enables the prescaler counter. 0 prescaler disabled. 1 prescaler enabled and the prescaler counter is loaded with uccpre value. 7 dma direct memory access bit. the dma bit selects whether th e flag generation is used as an interrupt or as a dma request. 0 flag/overrun assigned to interrupt request. 1 flag/overrun assigned to dma request. 8 reserved odissl emios channel flag number 00 11 01 10 10 9 11 8 ucpre divide ratio 00 1 01 2 10 3 11 4
enhanced modular input/output subsystem (emios200) 23-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 9?12 if input filter bits. the if bits contro l the programmable input filter, selecti ng the minimum input pulse width that can pass through the filter. for output modes, these bits have no meaning. 13 fck filter clock select bit. the fc k bit selects the clock source for the programmable input filter. 0 prescaled clock. 1 main clock. 14 fen flag enable bit. the fen bit allows the unified channel flag bit to generate an interrupt signal or a dma request signal (the type of signal to be generated is defined by the dma bit). 0 disable (flag does not generate an interrupt or dma request). 1 enable (flag generates an interrupt or dma request). 15?17 reserved 18 forcma force match a bit. for output modes, the forcma bit is equivalent to a successful comparison on comparator a (except that the flag bit is not set). this bit is cleared by reset and is always read as 0. this bit is valid for every output operation mode which uses comparator a, otherwise it has no effect. 0 has no effect. 1 force a match at comparator a. for input modes, the forcma bit is not used and writing to it has no effect. 19 forcmb force match b bit. for output modes, the forcmb bit is equivalent to a successful comparison on comparator b (except that the flag bit is not set). this bit is cleared by reset and is always read as 0. this bit is valid for every output operation mode which uses comparator b, otherwise it has no effect. 0 has no effect. 1 force a match at comparator b. for input modes, the forcmb bit is not used and writing to it has no effect. 20 reserved table 23-8. emios_ccr[ n ] field descriptions (continued) field description if 1 1 filter latency is three clock edges. minimum input pulse width [flt_clk periods] 0000 bypassed 2 0001 02 0010 04 0100 08 1000 16 all others reserved 2 the input signal is synchronized before arriving to the digital filter.
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-15 pxr40 microcontroller reference manual, rev. 1 21?22 bsl bus select bits. the bsl bits are used to select either one of the counter buses or the internal counter to be used by the unified channel. 23 edsel edge selection bit. for input modes, the edsel bit select s if the internal counter is triggered by both edges of a pulse or by a single edge only as defined by the edpol bit. when not shown in the mode of operation description, this bit has no effect. 0 single edge triggering defined by the edpol bit. 1 both edges triggering. for gpio in mode, the edsel bit selects if a flag can be generated. 0 a flag is generated as defined by the edpol bit. 1 no flag is generated. for saoc mode, the edsel bit selects the beha vior of the output flip-flop at each match. 0 the edpol value is transferred to the output flip-flop. 1 the output flip-flop is toggled. table 23-8. emios_ccr[ n ] field descriptions (continued) field description bsl selected bus 00 all channels: counter bus[a] 01 channels 0 to 7: counter bus[b] channels 8 to 15: counter bus[c] channels 16 to 23: counter bus[d] channels 24 to 31: counter bus[e] 10 reserved 11 all channels: internal counter
enhanced modular input/output subsystem (emios200) 23-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24 edpol edge polarity bit. for input modes, the edpol bit asserts which edge triggers either the internal counter or an input capture or a flag. when not shown in the mo de of operation description, this bit has no effect. 0 trigger on a falling edge. 1 trigger on a rising edge. for qdec (mode[6] cleared), the edpol bit selects the count dire ction according to direction signal (uc[n] input). 0 counts down when uc[n] is asserted 1 counts up when uc[n] is asserted note: uc[n-1] edpol bit selects which edge clocks the internal counter of uc[n] 0 trigger on a falling edge 1 trigger on a rising edge for qdec (mode[6] set), the edpol bit selects the count direction according to the phase difference. 0 internal counter decrements if phase_a is ahead phase_b signal 1 internal counter increments if phase_a is ahead phase_b signal note: in order to operate properly, edpol bit must contain the same value in uc[n] and uc[n-1] for output modes, the edpol bit is used to se lect the logic level on the output pin. 0 a match on comparator a clears the output flip -flop, while a match on comparator b sets it. 1 a match on comparator a sets the output flip-f lop, while a match on comparator b clears it. 25?31 mode mode selection bits. the mode bits select the mode of operation of the unified channel, as shown in ta b l e 2 3 - 9 . refer to ta bl e 2 3 - 1 for more information on the different modes. note: if a reserved value is written to mode, the results are unpredictable. table 23-9. mode bits mode mode description 000_0000 gpio (input) general-purpose input/output mode (input) 000_0001 gpio (output) general-purpose input/output mode (output) 000_0010 saic single action input capture 000_0011 saoc single action output compare 000_0100 ipwm input pulse width measurement 000_0101 ipm input period measurement 000_0110 daoc double action output compare (with flag set on b match) 000_0111 daoc double action output compare (with flag set on both match) 000_1000 pea pulse/edge accumulation (continuous) 000_1001 pea pulse/edge accumulation (single-shot) 000_1010 pec pulse/edge counting (continuous) 000_1011 pec pulse/edge counting (single-shot) 000_1100 qdec quadrature decode (for count & direction encoders type) table 23-8. emios_ccr[ n ] field descriptions (continued) field description
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-17 pxr40 microcontroller reference manual, rev. 1 000_1101 qdec quadrature decode (for phase_a & phase_b encoders type) 000_1110 wpta windowed programmable time accumulation 000_1111 reserved 001_0000 mc modulus counter (up counter with clear on match start, internal clock) 001_0001 mc modulus counter (up counter with clear on match start, external clock) 001_0010 mc modulus counter (up counter with clear on match end, internal clock) 001_0011 mc modulus counter (up counter with clear on match end, external clock) 001_0100 mc modulus counter (up/down counter with flag on a match, internal clock) 001_0101 mc modulus counter (up/down counter with flag on a match, external clock) 001_0110 mc modulus counter (up/down counter with flag on a match or cycle boundary, internal clock) 001_0111 mc modulus counter (up/down counter with flag on a match or cycle boundary, external clock) 001_1000 opwfm output pulse width and frequency mo dulation (flag on b match, immediate update) 001_1001 opwfm output pulse width and frequency mo dulation (flag on b match, next period update) 001_1010 opwfm output pulse width and frequency modulation (flag on a or b matches, immediate update) 001_1011 opwfm output pulse width and frequency modulation (flag on a or b matches, next period update) 001_1100 opwmc center aligned output pulse width modulation (flag in trailing edge, trailing edge dead time) 001_1101 opwmc center aligned output pulse width modulation (flag in trailing edge, leading edge dead time) 001_1110 opwmc center aligned output pulse width modulation (flag in both edges, trailing edge dead time) 001_1111 opwmc center aligned output pulse width modulation (flag in both edges, leading edge dead time) 010_0000 opwm output pulse width modulati on (flag on b match, immediate update) 010_0001 opwm output pulse width modulation (flag on b match, next period update) 010_0010 opwm output pulse width modulati on (flag on b match, immediate update) 010_0011 opwm output pulse width modulation (flag on b match, next period update) 010_0100 ? 100_1111 reserved 101_0000 mcb modulus counter buffered (up counter with clear on match start, internal clock) 101_0001 mcb modulus counter buffered (up counter with clear on match start, external clock) 101_0010 ? 101_0011 reserved 101_0100 mcb modulus counter buffered (up/down counter with flag on a match, internal clock) table 23-9. mode bits (continued) mode mode description
enhanced modular input/output subsystem (emios200) 23-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.3.2.8 emios200 status register (emios_csr[ n ]) 101_0101 mcb modulus counter buffered (up/down counter with flag on a match, external clock) 101_0110 mcb modulus counter buffered (up/down counter with flag on a match or cycle boundary, internal clock) 101_0111 mcb modulus counter buffered (up/down counter with flag on a match or cycle boundary, external clock) 101_1000 opwfmb output pulse width and frequen cy modulation buffered, (flag on b match) 101_1001 reserved 101_1010 opwfmb output pulse width and frequency mo dulation buffered, (flag on a or b matches) 101_1011 reserved 101_1100 opwmcb center aligned output pulse width modulation buffered (flag in trailing edge, trailing edge dead time) 101_1101 opwmcb center aligned output pulse width modulation buffered (flag in trailing edge, leading edge dead time) 101_1110 opwmcb center aligned output pulse width modulation buffered (flag in both edges, trailing edge dead time) 101_1111 opwmcb center aligned output pulse width modulation buffered (flag in both edges, leading edge dead time) 110_0000 opwmb output pulse width modulation buffered (flag on b match) 110_0001 reserved 110_0010 opwmb output pulse width modulati on buffered (flag on a or b matches) 110_0011 ? 111_1111 reserved offset: uc[ n ] base address + 0x0010 access: user read/write 0 1234567891011121314 15 rovr0000000000000 0 0 ww1c reset0 0000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rovfl000000000000ucinucoutflag ww1c w1c reset0 0000000000000 0 0 figure 23-9. emios200 status register (emios_csr[ n ]) table 23-9. mode bits (continued) mode mode description
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-19 pxr40 microcontroller reference manual, rev. 1 23.3.2.9 emios200 alternate a register (emios_alta[ n ]) the emios_alta[ n ] register provides an altern ate read-only address to access a2 channel registers in gpio, pec, wpta, and opwmt modes. if the emios_cadr[ n ] register is used with emios_alta[ n ], both a1 and a2 registers can be accessed in these modes. table 23-10. emios_csr[ n ] field descriptions field description 0 ovr overrun bit. the ovr bit indicates that flag generation occurred when the flag bit was already set. this bit can be cleared by clearing the flag bit or by software writing a 1. 0 overrun has not occurred. 1 overrun has occurred. 1?15 reserved 16 ovfl overflow bit. the ovfl bit indicates that an overflow ha s occurred in the internal counter. this bit must be cleared by software writing a 1. 0 an overflow has not occurred. 1 an overflow has occurred. 17?28 reserved 29 ucin unified channel input pin bit. the ucin bit reflects the input pin state after being filtered and synchronized. 30 ucout unified channel output. the ucout bi t reflects the output pin state. 31 flag flag bit. the flag bit is set when an input capture or a match event in the com parators occurred. this bit must be cleared by software writing a 1. 0 flag cleared. 1 flag set event has occurred. note: emios_flag_out reflects the flag bit value. when th e dma bit is set, the flag bit can be cleared by the dma controller. uc[ n ] base address + 0x0014 access: user read/write 0123456789101112131415 r00000000 alta[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r alta[0:23] w reset0000000000000000 figure 23-10. emios200 alternate a register (emios_alta[ n ])
enhanced modular input/output subsystem (emios200) 23-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.4 functional description the emios200 provides independently operating unified channels (uc) that can be configured and accessed by a host mcu. the five time bases can be shared by the channels th rough five counter buses and each unified channel can ge nerate its own time base. the emios200 block is reset asynchronously . all registers ar e cleared on reset. 23.4.1 unified channel (uc) figure ? shows the unified channel block diagra m.each unified channel consists of: ? counter bus selector, which selects the time base to be used by the channel fo r all timing functions ? a programmable clock prescaler ? two double-buffered data registers, a and b, th at allow up to two input capture and/or output compare events to occur before software intervention is needed ? two comparators (equal only), a and b, which comp are the selected counter bus with the value in the data registers ? internal counter, which can be used as a lo cal time base or to count input events ? programmable input filter, which ensures that only valid pin transitions are received by channel ? programmable input edge de tector, which detects the ri sing, falling or either edges ? an output flip-flop, which holds the logic level to be applied to the output pin ? emios200 status and control register
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-21 pxr40 microcontroller reference manual, rev. 1 ? an output disable input selector, which selects the output disable i nput signal to be used as output disable figure 23-11. unified channel block diagram figure 23-12 shows the unified channel control block diagram. channel_controller ipd_done ipd_req uc_int_flag biu_channel_en[ n ] biu_a_en biu_b_en biu_cnt_en clock prescaler biu_control_en biu_status_en ips_byte[7:0] ips_byte[15:8] ips_byte[23:16] ips_byte[31:24] ips_rwb programmable filter channel_datapath comparator a comparator b uc_cnt_rd_data[ n ] uc_cnt_rd_data[ n ] emios_counter_bus[0] emios_counter_bus[1] match logic mode logic rwcb rcb iib counter bus unified channel control signals uc_rd_data[31:0] ips_wdata[31:0] ips_addr[29:27]
enhanced modular input/output subsystem (emios200) 23-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-12. unified channel control block diagram 23.4.1.1 unified channel modes of operation the mode of operation of the unified channel is de termined by the mode select bits mode in the emios_ccr[ n ] register (see table 23-9 for details). when entering an output mode (except for gpio mode), the output flip-flop is set to the complement of the edpol bit in the emios_ccr[ n ] register. as the internal counter emios_ccntr[ n ] continues to run in all modes (except for gpio mode), it is possible to use this as a time base if the resource is not used in the current mode. in order to provide smooth waveform generation even if a and b registers are changed on the fly, the mcb, opwfmb, opwmb and opwmcb modes are availa ble. in these modes, the a and b registers are double-buffered. these mode s are presented in separa te sections since basic differences exist between these modes and the mc, opwfm, opwm, and opwmc modes, respectively. 23.4.1.1.1 general-purpose input/output (gpio) mode in gpio mode, all input capture a nd output compare functions of the unified channel are disabled, the internal counter (emios_ccntr[ n ] register) is cleared a nd disabled. all control bi ts remain accessible. in order to prepare the unified channel for a ne w operation mode, writing to registers emios_cadr[ n ] or emios_cbdr[ n ] stores the same value in regi sters a1/a2 or b1/b2, respectively. mode n _en mode 0 logic mode 1 logic mode n logic ? ? ? ? ? ? ? ? ? mode1_en mode0_en shared logic channel datapath channel controller ? ? control signals control signals control signals ? ? ? emios_ccr/mode
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-23 pxr40 microcontroller reference manual, rev. 1 the mode[6] bit selects between input (m ode[6] = 0) and output (mode[6] = 1) modes. when changing the mode bits, the a pplication software must go to gpio mode firs t to reset the unified channel?s internal functions prope rly. failure to do this could lead to invalid and unexpected output compare or input capture results or the flags being set incorrectly. in gpio input mode (mode = 000_0000) , the flag generation is determined according to edpol and edsel bits and the input pin status can be determined by reading the ucin bit. in gpio output mode (mode = 000_0001), th e unified channel is used as a single output port pin and the value of the edpol bit is permanently transferred to the output flip-flop. 23.4.1.1.2 single action in put capture (saic) mode in saic mode (mode = 000_0010), when a triggering event occurs on the input pin, the value on the selected time base is captured into register a2. at the same time, the fl ag bit is set to indicate that an input capture has occurred. the emios_cadr[ n ] register returns the value of register a2. the channel is ready to capture events as soon as saic mode is entered coming ou t from gpio mode. the events are captured as soon as they occur, t hus reading register a (emios_cadr) always returns the value of the latest captured event. subsequent captures are enabled with no need of further reads from the emios_cadr[ n ] register. the flag bit is set at any time a new event is captured. the input capture is triggered by a rising, falling, or ei ther edge on the input pi n, as configured by the edpol and edsel bits in emios_ccr[ n ] register. figure 23-13 and figure 23-14 show how the unified channel can be used for input capture. figure 23-13. saic with ri sing edge triggering example selected counter bus flag pin/register edge detect edge detect edge detect a2 (captured) value 2 0xxxxxxx 0x001000 0x001250 0x0016a0 notes: input signal 1 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 1. after input filter 2. emios_cadr[ n ] ? a2 edsel = 1 edpol = x
enhanced modular input/output subsystem (emios200) 23-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-14. saic with both edges triggering example 23.4.1.1.3 single action out put compare (saoc) mode in saoc mode (mode = 000_0011), a match value is load ed in register a2 a nd then transferred to register a1 to be compared with the selected ti me base. when a match occurs, the edsel bit selects whether the output flip-flop is toggled or the value in edpol is tran sferred to it. at the same time, the flag bit is set to indicate that the output comp are match has occurred. wr iting to the emios_cadr[ n ] register stores the value in register a2 and reading to the emios_cadr[ n ] register returns the value of register a1. an output compare match can be simulated in software by setting the forcma bit in the emios_ccr[ n ] register. in this case, the flag bit is not set. when saoc mode is entered coming out of gpio mode, the output flip-f lop is set to the complement of the edpol bit in the emios_ccr[ n ] register. the counter bus can be either internal or ex ternal and is selected through the bsl bits. figure 23-15 and figure 23-16 show how the unified channel can be used to perform a single output compare with the edpo l value being transferred to the output flip-flop and toggling the output flip-flop at each match, respectively. note that once in saoc mode, the matches are enabled. thus the desired match value on register a1 must be written before the mode is entered. register a1 can be updated at any time, thus modifying the match value, which is refl ected in the output signal generated by the channel. subsequent matches are enab led with no need of furthe r writes to emios_cadr[ n ]. the flag bit is set at the same time a match occurs (see figure 23-17 ). note in saoc mode, the internal channe l counter is free-running, and starts counting as soon as the saoc mode is entered. selected counter bus 0x001000 0x001102 flag set event a2 (captured) value 2 0xxxxxx 0x001000 input signal 1 edge detect 0x001103 0x001108 0x001104 0x001105 0x001106 0x001107 0x001001 flag pin/register edge detect flag clear edge detect 0x001103 0x001108 edsel = 1 edpol = x notes: 1 2 after input filter emios_cadr[ n ] ? a2
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-25 pxr40 microcontroller reference manual, rev. 1 figure 23-15. saoc example ? edpol value being transferred to the output flip-flop figure 23-16. saoc example ? toggling the output flip-flop figure 23-17. saoc example with flag behavior selected counter bus flag pin/register a1 match a1 match a1 match 0xxxxxxx 0x001000 0x001000 0x001000 notes: 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 1. emios_cadr[n] = a2 a2 = a1 according to ou[ n ] bit update to a1 edsel = 0 output flip-flop edpol = 1 a1 value 1 0x001000 selected counter bus flag pin/register a1 match a1 match a1 match 0xxxxxxx 0x001000 0x001000 0x001000 note: 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 1. emios_cadr[ n ] = a2 update to a1 edsel = 1 output flip-flop edpol = x a1 value 1 0x001000 selected counter bus 0x000000 0x000002 flag set event a2 value 1 0x000001 output flip-flop 0x000003 0x000002 0x000001 0x000002 0x000000 0x000001 0x000001 flag pin/register flag clear edsel = 1 system clock a1 match edpol = x note: 1. emios_cadr[ n ] ? a2
enhanced modular input/output subsystem (emios200) 23-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.4.1.1.4 input pulse-widt h measurement (ipwm) mode the ipwm mode (mode = 000_0100) allo ws measuring the width of a positive or negative pulse by capturing the leading edge on register b1 and the trai ling edge on register a2. su ccessive captures are done on consecutive edges of opposite polarit y. the leading edge sensitivity (i.e ., pulse polarity) is selected by the edpol bit in the emios_ccr[ n ] register. registers emios_cadr[ n ] and emios_cbdr[ n ] return the values in register a2 and b1, respectively. the capture function of register a2 remains disabled until the first leading edge triggers the first input capture on register b2. when this leading edge is det ected, the count value of th e selected time base is latched into register b2; the flag bit is not set. when the trailing edge is detected, the count value of the selected time base is latched into register a2. at the same time, the flag bit is set and the content of register b2 is transferred to re gister b1 and to register a1. if subsequent input capture events occur while the corresponding flag bit is set, registers a2, b1, and a1 are updated with the latest captured values and the flag remains set. registers emios_cadr[ n ] and emios_cbdr[ n ] return the value in regist ers a2 and b1, respectively. in order to guarantee coherent access, reading emios_cadr[ n ] forces b1 to be u pdated with the content of register a1. at the same time , transfers between b2 and b1 are disabled until the next read of emios_cbdr[ n ] register. reading emios_cbdr[ n ] register forces b1 be updated with a1 register content and re-enables transfers from b2 to b1, to take effect at the next trai ling edge capture. transfers from b2 to a1 are not blocked at any time. the input pulse width is calculated by subtracting the value in b1 from a2. figure 23-18 shows how the unified channel can be used for input pulse-width measurement. figure 23-18. ipwm example figure 23-19 shows the a1 and b1 updates when emios_cadr[ n ] and emios_cbdr[ n ] register reads occur. the a1 register has always coherent data related to the a2 register. when a emios_cadr[ n ] read is performed, the b1 register is loaded with the a1 register content. this guarantees that the data in register b1 always has the coherent data related to the last emios_cadr[ n ] read. the b1 regi ster updates remain 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 selected counter bus flag set event bbb a2 (captured) value 2 0xxxxxxx notes: 1. after input filter 2. emios_cadr[ n ] = a2 input signal 1 edpol = 1 a a b1 value 3 0x001525 0x001100 0xxxxxxx 0x001250 0x001000 0xxxxxxx 0x001000 0x001250 0x0016a0 b2 (captured) value 3. emios_cbdr[ n ] = b1 0xxxxxxx 0x001250 0x001000 a1 value 3
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-27 pxr40 microcontroller reference manual, rev. 1 locked until a emios_cbdr[ n ] read occurs. if a read of emios_cadr[ n ] is performed, b1 is updated with contents of a1 even if the b1 upda te is locked by a previous emios_cadr[ n ] read operation. figure 23-19. b1 and a1 updates at emios_cadr[ n ] and emios_cbdr[ n ] reads reading emios_cadr[ n ] followed by emios_cbdr[ n ] always provides cohere nt data. if coherent data is not required, the sequence of r eads should be invert ed, and emios_cbdr[ n ] should be read before emios_cadr[ n ]. even in this case, register b1 updates are blocked after emios_cadr[ n ] is read. therefore, a second emios_cbdr[ n ] read is required to rel ease the b1 register updates. 23.4.1.1.5 input period measurement (ipm) mode the ipm mode (mode = 000_0101) allows the measurement of the period of an input signal by capturing two consecutive rising edges or two consecutive falling edges. succe ssive input captur es are done on consecutive edges of the same polarity. the edge polarity is defined by the edpol bit in the emios_ccr[ n ] register. when the first edge of selected polarity is detected, th e selected time base is latched into the registers a2 and b2, and the data previously held in register b2 is transferred to re gister b1. on this first capture the flag line is not set and the values in registers b1 are meaningless. on the second and subsequent captures, the flag line is set and data in register b2 is transferred to register b1. when the second edge of the same polarity is detecte d, the counter bus value is latched into registers a2 and b2, and the data previously held in register b2 is transferred to da ta register b1 and to register a1. the flag bit is set to indicate that the start and end points of a complete period have been captured. this sequence of events is repeated for ea ch subsequent capture. the emios_cadr[ n ] and emios_cbdr[ n ] registers return the values in the a2 and b1 registers, respectively. to allow coherent data, reading emios_cadr[ n ] forces a1 content be tran sferred to b1 register and disables transfers between b2 and b1. these tran sfers are disabled until the next read of the 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 selected counter bus flag set event bbb a2 (captured) value 2 0xxxxxxx notes: 1 after input filter 2 emios_cadr[ n ] = a2 input signal 1 edpol = 1 a a b1 value 3 0x001525 0x001100 0xxxxxxx 0xxxxxxx 0x001000 0x001250 0x0016a0 0x001250 0x001000 b2 (captured) value 3 emios_cbdr[ n ] = b1 0xxxxxxx 0x001250 0x001000 a1 value 3 0x001000 read emios_cadr[ n ] read emios_cbdr[ n ]
enhanced modular input/output subsystem (emios200) 23-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 emios_cbdr[ n ] register. reading emios_cbdr[ n ] register forces a1 conten t to be transferred to b1 and re-enables transfers from b2 to b1, to take effect at the next edge capture. the input pulse period is calculated by subtracting the value in b1 from a2. figure 23-20 shows how the unified channel can be used for input period measurement. figure 23-20. ipm example figure 23-21 shows the a1 and b1 regist er updates when emios_cadr[ n ] and emios_cbdr[ n ] read operations are performed. when a emios_cadr[ n ] read occurs, the contents of a1 are transferred to b1, thus providing coherent data in th e a2 and b1 registers. transfers fro m b2 to b1 are then blocked until emios_cbdr[ n ] is read. after emios_cbdr[ n ] is read, the contents of re gister a1 are transferred to register b1 and the transfers from b2 to b1 are re-enabled to occur at the transfer edges, which is the leading edge in the figure 23-21 example. figure 23-21. a1 and b1 updates at emios_cadr[ n ] and emios_cbdr[ n ] reads selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 a1 value b2 (captured) value $0xxxxxxx 0x001000 0x001250 $0xxxxxxx 0x001000 0x001250 0x0016a0 $0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edpol = 1 flag pin register notes: 1. afte r input filter 2. emiosa[n] = a2 3. emiosb[n] = b1 a a a b1 value 3 $0xxxxxxx 0x001000 0x001250 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 selected counter bus flag set event aaa a2 (captured) value 2 0xxxxxxx notes: 1. after input filter 2. emios_cadr[ n ] = a2 input signal 1 edpol = 1 b1 value 3 0x001525 0xxxxxxx 0xxxxxxx 0x001000 0x001250 0x0016a0 b2 (captured) value 3. emios_cbdr[ n ] = b1 0xxxxxxx 0x001250 a1 value 0x001000 read emios_cadr[ n ] read emios_cbdr[ n ] 0x001100 0x001250 0x001000 0x001000 0x001250
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-29 pxr40 microcontroller reference manual, rev. 1 23.4.1.1.6 double action ou tput compare (daoc) mode in the daoc mode the leading and trailing edges of the variable pulse-width output are generated by matches occurring on comparators a and b, respectively. when the daoc mode is entered (coming out of gp io mode), both comparat ors are disabled and the output flip-flop is set to the compleme nt of the edpol bit in the emios_ccr[ n ] register data written to a2 and b2 are transf erred to a1 and b1, resp ectively, on the next syst em clock cycle if the ou[ n ] bit in emios_oudr re gister is cleared (see figure 23-24 ). the transfer is blocked if the ou[ n ] bit is set. comparator a is enabled only after the transf er to a1 register occurs, and is disabled on the next a match. comparator b is enabled only after the transfer to b1 register occurs, and is disabled on the next b match. comparators a and b are en abled and disabled independently. the output flip-flop is set to the value of edpol when a match occurs on comparator a and to the complement of edpol when a match occurs on comparator b. mode[6] controls if the flag bit is set on both matches or on the second match only (see table 23-9 for details). flag bit assertion de pends on comparator enabling. if subsequent enabled output compar es occur on registers a1 and b1, pulses continue to be generated, regardless of the state of the flag bit. at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a comparison event in comparator a or b, respectively. the flag b it is not affected by these forced operations. note if both a1 and b1 registers are loaded with the same value, the b match prevails concerning the output pin state. the output flip-flop is set to the complement of edpol, the flag bi t is set, and both comparators are disabled. figure 23-22 and figure 23-23 show how the unified channel can be used to generate a single output pulse with flag bit being set on the second ma tch or on both matches, respectively.
enhanced modular input/output subsystem (emios200) 23-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-22. daoc with flag set on the second match figure 23-23. daoc with flag set on both matches selected counter bus flag pin/register a1 match 0xxxxxxx 0x001000 0x001000 0x001000 notes: 1. emios_cadr[ n ] = a1 2. emios_cbdr[ n ] = b1 b1 match b1 match 0xxxxxxx 0x001100 0x001100 0x001100 a1 match update to a1 & b1 output flip-flop a1 value 1 b1 value 2 a2 = a1 according to ou[ n ] bit b2 = b1 according to ou[ n ] bit 0x000500 0x001000 0x001100 0x001000 0x001100 mode[6] = 0 selected counter bus flag pin/register a1 match 0xxxxxxx 0x001000 0x001000 0x001000 notes: 1. emios_cadr[ n ] = a1 2. emios_cbdr[ n ] = b1 b1 match b1 match 0xxxxxxx 0x001100 0x001100 0x001100 a1 match update to a1 & b1 output flip-flop a1 value 1 b1 value 2 a2 = a1 according to ou[ n ] bit b2 = b1 according to ou[ n ] bit 0x000500 0x001000 0x001100 0x001000 0x001100 mode[6] = 1
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-31 pxr40 microcontroller reference manual, rev. 1 figure 23-24. daoc with transfer disabling example 23.4.1.1.7 pulse/edge ac cumulation (pea) mode the pea mode returns the time taken to detect a de sired number of input events . the mode[6] bit selects between continuous or single-shot operation. after writing to register a1, the inte rnal counter is cleared on the first input event, ready to start counting input events, and the selected timeba se is latched into register b2. on the match between the internal counter and register a1, a c ounter bus capture is triggere d to register a2 and b2. the data previously held in register b2 is transferred to register b1 and the flag bit is set to indicate that an event has occurred. the desired time interval can be determined by subtracting register b1 from a2. registers emios_cadr[ n ] and emios_cbdr[ n ] return the values in register a2 and b1, respectively. as part of the coherency me chanism, reading emios_cadr[ n ] disables transfers fr om b2 to b1. these transfers are disabled until the next read of the emios_cbdr[ n ] register. reading the emios_cbdr[ n ] register re-enables transfers from b2 to b1, to take effect at the next transf er event, as previously described. 1 1. if b1 was not updated due to b2 to b1 transfer being disabled after reading register emios_cadr[ n ], further emios_cadr[ n ] and emios_cbdr[ n ] reads will not return coherent data until a ne w bus capture is triggered to registers a2 and b2. this capture event is indicated by the channel flag being asserted. if enabled, the flag also generates an interrupt. selected counter bus 0x000000 0x000002 flag set event a1 value 2 0xxxxxxx output flip-flop 2. emios_cadr[ n ] = a1 (when reading) 0x000000 0x000002 0x000001 0x000002 0x000000 0x000001 0x000001 flag pin/register flag clear edsel = 1 system clock enabled a1 match edpol = x b2 value 5 0x000002 b1 value 4 0xxxxxxx a2 value 3 0x000001 ou 1 enabled b1 match 0x000001 0xxxxxxx 0xxxxxxx 0x000002 0x000001 write to a2 0x000002 0x000002 0x000001 0x000002 0x000001 0x000001 0x000002 write to b2 write to a2 write to b2 write to a2 write tob2 mode[6] = 1 3. emios_cadr[ n ] = a2 (when writing) 4. emios_cbdr[ n ] = b1 (when reading) 5. emios_cbdr[ n ] = b2 (when writing) note: 1. ou[ n ] bit of emios_oudr register
enhanced modular input/output subsystem (emios200) 23-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 in order to have coherent data in continuous ope ration mode, the following steps should be performed, assuming the flag bit is initially cleared: 1. wait for flag assertion. 2. read the emios_cadr[ n ] register. 3. read the emios_cbdr[ n ] register. 4. clear the flag bit. 5. return to step #1. accumulation cycles may be lost if the read is not performed in a timely manner. whenever the overrun bit is asserted it means that one or more cycles have been lost. triggering of the counter clock (input event) is done by a rising or falling edge or both edges on the input pin. the polarity of the triggering edge is select ed by the edsel and edpol bits in emios_ccr[ n ] register. for continuous mode operation (m ode[6] cleared, mode[0:6] = 000_1000), the counter is cleared on the next input event after a flag generation and continues to operate as previously described. for single-shot operation (mode[ 6] set, mode[0:6] = 000_1001), the counter is not cleared or incremented after a flag generation until a new wr iting operation to regist er a (emios_cadr) is performed. figure 23-25 and figure 23-26 show how the unified channel can be used for continuous and single-shot pulse/edge accumulation mode. figure 23-25. pea continuous mode example 0xffffff 0x000000 emios_ccntr[ n ] 1 time a1 match write to a1 selected counter bus 0x000400 a1 value 3 0x001500 0xxxxxxx a2 value 4 0x000400 0xxxxxxx b1 value 0x000090 0xxxxxxx b2 value 5 0x001000 0xxxxxxx 0x001500 0x000090 0x000090 0x007000 0x001500 0x007000 0x001000 flag pin/register a1 match 0x001500 input signal 2 0x001000 a1 events a1 events no events events 0x000400 notes: 4. emios_cadr[ n ] = a2 (when reading) 5. emios_cbdr[ n ] = b1 3. emios_cadr[ n ] = a1 (when writing) 2. after input filter 1. cleared on the first input even t after writing to register a1 0x007000 mode[6] = 0
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-33 pxr40 microcontroller reference manual, rev. 1 figure 23-26. pea single-shot mode example 23.4.1.1.8 pulse/edge counting (pec) mode the pec mode returns the amount of pulses or edges detected on the i nput for a desired time window. the mode[6] bit selects between cont inuous or single-shot operation. triggering of the internal counter is done by a rising or falling edge or both edge s on the input signal. the polarity and the triggering edge is selected by edsel and edpol bits in the emios_ccr[ n ] register. register a1 holds the start time a nd register b1 holds the stop time for the time window. after writing to register a1, when a match occur betw een comparator a and th e selected timebase, th e internal counter is cleared and it is ready to start c ounting input events. when the time base matches comparator b, the internal counter is disabled and its content is transferred to regist er a2. at the same time the flag bit is set. reading registers emios_ccntr[ n ] or a2 returns the amount of detected pulses. for continuous operation (mode[6] cleared, mode[0:6] = 000_1010), the next match between comparator a and the se lected time base clears the internal counter and counting is enabled again. in order to guarantee coherent measuremen ts when reading emios_ccntr[ n ] after the flag is set, the software must check if the time base value is out of the time interval defined by register s a1 and b1. alternatively register a2 always holds the latest available measurement providing coherent data at any time after the first flag had occurred. this register is addressed by the alternate address emios_alta[ n ]. for single-shot operation (mode[6] set, mode[0:6] = 000_1011), the ne xt match between comparator a and the selected time base has no effect, until a ne w write to regist er a (emios_cadr) is performed. the emios_ccntr content is also tr ansferred to register a2 when a match in the b comparator occurs. figure 23-27 and figure 23-28 show how the unified channel can be used for continuous or single-shot pulse/edge counting mode. 0xffffff 0x000000 emios_ccntr[ n ] 1 time selected counter bus 0x000400 a1 value 3 0x001500 0xxxxxxx a2 value 4 0x000400 0xxxxxxx b1 value 0x000090 0xxxxxxx b2 value 5 0xxxxxxx 0x001500 0x000090 0x000090 flag pin/register 0x001500 input signal 2 a1 events notes: 4. emios_cadr[ n ] = a2 (when reading) 5. emios_cbdr[ n ] = b1 3. emios_cadr[ n ] = a1 (when writing) 2. after input filter events events 0x000400 1. cleared on the first input even t after writing to register a1 mode[6] = 1 a1 match write to a1
enhanced modular input/output subsystem (emios200) 23-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-27. pec continuous mode example figure 23-28. pec single-shot mode example amount of events detected 0x000000 emios_ccntr[ n ] time flag pin/register selected counter bus 0x000303 0x000090 0x000303 0x000090 a1 value 1 0x000090 0x000090 amount of events detected b1 value 2 0x000303 0x000303 0x000303 0x000090 notes: 1. emios_cadr[ n ] = a1 2. emios_cbdr[ n ] = b1 mode[6] = 0 3. emios_alta[ n ] = a2 a2 value 3 a2 ? emios_ccntr[ n ] a2 ? emios_ccntr[ n ] a1 match a1 & b1 b1 match b1 match a1 match write amount of events detected 0x000000 emios_ccntr[ n ] time flag pin/register selected counter bus 0x000303 0x000090 0x000303 0x000090 0x000090 0x000090 amount of events detected 0x000303 0x000303 0x000303 0x000090 mode[6] = 1 a2 ? emios_ccntr[ n ] a2 ? emios_ccntr[ n ] a1 & b1 write a1 match b1 match b1 match a1 match a1 value 1 b1 value 2 a2 value 3 notes: 1. emios_cadr[ n ] = a1 2. emios_cbdr[ n ] = b1 3. emios_alta[ n ] = a2
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-35 pxr40 microcontroller reference manual, rev. 1 23.4.1.1.9 quadratur e decode (qdec) mode qdec mode uses uc[ n ] operating in qdec mode and the i nput programmable fi lter (ipf) from uc[ n ? 1]. note that uc[ n ? 1] can be configured, at the same ti me, to an operation mode that does not use i/o pins, such as modulus count er mode (mc). the connection among th e unified channels is circular, i.e., when uc[0] is running in qdec mode, the input programmable filter from uc[31] is being used. this mode generates a flag every time the internal counter matches a1 register . the internal counter is automatically selected and is not cleared when entering this mode. mode[6] bit selects which t ype of encoder is used: count & direction encoder or phase_a & phase_b encoder. when operating with count & direction encoder (mode[6] cleared), the uc[ n ] input pin must be connected to the direction signal and the uc[ n ? 1] input pin must be connected to the count signal of the quadrature encoder. the edpol bit for uc[ n ] selects the count dir ection according to the direction signal and the edpol bit for uc[ n ? 1] selects whether the internal counter is clocked by the rising or falling edge of the count signal. when operating with phase_a & phase_b encoder (mode[6] set), the uc[ n ] input pin must be connected to the phase_a signal and the uc[ n ? 1] input pin must be connected to the phase_b signal of the quadrature encoder. the ed pol bit selects the count direction according to th e phase difference between phase_a & phase_b signals. figure 23-29 and figure 23-30 show two unified channels configur ed to quadrature decode mode for count & direction encoder and phase_a & phase_b encoders, respectively. figure 23-29. qdec mode example with count & direction encoder note: emios_cadr[ n ] ? a1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 ?1 ?1 ?1 ?1 emios_ccntr[ n ] inc/dec direction (from uc[ n ]) count (from uc[ n ?1]) 0x000000 emios_ccntr[ n ] time flag pin/register value 1 mode[6] = 0 edpol = 1 + 1 a1 write (value 1) a1 match a1 match ?1
enhanced modular input/output subsystem (emios200) 23-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-30. qdec example with phase_a & phase_b encoder 23.4.1.1.10 windowed programmable time accumulation (wpta) mode the wpta mode (mode = 000_1110) accumulates the sum of the total high time or low time of an input signal over a programmable interval (time window). the ucpre[1:0] prescaler bits in the emios_ccr[ n ] register define the increment rate of the internal counter. register a1 holds the start time and register b1 hol ds the stop time of the pr ogrammable time interval. when a match occurs between regist er a (emios_cadr) and the selected timebase, the internal counter is cleared and it is ready to start counting. the internal counter is used as a time accumulator, i.e., it counts up when the input signal has the same pola rity of the edpol bit in the emios_ccr[ n ] register and does not count otherwise. when a match occu rs in comparator b, the internal counter is disabled regardless of the input signal polarity a nd the flag bit is set. at the same time, the contents of the emios_ccntr[ n ] register is transferred to register a2. reading registers emios_ccntr[ n ] or a2 returns the high or low time of the input signal. note that emios_ccntr[ n ] is stable only outside the time wind ow defined from a1 to b1 matches. otherwise, its contents reflect a count in progress and not the final value. alternatively to emios_ccntr[ n ], register a2 returns the latest available measurement. since this register is updated only at comparator b matches, it always contains stable and up-to-date data. in this mode, this register is accessible through the alternate register address emios_alta[ n ]. figure 23-31 shows how the unified channel can be used to accumulate high time. note: emios_cadr[ n ]=a1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 ?1 ?1 ?1 ?1 ?1 + 1 + 1 + 1 + 1 + 1 + 1 ?1 emios_ccntr[ n ] phase a (from uc[ n ]) phase b (from uc[ n ?1]) 0x000000 emios_ccntr[ n ] time flag pin/register value 2 value 1 ?1 + 1 + 1 ?1 ?1 ?1 ?1 ?1 + 1 + 1 + 1 + 1 + 1 + 1 ?1 ?1 + 1 mode[6] = 1 a1 write (value 1) a1 match a1 match a1 match a1 match a1 match a1 write (value 2) inc/dec
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-37 pxr40 microcontroller reference manual, rev. 1 figure 23-31. wtpa example 23.4.1.1.11 modulus counter (mc) mode the mc mode can be used to provide a time base for a counter bus or as a general purpose timer. the mode[6] bit selects the internal or external clock source when clea red or set, respectively. when the external clock is selected, the input signal pin is used as the source and the triggering polarity edge is selected by the edpol and edsel bits in the emios_ccr[ n ] register. the internal counter counts up from th e current value until it matches the value in regi ster a1. register b1 is cleared and is not accessible to the mcu. the mode[4] bit selects up mode or up/down mode, when cleared or set, respectively. when in up count mode, a match betw een the internal counter and regist er a1 sets the flag and clears the internal counter. the timing of those events va ries according to the mc mode setup as follows: ? internal counter cleari ng on match start (mode = 001_000b) ? when mode[6] is set, the external clock is selected. in this case, the internal counter clears as soon as the match signal occurs. the channel flag bit is set at the same time the match occurs. note that by having the internal counter cleare d as soon as the match occurs and incremented at the next input event, a shor ter zero count is generated. see figure 23-61 and figure 23-63 . ? when mode[6] is cleared, the internal clock source is selected. in this case, the counter clears as soon as the match signal occu rs. the channel flag bit is se t at the same time the match occurs. at the next prescaler ti ck after the match, the internal counter remains at 0 and only resumes counting on the following tick. see figure 23-61 and figure 23-64 . ? internal counter clearing on match end (mode = 001_001b) 0xffffff 0x000000 time accumulator selected counter bus 0x001500 a1 value 2 0x001500 0x000100 0x000100 input signal 1 0x004200 0x003000 b1 value 3 0x001500 0x004200 0x000100 0x003000 0x004200 flag pin/register notes: 1. after the input filter edpol = 1 2. emios_cadr[ n ] = a1 3. emios_cbdr[ n ] = b1 0x003000 a2 value 4 a2 emios_ccntr[ n ] 4. emios_alta[ n ] = a2 a2 emios_ccntr[ n ] (emios_ccntr[ n ]) a1 & b1 write a1 match a1 & b1 write b1 match b1 match a1 match time
enhanced modular input/output subsystem (emios200) 23-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? when mode[6] is set, the external clock is sel ected. in this case, the internal counter clears when the match signal is asserted and the input event occurs. the channel flag bit is set at the same time the c ounter is cleared. see figure 23-61 and figure 23-65 . ? when mode[6] is cleared, the internal clock s ource is selected. in this case, the internal counter clears when the match signal is asserted and the prescaler tick occurs. the channel flag bit is set at the same time the counter is cleared. see figure 23-61 and figure 23-65 . note if the internal clock source is select ed and the prescaler of the internal counter is set to 1, the mc mode be haves the same way even in clear on match start or clear on match end sub-modes. when in up/down count mode (mod e = 001_01bb), a match between the inte rnal counter and register a1 sets the flag and changes the counter direction from increm ent to decrement. a ma tch between register b1 and the internal counter changes the counter dire ction from decrement to in crement and sets the flag only if mode[5] bit is set. only values other than 0x00_0000 must be written into regist er a (emios_cadr). loading 0x00_0000 leads to unpredictable results. updates on register a (emios_cadr) or the counter in mc mode may cause a loss of match in the current cycle if the transfer occurs near the match. in this case, the counter may roll over and resume operation in the next cycle. figure 23-32 and figure 23-33 show how the unified cha nnel can be used as a modul us counter in up mode and up/down mode, respectively. figure 23-32. mc up mode example 0xffffff 0x000303 0x000000 emios_ccntr[ n ] time a1 value 1 0x000303 0x000303 0x000200 0x000200 0xxxxxxx flag pin/register notes: 1. emios_cadr[ n ] = a1 0x000303 0x000200 a2 = a1 according to ou[ n ] bit mode[4] = 0 write to a2 a1 match write to a2 a1 match a1 a1 match match
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-39 pxr40 microcontroller reference manual, rev. 1 figure 23-33. mc up/down mode example 23.4.1.1.12 modulus counter buffered (mcb) mode the mcb mode provides a time base that can be shared with other channels through th e internal counter buses. register a1 is double-buffered, thus allowi ng smooth transitions betwee n cycles when changing the a2 register value on the fly. register a1 is upda ted at the cycle boundary, which is defined as when the internal counter reaches the value 0x00_0001. the internal counter values operate within a range from 0x00_0001 up to the value of register a1 in mcb mode. when entering mcb mode (comi ng out of gpio mode), the internal counter value must be within that range. otherwise, the first a ma tch will not occur, causing the channe l internal counter to wrap at the maximum counter value of 0xff_ffff. after the c ounter wrap occurs, it returns to 0x00_0001 and resumes normal mcb mode operation. to avoid this counter wrap condition, make sure the internal counter value is within the 0x00_0001 to a1 register value range when entering the mcb mode. mode[6] bit selects the internal clock source if set to 0, or external if set to 1. when the external clock is selected, the input channel pi n is used as the channel cl ock source. the active edge of this clock is defined by the edpol and edsel bits in the emios_ccr[ n ] channel register. when entering mcb mode, if the up counter is sele cted by mode[4] = 0, the internal counter starts counting up from its current va lue until the a1 match occurs. on the next system clock cycle after the a1 match, the internal counter is set to 0x00_0001 and the flag bit is set to '1'. if the up/down counter is selected by setting mode[4] = 1, the counter ch anges direction at the a1 match and counts down until it reaches 0x00_0001. after it reaches 0x00_0001, it count s up again. register b1 is set to 0x00_0001 on entering mcb mode cannot be changed while this mode is selected. b1 is used to generate a match to set the internal counter in up-count direction if up/ down mode is selected. the mcb mode counts between 0x00_0001 and the value in the a1 register. only values greater than 0x00_0001 are allowed to be written to the a1 regist er. loading values other than those leads to unpredictable results. the counter cycle period is equal to a1 value in up counter mode. if in up/down counter mode the peri od is defined by the expression: (2 a1) ? 2. figure 23-34 shows the counter cycle for severa l a1 values. register a1 is lo aded with the value in a2 at the cycle boundary. any value written to the a2 register within cycle ( n ) is updated to a1 at the next cycle 0xffffff 0x000303 0x000000 emios_ccntr[ n ] time a1 value 1 0x000303 0x000303 0x000200 0x000200 0xxxxxxx notes: 1. emios_cadr[ n ] = a1 0x000200 0x000200 flag pin/register a2 = a1 according to ou[ n ] bit mode[4] = 1 write to a2 a1 match write to a2 b1 match (= 0) b1 match (= 0) a1 match
enhanced modular input/output subsystem (emios200) 23-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 boundary and therefore is used on cycle ( n + 1). the cycle boundary between cycle ( n ) and cycle ( n +1) is defined as the first syst em clock cycle of cycle ( n + 1). the flags are generated as soon as the a1 match occurs. figure 23-34. modulus counter buffered (mcb) up count mode figure 23-35 shows the mcb in up/down counter mode. regist er a1 is updated at the cycle boundary. if a2 is written in cycle ( n ), this new value is used in cycle ( n + 1) for an a1 match. when mode[5] is cleared, flags are generated only on an a1 match. if mo de[5] is set to 1, flags are also generated at the cycle boundary. figure 23-35. mcb up/down mode figure 23-36 shows the a1 register update pr ocess in up counter mode. the a1 load signal is generated at the last system clock period of a counter cycle. emios_ccntr[ n ] time write to a2 a1 match a1 match a1 match write to a2 0x000001 0x000005 0x000006 0x000007 prescaler ratio = 1 cycle n cycle n +1 cycle n +2 flag set event a1 value 0x000006 0x000005 0x000007 0x000007 0x000005 0x000007 a2 value flag pin/register flag clear emios_ccntr[ n ] time write to a2 a1 match a1 match write to a2 0x000001 0x000005 0x000006 0x000007 0x000005 0x000007 a2 value a1 value 0x000006 0x000005 0x000007 flag set event flag pin/register prescaler ratio = 1 flag clear cycle n cycle n +1 cycle n +2
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-41 pxr40 microcontroller reference manual, rev. 1 the a1 load signal is generated based on the detect ion of the internal counter reaching 0x00_0001 and has the duration of one system clock cycle. during the load pulse, a1 still holds its prev ious value. it is updated at the second system clock cy cle only. thus, a1 is updated with a2 va lue at the same time that the counter (emios_ccntr[ n ]) is loaded with 0x00_0001. the load signa l pulse has the duration of one system clock period. if a2 is written within cycle ( n ), its value is available at a1 at the first clock of cycle ( n +1) and the new value is used for match at cycle ( n + 1). the update disable bits ou[ n ] of the emios_oudr register can be used to control the update of this register, thus allowing the a1 register update to be delayed for synchronization purposes. figure 23-36. mcb mode a1 register update in up counter mode figure 23-37 shows the a1 register update in up/down counter mode. note th at a2 can be written at any time within cycle ( n ) in order to be used in cycle ( n + 1). thus a1 receives this new value at the next cycle boundary. the update disable bits (ou[ n ] in emios_oudr) can be used to disable the update of a1 register. figure 23-37. mcb mode a1 register update in up/down counter mode a1 value 0x000008 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000008 0x000004 0x000006 0x000002 0x000004 0x000006 write to a2 a1 load signal 8 4 6 counter = a1 time cycle n cycle n +1 cycle n +2 a1 match a1 match a1 match write to a2 1 prescaler ratio = 2 emios_ccntr[ n ] time write to a2 a1 match a1 match write to a2 0x000001 0x000005 0x000006 0x000005 a2 value a1 value 0x000006 0x000005 selected counter = 2 a1 load signal 0x000006 0x000006 0x000006 cycle n cycle n +1 cycle n +2 prescaler ratio = 2
enhanced modular input/output subsystem (emios200) 23-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.4.1.1.13 output pulse width and frequency modulation (opwfm) mode in the opwfm mode, the duty cycle of the output signal is the value defi ned in register a1 plus 0x1, and the period is the value defined in re gister b1 plus 0x1. mode[6 ] bit controls the transf er from register b2 to b1, which can be done either immediately (mode[6] cleared, mode = 00110b0), providing the fastest change in the duty cycle, or at every match of register a1 (mode[6] set, mode = 00110b1). when opwfm mode is entered, co ming out from gpio mode, the out put flip-flop is set to the complement of the edpol bit in the emios_ccr[ n ] register. the internal counter is automatically selected as a time base, therefore the bsl[1:0] bits in register emios_ccr[ n ] have no meaning. when a match on comparator a occurs, the output flip-flop is set to the value of the edpol bit. when a match occurs on comparator b, the output flip-flop is set to the complement of the edpol bit and the internal counter is cleared. flag can be generated at match b, when mode[5] is cleared, or in both matches, when mode[5] is set. at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a or b respectively. als o, forcmb clears the internal counter. note that the flag bit is not set by the forcma or forcmb operations. if subsequent comparisons occur on comparators a and b, the pwfm pulses continue to be output, regardless of the state of the flag bit. in order to achieve 100% duty cycle, both registers a1 and b1 must be set to the same value. when a simultaneous match occurs on comparat ors a and b, the output flip-flop is set to the value of edpol bit. 0% duty cycle is possible by writi ng 0x0 to register a (emios_cadr). when a match occurs, the output flip-flop is set at every period to the complement of edpol bit. the transfer from register b2 to b1 is still controlled by mode[6] bit. note writing 0x0 to a1 and b1 produces a duty cycle of 0%. figure 23-38 shows the unified channel running in opwfm mode with immediate register update and figure 23-39 shows the unified channel running in opwfm mode with next period update.
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-43 pxr40 microcontroller reference manual, rev. 1 figure 23-38. opwfm with immediate update figure 23-39. opwfm with next period update 23.4.1.1.14 output pulse-width and freque ncy modulation buffered (opwfmb) mode the opwfmb mode provides waveforms with variab le duty cycle and frequenc y. the internal channel counter is automatically selected as the time base when this mode is selected. the a1 register indicates the duty cycle and the b1 register i ndicates the frequency. both a1 and b1 registers are double-buffered to allow smooth signal generation when changing the regist ers values on the fly. this mode supports 0% and 100% duty cycles. 0x001000 0x000000 time output flip-flop a1 value 1 b1 value b2 value 2 0x000900 0x000900 0x001000 0x001000 0x000200 0x000900 notes: 1. emios_cadr[ n ]=a1 0x000200 0x001000 0x000900 0x000200 mode[6] = 0 emios_ccntr[ n ] a1 match a2 & b2 write b1 match b1 match a1 match b2 write 0x000200 2. emios_cbdr[ n ]=b2 a2 = a1according to ou[ n ] bit b2 = b1according to ou[ n ] bit internal counter 0x000900 0xxxxxxx 0x001000 0x000200 0x001000 0x000900 0x000200 0x001000 0x000200 0x001000 0x000200 0x000900 0x001000 0x000000 time output flip-flop a1 value 1 b1 value b2 value 2 0x000900 notes: 1. emios_cadr[ n ]=a1 mode[6] = 1 a1 match a2 & b2 write b1 match b2 write 0x000200 2. emios_cbdr[ n ]=b2 a2 = a1according to ou[ n ] bit b2 = b1according to ou[ n ] bit a1 match a1 match b1 match b1 match
enhanced modular input/output subsystem (emios200) 23-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 at opwfmb mode entry, the output flip-flop is set to the value of the edpol bit in the emios_ccr[ n ] register. to provide smooth and consistent channel operation, this mode differs substantially from the opwfm mode. the main differences reside in the a1 and b1 registers update, on the delay from the a1 match to the output pin transition, and on the internal counter values, which range from 0x00_0001 up to the value in register b1. when entering opwfmb mode (coming out of gpio mode), if the in ternal counter value is not within that range, then the b match will not occur, causing the channel internal counter to wrap at the maximum counter value which is 0xff_ffff. after the counter wrap o ccurs, the value returns to 0x00_0001 and the counter resumes normal opwfmb mode operation. thus in order to avoid the counter wrap condition, make sure its initial value is within the range between 0x00_0001 and the b1 register value the opwfmb mode is entered. when a match on comparator a occurs, the output regist er is set to the value of edpol. when a match on comparator b occurs, the output regi ster is set to the complement of edpol. b1 match also causes the internal counter to transition to 0x00_0001, thus restarting the counter cycle. only values greater than 0x00_0001 are al lowed to be written to the b1 re gister. loading values other than those leads to unpr edictable results. figure 23-40 shows the operation of the opwfmb mode regarding output pin transitions and a1/b1 registers match events. the output pin transition occurs when the a1 or b1 match signal is deasserted, which is indicated by the a1 match negative edge detection signal. if register a1 is set to 0x00_0004, the output pin transitions four counter pe riods after the cycle has started, plus one system clock cycle. in the example shown in figure 23-40 the internal counter prescaler has a ratio of two. figure 23-40. opwfmb a1 and b1 match to output register delay 8 1 4 a1 match 5 a1 value 0x000004 a1 match a1 match negative edge detection output pin emios_ccntr[ n ] time b1 match b1 match b1 match negative edge detection b1 value 0x000008 system clock prescaler negative edge detection negative edge detection edpol = 0 prescaler ratio = 2
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-45 pxr40 microcontroller reference manual, rev. 1 figure 23-41 shows the generated output signal if a1 is se t to 0x0. because the c ounter does not reach 0 in this mode, the channel internal logic infers a match as if a1 = 0x00_0001 wi th the difference that in this case, the positive edge of the match signal is used to trigger the output pin transition inst ead of the negative edge used when a1 = 0x00_0001. an a1 positi ve edge match signal from cycle ( n + 1) occurs at the same time as b1 negative edge match signal from cycle ( n ). this allows using the a1 positive edge match to mask the b1 negative edge match when they occur at the same time. the result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. figure 23-41. opwfmb mode with a1 = 0 (0% duty cycle) figure 23-42 shows the timing for the a1 and b1 registers load. the a1 and b1 load use the same signal which is generated at the last sy stem clock period of a counter cy cle. thus, a1 and b1 are updated respectively with a2 and b2 values at the same time that the emios_ccntr[ n ] counter is loaded with 0x00_0001. this event is defined as the cycle boundary. the load signal pulse has the duration of one system clock period. if a2 and b2 are written within cycle ( n ), their values are loaded into a1 and b1, respectively, at the fi rst clock of cycle ( n + 1) and the new values are us ed for matches at cycle ( n +1). the update disable bits (ou[ n ] in emios_oudr) can be used to contro l the update of these registers, thus allowing to delay the a1 and b1 regi sters update for synchronization purposes. in figure 23-42 , it is assumed that both th e channel and global prescalers are set to 0x00_0001 (each divide ratio is two), meaning that the cha nnel internal counter transitions at every four system clock cycles. flags can be generated only on b1 matches when m ode[5] is cleared, or on ei ther a1 or b1 matches when mode[5] is set. because the b1 flag occurs at the cycle boundary, th is flag can be used to indicate that a2 or b2 data written on cycle ( n ) were loaded to a1 or b1, respect ively, thus generating matches in 1 4 5 a1 value 0x000004 a1 match a1 match negative edge detection output pin emios_ccntr time b1 match negative edge detection b1 match b1 match negative edge detection b1 value 0x000008 system clock prescaler a2 value 0x000000 0x000000 a1 match positive edge detection a1 match positive edge detection no transition at this point 1 cycle n cycle n +1 a1 match negative edge detection edpol = 0 write to a2 prescaler ratio = 2
enhanced modular input/output subsystem (emios200) 23-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 cycle ( n + 1). note that the flag has a synchronous opera tion, meaning that it is asserted one system clock cycle after the flag set event. figure 23-42. opwfmb a1 and b1 registers update and flags figure 23-43 shows the operation of the out put disable feature in opwfmb mode. in contrast to the opwfm mode, the output disable forces the channel output flip-flop to th e value of the edpol bit. this functionality targets applications th at use active-high signals and a high- to-low transition at a1 match. in this case, edpol should be set to 0. note that both the channel and global prescalers are set to 0x00_0000 (each divide ratio is one), meaning th at the channel internal counter tran sitions at every sy stem clock cycle. flag pin/register cycle n cycle (n +1) cycle ( n +2) a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 match a1 match b1 match b1 due to b1 match flag set event cycle (n ?1) time write to a2 match a1 write to a2 match b1 mode[6] = 1 edpol = 0 prescaler ratio = 4 a1/b1 load signal flag clear
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-47 pxr40 microcontroller reference manual, rev. 1 figure 23-43. opwfmb mode with active output disable the output disable has a synchronous operation, meaning that the asserti on of the output disable input pin causes the channel output flip-flop to transition to edpol at the next system clock cycle. if the output disable input is deasserted the output pin tr ansition at the following a1 or b1 match. in figure 23-43 it is assumed that the output disable input is enabled and selected for the channel. refer to section 23.3.2.7, emios200 control register (emios_ccr[n]), for a description of how the odis and odissl bits enable and se lect the output disable inputs. the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on comparators a or b, re spectively. similar to a b1 match, forcmb sets the internal counter to 0x00_0001. the flag bit is not set by the forcma or forcmb bits being asserted. figure 23-44 shows the generation of 100% and 0% duty cycle signals. it is assumed edpol = 0 and the resultant prescaler value is 1. initially, a1 = 0x00_0008 and b1 = 0x00_0008. in this case, the b1 match has precedence over the a1 ma tch, thus the output flip-flop is set to the complement of edpol bit. this cycle corresponds to a 100% duty cycle signal. the same output signal can be gene rated for any a1 value greater or equal to b1. write to b2 match a1 match b1 match b1 time write to a2 write to a2 cycle n cycle ( n +1) cycle ( n +2) a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin due to b1 match cycle ( n ?1) flag set event output disable flag pin/register flag set event mode[6] = 1 edpol = 0 prescaler ratio = 1 match a1 match b1
enhanced modular input/output subsystem (emios200) 23-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-44. opwfmb mode from 100% to 0% duty cycle a 0% duty cycle signal is generated if a1 = 0x00_0000 as shown in cycle 9 in figure 23-44 . in this case, the b1 = 0x00_0008 match from cycle 8 occurs at the same time as the a1 = 0x00_0000 match from cycle 9. refer to figure 23-41 for a description of the a1 and b1 match generation. in this case, the a1 match has precedence over the b1 match and the output signal transitions to edpol. 23.4.1.1.15 center aligned ou tput pulse width modulati on with dead time (opwmc) mode the opwmc mode generates a center aligned pwm with dead time insertion in the leading (mode = 001_11b1) or trailing edge (mode = 001_11b0). the selected counter bus must be runni ng an up/down time ba se, as shown in figure 23-33 . bsl[1:0] bits select the time base. register a1 contains the ideal duty cycle for th e pwm signal and is compared with the selected time base. register b1 contains the dead time value and is compared with the internal counter. for a leading-edge dead time inse rtion, the output pwm duty cycle is equal to the difference between register a1 and register b1, and for a trailing edge dead time insertion, the output pwm duty cycle is equal to the sum of register a1 and register b1. mode[6 ] bit selects between traili ng and leading dead time insertion. note the internal counter may be running in the internal prescaler ratio, while the selected time base may be runni ng in a different prescaler ratio. the output signal may produce an unexpected out put if the dead time interval is greater than the duty cycle of the pwm signal. when opwmc mode is entered, coming out from gp io mode, the output flip-flop is set to the complement of the edpol bit in the emios_ccr[ n ] register. when operating with leading edge dead time inserti on, the first match between a1 and the selected time base clears the internal counter a nd switches the selected t ime base to the internal counter. when a match occurs between register b1 and the selected time base , the output flip-flop is set to the value of the edpol bit and the time base is switched to the selected co unter bus. in the next match between register a1 and the selected time base, the output flip-flop is set to the complement of the edpol bit. this sequence repeats continuously. 0x000008 0x000007 0x000006 0x000005 0x000 004 0x000003 0x000002 0x000001 0x000000 0% 100% emios_ccntr[ n ] edpol = 0 a1 value b1 value output pin 0x000008 prescaler = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 0x000007 0x000006 0x000005 0x000004 0 x000003 0x000002 0x000001 0x000000 a2 value time
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-49 pxr40 microcontroller reference manual, rev. 1 when operating with trailing edge dead time inserti on, the first match between a1 and the selected time base sets the output flip-fl op to the value of the edpol bit. in the next match be tween register a1 and the selected time base, the internal counter is cleared and the selected time base is switched to the internal counter. when a match occurs between register b1 and the selected time base, the output flip -flop is set to the complement of the edpol bit and the time base is switched to the selected counter bus. this sequence repeats continuously. flag can be generated in the trailing edge of th e output pwm signal when m ode[5] is cleared, or in both edges, when mode[5] is set. at any time, the forcma or forcmb bits are equiva lent to a successful comparison on comparator a or b with the exception that the flag bit is not set. note when in freeze state, the forcma or forcmb bits only allow the software to force the output flip-fl op to the level corresponding of a match on a or b respectively. if subsequent matches occur on comparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. in order to achieve a duty cycle of 100%, both registers a1 and b1 must be set to the same value. when a simultaneous match occurs between th e selected time base and registers a1 and b1, the output flip-flop is set to the value of edpol bit and th e selected time base swit ches to the selected counter bus, allowing a new cycle to begin at an y time, as previously described. 0% duty cycle is possible by writing 0x00_0000 to register a (emios_cadr). when a match occurs, the output flip-flop is set to the complement of edpol bit and the selected time base switches to th e selected counter bus, allowing a new cycle to begin at any time, as previously described. in both cases , flag is generated rega rdless of the mode[6] bit. note if a1 and b1 are set to 0x00_0000, a 0% duty cycle waveform is produced. figure 23-45 and figure 23-46 show the unified channel running in opwmc with leading and trailing dead time, respectively.
enhanced modular input/output subsystem (emios200) 23-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-45. opwmc with leading dead time insertion figure 23-46. opwmc with trailing dead time insertion 0x000303 0x000000 selected counter bus time a1 value 1 0x000303 0x000303 0x000200 0x000200 0xxxxxxx 0x000200 output flip-flop notes: 1. emios_cadr[ n ] = a1 2. emios_cbdr[ n ] = b1 0x000303 0x000200 0x000000 internal counter time 0x000010 0x000010 b1 value 2 a2 = a1 according to ou[ n ] bit b2 = b1 according to ou[ n ] bit mode[0] = 1 match a1 update b1 match b1 match b1 match a1 match a1 match a1 update a1 update a1 output flip-flop 0x000000 internal counter 0x000010 b1 value 2 0x000010 time 0x000303 0x000000 selected counter bus time a1 value 1 0x000303 0x000303 0x000200 0x000200 0xxxxxxx 0x000200 0x000303 0x000200 match a1 match a1 match a1 match a1 update a1 update a1 mode[0] = 1 notes: 1. emios_cadr[ n ] = a1 2. emios_cbdr[ n ] = b1 a2 = a1 according to ou[ n ] bit b2 = b1 according to ou[ n ] bit match b1 match b1 update b1
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-51 pxr40 microcontroller reference manual, rev. 1 23.4.1.1.16 center-aligned ou tput pwm buffered with dead time (opwmcb) mode the opwmcb mode generates a center- aligned pwm with dead time insertion to the leading or trailing edge. a1 and b1 registers are do uble-buffered to allow smooth output signal generation when changing a2 or b2 registers values on the fly. the bsl bits select the time base. the time base se lected for a channel configured to opwmcb mode should be a channel configured to mcb up/down mode, as shown in figure 23-35 . it is recommended to start the mcb channel time base af ter the opwmcb mode is entered in order to avoid missing a matches at the very first duty cycle. register a1 contains the ideal duty cycle for the pwm signal and is compar ed with the selected time base. register b1 contains the dead time value and is compared against the internal counter. for a leading edge dead time insertion, the output pwm duty cycle is equal to the difference between register a1 and register b1. for a trailing edge dead time in sertion, the output pwm duty cycle is equal to the sum of register a1 and register b1. mode[6] se lects between trailing and l eading dead time insertion. note the internal counter runs in the intern al prescaler ratio, while the selected time base may be running in a different prescaler ratio. when opwmcb mode is entered (coming out of gpio mode), the output flip-flop is set to the complement of the edpol bit in the emios_ccr[ n ] register. the following basic steps summari ze proper opwmcb start up, assuming the channels are initially in gpio mode: 1. [global] disable global prescaler. 2. [mcb channel] disable channel prescaler. 3. [mcb channel] write $1 at internal counter. 4. [mcb channel] set a register. 5. [mcb channel] set channel to mcb up mode. 6. [mcb channel] set prescaler ratio. 7. [mcb channel] enable channel prescaler. 8. [opwmcb channel] disable channel prescaler. 9. [opwmcb channel] set a register. 10. [opwmcb channel] set b register. 11. [opwmcb channel] select time base input through bsl[1:0] bits. 12. [opwmcb channel] enter opwmcb mode. 13. [opwmcb channel] set prescaler ratio. 14. [opwmcb channel] enable channel prescaler. 15. [global] enable global prescaler. figure 23-47 shows the load of a1 and b1 registers, which occurs when the selected counter bus transitions from 0x00_0002 to 0x00_0001. this event defines the cycle boundary. values written to a2 or
enhanced modular input/output subsystem (emios200) 23-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 b2 within cycle ( n ) are loaded into a1 or b1 registers, respect ively, and used to generate matches in cycle ( n +1). figure 23-47. opwmcb a1 and b1 registers load the (ou[ n ] in emios_oudr) bit can be used to disabl e the a1 and b1 updates, thus allowing to synchronize the load on these registers with the load of a1 or b1 registers in others channels. using the update disable bit, a1 and b1 registers can be upda ted at the same counter cy cle, allowing both registers to change at the same time. in this mode a1 matches always sets the internal counter to 0x00_0001. when operating with leading edge dead time insertion the first a1 match sets th e internal counter to 0x00_0001. when a match occurs between register b1 and the internal time base, the output flip-flop is set to the value of the edpol bit. in the following match between register a1 and the selected time base, th e output flip-flop is set to the complement of the edpol bit. this sequence repeats continuously. the internal counter should not reach 0x00_0000 as consequence of a rollover. to avoid this, the user must not write a value greater than twice the difference between external count up limit and emios_cadr[ n ] value to the emios_cbdr[ n ] register. figure 23-48 shows two cycles of a center-aligned pwm si gnal. both a1 and b1 register values are changing within the same cycle, which allows to vary at the same time the duty cycle and dead time values. selected time write to a2 write to b2 write to b2 write to a2 0x000001 0x000005 0x000006 0x000015 a1 value a2 value 0x000020 0x000015 selected counter = 2 a1/b1 load signal 0x000020 0x000016 0x000016 cycle n cycle ( n + 1) cycle ( n +2) b1 value 0x000004 b2 value 0x000004 0x000006 0x000005 0x000005 0x000006 counter bus prescaler ratio = 2
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-53 pxr40 microcontroller reference manual, rev. 1 figure 23-48. opwmcb with leading dead time insertion when operating with trailing edge dead time inserti on, the first match between a1 and the selected time base sets the output flip-f lop to the value of the edpol bit and sets the in ternal counter to 0x00_0001. in the second match between register a1 and the selected time base, th e internal counter is set to 0x00_0001 and b1 matches are enabled. when th e match between register b1 and th e selected time base occurs, the output flip-flop is set to the complement of th e edpol bit. this sequence repeats continuously. edpol = 1 internal internal counter is dead time a1 value a2 value b1 value b2 value selected 0x000002 0x000004 0x000002 0x000004 0x000015 0x000015 0x000013 0x000013 0x000001 0x000002 0x000004 0x000015 0x000013 0x000020 output flip-flop flag pin/register 0x000001 counter bus time time time base dead time set to 0x00_0001 on a1 match write to b2 write to a2
enhanced modular input/output subsystem (emios200) 23-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-49. opwmcb with trailing dead time insertion flag can be generated in the trailing edge of th e output pwm signal when m ode[5] is cleared, or in both edges when mode[5] is set. if subsequent matches occur on comparator s a and b, the pwm pulses continue to be generated regardle ss of the state of the flag bit. note in opwmcb mode, forcma and forcmb do not have the same behavior as a regular match. instead they force the output flip-flop to constant value, which depends on the selected dead time insertion mode, leading or trailing, and the value of the edpol bit. forcma has different behaviors depending on the selected dead time insertion mode , leading or trail. in leading dead time insertion, forcma forces a trans ition in the output flip-flop to the opposite of the edpol bit. in trailing dead time in sertion, the output flip-flop is for ced to the value of the edpol bit. if the forcmb bit is set, the output flip-flop value depends on the select ed dead time insertion mode. in leading dead time insertion, forcmb fo rces the output flip-flop to transi tion to the edpol bit value. in trailing dead time insertion the output flip-flop is for ced to the opposite of the edpol bit value. note the forcma bit set does not set the internal time-base to 0x00_0001 as a regular a1 match. edpol = 1 internal internal counter is dead time a1 value a2 value b1 value b2 value selected 0x000002 0x000004 0x000002 0x000004 0x000015 0x000015 0x000013 0x000013 0x000001 0x000002 0x000004 0x000015 0x000013 0x000020 output flip-flop flag pin/register 0x000001 counter bus time time time base dead time set to 1 on a1 match write to b2 write to a2
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-55 pxr40 microcontroller reference manual, rev. 1 the flag bit is not set either in cas e of forcma or forcmb, even if both forces ar e issued at the same time. note forcma and forcmb have the same be havior even in freeze or normal mode regarding the output pin transition. when forcma is issued along with forcmb, the output flip-flop is set to the opposite of the edpol bit value. this is the equivalent of saying that forcma has precedence over forcmb when leading dead time insertion is selected, and forcmb has precedence over forcma when trailing dead time insertion is selected. duty cycles from 0% to 100% can be generated by se tting appropriate values to the a1 and b1 registers relative to the period of the external time base. setting a1 = 0x00_0001 generates a 100% duty cycle waveform. if a1 is greater than the maximum value of the selected counter bus period, then a 0% duty cycle is produced. assuming edpol is set to 1 in opwmcb mode with trailing dead time insertion, 100% duty cycle signals can be genera ted if b1 occurs at or after th e cycle boundary (external counter = 1). if a1 is greater than the maximum value of the se lected counter bus period, then a 0% duty cycle is produced, only if the pin starts the current cycle in the opposite of the edpol value. in case of 100% duty cycle, the transition from edpol to the opposite of edpol may be obtained by forcing the pin using forcma and/or forcmb. note if a1 is set to 0x00_0001 at opwmcb en try the 100% duty cycle may not be obtained in the very first pwm cy cle due to the pin condition at mode entry. only values different than 0x0 are al lowed to be writ ten to a1 register. if 0x00_000 0 is loaded to a1, the results are unpredictable. note a special case occurs when a1 is se t to (external counter bus period)/2, which is the maximum value of the external counter. in this case, the output flip-flop is constantly set to the edpol bit value. the internal channel logic prevents matches from one cycl e to propagate to the next cycle. in trailing dead time insertion, a b1 match from cycle ( n ) could eventually cross the cycle boundary and occur in cycle ( n + 1). in this case, the b1 match is masked out and does not cause the output flip-flop to transition. therefore, matches in cycle ( n + 1) are not affected by the late b1 matches from cycle ( n ). figure 23-50 shows a 100% duty cycle output signal generated by setting a1 = 4 and b1 = 3. in this case the trailing edge is positio ned at the boundary of cycle n + 1, which is actually c onsidered to belong to cycle n + 2 and therefore does not cause the output flip-flip to transition.
enhanced modular input/output subsystem (emios200) 23-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-50. opwmcb with 100% duty cycle (a1 = 4 and b1 = 3) the output disable feature, if enable d, causes the output flip-flop to tran sition to the edpol inverted state. this feature allows an application to force the channel output pin to a ?safe? state. the internal channel matches continue to occur even in this case, thus generating flags. as soon as the output disable is deasserted, the channel output pin is again controll ed by the a1 and b1 matches. this process is synchronous, meaning that the output channel pin transitions on system clock edges only. it is important to notice that, as in opwmb and opwf mb modes, the match signal used to set or clear the channel output flip-flop is generated on the deas sertion of the channel combinational comparator output signal, which compares the selected time ba se with a1 or b1 register values. refer to figure 23-40 , which shows the delay from matche s to output flip-flop transition in opwfmb mode. the operation of opwmcb mode is similar to opwfmb rega rding matches and output pin transition. 23.4.1.1.17 output pulse wi dth modulation (opwm) mode in opwm mode, registers a1 and b1 define the leading and traili ng edges of the pwm output pulse, respectively. the mode[6] bit controls the transfer fr om register b2 to b1, wh ich can be done either immediately (mode[6] cleared, mode = 010_00b0), providi ng the fastest change in the duty cycle, or at every match of register a1 (mode[6] set, mode = 010_00b1). the value loaded in register a1 is compared with the value on the selected time base. when a match on comparator a occurs, the output flip -flop is set to the value of the edpol bit. when a match occurs on comparator b, the output flip-flop is se t to the complement of the edpol bit. flag can be generated at match b, when mode[5] is cleared, or in both matches, when mode[5] is set. 0x000001 0x000020 0x000004 a1 value a2 value b1 value b2 value 0x000004 0x000001 output flip-flop 0x000003 0x000015 0x000003 0x000015 0x000003 selected counter bus time write to b2 time cycle n cycle ( n +1) cycle ( n +2) dead time dead time dead time internal time base
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-57 pxr40 microcontroller reference manual, rev. 1 at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a or b respectively. no te that flag bit is not set by the forcma and forcmb operations. if subsequent matches occur on comparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. at opwm mode entry, the output flip-flop is se t to the complement of the edpol bit in the emios_ccr[ n ] register. in order to achieve 100% duty cycle, both registers a1 and b1 must be set to the same value. when a simultaneous match on comparators a and b occur, the output flip-flop is set at every period to the value of edpol bit. 0% duty cycle is possible by writing 0x0 to register a (emios_cadr). when a match occurs, the output flip-flop is set at every period to the complement of edpol bit. the transfer from register b2 to b1 is still controlled by mode[6] bit. note if a1 and b1 are set to 0x00_0000, a 0% duty cycle waveform is produced. figure 23-51 and figure 23-52 show the unified channel running in opwm with immediate update and next period update, respectively. figure 23-51. opwm wi th immediate update 0xffffff 0x001000 0x000000 selected counter bus time output flip-flop a1 value 1 0x000200 b1 value b2 value 2 0x000900 0xxxxxxx 0xxxxxxx 0xxxxxxx 0x000200 0x001000 0x001000 0x000900 notes: 1. emios_cadr[ n ] = a1 2. emios_cbdr[ n ] = b2 0x000900 0x001000 0x001000 a2 = a1 according to ou[ n ] bit b2 = b1 according to ou[ n ] bit mode[6] = 0 a1 match b1 match b2 write update to a1 match b1 match a1 update to a1
enhanced modular input/output subsystem (emios200) 23-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-52. opwm with next period update 23.4.1.1.18 output pulse-width modulation buffered (opwmb) mode opwmb mode (mode = 110_00b0) is used to genera te pulses with program mable leading- and trailing-edge placement. an external counter must be selected from one of the counter buses. the a1 register value defines the first edge and b1 defines the second edge. the output signal polarity is defined by the edpol bit. if edpol is 0, a negative edge oc curs when a1 matches the selected counter bus; and a positive edge occurs when b1 matches the selected counter bus. the a1 and b1 registers are double buffered and updated from a2 and b2, respectively, at the cycle boundary. the load operation is similar to the opwfmb mode. please refer to figure 23-42 for more information about a1 and b1 registers update. flag can be generated at b1 matches, when mode[5 ] is cleared, or in both a1 and b1 matches, when mode[5] is set. if subsequent matches occur on co mparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a1 or b1 respectively. the flag bit is not set by the forcma and forcmb operations. at opwmb mode entry the output flip-flop is set to the value of the edpol bit in the emios_ccr[ n ] register. some rules applicable to the opwmb mode include: ? b1 matches have precedence over a1 matches if they occur at the same time within the same counter cycle ? a1 = 0 match from cycle( n ) has precedence over b1 match from cycle( n ?1) ? a1 matches are masked out if they occur after b1 match within the same cycle 0x ffffff 0x 001000 0x 000000 selected counter bus time output flip-flop a1 value 1 0x 000200 b1 value b2 value 2 0x000200 0x000900 0xxxxxxx 0x000200 0x001000 0x 000900 0x001000 notes: 1. emios_cadr[ n ]=a1 2. emios_cbdr[ n ]=b2 0x001000 0x000900 0x000900 a2 = a1 and a2 = a1 according to ou[ n ] bit mode[6] = 1 a1 match a1 & b2 write b1 match b2 write a1 match b1 match
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-59 pxr40 microcontroller reference manual, rev. 1 ? any value written to a2 or b2 on cycle( n ) is loaded to a1 and b1 re gisters at the following cycle boundary (assuming (ou[ n ] in emios_oudr) is not asserted). the new values are used for a1 and b1 matches in cycle( n +1) figure 23-53 shows the operation of the op wmb mode regarding a1 and b1 matches and the transition of the channel output pin. in this example, edpol is set to 0. figure 23-53. opwmb mode matches and flags the output pin transitions are based on the nega tive edges of the a1 and b1 match signals. figure 23-53 shows in cycle( n + 1) the value of the a1 register being set to 0. in this case, the match positive edge is used instead of the negative edge to transition the output flip-flop. figure 23-54 shows the channel operation for 0% duty cycle. note that the a1 match positive edge signal occurs at the same time as the b1 = 0x00_0008 negative edge signal. in th is case a1 match has precedence over b1 match, causing the output pin to remain at edpol bit value, thus generating a 0% duty cycle signal. 1 4 a1 match negative edge 6 a1 value 0x000004 a1 match output pin selected time b1 match negative edge b1 match b1 value 0x000006 clock prescaler a2 value 0x000000 0x000000 a1 match positive edge detection 1 8 6 flag bit set edpol = 0 a1 match negative b1 match negative a1 match positive edge detection edge detection edge detection detection cycle n cycle ( n +1) detection counter bus write to a2
enhanced modular input/output subsystem (emios200) 23-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-54. opwmb mode with 0% duty cycle figure 23-55 shows the operation of the opwmb mode with the output di sable signal asse rted. the output disable forces a tran sition in the output pin to the edpol bit va lue. after deassertion, the output disable allows the output pin to transition at the following a1 or b1 match. the output disable does not modify the flag bit behavior. there is a de lay of one system clock between the assertion of the out put disable signal and the transition of th e output pin to edpol. 1 4 a1 match negative edge a1 value 0x000004 a1 match output pin selected time b1 match b1 value 0x000008 clock prescaler a2 value 0x000000 0x000000 a1 match positive edge detection 1 8 flag pin/register edpol = 0 a1 match negative b1 match negative a1 match positive edge detection edge detection edge detection cycle n cycle ( n +1) write to a2 detection 8 counter bus a1 match negative edge detection flag set event edpol = 0
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-61 pxr40 microcontroller reference manual, rev. 1 figure 23-55. opwmb mode with active output disable figure 23-56 shows a waveform changing from 100% to 0% dut y cycle. in this case, edpol is 0. in this example, b1 is programmed to the same value as the period of the external selected time base. figure 23-56. opwmb mode from 100% to 0% duty cycle in figure 23-56 , if b1 is set to a value lo wer than 0x00_0008, it is not possibl e to achieve 0% duty cycle by changing only the a1 register va lue. because b1 matches have pr ecedence over a1 matches, the output pin transitions to the opposite of ed pol bit at b1 match. if b1 is se t to 0x00_0009, for instance, b1 match does not occur, thus a 0% dut y cycle signal is generated. cycle n cycle ( n + 1) cycle ( n +2) a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 selected 0x000004 0x000006 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 match a1 match b1 match b1 flag set event time write to a2 match a1 write to a2 match b1 output disable counter bus due to b1 match cycle ( n ?1) edpol = 0 mode[6] = 1 0x000008 0x000007 0x000006 0x000005 0 x000004 0x000003 0x000002 0x000001 0x000000 0% 100% selected edpol = 0 a1 value b1 value output pin 0x000008 prescaler = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 0x000007 0x000006 0x000005 0x00000 4 0x000003 0x000002 0x000001 0x000000 a2 value time counter bus
enhanced modular input/output subsystem (emios200) 23-62 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.4.1.2 input programmable filter (ipf) the ipf is a 5-bit programmable up counter that is in cremented by the selected clock source, according to if bits in emios_ccr[ n ]. the ipf ensures that only valid input pin transitions are received by the unified channel edge detector. figure 23-57 shows a block diagram of the ipf. figure 23-57. lnput programmable filter submodule diagram the input signal is synchronized by sy stem clock. when a state change occurs in this signal, the 5-bit counter starts counti ng up. as long as the new state is stable on the pin, the counter remains incrementing. if a counter overflow occurs, the new pin value is validated. in this case, it is transmitted as a pulse edge to the edge detector. if the opposite edge appears on the pin before validation (o verflow), the counter is reset. at the next pin tran sition, the counter starts coun ting again. any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge detector. figure 23-58 shows a timing diagram of the input filter. figure 23-58. input programmable filter example the filter is not disabled during eith er freeze state or negated gtbe input. 23.4.1.3 clock prescaler (cp) the cp divides the gcp output signal to generate a cl ock enable for the internal counter of the unified channels. it is a programmable 2-bit down counter. the gcp output signal is prescaled by the value defined in the ucpre bits in the emios_ccr[ n ] register. the output is cloc ked every time the counter reaches zero. counting is enabled by sett ing the ucpren bit in the emios_ccr[ n ]. the counter can be stopped at any time by clearing this bit, thereby st opping the internal counter in the unified channel. synchronizer if3 clk if2 if1 if0 5-bit up counter fck prescaled clock emiosi clock system clock filter out selected clock 5-bit counter filter out emiosi time if[3:0] = 0010
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-63 pxr40 microcontroller reference manual, rev. 1 in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write 0 at both gpren bit in emiosmcr register and ucpren bit in emios_ccr[ n ] register, thus disabling prescalers; 2. write the desired value for prescaling rate at uc pre[] bits in emios_ccr[ n ] register; 3. enable channel prescaler by writi ng 1 at ucpren bit in emios_ccr[ n ] register; 4. enable global prescaler by writing 1 at gpren bit in emiosmcr register. the prescaler is not disabl ed during either freeze stat e or negated gtbe input. 23.4.1.4 effect of freeze on the unified channel when in debug mode, if the frz bit in the em ios_mcr register and the fren bit in the emios_ccr[ n ] are both set, the internal counter and unifi ed channel capture and compare functions are halted. the unified channel is frozen in its current state. during freeze, all registers are accessi ble. when the unified channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. during input modes, any input events that may occur while the channel is frozen are ignored. when exiting debug mode or when the freeze enable bit is cleared (frz in the emios_mcr or fren in the emios_ccr[ n ] register), the channel actions resume but may be inconsiste nt until the channel enters gpio mode again. 23.4.2 ip bus inte rface unit (biu) the biu provides the interf ace between the internal interface bus (iib) and the peripheral bus, allowing communication among a ll submodules and this ip interface. the biu allows 8-, 16-, and 32-bit access. they are performed over a 32-bit data bus in a single cycle clock. 23.4.2.1 effect of freeze on the biu when the frz bit in the emios_mcr register is se t and the module is in debug mode, the operation of biu is not affected. 23.4.3 stac client submodule the shared time and angle count (sta c) bus provides access to one extern al time base, imported from the stac bus to the emios unified cha nnels. the etpu module's time base s and angle count can be exported and/or imported through the stac cl ient submodule interface. time ba ses and/or angle information of either etpu engine can be exported to the other etpu engine and to the emios module, which is only a stac client. there are rest rictions on engine export/ import targets: one engine cannot export from or import to itself, nor can it import time ba se and/or angle count if in angle mode.
enhanced modular input/output subsystem (emios200) 23-64 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the device?s stac server identi fication assignment is shown in table 23-11 . the time slot assignment is fixed, so only time bases running at sy stem clock divided by four or slow er can be integr ally exported. the stac client submodule runs with the system clock, and its time slot timing is synchronized with the etpu timing on reset. the time slot sequence is 0-1-2-3, su ch that they alternate between engines one and two. figure 23-59 provides a block diagram fo r the stac client submodule. figure 23-59. stac client submodule block diagram emios_mcr[srv] bits select the ti me slot of the stac output bus. figure 23-60 shows a timing diagram for the stac client submodule. figure 23-60. timing diagram for the stac bus and stac client submodule output every time the selected time slot changes, the stac client subm odule output is updated. table 23-11. stac client submodule server slot assignment engine time base server id 1 tcr1 0 1 tcr2 2 2 tcr1 1 2 tcr2 3 srv3 srv2 srv1 srv0 stac bus time base stac client submodule (24-bit wide) output time slot selector bits ts[02] stac bus (submodule input) ts[00] ts[01] ts[02] time base (submodule output) ts[01] xx the srv bits are set to capture ts[01]. ts[03] ts[00] ts[03] ts[00] ts[01] system clock ts[01] stac bus (redc input) ts[00] ts[01] ts[02] 1. maximum of 16 time slots (ts n ) notes: ts[01] ts[00] tsn1 ts[02] time base (redc output) ts[01] ts[01] xx 2. the srv bits capture ts[01]
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-65 pxr40 microcontroller reference manual, rev. 1 23.4.3.1 effect of freeze on the stac client submodule when the frz bit in the emios_mcr is set and the module is in debug mode, the operation of the stac client submodule is not affected; that is, there is no freeze function in this submodule. 23.4.4 global clock prescaler submodule (gcp) the gcp divides the system clock to generate a clock fo r the clock prescalers (cp) of the unified channels. it is a programmable 8-bit up counter. the main clock si gnal is prescaled by the value defined in the gpre bits in emios_mcr. the output is clocked every t ime the counter overflows. counting is enabled by setting the gpren bit in the emios_mcr. the counter can be stopped at any ti me by clearing this bit, thereby stopping the internal count er in all the unified channels. in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write 0 at gpren bit in emiosmcr regi ster, thus disabli ng global prescaler; 2. write the desired value for prescaling rate at gpre[0:7] bits in emiosmcr register; 3. enable global prescaler by writing 1 at gpren bit in emiosmcr register. the prescaler is not disabl ed during either freeze stat e or negated gtbe input. 23.4.4.1 effect of freeze on the gcp when the frz bit in the emios_mcr register is se t and the module is in debug mode, the operation of gcp submodule is not affected, i.e., there is no freeze function in this submodule. 23.5 reset the emios200 is reset by the globa l asynchronous system reset signal. the mdis bit in the emios_mcr register is cleared during reset. on resetting the emios200 all unified channels enter gpio input mode. 23.6 interrupts the emios200 can generate one interrupt per channel. an interrupt request is generated according to the configuration of the channel and input events or matches. see chapter 10, interrupts and interrupt controller (intc), for details on the emios200 interrupt vectors.
enhanced modular input/output subsystem (emios200) 23-66 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 23.7 initialization/application information on resetting the emios200 all unified channels enter gpio input mode. 23.7.1 considerations before changing an operating mode, the unified ch annel must be programme d to gpio mode and emios_cadr[ n ] and emios_cbdr[ n ] registers must be updated with the correct values for the next operating mode. then the emios_ccr[ n ] register can be written wi th the new operating mode. if a unified channel is changed from one mode to another without performing this proc edure, the first operation cycle of the selected time base can be random, i.e., matches can occur in random time if the contents of emios_cadr[ n ] or emios_cbdr[ n ] were not updated with the correct value before the time base matches the previous contents of emios_cadr[ n ] or emios_cbdr[ n ]. when interrupts are enabled, the software must clear the flag bits before exi ting the interrupt service routine. 23.7.2 application information correlated output signals can be genera ted by all output opera tion modes. the ou[ n ] bits in emios_oudr can be used to control the update of these output signals. in order to guarantee the internal c ounters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set before enabling th e global prescaler. if the internal prescalers are set after enabling the global prescaler, th e internal counters may increment in the same ratio but at a different clock cycle. 23.7.3 time base generation for mc, opwfm, and opwm wi th internal clock source operation modes, the in ternal counter rate can be modified by configuring the clock prescaler ratio. figure 23-61 shows an example of a time base with prescaler ratio equal to one. when th e prescaler is greater than one, th e counter is imme diately cleared on a match and then incremented in th e next prescaled clock edge, except when runni ng in opwfm mode or mc mode with internal clock source. in these cases, the counter will skip the next prescaled clock edge and continue incremented on subs equent edges, as shown in figure 23-62 . note mcb, opwfmb, and op wmb modes have a different behavior.
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-67 pxr40 microcontroller reference manual, rev. 1 figure 23-61. time base period when running in the fastest prescaler ratio if the prescaler ratio is greater than one or external clock is selected, the c ounter may behave in three different ways dependi ng on the channel mode: ? if mc mode and clear on match start and external clock source are selected the internal counter behaves as described in figure 23-63 . ? if mc mode and clear on match start and internal clock source are selected the internal counter behaves as described in figure 23-64 . ? if mc mode and clear on match end are selected the internal counter behaves as described in figure 23-65 . ? if opwfm mode is selected the intern al counter behaves as described in figure 23-64 . the internal counter clears at the star t of the match signal, skips the ne xt prescaled clock edge and then increments in the subsequent prescaled clock edge. note mcb and opwfmb modes have a different behavior. figure 23-62. time base period when runni ng with a prescaler ratio greater than 1 when a match occurs, the first clock cycle is used to clear t he internal counter, starting another period. note: prescaled clock = 1 internal counter 1 23 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 match value = 3 clock see note prescaled clock ratio = 1 (bypassed) when a match occurs, the first clock cycle is us ed to clear the inte rnal counter, and only after a second edge of prescaled clock the counter will start counting. note: prescaled clock internal counter 1 2 0 match value = 3 clock see note 3 1 2 3 00 0 prescaled clock ratio = 3
enhanced modular input/output subsystem (emios200) 23-68 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 23-63. time base generation with external clock and clear on match start figure 23-64. time base generation with internal clock and clear on match start figure 23-65. time base genera tion with clear on match end system clock input event internal counter match value = 3 1 2 3 0 see note note: when a match occurs, the first system clock cycle is used to clear the internal counter, and at the next edge 1 2 1 2 3 0 flag set event flag clear flag pin/register of prescaler clock enable the counter will start counting. system clock prescaler clock enable internal counter match value = 3 0 1 3 0 2 0 3 0 prescaled clock ratio = 3 see note note: when a match occurs, the first clock cycl e is used to clear the internal counter, 1 2 flag set event flag clear flag pin/register and only after a second edge of prescaled clock the counter will start counting. system clock input event/ internal counter match value = 3 0 1 3 2 0 prescaled clock ratio = 3 see note note: the match occurs only when the input event/prescaler clock enable is active. then, the internal counter is immediately cleared. 1 2 3 flag set event flag clear flag pin/register prescaler clock enable
enhanced modular input/output subsystem (emios200) freescale semiconductor 23-69 pxr40 microcontroller reference manual, rev. 1 23.7.4 coherent accesses for ipwm and ipm modes, it is recommended that th e software wait for a new flag set event before reading emios_cadr[ n ] and emios_cbdr[ n ] registers to get a new measurement. the flag indicates that new data has been captured and it is the only way to a ssure data coherency. the flag set event can be detected by polling the fl ag bit or by enabling the interrupt or dma request generation. reading the emios_cadr[ n ] register again in the same peri od of the last read of emios_cbdr[ n ] register may lead to incoherent results. th is occurs if the last read of emios_cbdr[ n ] register occurred after a disabled b2 to b1 transfer.
enhanced modular input/output subsystem (emios200) 23-70 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 24-1 pxr40 microcontroller reference manual, rev. 1 chapter 24 flexcan module 24.1 introduction this device has four flexcan modules: a, b, c, a nd d. the remainder of this chapter describes one module. each flexcan module is a communication controller implementing the can pr otocol according to the can 2.0b protocol specification [ref. 1] . a general block diagram is shown in figure 24-1 , which describes the main sub-blocks im plemented in the flexcan module, including two embedded memories, one for storing message buff ers (mb) and another one for storing rx individual mask registers. support for 64 message buffers is provided. the functions of the sub-modules are described in subsequent sections.
flexcan module 24-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 24-1. flexcan block diagram 24.1.1 overview the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this fi eld: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specificati on, version 2.0 b [ref. 1], which support s both standard and extended message frames. a flexible number of messa ge buffers (16, 32 or 64) is also supported. the message buffers are stored in an embedded ram dedicate d to the flexcan module. please re fer to the device user guide for the actual number of message bu ffer configured in the mcu 288/544/1056- bus interface unit max mb # (0?63) ip bus interface can message can tx can rx mb1 mb0 mb62 mb63 clocks, address & data buses, interrupt and test signals buffer management protocol interface byte ram message buffer storage 64/128/256- rximr1 rximr0 rximr62 rximr63 byte ram id mask storage
flexcan module freescale semiconductor 24-3 pxr40 microcontroller reference manual, rev. 1 the can protocol interface (cpi) sub-module ma nages the serial comm unication on the can bus, requesting ram access for receiving and transmitting message frames, va lidating received messages and performing error handling. the me ssage buffer management (mbm ) sub-module handles message buffer selection for reception and transmission, taking care of arbitrat ion and id matching algorithms. the bus interface unit (biu) sub-module controls the acce ss to and from the internal interface bus, in order to establish connecti on to the cpu and to other bl ocks. clocks, address and data buses, interrupt outputs and test signals are accessed through the bus interface unit. 24.1.2 flexcan module features the flexcan module includes these distinctive features: ? full implementation of the can pr otocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mb/sec ? content-related addressing ? flexible message buffers (64) of zero to eight bytes data length ? each mb configurable as rx or tx, al l supporting standard and extended messages ? individual rx mask registers per message buffer ? includes 1056 bytes (64 mbs) of ram used for mb storage ? includes 256 bytes (64 mbs) of ram us ed for individual rx mask registers ? full featured rx fifo with storage capacity for 6 frames and internal pointer handling ? powerful rx fifo id filtering, capable of ma tching incoming ids against either 8 extended, 16 standard or 32 partial (8 bits) id s, with individual masking capability ? selectable backwards compatibilit y with previous flexcan version ? programmable clock source to th e can protocol interface, either bus clock or crystal oscillator ? unused mb and rx mask register space ca n be used as general purpose ram space ? listen only mode capability ? programmable loop-back mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buffer number or highest priority ? time stamp based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed) ? short latency time due to an arbitration scheme for high-priority messages
flexcan module 24-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? low power modes 24.1.3 modes of operation the flexcan module has these functional modes: norm al mode (user and supe rvisor), freeze mode, listen-only mode and loop-back m ode. there are also thes e low power modes: di sable mode and stop mode. ? normal mode (user or supervisor): in normal mode, the module operates receiving a nd/or transmitting message frames, errors are handled normally and all the can protocol functions are enable d. user and supervisor modes differ in the access to some restricted control registers. ? freeze mode: it is enabled when the frz bit in the flexcan_x_mcr register is asserted. if enabled, freeze mode is entered when the halt bit in f lexcan_x_mcr is set or when debug mode is requested at mcu level. in th is mode, no transmission or rece ption of frames is done and synchronicity to the can bus is lost. see section 24.4.9.1, freeze mode, for more information. ? listen-only mode: the module enters this mode when the lom bit in the control regist er is asserted. in this mode, transmission is disable d, all error counters are frozen and the module operates in a can error passive mode [ref. 1]. only messa ges acknowledged by another can station will be received. if flexcan detects a message that has not been ac knowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. ? loop-back mode: the module enters this mode when the lpb bit in the control register is asserted. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessi ve state (logic ?1?). flexcan behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. in this mode , flexcan ignores the bit sent during the ac k slot in the can frame acknowledge field to ensure proper reception of its own messa ge. both transmit and receive interrupts are generated. ? module disable mode: this low power mode is entered when the mdis bit in the flexca n_x_mcr register is asserted by the cpu. when the flexcan module is disable d, the module sends a request to disable the clocks to the can protocol interface and mess age buffer management sub-modules. exit from this mode is done by negating the mdis bit in the flexcan_x_mcr register. see section 24.4.9.2, module disable mode, for more information. ? stop mode: this low power mode is entered when stop mode is requested at mcu level. when in stop mode, the module puts itself in an inactive state and th en informs the cpu that the clocks can be shut down globally. exit from this mode happens when the stop mode request is removed.
flexcan module freescale semiconductor 24-5 pxr40 microcontroller reference manual, rev. 1 24.2 external signal description 24.2.1 overview the flexcan module has two i/o si gnals connected to the external mcu pins. these signals are summarized in table 24-1 and described in more detail in the next subsections. 24.2.2 signal descriptions 24.2.2.1 can rx this pin is the receive pin from the can bus transceive r. dominant state is repr esented by logic level ?0?. recessive state is represented by logic level ?1?. 24.2.2.2 can tx this pin is the transmit pin to th e can bus transceiver. dominant stat e is represented by logic level ?0?. recessive state is represented by logic level ?1?. 24.3 memory map/register definition this section describes the registers and data structures in the flexca n module. the base address of the module depends on the particul ar memory map of the mcu. the addres ses presented here are relative to the base address. the address space occupied by flexcan has 96 bytes fo r registers starting at the module base address, followed by mb storage space in embedded ram st arting at address 0x0060, and an extra id mask storage space in a separate em bedded ram starting at address 0x0880. 24.3.1 flexcan memory mapping the complete memory map fo r a flexcan module with 64 mb s capability is shown in table 24-2 . each individual register is identified by its complete name and the corres ponding mnemonic. the access type is always supervisor (s). the flexcan_x_iflag2 and flexcan_x_imask2 regi sters are considered reserved space when flexcan is configured with 16 or 32 mbs. the rx global mask (flexcan_x_rxgmask), rx buffer 14 mask (flexcan_x_rx14mask) and the rx buffer 15 mask (flexcan_x_rx15mask) table 24-1. flexcan signals signal name 1 notes: 1 the actual mcu pins may have different names. please consult the device user guide for the actual signal names. direction description can rx input can receive pin can tx output can transmit pin
flexcan module 24-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 registers are provided for back wards compatibility, and are not used when the mbfen bit in flexcan_x_mcr is asserted. the address ranges 0x0060?0x047f a nd 0x0880?0x097f are occupied by two separate embedded memories. these two ranges are completely occ upied by ram (1056 and 256 bytes, respectively) only when flexcan is configured with 64 mbs. when it is c onfigured with 16 mbs, the memory sizes are 288 and 64 bytes, so the address ranges 0x0180?0x047f and 0x08c0?0x097f are c onsidered reserved space. when it is configured with 32 mbs, the memory sizes are 544 a nd 128 bytes, so the address ranges 0x0280?0x047f and 0x0900?0x097f are consider ed reserved space. furtherm ore, if the mbfen bit in flexcan_x_mcr is negated, then the whole rx individual mask registers address range (0x0880?0x097f) is considered reserved space.
flexcan module freescale semiconductor 24-7 pxr40 microcontroller reference manual, rev. 1 table 24-2. module memory map address 1 register bits access reset value affected by hard reset affected by soft reset section/page base + 0x0000 flexcan_x_mcr?module configuration 32 s 0x5990_000f yes yes 24.3.4.1/14 base + 0x0004 flexcan_x_ctrl?control register 32 s 0x0000_0000 yes no 24.3.4.2/18 base + 0x0008 flexcan_x_timer?free running timer 32 s 0x0000_0000 yes yes 24.3.4.3/21 base + 0x000c reserved base + 0x0010 flexcan_x_rxgmask?rx global mask 32 s 0xffff_ffff yes no 24.3.4.4/22 base + 0x0014 flexcan_x_rx14mask?rx buffer 14 mask 32 s 0xffff_ffff yes no 24.3.4.5/22 base + 0x0018 flexcan_x_rx15mask?rx buffer 15 mask 32 s 0xffff_ffff yes no 24.3.4.6/23 base + 0x001c flexcan_x_ecr?error counter register 32 s 0x0000_0000 yes yes 24.3.4.7/23 base + 0x0020 flexcan_x_esr?error and status register 32 s 0x0000_0000 yes yes 24.3.4.8/25 base + 0x0024 flexcan_x_imask2?interrupt masks 2 32 s 0x0000_0000 yes yes 24.3.4.9/28 base + 0x0028 flexcan_x_imask1?interrupt masks 1 32 s 0x0000_0000 yes yes 24.3.4.10/28 base + 0x002c flexcan_x_iflag2?interrupt flags 2 32 s 0x0000_0000 yes yes 24.3.4.11/29 base + 0x0030 flexcan_x_iflag1?interrupt flags 1 32 s 0x0000_0000 yes yes 24.3.4.12/30 base + 0x0034?0x005f reserved base + 0x0060?0x007f reserved base + 0x0080?0x017f message buffers mb0 ? mb15 ? s ? no no ? base + 0x0180?0x027f message buffers mb16 ? mb31 ? s ? no no ? base + 0x0280?0x047f message buffers mb32 ? mb63 ? s ? no no ? base + 0x0480-087f reserved base + 0x0880-0x08bf rximr0-rximr15?rx individual mask registers snono 24.3.4.13/32 base + 0x08c0-0x08ff rximr16-rximr31?rx individual mask registers snono 24.3.4.13/32 base + 0x0900-0x097f rximr32-rximr63?rx individual mask registers snono 24.3.4.13/32
flexcan module 24-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the flexcan module stores can messages for tran smission and reception us ing a message buffer structure. each individual mb is formed by 16 bytes mapped in memory as described in table 24-3 . table 24-3 shows a standard/extended message buffer (mb0) memory map, using 16 bytes total (0x80 ? 0x8f space). 24.3.2 message buffer structure the message buffer structure used by the flexcan module is represented in figure 24-2 . both extended and standard frames (29-bit identifier and 11-bit identifier, re spectively) used in the can specification (version 2.0 part b) are represented. notes: 1 flexcan_a = 0xfffc_0000 flexcan_b = 0xfffc_4000 flexcan_c = 0xfffc_8000 flexcan_d = 0xfffc_c000 table 24-3. message buffer mb0 memory mapping address offset mb field 0x80 control and status (c/s) 0x84 identifier field 0x88 ? 0x8f data field 0 ? data field 7 (1 byte each) 0 3 4 7 9 101112 1516 2324 31 0x0 code s r r i d e r t r length time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved figure 24-2. message buffer structure
flexcan module freescale semiconductor 24-9 pxr40 microcontroller reference manual, rev. 1 table 24-4. message buffer structure field descriptions field description code message buffer code this 4-bit field can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitration process. the encoding is shown in ta b l e 2 4 - 5 and ta b l e 2 4 - 6 . see section 24.4, functional description, for additional information. srr substitute remote request fixed recessive bit, used only in extended format. it must be set to ?1? by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan receives this bit as dominant, then it is interpreted as arbitration loss. 0 dominant is not a valid value for transmission in extended format frames 1 recessive value is compulsory for transmission in extended format frames ide id extended bit this bit identifies whether the fram e format is standard or extended. 0 frame format is standard 1 frame format is extended rtr remote transmission request this bit is used for requesting transmissions of a data fram e. if flexcan transmits this bit as ?1? (recessive) and receives it as ?0? (dominant), it is interpreted as arbitration loss. if this bit is transmitted as ?0? (dominant), then if it is received as ?1? (recessive), the flexcan module treats it as bit error. if the value received matches the value transmitted, it is considered as a successful bit transmission. 0 indicates the current mb has a data frame to be transmitted 1 indicates the current mb has a remote frame to be transmitted length length of data in bytes this 4-bit field is the length (in bytes) of the rx or tx dat a, which is located in offset 0x8 through 0xf of the mb space (see figure 24-2 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the received frame. in transmission, this field is wr itten by the cpu and corresponds to the dlc field value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remote frame and does not include the data field, regardless of the length field. time stamp free-running counter time stamp this 16-bit field is a copy of the free-running timer, capt ured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio local priority this 3-bit field is only used when lprio_en bit is set in flexcan_x_mcr and it only makes sense for tx buffers. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see section 24.4.3, arbitration process. id frame identifier in standard frame format, only the 11 most significant bits (3 to 13) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignore d. in extended frame format, all bits are used for frame identification in both receive and transmit cases. data data field up to eight bytes can be used for a data frame. for rx frames , the data is stored as it is received from the can bus. for tx frames, the cpu prepares the data field to be transmitted within the frame.
flexcan module 24-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 24-5. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: mb is not active. ? mb does not participate in the matching process. 0100 empty: mb is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. 0010 full: mb is full. 0010 the act of reading the c/s word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame is overwritten to this mb before the cpu had time to read it, the code is automatically updated to overrun. refer to section 24.4.5, matching process, for details about overrun behavior. 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb the code returns to full. 0110 if the code already indicates overrun, and yet another new frame must be written, the mb will be overwritten again, and the code will remain overrun. refer to section 24.4.5, matching process, for details about overrun behavior. 0xy1 1 notes: 1 note that for tx mbs (see ta b l e 2 4 - 6 ), the busy bit should be ignored up on read, except when aen bit is set in the flexcan_x_mcr register. busy: flexcan is updating the contents of the mb. the cpu must not access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11). table 24-6. message buffer code for tx buffers rtr initial tx code code after successful transmission description x 1000 ? inactive: mb does not partic ipate in the arbitration process. x 1001 ? abort: mb was configured as tx and cpu aborted the transmission. this code is only valid when aen bit in flexcan_x_mcr is asserted. mb does not participate in the arbitration process. 0 1100 1000 transmit data frame unconditionally once. after transmission, the mb automatically returns to the inactive state.
flexcan module freescale semiconductor 24-11 pxr40 microcontroller reference manual, rev. 1 1 1100 0100 transmit remote frame unconditionally once. after transmission, the mb automatically becomes an rx mb with the same id. 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this mb participates simultaneously in both the matching and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs this mb is allowed to participate in the current arbitration process and the code field is automatically updated to ?1110? to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to ?1010? to restart the process again. 0 1110 1010 this is an intermediate code t hat is automatically written to the mb by the mbm as a result of match to a remote request frame. the data frame will be transmitted unconditionally once and then the code will automatically return to ?1010?. the cpu can also write this code with the same effect. table 24-6. message buffer code for tx buffers (continued) rtr initial tx code code after successful transmission description
flexcan module 24-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.3.3 rx fifo structure when the fen bit is set in the flexcan_x_mcr, the memory area from 0x80 to 0xfc (which is normally occupied by mbs 0 to 7) is used by the reception fifo engine. figure 24-3 shows the rx fifo data structure. the region 0x80-0x8c contains an mb structure which is the port through which the cpu reads data from the fifo (the oldest frame received and not read yet). the re gion 0x90-0xdc is reserved for internal use of the fifo engine. the region 0xe0- 0xfc contains an 8-entry id table that specifies filtering criteria for accepting frames into the fifo. figure 24-4 shows the three different formats that the elements of the id table ca n assume, depending on the idam field of the flexcan_x_mcr. note that all elements of the table must have the same format. see section 24.4.7, rx fifo, for more information. 0 3 7 8 9 10 11 12 13 14 15 16 23 24 31 0x80 s r r i d e r t r length time stamp 0x84 id (standard/extended) id (extended) 0x88 data byte 0 data byte 1 data byte 2 data byte 3 0x8c data byte 4 data byte 5 data byte 6 data byte 7 0x90 reserved to 0xdc 0xe0 id table 0 0xe4 id table 1 0xe8 id table 2 0xec id table 3 0xf0 id table 4 0xf4 id table 5 0xf8 id table 6 0xfc id table 7 = unimplemented or reserved figure 24-3. rx fifo structure
flexcan module freescale semiconductor 24-13 pxr40 microcontroller reference manual, rev. 1 0 3 4 7 9 101112 1516 2324 31 a r e m e x t rxida (standard = 29-19, extended = 29-1) b r e m e x t rxidb_0 (standard = 29-19, extended = 29-16) r e m e x t rxidb_1 (standard = 13-3, extended = 13-0) c rxidc_0 (std/ext = 31-24) rxidc_1 (std/ext = 23-16) rxidc_2 (std/ext = 15-8) rxidc_3 (std/ext = 7-0) = unimplemented or re- served figure 24-4. id table 0 - 7 table 24-7. rx fifo structure field descriptions field description rem remote frame this bit specifies if remote frames are accepted into the fifo if they match the target id. 0 remote frames are rejected and data frames can be accepted 1 remote frames can be accepted and data frames are rejected ext extended frame specifies whether extended or standard frames are acc epted into the fifo if they match the target id. 0 extended frames are rejected and standard frames can be accepted 1 extended frames can be accepted and standard frames are rejected rxida rx frame identifier (format a) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, only the 11 most significant bits (3 to 13)are used for frame identifica tion. in the extended frame format, all bits are used. rxidb_0 rxidb_1 rx frame identifier (format b) specifies an id to be used as acceptance criteria for the fifo. in the standard frame fo rmat, the 11 most significant bits (a full standard id) (3 to 13)are used for frame identific ation. in the extended frame form at, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0 rxidc_1 rxidc_2 rxidc_3 rx frame identifier (format c) specifies an id to be used as acceptance criteria for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id.
flexcan module 24-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.3.4 register descriptions the flexcan registers are described in this section in as cending address order. 24.3.4.1 module configurati on register (flexcan_x_mcr) this register defines global system configurations, such as the m odule operation mode (e.g., low power) and maximum message buffer configuratio n. most of the fields in this re gister can be acce ssed at any time, except the maxmb field, which should only be ch anged while the module is in freeze mode. figure 24-5. module configuration register (flexcan_x_mcr) base + 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mdis frz fen halt not_ rdy 0 soft _rst frz_ ack supv 0 wrn _en mdi- sack 0 doze srx _dis mbf en w reset: 0 1 0 1 1 0 0 1 1 0 0 1 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 lpri o_en aen 0 0 idam 0 0 maxmb w reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 table 24-8. flexcan_x_mcr field descriptions field description 0 mdis module disable this bit controls whether flexcan is enabled or not. when disabled, flexcan shuts down the clocks to the can protocol interface and message buffer management sub-modules. this is the only bit in flexcan_x_mcr not affected by soft reset. see section 24.4.9.2, module disable mode, for more information. 0 enable the flexcan module 1 disable the flexcan module 1 frz freeze enable the frz bit specifies the flexcan behavior when the halt bit in the flexcan_x_mcr register is set or when debug mode is requested at mcu level. w hen frz is asserted, flexcan is enabled to enter freeze mode. negation of this bit field causes flexcan to exit from freeze mode. 0 not enabled to enter freeze mode 1 enabled to enter freeze mode 2 fen fifo enable this bit controls whether the fifo feature is enabled or not. when fen is set, mbs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xff) is used by the fifo engine. see section 24.3.3, rx fifo structure and section 24.4.7, rx fifo, for more information. 0 fifo not enabled 1 fifo enabled
flexcan module freescale semiconductor 24-15 pxr40 microcontroller reference manual, rev. 1 3 halt halt flexcan assertion of this bit puts the flexcan module into fr eeze mode. the cpu should clear it after initializing the message buffers and control register. no reception or transmission is performed by flexcan before this bit is cleared. while in freeze mode, the cpu has write access to the error counter register, that is otherwise read-only. freeze mode can not be entered wh ile flexcan is in any of the low power modes. see section 24.4.9.1, freeze mode, for more information. 0 no freeze mode request. 1 enters freeze mode if the frz bit is asserted. 4 not_rdy flexcan not ready this read-only bit indicates that flexcan is either in disable mode, stop mode or freeze mode. it is negated once flexcan has exited these modes. 0 flexcan module is either in normal mode, listen-only mode or loop-back mode 1 flexcan module is either in disable mode, stop mode or freeze mode 5 reserved 6 soft_rst soft reset when this bit is asserted, flexcan resets its inte rnal state machines and some of the memory mapped registers. the following regi sters are reset: flexcan_x_mcr (except the mdis bit), flexcan_x_timer, flexcan_x_ecr, flexcan_x_esr, flexcan_x_imask1, flexcan_x_imask2, flexcan_x_iflag 1, flexcan_x_iflag2. configur ation registers that control the interface to the can bus are not affected by so ft reset. the following registers are unaffected: ? flexcan_x_ctrl ?rximr0?rximr63 ? flexcan_x_rxgmask, flexcan_x_rx14mask, flexcan_x_rx15mask ? all message buffers the soft_rst bit can be asserted directly by the cpu when it writes to the flexcan_x_mcr register, but it is also asserted when global soft reset is requ ested at mcu level. since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the soft_rst bit remains assert ed while reset is pending, and is automatically negated when reset completes. therefore, software can poll this bit to know when the soft reset has completed. soft reset cannot be applied while clocks are shut down in any of the low power modes. the module should be first removed from low power mode, and then soft reset can be applied. 0 no reset request 1 resets the registers marked as ?affected by soft reset? in table 24-2 7 frz_ack freeze mode acknowledge this read-only bit indicates that flexcan is in freeze mode and its prescaler is stopped. the freeze mode request cannot be granted until current trans mission or reception processes have finished. therefore the software can poll the frz_ack bit to know when flexcan has actually entered freeze mode. if freeze mode request is neg ated, then this bit is negated once the flexcan prescaler is running again. if freeze mode is requested while flexcan is in any of the low power modes, then the frz_ack bit will only be set when the low power mode is exited. see section 24.4.9.1, freeze mode, for more information. 0 flexcan not in freeze mode, prescaler running 1 flexcan in freeze mode, prescaler stopped table 24-8. flexcan_x_mcr field descriptions (continued) field description
flexcan module 24-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 8 supv supervisor mode although the flexcan module provides a differentiati on between supervisor and user access types, all accesses will be always considered of the supervisor type. as a consequence, the supv bit in the module configuration register (flexcan_x_mcr) has no effect on the module behavior. . 1 affected registers are in supervisor memory s pace. any access without supervisor permission behaves as though the access was done to an unimplemented register location 9 reserved 10 wrn_en warning interrupt enable when asserted, this bit enables the generation of the twrn_int and rwrn_int flags in the error and status register. if wrn_en is negated, the tw rn_int and rwrn_int flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. 0 twrn_int and rwrn_int bits are zero, independent of the values in the error counters. 1 twrn_int and rwrn_int bits are set when the respective error counter transition from <96 to ? 96. 11 mdisack module disable acknowledge this read-only bit indicates that flexcan is either in disable mode or stop mode. either of these low power modes can not be entered until all current transm ission or reception processes have finished, so the cpu can poll the mdisack bit to know when flexcan has actually entered low power mode. see section 24.4.9.2, module disable mode, and section 24.4.9.3, stop mode, for more information. 0 flexcan not in any of the low power modes 1 flexcan is either in disable mode or stop mode 12 reserved 13 doze doze mode enable doze mode is not supported on this device. leave this bit as ?0?. 0 flexcan is not enabled to enter low power mode when doze mode is requested 14 srx_dis self reception disable this bit defines whether flexcan is allowed to receive fr ames transmitted by itself. if this bit is asserted, frames transmitted by the module will not be stored in any mb, regardless if the mb is programmed with an id that matches the transmitted frame, and no in terrupt flag or interrupt signal will be generated due to the frame reception. 0 self reception enabled 1 self reception disabled 15 mbfen message buffer filter enable. this bit provides the ca pability of enabling either individual masking of every message buffer, or global masking of message buffers. this bit is provided to support backwards compatibility with previous flexcan versions. when this bit is negated, the following configuration is applied: ? individual rx id masking is disabled. instead of individual id masking per mb, flexcan uses its previous masking scheme with flexc an_x_rxgmask, flexcan_x_rx14mask and flexcan_x_rx15mask. ? the reception queue feature is disabled. upon receiving a message, if the first mb with a matching id that is found is still occupied by a previous unr ead message, flexcan will not look for another matching mb. it will override this mb with the new message and set the code field to ?0110? (overrun). upon reset this bit is negated, allowing legacy software to work without modification. 0 individual rx masking and queue feature are disabled. 1 individual rx masking and queue feature are enabled. 16?17 reserved table 24-8. flexcan_x_mcr field descriptions (continued) field description
flexcan module freescale semiconductor 24-17 pxr40 microcontroller reference manual, rev. 1 18 lprio_en local priority enable this bit is provided for backwards compatibility reasons. it controls whether the local priority feature is enabled or not. it is used to ext end the id used during the arbitrati on process. with this extended id concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted id still has 11-bit for standard frames and 29-bit for extended frames. 0 local priority disabled 1 local priority enabled 19 aen abort enable this bit is supplied for backwards compatibility reas ons. when asserted, it enables the tx abort feature. this feature guarantees a safe procedure for aborting a pending transmission, so that no frame is sent in the can bus without notification. 0 abort disabled 1 abort enabled 20?21 reserved 22?23 idam id acceptance mode this 2-bit field identifies the format of the elem ents of the rx fifo filter table, as shown in table 24-9 . note that all elements of the tabl e are configured at the same time by this field (they are all the same format). see section 24.3.3, rx fifo structure . 24?25 reserved 26?31 maxmb maximum number of message buffers this 6-bit field defines the maximum number of message buffers that will take part in the matching and arbitration processes. the reset value (0x0f) is equivalent to 16 mb configuration. this field should be changed only while the module is in freeze mode. maximum mbs in use = maxmb + 1. note: maxmb must be programmed with a value smaller or equal to the number of available message buffers, otherwise flexcan can tran smit and receive wrong messages. table 24-9. idam coding idam format explanation 00 a one full id (standard or ex tended) per filter element. 01 b two full standard ids or two partia l 14-bit extended ids per filter element. 10 c four partial 8-bit ids (standard or extended) per filter element. 11 d all frames rejected. table 24-8. flexcan_x_mcr field descriptions (continued) field description
flexcan module 24-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.3.4.2 control register (flexcan_x_ctrl) this register is defined for specifi c flexcan control features related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop back mode, listen only mode, bus off recovery behavior and interrupt enabling (bus-off, error, warni ng). it also determines th e division factor for the clock prescaler. most of the fields in this register shoul d only be changed while the module is in disable mode or in freeze mode. exceptions are the boff_msk, err_msk, twrn_msk, rwrn_msk and boff_rec bits, that can be accessed at any time. figure 24-6. control register (flexcan_x_ctrl) base + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r presdiv rjw pseg1 pseg2 w re- set: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r boff _msk err_ msk clk_ src lpb twr n_ms k rwr n_ms k 0 0 smp boff _rec tsyn lbuf lom propseg w re- set: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 24-10. flexcan_x_ctrl field descriptions field description 0?7 presdiv prescaler division factor this 8-bit field defines the ratio between the cpi cloc k frequency and the serial clock (sclock) frequency. the sclock period defines the time quantum of the can protoc ol. for the reset value, the sclock frequency is equal to the cpi clock frequency. the maximum value of this register is 0xff, that gives a minimum sclock frequency equal to the cpi clock frequency divided by 256. for more information refer to section 24.4.8.4, protocol timing. sclock frequency = cpi clock frequency / (presdiv + 1) 8?9 rjw resync jump width this 2-bit field defines the maximum number of time quanta 1 that a bit time can be changed by one re-synchronization. the valid programmable values are 0 ? 3. resync jump width = rjw + 1. 10?12 pseg1 phase segment 1 this 3-bit field defines the length of phase buffer segm ent 1 in the bit time. the valid programmable values are 0 ? 7. phase buffer segment 1 = (pseg1 + 1) x time-quanta. 13?15 pseg2 phase segment 2 this 3-bit field defines the length of phase buffer segm ent 2 in the bit time. the valid programmable values are 1 ? 7. phase buffer segment 2 = (pseg2 + 1) x time-quanta. 16 boff_ms k bus off mask this bit provides a mask for the bus off interrupt. 0 bus off interrupt disabled 1 bus off interrupt enabled
flexcan module freescale semiconductor 24-19 pxr40 microcontroller reference manual, rev. 1 17 err_msk error mask this bit provides a mask for the error interrupt. 0 error interrupt disabled 1 error interrupt enabled 18 clk_src can engine clock source this bit selects the clock so urce to the can protocol interface (cpi) to be either the system clock (driven by the pll) or the crystal oscillator clock (direct feed from the oscillator pin extal). the selected clock is the one fed to the prescaler to generate the serial clock (sclock). in orde r to guarantee reliable operation, this bit should only be changed while the module is in disable mode. see section 24.4.8.4, protocol timing, for more information. 0 the can engine clock source is the oscillator clock 1 the can engine clock source is the bus clock 19 twrn_ms k tx warning interrupt mask this bit provides a mask for the tx warning interrupt asso ciated with the twrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in flexcan_x_mcr is negated and it is read as zero when wrn_en is negated. 0 tx warning interrupt disabled 1 tx warning interrupt enabled 20 rwrn_ms k rx warning interrupt mask this bit provides a mask for the rx warning interrupt a ssociated with the rwrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in flexcan_x_mcr is negated and it is read as zero when wrn_en is negated. 0 rx warning interrupt disabled 1 rx warning interrupt enabled 21 lpb loop back this bit configures flexcan to operate in loop-back mode. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. 0 loop back disabled 1 loop back enabled 22?23 reserved 24 smp sampling mode this bit defines the sampling mode of can bits at the rx input. 0 just one sample is used to determine the bit value 1 three samples are used to determine the value of th e received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used table 24-10. flexcan_x_ctrl fiel d descriptions (continued) field description
flexcan module 24-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25 boff_re c bus off recovery mode this bit defines how flexcan recovers from bus off state. if this bit is negated, automatic recovering from bus off state occurs according to the can specification 2.0b. if t he bit is asserted, automatic recovering from bus off is disabled and the module remains in bus off state until the bi t is negated by the user. if the negation occurs before 128 sequences of 11 recessive bits are detected on the can bus, then bus off recovery happens as if the boff_rec bit had never been asserted. if the negation occu rs after 128 sequences of 11 recessive bits occurred, then flexcan will re-synchronize to the bus by waiting for 11 recessive bits before joining the bus. after negation, the boff_rec bit can be re-asserted again during bus off, but it will only be effective the next time the module enters bus off. if boff_rec was negated when the module entered bus off, asserting it during bus off will not be effective for the current bus off recovery. 0 automatic recovering from bus off state enabled, according to can spec 2.0 part b 1 automatic recovering from bus off state disabled 26 tsyn timer sync mode this bit enables a mechanism that resets the free-running timer each time a message is received in message buffer 0. this feature provides means to synchronize multiple flexcan stations with a special ?sync? message (i.e., global network time). if the fen bit in flexcan_ x_mcr is set (fifo enabled), mb8 is used for timer synchronization instead of mb0. 0 timer sync feature disabled 1 timer sync feature enabled 27 lbuf lowest buffer transmitted first this bit defines the ordering mechanism for message buff er transmission. when asserted, the lprio_en bit does not affect the priority arbitration. 0 buffer with highest priority is transmitted first 1 lowest number buffer is transmitted first 28 lom listen-only mode this bit configures flexcan to operate in listen only mode. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode [ref. 1]. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing t he rec), as if it was trying to acknowledge the message. 0 listen only mode is deactivated 1 flexcan module operates in listen only mode 29?31 propseg propagation segment this 3-bit field defines the length of the propagation se gment in the bit time. the valid programmable values are 0 ? 7. propagation segm ent time = (propseg + 1) * time-quanta. time-quantum = one sclock period. notes: 1 one time quantum is equal to the sclock period. table 24-10. flexcan_x_ctrl fiel d descriptions (continued) field description
flexcan module freescale semiconductor 24-21 pxr40 microcontroller reference manual, rev. 1 24.3.4.3 free running ti mer (flexcan_x_timer) this register represents a 16-bit free running counter that can be read and written by the cpu. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flex can bit-clock (which de fines the baud rate on the can bus). during a message transmission/recepti on, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it counts using the previously program med baud rate. du ring freeze mode, the timer is not incremented. the timer value is captured at the beginning of the identifier field of any frame on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. writing to the timer is an indirect operation. the data is first written to an auxili ary register and then an internal request/acknowledge procedur e across clock domains is executed. all this is transparent to the user, except for the fact that the data will take some tim e to be actually written to the register. if desired, software can poll the register to discove r when the data was actually written. figure 24-7. free running timer (flexcan_x_timer) base + 0x0008 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r timer w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
flexcan module 24-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.3.4.4 rx global mask (flexcan_x_rxgmask) this register is provided for legacy support. se tting the mbfen bit in flexcan_x_mcr causes the flexcan_x_rxgmask register to have no effect on the module operation. flexcan_x_rxgmask is used as acceptance mask for all rx mbs, excluding mbs 14 ? 15, which have individual mask registers. when the fen bit in flexcan_x_mcr is set (fifo enabled), the flexcan_x_rxgmask also applies to a ll elements of the id filter table, except elements 6-7, which have individual masks. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. figure 24-8. rx global mask register (flexcan_x_rxgmask) 24.3.4.5 rx 14 mask ( flexcan_x_rx14mask) this register is provided for legacy support. se tting the mbfen bit in flexcan_x_mcr causes the flexcan_x_rx14mask register to have no effect on the module operation. flexcan_x_rx14mask is used as ac ceptance mask for the identifier in message buffer 14. when the fen bit in flexcan_x_mcr is set (fifo enabled), the rxg14mask also applies to element 6 of the id filter table. this regi ster has the same structure as the rx global mask regist er. it must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. ? address offset: 0x14 ? reset value: 0xffff_ffff base + 0x0010 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 = unimplemented or reserved table 24-11. flexcan_x_rxgmask field descriptions field description 0?31 mi31?mi0 mask bits for normal rx mbs, the mask bits affect the id filter pr ogrammed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 0 the corresponding bit in the filter is ?don?t care? 1 the corresponding bit in the filter is checked against the one received
flexcan module freescale semiconductor 24-23 pxr40 microcontroller reference manual, rev. 1 24.3.4.6 rx 15 mask ( flexcan_x_rx15mask) this register is provided for legacy support. se tting the mbfen bit in flexcan_x_mcr causes the flexcan_x_rx15mask register to have no effect on the module operation. when the mbfen bit is negated, flexcan_x_rx 15mask is used as acceptance mask for the identifier in message buffer 15. when the fen bit in flexcan_x_mcr is set (fifo enabled), the rxg14mask also applies to element 7 of the id filter table. this regist er has the same structure as the rx global mask register. it must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. ? address offset: 0x18 ? reset value: 0xffff_ffff 24.3.4.7 error counter re gister (flexcan_x_ecr) this register has 2 8-bit fields re flecting the value of two flexcan error counters: transmit error counter (tx_err_counter field) and receive error counter (rx_err_counter field) . the rules for increasing and decreasing these counters are descri bed in the can protocol and are completely implemented in the flexcan module. both counters are read only except in fr eeze mode, where they can be written by the cpu. writing to the error counter register while in free ze mode is an indirect ope ration. the data is first written to an auxiliary register an d then an internal request/acknowle dge procedure acro ss clock domains is executed. all this is transparent to the user, except for the fact that the data wi ll take some time to be actually written to the register. if desired, software can poll the regist er to discover when the data was actually written. flexcan responds to any bus state as described in th e protocol, e.g. transmit ?e rror active? or ?error passive? flag, delay its transmission start time (?error passive?) and avoid any influence on the bus when in ?bus off? state. the following are the basic rules for flexcan bus state transitions. ? if the value of tx_err_counter or rx_err_counter increases to be greater than or equal to 128, the flt_conf field in the error and status register is updated to reflect ?error passive? state. ? if the flexcan state is ?error passive?, and either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while the other already sati sfies this condition, the flt_conf field in the error and status register is updated to reflect ?error active? state. ? if the value of tx_err_c ounter increases to be greater than 255, the flt_conf field in the error and status register is updated to reflect ?bus off? state, and an interrupt may be issued. the value of tx_err_counter is then reset to zero. ? if flexcan is in ?bus off? state, then tx_err_co unter is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, tx_err_counter is reset to zero a nd counts in a manner where the in ternal counter counts 11 such bits and then wraps around wh ile incrementing the tx_err_counter. when tx_err_counter reaches the value of 128, the flt_conf field in th e error and status register is updated to be ?error active? and both error counters are reset to zero. at any instance of dominant bit following
flexcan module 24-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 a stream of less than 11 consecutive recessive bits, the internal coun ter resets itself to zero without affecting the tx_err_counter value. ? if during system start-up, only one node is operati ng, then its tx_err_counter increases in each message it is trying to transmit, as a result of acknowledge erro rs (indicated by the ack_err bit in the error and status register). after the transi tion to ?error passive? state, the tx_err_counter does not increment anymore by acknow ledge errors. therefore the device never goes to the ?bus off? state. ? if the rx_err_counter increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to ?error active? state. figure 24-9. error counter register (flexcan_x_ecr) base + 0x001c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_err_counter tx_err_counter w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
flexcan module freescale semiconductor 24-25 pxr40 microcontroller reference manual, rev. 1 24.3.4.8 error and status register (flexcan_x_esr) this register reflects various error conditions, some genera l status of the de vice and it is th e source of four interrupts to the cpu. the reported er ror conditions (bits 16-21) are those th at occurred since the last time the cpu read this register. the cpu read acti on clears bits 16-23. bits 22-28 are status bits. most bits in this register are read only, excep t twrn_int, rwrn_int, boff_int and err_int, that are interrupt flags that can be cleared by writi ng ?1? to them (writing ?0? has no effect). see section 24.4.10, interrupts, for more details. figure 24-10. error and status register base + 0x0020 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 twrn _int rwrn _int w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bit1_ err bit0_ err ack_ err crc_ err frm_ err stf_ err tx_w rn rx_ wrn idle txrx flt_conf 0 boff _int err_ int 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
flexcan module 24-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 24-12. flexcan_x_esr field descriptions field description 0?13 reserved 14 twrn_int tx warning interrupt flag if the wrn_en bit in flexcan_x_mcr is asserted, the twrn_int bit is set when the tx_wrn flag transition from ?0? to ?1?, meaning that the tx error counter reached 96. if the corresponding mask bit in the control register (twrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 0 no such occurrence 1 the tx error counter transition from < 96 to ? 96 15 rwrn_int rx warning interrupt flag if the wrn_en bit in flexcan_x_mcr is asserted, the rwrn_int bit is set when the rx_wrn flag transition from ?0? to ?1?, meaning that the rx error c ounters reached 96. if the corresponding mask bit in the control register (rwrn_msk) is set, an interrupt is gene rated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 0 no such occurrence 1 the rx error counter transition from < 96 to ? 96 16 bit1_err bit1 error this bit indicates when an inconsistency occurs betw een the transmitted and the received bit in a message. 0 no such occurrence 1 at least one bit sent as recessive is received as dominant note: this bit is not set by a transmitter in case of arbitration field or ack slot, or in case of a node sending a passive error flag that detects dominant bits. 17 bit0_err bit0 error this bit indicates when an inconsistency occurs betw een the transmitted and the received bit in a message. 0 no such occurrence 1 at least one bit sent as dominant is received as recessive 18 ack_err acknowledge error this bit indicates that an acknowledge error has been det ected by the transmitter node, i.e., a dominant bit has not been detected during the ack slot. 0 no such occurrence 1 an ack error occurred since last read of this register 19 crc_err cyclic redundancy check error this bit indicates that a crc error has been detected by the receiver node, i.e., the calculated crc is different from the received. 0 no such occurrence 1 a crc error occurred since last read of this register. 20 frm_err form error this bit indicates that a form error has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 0 no such occurrence 1 a form error occurred since last read of this register 21 stf_err stuffing error this bit indicates that a stuffing error has been detected. 0 no such occurrence. 1 a stuffing error occurred since last read of this register. 22 tx_wrn tx error counter this bit indicates when repetitive errors are occurring during message transmission. 0 no such occurrence 1 tx_err_counter ? 96
flexcan module freescale semiconductor 24-27 pxr40 microcontroller reference manual, rev. 1 23 rx_wrn rx error counter this bit indicates when repetitive errors are occurring during message reception. 0 no such occurrence 1 rx_err_counter ?? 96 24 idle can bus idle state this bit indicates when can bus is in idle state. 0 no such occurrence 1 can bus is now idle 25 txrx current flexcan status (transmitting/receiving) this bit indicates if flexcan is transmitting or receiv ing a message when the can bus is not in idle state. this bit has no meaning when idle is asserted. 0 flexcan is receiving a message (idle=0) 1 flexcan is transmitting a message (idle=0) 26?27 flt_conf fault confinement state this 2-bit field indicates the confin ement state of the flexcan module, as shown below. if the lom bit in the control register is asserted, the flt_conf field will indi cate ?error passive?. since the control register is not affected by soft reset, the flt_conf field will not be affected by soft reset if the lom bit is asserted. 00 error active 01 error passive 1x bus off 28 reserved 29 boff_int ?bus off? interrupt this bit is set when flexcan enters ?bus off? state. if the corresponding mask bit in the control register (boff_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 0 no such occurrence 1 flexcan module entered ?bus off? state 30 err_int error interrupt this bit indicates that at least one of the error bits (b its 16-21) is set. if the corre sponding mask bit in the control register (err_msk) is set, an interrupt is generated to t he cpu. this bit is cleared by writing it to ?1?.writing ?0? has no effect. 0 no such occurrence 1 indicates setting of any error bi t in the error and status register 31 reserved table 24-12. flexcan_x_esr field descriptions (continued) field description
flexcan module 24-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.3.4.9 interrupt masks 2 register (flexcan_x_imask2) this register allows any num ber of a range of 32 message buffer in terrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to de termine which buffer generates an interrupt after a successf ul transmission or reception (i.e. when the corresponding flexcan_x_iflag2 bit is set). figure 24-11. interrupt masks 2 register (flexcan_x_imask2) 24.3.4.10 interrupt masks 1 register (flexcan_x_imask1) this register allows to enable or disable any number of a ra nge of 32 message buffer interrupts. it contains one interrupt mask bit per buffer, en abling the cpu to determine which bu ffer generates an interrupt after a successful transmission or rece ption (i.e., when the corresponding flexcan_x_iflag1 bit is set). figure 24-12. interrupt masks 1 register (flexcan_x_imask1) base + 0x0024 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 63m buf 62m buf 61m buf 60m buf 59m buf 58m buf 57m buf 56m buf 55m buf 54m buf 53m buf 52m buf 51m buf 50m buf 49m buf 48m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47m buf 46m buf 45m buf 44m buf 43m buf 42m buf 41m buf 40m buf 39m buf 38m buf 37m buf 36m buf 35m buf 34m buf 33m buf 32m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 24-13. flexcan_x_imask2 field descriptions field description 0?31 buf63m ?buf32 m buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb32 to mb63) interrupt. 0 the corresponding buffer interrupt is disabled 1 the corresponding buffer interrupt is enabled note: setting or clearing a bit in the flexcan_x_imask2 regist er can assert or negate an interrupt request, if the corresponding flexcan_x_iflag2 bit is set. base + 0x0028 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 31m buf 30m buf 29m buf 28m buf 27m buf 26m buf 25m buf 24m buf 23m buf 22m buf 21m buf 20m buf 19m buf 18m buf 17m buf 16m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15m buf 14m buf 13m buf 12m buf 11m buf 10m buf 9m buf 8m buf 7m buf 6m buf 5m buf 4m buf 3m buf 2m buf 1m buf 0m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
flexcan module freescale semiconductor 24-29 pxr40 microcontroller reference manual, rev. 1 24.3.4.11 interrupt flags 2 re gister (flexcan_x_iflag2) this register defines the fl ags for 32 message buffer inte rrupts. it contains one inte rrupt flag bit per buffer. each successful transmission or reception sets the corresponding flexcan_x_iflag2 bit. if the corresponding flexcan_x_imask2 bit is set, an interrupt will be generated. the interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when the aen bit in the flexcan_x_mcr is se t (abort enabled), while the flexcan_x_iflag2 bit is set for a mb configured as tx, the writing access done by cpu in to the corresponding mb will be blocked. figure 24-13. interrupt flags 2 register (flexcan_x_iflag2) table 24-14. flexcan_x_imask1 field descriptions field description 0?31 buf31m ?buf0m buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb0 to mb31) interrupt. 0 the corresponding buffer interrupt is disabled 1 the corresponding buffer interrupt is enabled note: setting or clearing a bit in the flexcan_x_imask1 regist er can assert or negate an interrupt request, if the corresponding flexcan_x_iflag1 bit is set. base + 0x002c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 63i buf 62i buf 61i buf 60i buf 59i buf 58i buf 57i buf 56i buf 55i buf 54i buf 53i buf 52i buf 51i buf 50i buf 49i buf 48i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47i buf 46i buf 45i buf 44i buf 43i buf 42i buf 41i buf 40i buf 39i buf 38i buf 37i buf 36i buf 35i buf 34i buf 33i buf 32i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 24-15. flexcan_x_iflag2 field descriptions field description 0?31 buf32i? buf63i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb32 to mb63) interrupt. 0 no such occurrence 1 the corresponding buffer has successfully completed transmission or reception
flexcan module 24-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.3.4.12 interrupt flags 1 re gister (flexcan_x_iflag1) this register defines the flags fo r 32 message buffer interrupts and fi fo interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding flexcan_x_iflag1 bit. if the co rresponding flexcan_x_imask1 bit is set, an interrupt will be generated. the interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when the aen bit in the flexcan_x_mcr is se t (abort enabled), while the flexcan_x_iflag1 bit is set for a mb configured as tx, the writing access done by cpu in to the corresponding mb will be blocked. when the fen bit in the flexcan_x_mcr is set (fifo enabled), the function of the 8 least significant interrupt flags (buf7i - buf0i) is changed to support the fifo operation. buf7i, buf6i and buf5i indicate operating conditions of the fifo , while buf4i to buf0i are not used. figure 24-14. interrupt flags 1 register (flexcan_x_iflag1) base + 0x0030 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 31i buf 30i buf 29i buf 28i buf 27i buf 26i buf 25i buf 24i buf 23i buf 22i buf 21i buf 20i buf 19i buf 18i buf 17i buf 16i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15i buf 14i buf 13i buf 12i buf 11i buf 10i buf 9i buf 8i buf 7i buf 6i buf 5i buf 4i buf 3i buf 2i buf 1i buf 0i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 24-16. flexcan_x_iflag1 field descriptions field description 0?23 buf31i? buf8i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb8 to mb31) interrupt. 0 no such occurrence 1 the corresponding mb has successfully completed transmission or reception
flexcan module freescale semiconductor 24-31 pxr40 microcontroller reference manual, rev. 1 24 buf7i buffer mb7 interrupt or ?fifo overflow? if the fifo is not enabled, this bit flags the interrupt for mb 7. if the fifo is enabled, th is flag indicates an overflow condition in the fifo (frame lost because fifo is full). 0 no such occurrence 1 mb7 completed transmission/reception or fifo overflow 25 buf6i buffer mb6 interrupt or ?fifo warning? if the fifo is not enabled, this bit flags the interrupt for mb6. if the fifo is enabled, this flag indicates that 5 out of 6 buffers of the fifo are already occupied (fifo almost full). 0 no such occurrence 1 mb6 completed transmission/reception or fifo almost full 26 buf5i buffer mb5 interrupt or ?frames available in fifo? if the fifo is not enabled, this bit flags the interrupt for mb5. if the fifo is enabled, this flag indicates that at least one frame is available to be read from the fifo. 0 no such occurrence 1 mb5 completed transmission/reception or frames available in the fifo 27?31 buf4i?b uf0i buffer mb i interrupt or ?reserved? if the fifo is not enabled, these bits flag the interrupts for mb0 to mb4. if the fifo is enabled, these flags are not used and must be considered as reserved locations. 0 no such occurrence 1 corresponding mb completed transmission/reception table 24-16. flexcan_x_iflag1 fi eld descriptions (continued) field description
flexcan module 24-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.3.4.13 rx individual mask registers (rximr0 ? rximr63) these registers are used as acceptan ce masks for id filtering in rx mbs and the fifo. if the fifo is not enabled, one mask register is provi ded for each available message buff er, providing id masking capability on a per message buffer basis. when the fifo is en abled (fen bit in flexcan_x_mcr is set), the first 8 mask registers apply to the 8 el ements of the fifo filter table (on a one-to-one co rrespondence), while the rest of the registers apply to the regular mbs, starting from mb8. the individual rx mask regi sters are implemented in ram, so they are not affected by reset and must be explicitly initialized prior to any reception. furtherm ore, they can only be accessed by the cpu while the module is in freeze mode. out of freeze mode, write accesse s are blocked and read accesses will return ?all zeros?. furthermore, if the mbfen bit in th e flexcan_x_mcr register is negated, any read or write operation to these regi sters results in access error. figure 24-15. rx individual mask registers (rximr0 - rximr63) 24.4 functional description 24.4.1 overview the flexcan module is a can protocol engine with a very flexible mailbox system for transmitting and receiving can frames. the mailbox syst em is composed by a set of 64 message buffers (mb) that store configuration and control data, time stamp, message id and data (see section 24.3.2, message buffer structure ). the memory corresponding to the first 8 mbs can be configured to support a fifo reception scheme with a powerful id filteri ng mechanism, capable of checking in coming frames against a table of ids (up to 8 extended ids or 16 standard ids or 32 8-bi t id slices), each one wi th its own i ndividual mask register. simultaneous reception through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to store received frames only in to mbs that have the same id programmed on its id field. a masking scheme makes it possibl e to match the id programmed on the mb with a range of ids on received can frames. for tr ansmission, an arbitratio n algorithm decides the base + 0x0880?0x097f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 table 24-17. rximr0 ? rximr63 field descriptions field description 0?31 mi31?mi0 mask bits for normal rx mbs, the mask bits affect the id filter pr ogrammed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 0 the corresponding bit in the filter is ?don?t care? 1 the corresponding bit in the filter is checked against the one received\
flexcan module freescale semiconductor 24-33 pxr40 microcontroller reference manual, rev. 1 prioritization of mbs to be transm itted based on the message id (optionally augmented by 3 local priority bits) or the mb ordering. before proceeding with the functional description, an important concept must be explained. a message buffer is said to be ?active? at a given time if it can participate in the matchi ng and arbitrat ion algorithms that are happening at that time. an rx mb with a ?0000? code is inactive (refer to table 24-5 ). similarly, a tx mb with a ?1000? or ?1001? c ode is also inac tive (refer to table 24-6 ). an mb not programmed with ?0000?, ?1000? or ?1001? will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that mb (see section 24.4.6.2, message buffer deactivation ). 24.4.2 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: ? if the mb is active (transmission pending), write ? 1000? to the code field to deactivate the mb. the deactivated mb can transmit without setting iflag and wit hout updating the c ode field (see section 24.4.6.2, message buffer deactivation ). ? write the id word. ? write the data bytes. ? write the length, control and c ode fields of the control and status word to activate the mb. once the mb is activated in the fourth step, it will participate into the arbitrat ion process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, a status flag is set in the interrupt flag regi ster and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code fi eld after transmission de pends on the code that was used to activate the mb in step four (see table 24-5 and table 24-6 in section 24.3.2, message buffer structure ). when the abort feature is enabled (aen in flexcan_x_mcr is asserted), after the interrupt flag is asserted for a mb configured as transmit buffer, the mb is bl ocked, therefore the cpu is not able to update it until the interrupt flag be negated by cpu. it means that the cpu must cl ear the corresponding iflag before starting to prepare this mb for a new transmission or reception. 24.4.3 arbitration process the arbitration process is an algorithm executed by the mbm that scans th e whole mb memory looking for the highest priority message to be transmitted. all mbs program med as transmit buffers will be scanned to find the lowest id 1 or the lowest mb number or the hi ghest priority, depending on the lbuf and lprio_en bits on the control register. the arbitr ation process is triggered in the following events: ? during the crc field of the can frame ? during the error delimiter field of the can frame 1. actually, if lbuf is negated, the arbitration considers not only the id, but also the rtr and ide bits placed inside the id at the same positions they are transmitted in the can frame.
flexcan module 24-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? during intermission, if the winner mb defined in a previous arbitration was deactivated, or if there was no mb to transmit, but the cpu wrote to the c/s word of a ny mb after the previous arbitration finished ? when mbm is in idle or bus off state and the cpu writes to the c/s word of any mb ? upon leaving freeze mode when lbuf is asserted, the lprio_en bit has no effect and the lowest number buffer is transmitted first. when lbuf and lprio_en ar e both negated, the mb with the lowest id is transmitted fi rst but. if lbuf is negated and lprio_en is asserte d, the prio bits augment the id us ed during the arb itration process. with this extended id concept, arbi tration is done based on the full 32- bit id and the prio bits define which mb should be transmitted first, therefore mbs wi th prio = 000 have higher pr iority. if two or more mbs have the same priority, the regul ar id will determine th e priority of transmission. if two or more mbs have the same priority (3 extra bits) and the same regular id, the lowest mb will be transmitted first. once the highest priority mb is sel ected, it is transferred to a tem porary storage space called serial message buffer (smb), which has the same structure as a normal mb but is not user accessible. this operation is called ?move-out? and after it is done, wr ite access to the corresponding mb is blocked (if the aen bit in flexcan_x_mcr is a sserted). the write access is rel eased in the following events: ? after the mb is transmitted ? flexcan enters in halt or bus off ? flexcan loses the bus arbitration or th ere is an error during the transmission at the first opportunity window on the can bus, the me ssage on the smb is tran smitted according to the can protocol rules. flexc an transmits up to eight data bytes, even if the dlc (data length code) value is bigger. 24.4.4 receive process to be able to receive can frames into the mail box mbs, the cpu must prep are one or more message buffers for reception by executing the following steps: ? if the mb has a pending transmission, write an abort code (?1001?) to the code field of the control and status word to request an abortion of the transmission, then r ead back the code field and the iflag register to check if the transmission was aborted (see section 24.4.6.1, transmission abort mechanism ). if backwards compatibili ty is desired (aen in flexcan_x_mcr negated), just wr ite ?1000? to the code field to inactivate the mb, but then the pending frame may be transm itted without notification (see section 24.4.6.2, message buffer deactivation ). if the mb already programmed as a receive r, just write ?0000? to the code field of the control and status word to keep the mb inactive. ? write the id word ? write ?0100? to the code field of the c ontrol and status word to activate the mb once the mb is activated in the third step, it will be able to receive frames that match the programmed id. at the end of a successful reception, the mb is updated by the mbm as follows:
flexcan module freescale semiconductor 24-35 pxr40 microcontroller reference manual, rev. 1 ? the value of the free running timer is written into the time stamp field ? the received id, data (8 bytes at most) and length fields are stored ? the code field in the control and status word is updated (see table 24-5 and table 24-6 in section 24.3.2, message buffer structure ) ? a status flag is set in the interrupt flag regist er and an interrupt is generated if allowed by the corresponding interrupt mask register bit upon receiving the mb interrupt, the cpu should se rvice the received frame using the following procedure: ? read the control and status word (mandatory ? activates an internal lock for this buffer) ? read the id field (optional ? needed only if a mask was used) ? read the data field ? read the free running timer (optional ? releases the internal lock) upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the mb until this bit is negate d. reading the free running timer is not mandatory. if not executed the mb remains locke d, unless the cpu reads th e c/s word of another mb. note that only a single mb is locked at a time. th e only mandatory cpu read operation is the one on the control and status word to assure data coherency (see section 24.4.6, data coherence ). the cpu should synchronize to frame reception by the status flag bit for the specific mb in one of the iflag registers and not by the code field of that mb. polling the co de field does not work because once a frame was received and the cpu services the mb (by reading the c/s word followed by unlocking the mb), the code field will not return to empt y. it will remain full, as explained in table 24-5 . if the cpu tries to workaround this behavi or by writing to the c/s word to force an empty c ode after reading the mb, the mb is actually deactiva ted from any currently ongoing matching process. as a result, a newly received frame matching the id of th at mb may be lost. in summary: never do polling by reading directly the c/s word of the mbs. instead, read the iflag registers. note that the received id field is al ways stored in the matching mb, thus the contents of the id field in an mb may change if the match was due to masking. note also that flexcan does r eceive frames transmitted by itself if there exists an rx matching mb, provi ded the srx_dis bit in the flexcan_x_mcr is not asserted. if srx_dis is asserted, fl excan will not store fram es transmitted by itself in any mb, even if it contains a matching mb, and no in terrupt flag or interrupt signal w ill be generated due to the frame reception. to be able to receive can frames through the fifo, the cpu must enab le and configure the fifo during freeze mode (see section 24.4.7, rx fifo ). upon receiving the frames avai lable interrupt from fifo, the cpu should service the received fram e using the following procedure: ? read the control and status word (optional ? ne eded only if a mask wa s used for ide and rtr bits) ? read the id field (optional ? needed only if a mask was used) ? read the data field
flexcan module 24-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? clear the frames available interr upt (mandatory ? release the buffe r and allow the cpu to read the next fifo entry) 24.4.5 matching process the matching process is an algorithm executed by th e mbm that scans the mb memory looking for rx mbs programmed with the same id as the one receiv ed from the can bus. if the fifo is enabled, the 8-entry id table from fifo is sca nned first and then, if a match is not found within the fifo table, the other mbs are scanned. in the event that the fifo is full, the matching algorithm will always look for a matching mb outside the fifo region. when the frame is received, it is te mporarily stored in a hi dden auxiliary mb called serial message buffer (smb). the matching process takes pl ace during the crc field of the receiv ed frame. if a matching id is found in the fifo table or in one of the regular mbs, the contents of the smb will be transferred to the fifo or to the matched mb during the 6th bit of the end-of-frame field of the can protocol. this operation is called ?move-in?. if a ny protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. for the regular mailbox mbs, an mb is said to be ?free to receive? a new frame if the following conditions are satisfied: ? the mb is not locked (see section 24.4.6.3, message buffer lock mechanism ) ? the code field is either empty or else it is full or overrun but the cpu has already serviced the mb (read the c/s word and then unlocked the mb) if the first mb with a matching id is not ?free to receive? the new frame, then the matching algorithm keeps looking for another free mb until it finds one. if it can not find one that is fr ee, then it will overwrite the last matching mb (unless it is locked) and set the code field to overrun (refer to table 24-5 and table 24-6 ). if the last matching mb is locked, then th e new message remains in the smb, waiting for the mb to be unlocked (see section 24.4.6.3, message buff er lock mechanism ). suppose, for example, that the fifo is disabled a nd there are two mbs with the same id, and flexcan starts receiving messages with that id . let us say that these mbs are the second and the fifth in the array. when the first message arrives, the matching algorithm will find the first match in mb number 2. the code of this mb is empty, so the message is stored there. when the second message arrives, the matching algorithm will find mb number 2 again, but it is not ?free to receive,? so it will keep looking and find mb number 5 and store the message there. if yet anothe r message with the same id arrives, the matching algorithm finds out that there are no matching mbs that are ?free to receiv e,? so it decides to overwrite the last matched mb, which is number 5. in doing so, it se ts the code field of th e mb to indicate overrun. the ability to match the same id in more than one mb can be exploited to implement a reception queue (in addition to the full featured fi fo) to allow more time for the cpu to service the mbs. by programming more than one mb with the same id, received me ssages will be queued into the mbs. the cpu can examine the time stamp field of the mbs to dete rmine the order in which the messages arrived. the matching algorithm described above can be changed to be the same one used in previous versions of the flexcan module. when the mbfen bit in f lexcan_x_mcr is negated, the matching algorithm
flexcan module freescale semiconductor 24-37 pxr40 microcontroller reference manual, rev. 1 stops at the first mb with a matchi ng id that it founds, whether this mb is free or not. as a result, the message queueing feature does not wo rk if the mbfen bit is negated. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per mb. please refer to section 24.3.4.13, rx individual mask registers (rximr0?rximr63). during the matching algorithm, if a ma sk bit is asserted, th en the corresponding id bi t is compared. if the mask bit is negated, the corresponding id bit is ?d on?t care?. please note th at the individual mask registers are implemented in ram, so they are not initialized out of reset. also, they can only be programmed if the mbfen bit is asserted and while the module is in freeze mode. flexcan also supports an alternate masking sche me with only three mask registers (rgxmask, flexcan_x_rx14mask and flexcan_x_rx15mas k) for backwards compatibility. this alternate masking scheme is enab led when the mbfen bit in the flexcan_x_mcr register is negated. 24.4.6 data coherence in order to maintain data cohere ncy and flexcan proper ope ration, the cpu must obe y the rules described in section 24.4.2, transmit process and section 24.4.4, receive process . any form of cpu accessing an mb structure within flexcan ot her than those specified may cause flexcan to behave in an unpredictable way. 24.4.6.1 transmission abort mechanism the abort mechanism provides a safe way to request the abortion of a pending transmission. a feedback mechanism is provided to inform th e cpu if the transmission was aborte d or if the frame could not be aborted and was transmitted instead. in order to maintain backwards compatibility, the abort mechanism must be explicitly enabled by assert ing the aen bit in the flexcan_x_mcr. in order to abort a transmission, the cpu must write a specific abort code (1001) to the code field of the control and status word. when the abort mechanism is enabled, the active mbs configured as transmission must be aborte d first and then they may be updated. if th e abort code is written to an mb that is currently being transmitted, or to an mb that was already loaded into th e smb for transmission, the write operation is blocked and the mb is not deactivated, but the abort request is ca ptured and kept pending until one of the followi ng conditions are satisfied: ? the module loses the bus arbitration ? there is an error during the transmission ? the module is put into freeze mode if none of conditions above are reache d, the mb is transmitted correctly, the interrupt flag is set in the iflag register and an interrupt to the cpu is generated (if enabled). the abort request is automatically cleared when the interrupt fl ag is set. in the other hand, if one of the above conditions is reached, the frame is not transmitted, therefore the abort code is written into the code field, the interrupt flag is set in the iflag and an interrupt is (opt ionally) generated to the cpu. if the cpu writes the abort code before the transmissi on begins internally, then the write operation is not blocked, therefore the mb is updated and no interrupt flag is set. in th is way the cpu just needs to read the abort code to make sure the active mb was deactivated. although th e aen bit is asserted and the cpu
flexcan module 24-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 wrote the abort code, in this case the mb is deactiv ated and not aborted, because the transmission did not start yet. one mb is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. the abort procedure can be summarized as follows: ? cpu writes 1001 into the code field of the c/s word ? cpu reads the code field and compares it to the value that was written ? if the code field that was read is different from the value that was written, the cpu must read the corresponding iflag to check if th e frame was transmitte d or it is being cu rrently transmitted. if the corresponding iflag is set, the frame was tr ansmitted. if the corresponding iflag is reset, the cpu must wait for it to be se t, and then the cpu must read th e code field to check if the mb was aborted (code=1001) or it was transmitted (code=1000). note an abort request to a txmb can bloc k any write operation into its code field. therefore, the txmb cannot be aborted or deactivated until it completes a transmission by winn ing the can bus arbitration. 24.4.6.2 message buffer deactivation deactivation is mechanism pr ovided to maintain data coherence when the cpu writes to the control and status word of active mbs out of freeze mode. any cpu write access to the control and status word of an mb causes that mb to be excluded from the tran smit or receive processes during the current matching or arbitration round. the de activation is temporary, affecting only for the current match/arbitration round. the purpose of deactivation is data coherency. the match/arbitration process scans the mbs to decide which mb to transmit or receive. if the cpu updates the mb in the middle of a match or arbitration process, the data of that mb ma y no longer be coherent, therefore de activation of that mb is done. even with the coherence mechanism described above, writing to the control and status word of active mbs when not in freeze mode may produ ce undesirable results. examples are: ? matching and arbitration are one-p ass processes. if mbs are deactivated after they are scanned, no re-evaluation is done to determine a new match/ winner. if an rx mb with a matching id is deactivated during the matching proce ss after it was scanned, then this mb is marked as invalid to receive the frame, and flexcan wi ll keep looking for another matc hing mb within the ones it has not scanned yet. if it can not find one, then the message will be lost . suppose, for example, that two mbs have a matching id to a recei ved frame, and the user deactivat ed the first matching mb after flexcan has scanned the second. the received frame will be lost ev en if the second matching mb was ?free to receive?. ? if a tx mb containing th e lowest id is deactivated after fl excan has scanned it, then flexcan will look for another winner within the mbs that it has not scanned yet. ther efore, it may transmit an mb with id that may not be the lowest at the time because a lo wer id might be present in one of the mbs that it had already scanned before the deactivation. ? there is a point in time until which the deactivati on of a tx mb causes it not to be transmitted (end of move-out). after this point, it is transmitted but no interrupt is issued and the code field is not
flexcan module freescale semiconductor 24-39 pxr40 microcontroller reference manual, rev. 1 updated. in order to avoid this situati on, the abort procedures described in section 24.4.6.1, transmission abort mechanism , should be used. 24.4.6.3 message buffer lock mechanism besides mb deactivation, flexcan ha s another data coherence mechanis m for the receive process. when the cpu reads the control and status word of an ?active not empty? rx mb, flexcan assumes that the cpu wants to read the whole mb in an atomic operation, and thus it sets an internal lock flag for that mb. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another mb. th e mb locking is done to prevent a new frame to be written into the mb while the cpu is reading it. note the locking mechanism only applies to rx mbs which have a code different than inactive (?0000?) or empty 1 (?0100?). also, tx mbs can not be locked. suppose, for example, that the fifo is disabled and the second and the fifth mbs of the array are programmed with the same id, and flexcan has already received and stored messages into these two mbs. suppose now that the cpu decide s to read mb number 5 and at th e same time another message with the same id is arriving. when the cpu reads the cont rol and status word of mb number 5, this mb is locked. the new message arrives and the matching algorithm finds out that there are no ?free to receive? mbs, so it decides to override mb number 5. however, this mb is lock ed, so the new me ssage can not be written there. it will remain in the smb waiting fo r the mb to be unlocked, a nd only then will be written to the mb. if the mb is not unlocke d in time and yet anothe r new message with the same id arrives, then the new message overwrites th e one on the smb and there wi ll be no indication of lo st messages either in the code field of the mb or in the error and status register. while the message is being moved-in from the smb to the mb, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the mb until the busy bit is negated. note if the busy bit is asserted or if the mb is empty, then reading the control and status word does not lock the mb. deactivation takes precedence over lock ing. if the cpu deactivates a locked rx mb, then its lock status is negated and the mb is marked as invalid fo r the current matching round. any pending message on the smb will not be transferred anymore to the mb. 24.4.7 rx fifo the receive-only fifo is enabled by asserting the fen bit in the fl excan_x_mcr. the reset value of this bit is zero to maintain softwa re backwards compatibilit y with previous versions of the module that did not have the fifo feature. when the fifo is enabled, the memory re gion normally occupied by the first 1. in previous flexcan versions, reading the c/s word locked th e mb even if it was empty. this behavior will be honoured when the mbfen bit is negated.
flexcan module 24-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 8 mbs (0x80-0xff) is now reserved for use of the fifo engine (see section 24.3.3, rx fifo structure ). management of read and write pointers is done inte rnally by the fifo engine. the cpu can read the received frames sequentially, in the order they we re received, by repeatedly accessing a message buffer structure at the beginning of the memory. the fifo can store up to 6 frames pending service by the cpu. an interr upt is sent to the cpu when new frames are available in the fifo. upon receiving the interrupt, the cpu must read the frame (accessing an mb in the 0x80 address) and then clear the interrupt. the act of clearing the interrupt triggers the fifo engine to replace the mb in 0x80 with the next frame in the queue, and then issue another interrupt to the cpu. if the fifo is full and more frames continue to be received, an overflow interrupt is issued to the cpu and subsequent frames are not accepted until the cpu creates space in the fifo by reading one or more frames. a warning interrupt is also gene rated when 5 frames are accumulated in the fifo. a powerful filtering scheme is provided to accept onl y frames intended for the target application, thus reducing the interrupt servicing work load. the filtering criteria is sp ecified by programmin g a table of 8 32-bit registers that can be configured to one of the following formats (see also section 24.3.3, rx fifo structure ): ? format a: 8 extended or standard ids (including ide and rtr) ? format b: 16 standard ids or 16 extended 14-bit id slices (i ncluding ide and rtr) ? format c: 32 standard or extended 8-bit id slices note a chosen format is applied to all 8 regi sters of the filter table. it is not possible to mix formats within the table. the eight elements of the filter ta ble are individually affected by the first eight individual mask registers (rximr0 - rximr7), allowing very powerful filtering criteria to be defined. the rest of the rximr, starting from rxim8, continue to affect the regular mb s, starting from mb8. if the mbfen bit is negated (or if the rximr are not available for the particular mcu), then the fifo filter table is affected by the legacy mask registers as follow s: element 6 is affected by f lexcan_x_rx14mask, element 7 is affected by flexcan_x_rx15mask and the othe r elements (0 to 5) are affected by flexcan_x_rxgmask. 24.4.7.1 precautions when using global mask and i ndividual mask registers mask filtering alignment is affected base d on the setting of the fen and bcc of mcr. table 24-18 table shows recommended actions depe nding on fen and bcc settings.
flexcan module freescale semiconductor 24-41 pxr40 microcontroller reference manual, rev. 1 24.4.8 can protocol related features 24.4.8.1 remote frames a remote frame is a special kind of frame. the user can program a mb to be a request remote frame by writing the mb as transmit with th e rtr bit set to ?1?. after the remote request frame is transmitted successfully, the mb becomes a receive message buffer, with the same id as before. when a remote request frame is received by the flex can module, its id is compared to the ids of the transmit message buffers with the code field ?1010?. if there is a ma tching id, then this mb frame is transmitted. note that if the matching mb has the rtr bit set, then the fl excan module transmits a remote frame as a response. a received remote request frame is not stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask re gisters are not used in remote fram e matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was re ceived and matched an mb, this message buffer immediately enters the internal arbi tration process, but is considered as normal tx mb, with no higher priority. the data length of this fr ame is independent of the dlc field in the remote frame that initiated its transmission. 24.4.8.2 overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: ? detection of a dominant bit in th e first/second bit of intermission table 24-18. recommended fen and bcc settings case mcr[fen] rxfifo mcr[bcc] rx individual mask notes case 1 fen = 0 bcc = 0 rxgmask, rx14mask, and rx15mask can safely be used. this allows backwards compatibility to older devices (e.g., devices without the individual masks feature). in this case, individual masks are not used. case 2 fen = 1 bcc = 0 1st alternative: do not use rxgmask, rx14mask, and rx15mask in this case, leave the masks in their reset state. case 3 fen = 1 bcc = 0 2nd alternative: do not configure any mb as rx (i.e., let all mbs as either tx or inactive). in this case, rxgmask, rx14mask, and rx15mask can be used to affect id tables without affecting the filtering process for rx mbs. case 4 don?t care bcc = 1 if mcr[bcc] = 1, then the rximrs are enabled. thus, rxgmask, rx14mask, and rx15mask are not used. particularly, when mcr[fen] = 0, rxfifo is disabled; rxgmask, rx14mask, and rx 15mask do not affect filtering. individual masks are used.
flexcan module 24-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) ? detection of a dominant bit at th e 8th bit (last) of error fram e delimiter or overload frame delimiter 24.4.8.3 time stamp the value of the free running timer is sampled at the beginning of th e identifier field on the can bus, and is stored at the end of ?move -in? in the time stamp field, provi ding network behavior with respect to time. note that the free running timer can be reset upon a specific frame recepti on, enabling network time synchronization. refer to tsyn description in section 24.3.4.2, control regi ster (flexcan_x_ctrl). 24.4.8.4 protocol timing figure 24-16 shows the structure of the clock generation ci rcuitry that feeds the can protocol interface (cpi) sub-module. the clock source bit (clk_src) in the flexcan _x_ctrl register defines whether the internal clock is connected to the output of a crys tal oscillator (oscillator cl ock) or to the peripheral (system) clock from pll). in orde r to guarantee reliable operation, th e clock source should be selected while the module is in disable mode (bit md is set in the module configuration register). figure 24-16. can engine clocking scheme the crystal oscillator cloc k should be selected whenever a tight to lerance (up to 0.1%) is required in the can bus timing. the crystal oscillator clock has better jitter pe rformance than pll generated clocks. the flexcan module supports a variet y of means to setup bi t timing parameters th at are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, propseg, pseg1, pseg2 and rjw. see section 24.3.4.2, control register (flexcan_x_ctrl). the presdiv field controls a prescal er that generates the serial cloc k (sclock), whose period defines the ?time quantum? used to compose th e can waveform. a time quantum is the atomic unit of time handled by the can engine. a bit time is subdivided into three segments 1 (reference figure 24-17 and table 24-19 ): peripheral clock (pll) oscillator clock (xtal) clk_src prescaler (1 .. 256) sclock cpi clock f tq f canclk prescaler v alue t ?? ------------------- --------------------- --------------- =
flexcan module freescale semiconductor 24-43 pxr40 microcontroller reference manual, rev. 1 ? sync_seg: this segment has a fixed length of one time quantum. signal e dges are expected to happen within this section ? time segment 1: this segment includes the propa gation segment and the phase segment 1 of the can standard. it can be programmed by setti ng the propseg and the pseg1 fields of the flexcan_x_ctrl register so that their sum (plu s 2) is in the range of 4 to 16 time quanta ? time segment 2: this segment represents the ph ase segment 2 of the can standard. it can be programmed by setting the pse g2 field of the flexcan_x_ctrl re gister (plus 1) to be 2 to 8 time quanta long figure 24-17. segments within the bit time table 24-20 gives an overview of the can compliant segmen t settings and the related parameter values. 1. for further explanation of the underlying concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol specificatio n dated september 1991 for bit timing. table 24-19. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. bit rate f tq number of time quanta tt t ?? ------------------- ------------------ ----------------- ------------------ ---------------- - = t sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point
flexcan module 24-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. 24.4.8.5 arbitration a nd matching timing during normal transmission or rece ption of frames, the arbitrati on, matching, move-in and move-out processes are executed during certain time windows inside the can frame, as shown in figure 24-18 . figure 24-18. arbitration, match and move time windows when doing matching and arbitration, flexcan needs to scan the whole message bu ffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: ? a valid can bit timing must be programmed, as indicated in table 24-20 ? the peripheral clock frequency can not be smaller than the oscillator clock frequency, i.e. the pll can not be programmed to divi de down the oscillator clock ? there must be a minimum ratio between the peri pheral clock frequency and the can bit rate, as specified in table 24-21 table 24-20. can standard compliant bit time segment settings time segment 1 time segment 2 re-synchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4 crc (15) eof (7) interm start move matching/arbitration window (24 bits) move (bit 6) window
flexcan module freescale semiconductor 24-45 pxr40 microcontroller reference manual, rev. 1 a direct consequence of the first re quirement is that the minimum numbe r of time quanta per can bit must be 8, so the oscillator cl ock frequency should be at least 8 times the can bit ra te. the minimum frequency ratio specified in table 24-21 can be achieved by choosing a high e nough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (presdiv, propseg, pseg1, pseg2). as an example, taking the case of 64 mbs, if the oscillator and peripheral clock frequencies are e qual and the can bit timing is progr ammed to have 8 time quanta per bit, then the prescaler factor (pre sdiv + 1) should be at least 2. for prescaler factor equal to one and can bit timing with 8 time quanta per bit, the ratio between peripheral and os cillator clock frequencies should be at least 2. 24.4.9 modes of operation details 24.4.9.1 freeze mode this mode is entered by asserting the halt bit in the flexcan_x_mcr register or when the mcu is put into debug mode. in both cases it is also n ecessary that the frz bit is asserted in the flexcan_x_mcr register and the m odule is not in any of the low pow er modes (disable, stop). when freeze mode is requested dur ing transmission or recepti on, flexcan does the following: ? waits to be in either intermission, passive error, bus off or idle state ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores the rx input pin and dr ives the tx pin as recessive ? stops the prescaler, thus halt ing all can prot ocol activities ? grants write access to the erro r counters register, which is read-only in other modes ? sets the not_rdy and frz_ ack bits in flexcan_x_mcr after requesting freeze mode, the user must wa it for the frz_ack bit to be asserted in flexcan_x_mcr before executin g any other action, otherwise flexcan may operate in an unpredictable way. in freeze mode, all memory mapped registers are accessible. exiting freeze mode is done in one of the following ways: ? cpu negates the frz bit in the flexcan_x_mcr register ? the mcu is removed from debug mode and/or the halt bit is negated once out of freeze mode, flexcan tries to re-synchr onize to the can bus by waiting for 11 consecutive recessive bits. table 24-21. minimum ratio between peri pheral clock frequency and can bit rate number of message buffers minimum ratio 16 8 32 8 64 16
flexcan module 24-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.4.9.2 module disable mode this low power mode is entered when the mdis bit in the flexcan_x_mcr register is asserted. if the flexcan module is disabled during freeze mode, the mo dule sends a request to di sable the clocks to the can protocol interface (cpi) and message buffer management (mbm) sub-modules, sets the mdisack bit and negates the frz_ac k bit. if the module is disabled during transmissi on or reception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for th e third bit of intermission and then checks it to be recessive ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? shuts down the clocks to the cpi and mbm sub-modules ? sets the not_rdy and mdisack bits in flexcan_x_mcr the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the free running timer, the error counter register and the message buffers, which cannot be accessed when the module is in disable mode . exiting from this mode is done by negating the mdis bit, which will resume the clocks and negate the mdisack bit. 24.4.9.3 stop mode this is a system low power mode in which all mcu clocks are st opped for maximum power savings. if flexcan receives the global stop mode request during freeze mode, it sets the mdisack bit, negates the frz_ack bit and then sends a stop acknowledge signal to the cpu, in order to shut down the clocks globally. if stop mode is requested during tran smission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or el se waits for the third bit of intermission and checks it to be recessive ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? sets the not_rdy and mdisack bits in flexcan_x_mcr ? sends a stop acknowledge signal to the cpu, so that it can shut down the clocks globally exiting stop mode is done by cpu resuming th e clocks and removing the stop mode request. 24.4.10 interrupts the module can generate up to 69 inte rrupt sources (64 interrupts due to message buffers and 5 interrupts due to ored interrupts from mbs, bus off, error, tx warning, and rx warning). the number of actual sources depends on the configur ed number of message buffers. each one of the message buffers can be an interrupt source, if its co rresponding imask bi t is set. there is no distinction between tx and rx interrupts for a particular buffer, under the assumption that the buffer is initialized for eith er transmission or reception. each of the buffers has assi gned a flag bit in the iflag
flexcan module freescale semiconductor 24-47 pxr40 microcontroller reference manual, rev. 1 registers. the bit is set when th e corresponding buffer completes a succ essful transmission/reception and is cleared when the cpu writes it to ?1? (unless another interrupt is gene rated at the same time). note it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulati on instructions (bset) must not be used to clear interrupt flags. thes e instructions may cause accidental clearing of interrupt flags which are se t after entering the current interrupt service routine. if the rx fifo is enabled (bit fen on flexcan_x_m cr set), the interrupts co rresponding to mbs 0 to 7 have a different behavior. bit 7 of the flexca n_x_iflag1 becomes the ?fifo overflow? flag; bit 6 becomes the fifo warning flag, bi t 5 becomes the ?frames available in fifo flag? and bits 4-0 are unused. see section 24.3.4.12, interrupt flags 1 register (flexcan_x_iflag1), for more information. a combined interrupt for all mbs is also generated by an or of all the interrupt sources from mbs. this interrupt gets generated when any of the mbs generate s an interrupt. in this case the cpu must read the iflag registers to determine wh ich mb caused the interrupt. the other 4 interrupt sources (bus off, error, tx wa rning, and rx warning) generate interrupts like the mb ones, and can be read from th e error and status register. the bu s off, error, tx warning and rx warning interrupt mask bits are located in the control register. 24.4.11 bus interface the cpu access to flexcan registers ar e subject to the following rules: ? read and write access to supe rvisor registers in user mo de results in access error. ? read and write access to unimpleme nted or reserved address space also results in access error. any access to unimplemented mb or rx individual mask register locati ons results in access error. any access to the rx individual mask register sp ace when the mbfen bit in flexcan_x_mcr is negated results in access error. ? if maxmb is programmed with a value smaller than the available number of mbs, then the unused memory space can be used as general pu rpose ram space. note that the rx individual mask registers can only be accessed in freeze mode , and this is still true for unused space within this memory. note also that reserved words wi thin ram cannot be used. as an example, suppose flexcan is configured with 64 mbs and maxmb is program med with zero. the maximum number of mbs in this case b ecomes one. the mb memory star ts at 0x0060, but the space from 0x0060 to 0x007f is reserved (for smb usage), and the space fr om 0x0080 to 0x008f is used by the one mb. this leaves us with the availabl e space from 0x0090 to 0x047f . the available memory in the mask registers space would be from 0x0884 to 0x097f. note unused mb space must not be us ed as general purpose ram while flexcan is transmitting an d receiving can frames.
flexcan module 24-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 24.5 initialization/application information this section provide instructions for initializing the flexcan module. 24.5.1 flexcan initialization sequence the flexcan module may be reset in three ways: ? mcu level hard reset, which resets all memory mapped re gisters asynchronously ? mcu level soft reset, which rese ts some of the memory mapped re gisters synchronous ly (refer to table 24-2 to see what registers are affected by soft reset) ? soft_rst bit in flexcan_x_mcr, which has the same effect as the mcu level soft reset soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to full y propagate its effects. the soft_rst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset can not be applied while clocks ar e shut down in any of the low power modes. the low power mode should be exited and the cloc ks resumed before applying soft reset. the clock source (clk_src bit) should be selected while the module is in disa ble mode. after the clock source is selected and the module is enabled (mdis bit negated), fl excan automatically goes to freeze mode. in freeze mode, flexcan is un-synchronized to the can bus, the halt and frz bits in flexcan_x_mcr register are set, the internal st ate machines are disabl ed and the frz_ack and not_rdy bits in the flexcan_x_mcr register are set. the tx pin is in recessive state and flexcan does not initiate any transmission or reception of can frames . note that the message buffers and the rx individual mask registers are not affected by rese t, so they are not automatically initialized. for any configuration change/initialization it is re quired that flexcan is put into freeze mode (see section 24.4.9.1, freeze mode ). the following is a generic initia lization sequence applicable to the flexcan module: ? initialize the module configuration register ? enable the individual filtering per mb and r eception queue features by setting the mbfen bit ? enable the warning interrupts by setting the wrn_en bit ? if required, disable frame self re ception by setting the srx_dis bit ? enable the fifo by setting the fen bit ? enable the abort mechanism by setting the aen bit ? enable the local priority feature by setting the lprio_en bit ? initialize the control register ? determine the bit timing parame ters: propseg, pseg1, pseg2, rjw ? determine the bit rate by programming the presdiv field ? determine the internal ar bitration mode (lbuf bit)
flexcan module freescale semiconductor 24-49 pxr40 microcontroller reference manual, rev. 1 ? initialize the message buffers ? the control and status word of al l message buffers mu st be initialized ? if fifo was enabled, the 8-entr y id table must be initialized ? other entries in each message buffer should be initia lized as required ? initialize the rx individual mask registers ? set required interrupt mask bits in the imask registers (for all mb interrupts), in flexcan_x_ctrl register (for bus off and error interrupts) ? negate the halt bit in flexcan_x_mcr starting with the last event, flexcan attempts to synchronize to the can bus. 24.5.2 flexcan addressing an d ram size configurations there are 3 ram configurations that can be impl emented within the flexcan module. the possible configurations are: ? for 16 mbs: 288 bytes for mb memory an d 64 bytes for individual mask registers ? for 32 mbs: 544 bytes for mb memory an d 128 bytes for individual mask registers in each configuration the user ca n program the maximum number of mbs that will take part in the matching and arbitration processe s using the maxmb field in the flexcan_x_mcr register. for 16 mb configuration, maxmb can be any number be tween 0?15.for 32 mb configuration, maxmb can be any number between 0?31.for 64 mb configur ation, maxmb can be any number between 0 ? 63.
flexcan module 24-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 25-1 pxr40 microcontroller reference manual, rev. 1 chapter 25 deserial serial peripheral interface (dspi) 25.1 introduction this device includes four dspi bloc ks (dspi_a, dspi_b, dspi_c, dspi_d). figure 25-1 is a block diagram of a single deserial serial peripheral interface (dspi) block. figure 25-1. dspi block diagram note the txss signal is described on section 25.3.2.1, dspi module configuration register (dspi_mcr) . for details on 32 bits operation see section 25.4.9, timed serial bus (tsb) . cmd dma and interrupt control tx fifo rx fifo tx data rx data 16 16 shift register sout x spi spi and dsi baud rate, delay and transfer control csi priority logic txss dsi dspi biu 32 from etpu and emios output channels 32 to e t p u o r emios input channels siu_disr sin x sck x intc edma slave interface 8 pcs x /ss /pcss/mtrig ht 32 32 16 16 16 16
deserial serial peripheral interface (dspi) 25-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.1.1 overview the deserial serial periphera l interface (dspi) block provides a synchronous serial bus for communication between an mcu and an external peripheral device. the dspi supports pin count reduction through serialization and dese rialization of parallel signals transmitted ove r the spi serial link. the dspi has three configurations: ? serial peripheral interface (spi) configuration where the dspi ope rates as a basic spi or as a queued spi through the use of internal fifos. ? deserial serial interface (dsi) configuration where the dspi se rializes etpu and emios output channels and deserializes the received data by placing the data on the etpu and emios input channels and as inputs to the external interrupt request submodule of the siu. ? combined serial interface (csi) configurati on where the dspi operates in both spi and dsi configurations interleaving ds i frames with spi frames, givi ng priority to spi frames. for queued operations the spi queues re side in system ram which is exte rnal to the dspi. data transfers between the queues and the dspi fi fos are accomplished th rough the use of a dma controller or through host software. figure 25-2 shows a dspi with extern al queues in system ram. figure 25-2. dspi with queues and dma 25.1.2 features the dspi supports these spi features: ? full-duplex, three-wire synchronous transfers ? master and slave mode ? buffered transmit operation using th e tx fifo (depth of 4 entries) ? buffered receive operation using th e rx fifo (depth of 4 entries) ? tx and rx fifos can be disabled indivi dually for low-latency updates to spi queues ? visibility into tx and rx fifos for ease of debugging system ram dspi dma controller tx queue rx fifo tx fifo shift register data data addr/ctrl rx queue data data addr/ctrl done req
deserial serial peripheral interface (dspi) freescale semiconductor 25-3 pxr40 microcontroller reference manual, rev. 1 ? programmable transfer attributes on a per-frame basis: ? eight transfer attribute registers ? serial clock with programmable polarity and phase ? various programmable delays ? programmable serial frame size of 4 to 32 bits, expa ndable by software control ? continuously held chip select capability ? 8 peripheral chip selects, expandabl e to 256 with external demultiplexer ? deglitching support for up to 128 peripheral ch ip select with external demultiplexer ? dma support for adding entries to tx fi fo and removing entries from rx fifo: ? tx fifo is not full (tfff) ? rx fifo is not empty (rfdf) ? 6 interrupt conditions: ? end of queue reached (eoqf) ? tx fifo is not full (tfff) ? transfer of current frame complete (tcf) ? attempt to transmit with an empty transmit fifo (tfuf) ? rx fifo is not empty (rfdf) ? frame received while rece ive fifo is full (rfof) ? modified spi transfer formats for comm unication with slower peripheral devices ? power-saving arch itectural features ? support for stop mode the dspi also supports pin reduction th rough serialization a nd deserialization. ? two sources of serialized data: ? dspi memory-mapped register ? parallel input signals ? deserialized data is provided as parallel output signals and as bits in a memory-mapped register ? transfer initiat ion conditions: ? continuous ? edge sensitive hardware trigger ? change in data ? support for parallel and serial chai ning of up to four dspi blocks ? pin serialization/dese rialization with interleaved spi frames for control and diagnostics ? continuous serial communications clock ? enhanced dsi logic to implemen t a 32 bits timed serial bus (t sb) configuration, supporting the micro second bus downstream frame format.
deserial serial peripheral interface (dspi) 25-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 dspi_c clock and data signals are available on lv ds pairs to support micr osecond bus functionality. table 25-1 is an example of the options for pa on tw o balls, where ?true? a nd ?complement? lvds outputs are multiplexed with sckc and sinc. signals lvds_opt0 and lvds_opt1 control the voltage swing on the lvds pad. these two signals are controlled by bits src[0:1] of the respective pcr register. table 25-2 gives the configuration for these bits. 25.1.3 dspi configurations the dspi block has three distinct serial transmission configurations: spi, dsi and csi. 25.1.3.1 spi configuration the spi configuration allows the dspi to send and recei ve serial data. this conf iguration allows the dspi to operate as a basic spi block w ith the fifos providing support for external queue operation. data to be transmitted and data received resi de in separate fifos. the fifos can be popped and pushed by host software or by a dma controller. 25.1.3.2 dsi configuration in the dsi configuration the dspi seri alizes up to 16 parallel input signals or register bits. the dspi also deserializes the received data to parallel output signals or to a memory-mapped register. the data is transferred using a spi-like protocol. table 25-1. lvds example pcr235 1 [pa] selection notes: 1 sckc_sck_c_lvdsp_gpio235 pcr236 2 [pa] selection 2 sinc_sck_c_lvdsm_gpio236 sckc ball function sinc ball function sckc sinc sckc sinc lvds lvds sck_c_lvds+ sck_c_lvds? sckc lvds sckc undriven lvds sinc undriven sinc table 25-2. lvds pads voltage swing src[0] src[1] current flowing in the driver differential voltage across pad_p and pad_n 0 0 normal default 0 1 decreased decreased 1 0 increased increased 1 1 normal same as default
deserial serial peripheral interface (dspi) freescale semiconductor 25-5 pxr40 microcontroller reference manual, rev. 1 specifically in the tsb configuration, detailed on section 25.4.9, timed serial bus (tsb) , the dspi serializes from 4 to 32 parallel input signals or register bi ts. the tsb downstream frame used to communicate with a single slave is shown in figure 25-38 .the dspi does not use dedicated pad configuration registers (pcrs). instead the siu selects either gpio, etpu or emios bits for serialization, and generates serialized dspi_a, _b, _c, _d outputs accordingly. th ese then connect to the 4 dspis. 25.1.3.3 csi configuration the csi configuration is a combination of the spi and dsi configurations. in this configuration the dspi interleaves dsi data with spi da ta. interleaving is done on the fram e boundaries. in this configuration transmission of spi data has higher priority than dsi data. 25.1.4 modes of operation the dspi?s modes of operation can be divided into tw o categories: block-specific modes such as master, slave, and module disable modes, and mcu-speci fic modes like external stop and debug modes. the block-specific modes are entered by host software writing to a register. the mcu-specific modes are controlled by signals external to the dspi. the mcu- specific modes are modes that the entire mcu may enter, in parallel to the dspi bei ng in one of its block-specific modes. 25.1.4.1 master mode master mode allows the ds pi to initiate and control serial co mmunication. in this mode, the sck signal and the pcs[ x ] signals are controlled by the dspi and configured as outputs. 25.1.4.2 slave mode the slave mode allows the dspi to communicate with spi/dsi bus masters. in this mode the dspi responds to externally controlled serial transfers. th e dspi cannot control serial transfers in slave mode. in this mode, the sck si gnal and the pcs[0]/ss signal are configured as inputs and provided by a bus master. 25.1.4.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi can be stopped whil e in the module disable mode. logic external to the dspi is needed to fully implement the module disable mode. 25.1.4.4 external stop mode the external stop mode is used for mcu power management. the dspi supports the stop mode mechanism. when a request is made to enter ex ternal stop mode, the dspi block acknowledges the request and completes the transfer in progress. when the dspi reache s the frame boundary it signals that the system clocks to the d spi block may be shut off.
deserial serial peripheral interface (dspi) 25-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.1.4.5 debug mode the debug mode is used for system development and debugging. if the device enters debug mode while the frz bit in the dspi_mcr is set, the dspi stops all serial transfer s. if the device enters debug mode while the frz bit is negated, the d spi behavior is unaffected and rema ins dictated by the block-specific mode and configuration of the dspi. 25.2 external signal description 25.2.1 overview table 25-3 lists the signals that may connect off chip. 25.2.2 detailed signal description 25.2.2.1 pcs[0]/ss ? peripheral chip select/slave select in master mode, the pcs[0] signal is a peripheral ch ip select output that selects which slave device the current transmissi on is intended for. in slave mode, the ss signal is a slave select input signal that allows a spi mast er to select the dspi as the target for transmission. 25.2.2.2 pcs[1] - pcs[3] ? peripheral chip selects 1 - 3 pcs[1] - pcs[3] are peripheral chip select output signals in master mode. in slave mode these signals are not used. table 25-3. signal properties name i/o type function master mode slave mode pcs[0]/ss output / input peripheral chip select 0 slave select pcs[1] - pcs[3] output peripheral chip select 1 - 3 unused pcs[4]/mtrig 1 notes: 1 mtrig and ht are internal connections and not available on a pin. output peripheral chip select 4 master trigger 2 2 the master and hardware trigger signals are specifica lly for mto mode, and not used in standard spi slave mode. pcs[5]/pcss output peripheral chip select 5 / peripheral chip select strobe unused sin input serial data in serial data in sout output serial data out serial data out sck output / input serial clock (output) serial clock (input) ht 1 input hardware trigger hardware trigger 2
deserial serial peripheral interface (dspi) freescale semiconductor 25-7 pxr40 microcontroller reference manual, rev. 1 25.2.2.3 pcs[4]/mtrig ? peripheral chip se lect 4/master trigger note mtrig is an internal connect ion and not available on a pin. in master mode, pcs[4] is a pe ripheral chip select output signal. in slave mode, mtrig is an output trigger signal that indicates th at a change in data to be serialized has occurred. the mtrig provides a pulse in dsi confi guration when a change in data to be serialized occurs. the mtrig pulse is four system clock cycles in duratio n. if the dspi is in slave mode and the mto is disabled, the pcs[4]/mtrig signal is unused. 25.2.2.4 pcs[5]/pcss ? peripheral chip select 5/ peripheral chip select strobe pcs[5] is a peripheral chip select output signal. when the dspi is in master mode and pcsse bit in the dspi_mcr is negated, this si gnal is used to select which slave devi ce the current transfer is intended for. pcss provides a strobe signal that can be used with an external demult iplexer for deglitching of the pcs signals. when the dspi is in master mode and the pcsse bit in the dspi _mcr is set, the pcss provides the appropriate timing for the decoding of the pcs[ 0] - pcs[4] and pcs[6] - pcs[7] signals which prevents glitches from occurring. this signal is not used in slave mode. 25.2.2.5 sin ? serial input sin is a serial data input signal. 25.2.2.6 sout ? serial output sout is a serial data output signal. 25.2.2.7 sck ? serial clock sck is a serial communication clock signal. in master mode, the dspi generates the sck. in slave mode, sck is an input from an external bus master. 25.2.2.8 ht ? hardware trigger ht is an internal connection and not available on a pin. ht is a trigger input signal to the dspi module that is used with multiple transfer operations in dsi configuration. in master mode while in dsi or cs i configurations, the ht signal initia tes a data transfer when the trre bit in the dspi_dsicr is set and a risi ng or falling edge is detected on ht. which edge to trigger on is determined by the tpol bit in the dspi_dsicr.
deserial serial peripheral interface (dspi) 25-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 in slave mode, the dspi generates a trigger pulse on the mtrig pin when a rising or falling edge is detected on ht. which edge that generates an out put pulse is selected by the tpol bit in the dspi_dsicr. 25.3 memory map and register definition 25.3.1 memory map register accesses to memory addresses that are reserv ed or undefined result in a transfer error. write access to the dspi_popr register al so result in a transfer error. table 25-4 shows the dspi memory map. table 25-4. dspi memory map address register bits access reset value section/page dspi_base 1 dspi_mcr?dspi module configuration register 32 r/w 0x0000_0001 25.3.2.1/9 dspi_base+0x4 reserved dspi_base+0x8 dspi_tcr?dspi transf er count register 32 r/w 0x0000_0000 25.3.2.2/11 dspi_base+0xc? dspi_base+0x28 dspi_ctar0?dspi clock and transfer attributes register 0 - dspi_ctar7?dspi clock and transfer attributes register 7 32 r/w 0x7800_0000 25.3.2.3/12 dspi_base+0x2c dspi_sr?dspi status register 32 r/w 0x0200_0000 25.3.2.4/18 dspi_base+0x30 dspi_rser?dspi dm a/interrupt request select and enable register 32 r/w 0x0000_0000 25.3.2.5/20 fifo registers dspi_base+0x34 dspi_pushr? dspi push tx fifo register 32 r/w 0x0000_0000 25.3.2.6/22 dspi_base+0x38 dspi_popr?dspi pop rx fifo regist er 32 r 0x0000_0000 25.3.2.7/23 dspi_base+0x3c - dspi_base+0x48 dspi_txfr0?dspi transmit fifo register 0 - dspi_txfr3?dspi transm it fifo register 3 32 r 0x0000_0000 25.3.2.8/24 dspi_base+0x4c - dspi_base+0x78 reserved dspi_base+0x7c - dspi_base+0x88 dspi_rxfr0?dspi receive fifo register 0 - dspi_rxfr3?dspi receive fifo register 3 32 r 0x0000_0000 25.3.2.9/25 dspi_base+0x8c - dspi_base+0xb8 reserved dsi registers dspi_base+0xbc dspi_dsicr?dspi dsi co nfiguration regist er 32 r/w 0x0000_0000 25.3.2.10/25 dspi_base+0xc0 dspi_sdr?dspi dsi seri alization data register 32 r 0x0000_0000 25.3.2.11/27
deserial serial peripheral interface (dspi) freescale semiconductor 25-9 pxr40 microcontroller reference manual, rev. 1 25.3.2 register descriptions 25.3.2.1 dspi module configuration register (dspi_mcr) the dspi_mcr contains bits whic h configure various attributes as sociated with dspi operation. the halt and mdis bits can be changed at any time but will only take effect on the next frame boundary. only the halt and mdis bits in the dspi_mcr may be changed while the dspi is in the running state. dspi_base+0xc4 dspi_asdr?dspi ds i alternate serialization data register 32 r/w 0x0000_0000 25.3.2.12/28 dspi_base+0xc8 dspi_compr?dspi dsi transmit comparison register 32 r 0x0000_0000 25.3.2.13/29 dspi_base+0xcc dspi_ddr?dspi dsi deserialization data register 32 r 0x0000_0000 25.3.2.14/29 dspi_base+0xd0 dspi_dsicr1?d spi dsi tsb configuration register 1 32 r/w 0x0000_0000 25.3.2.15/30 notes: 1 dspi_a = 0xfff9_0000 dspi_b = 0xfff9_4000 dspi_c = 0xfff9_8000 dspi_d = 0xfff9_c000 address: dspi_base access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mstr cont_scke dconf frz mtfe pcsse rooe 00 pcsis5 pcsis4 pcsis3 pcsis2 pcsis1 pcsis0 w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r doze mdis dis_txf dis_rxf clr_txf clr_rxf smpl_pt 0000000 halt w reset0 00000 0 000000001 figure 25-3. dspi module configuration register (dspi_mcr) table 25-4. dspi memory map (continued) address register bits access reset value section/page
deserial serial peripheral interface (dspi) 25-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 25-5. dspi_mcr field descriptions field description 0 mstr master/slave mode select. the mstr bit configures the dspi for either master mode or slave mode. 0 dspi is in slave mode 1 dspi is in master mode 1 cont_scke continuous sck enable. the cont_scke bit enables the serial communication clock (sck) to run continuously. see section 25.4.8, continuous serial communications clock , for details. 0 continuous sck disabled 1 continuous sck enabled 2?3 dconf[0:1] dspi configuration. the dconf field selects between the three different configurations of the dspi. the values below list the dconf values for the various configurations. 4 frz freeze. the frz bit enables the dspi transfers to be stopped on the next frame boundary when the device enters debug mode. 0 do not stop serial transfers1stop serial transfers 5 mtfe modified timing format enable. the mtfe bit en ables a modified transfer format to be used. see section 25.4.7.4, modified spi/dsi transfer format (mtfe = 1, cpha = 1) , for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled 6 pcsse peripheral chip select strobe enable. the pcsse bit enables the pcs[5]/pcss to operate as an pcs strobe output signal. see section 25.4.6.5, peripheral chip select strobe enable (pcss) , for more information. 0 pcs[5]/pcss is used as the peripheral chip select[5] signal 1 pcs[5]/pcss is used as an active-low pcs strobe signal 7 rooe receive fifo overflow overwrite enable. the rooe bit enables an rx fifo overflow condition to either ignore the incoming serial data or to overwrite existing data. if the rx fifo is full and new data is received, the data from the transfe r that generated the overflow is either ignored or shifted in to the shift register. if the rooe bit is asserted, the incomi ng data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. see section 25.4.10.6, receive fifo overflow interrupt request , for more information. 0 incoming data is ignored 1 incoming data is shifted in to the shift register 8?9 reserved, should be cleared 10?15 pcsis x peripheral chip select inactive state. the pc sis bit determines the inac tive state of the pcs x signal. 0 the inactive state of pcs x is low 1 the inactive state of pcs x is high 16 doze doze enable. the doze bit provides support for externally controlled doze mode power-saving mechanism. see section 25.4.11, power saving features , for details. dconf dspi configuration 00 spi 01 dsi 10 csi 11 reserved
deserial serial peripheral interface (dspi) freescale semiconductor 25-11 pxr40 microcontroller reference manual, rev. 1 25.3.2.2 dspi transfer co unt register (dspi_tcr) the dspi_tcr contains a counter th at indicates the number of spi tran sfers made. the transfer counter is intended to assist in queue mana gement. the user must not write to the dspi_tcr while the dspi is in the running state. 17 mdis module disable. the mdis bit allows the clock to be stopped to the non-memory mapped logic in the dspi effectively putting the dspi in a software controlled power-saving state. see section 25.4.11, power saving features , for more information. 0 enable dspi clocks. 1 allow external logic to disable dspi clocks. 18 dis_txf disable transmit fifo. the dis_txf bit provides a mechanism to disable the tx fifo. when the tx fifo is disabled, the transmit part of the dspi operates as a simplified double-buffered spi. see section 25.4.3.3, fifo disable operation , for details. 0 tx fifo is enabled 1 tx fifo is disabled 19 dis_rxf disable receive fifo. the dis_rx f bit provides a mechanism to disable the rx fifo. when the rx fifo is disabled, the receive part of the dspi operates as a simplified double-buffered spi. see section 25.4.3.3, fifo disable operation , for details. 0 rx fifo is enabled 1 rx fifo is disabled 20 clr_txf clear tx fifo. clr_txf is used to flush the tx fi fo. writing a ?1? to clr_txf clears the tx fifo counter. the clr_txf bit is always read as zero. 0 do not clear the tx fifo counter 1 clear the tx fifo counter 21 clr_rxf clear rx fifo. clr_rxf is used to flush the rx fifo. writing a ?1? to clr_rxf clears the rx counter. the clr_rxf bit is always read as zero. 0 do not clear the rx fifo counter 1 clear the rx fifo counter 22?23 smpl_pt smpl_pt ? sample point. smpl_pt allows the hos t software to select when the dspi master samples sin in modified transfer format. figure 25-31 shows where the master can sample the sin pin. the table below lists the various delayed sample points. 24?30 reserved, should be cleared. 31 halt halt. the halt bit provides a mechanism by so ftware to start and stop dspi transfers. see section 25.4.2, start a nd stop of dspi transfers , for details on the operation of this bit. 0 start transfers 1 stop transfers table 25-5. dspi_mcr field descriptions (continued) field description smpl_pt number of system clock cycles be tween odd-numbered edge of sck and sampling of sin. 00 0 01 1 10 2 11 reserved
deserial serial peripheral interface (dspi) 25-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.3.2.3 dspi clock and transfer attributes registers 0?7 (dspi_ctar0?dspi_ctar7) the dspi_ctar registers are used to define differ ent transfer attribute c onfigurations. spi and dsi transfers select which one of the dspi_ctars to get th eir transfer attributes from . the user must not write to the dspi_ctar registers while the dspi is in the running state. in master mode, the dspi_ctar0 - dspi_ctar7 regist ers define combinations of transfer attributes such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. in slave mode, a subset of the bitfields in the dspi_ctar0 and dspi_ctar1 re gisters are used to set the slave transfer attributes. see the individua l bit descriptions for details on wh ich bits are used in slave modes. when the dspi is configured as a spi master, the ctas field in the command portion of the tx fifo entry selects which of the dspi_ctar register is used. when the dspi is configured as a spi bus slave, the dspi_ctar0 register is used. when the dspi is configured as a dsi master, the dsictas field in the dspi dsi configuration register (dspi_dsicr) , selects which of the dspi_ctar register is used. when the dspi is configured as a dsi bus slave, the dspi_cta r1 register is used. in csi configuration, the transfer at tributes are selected ba sed on whether the current frame is spi data or dsi data. spi transfers in csi conf iguration follow the pr otocol described for spi configuration, and dsi transfers in csi configuration foll ow the protocol described for dsi configuration. csi configuration is address: dspi_base + 0x8 access: r/w 0123456789101112131415 r spi_tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 25-4. dspi transfer count register (dspi_tcr) table 25-6. dspi_tcr field descriptions field description 0?15 spi_tcnt spi transfer counter. spi_tcnt is used to keep track of the number of spi transfers made. the spi_tcnt field counts the number of spi tran sfers the dspi makes. the spi_tcnt field is incremented every time the last bit of a spi frame is transmitted. a value written to spi_tcnt presets the counter to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the transfer counter ?wraps around? i.e. incrementing the counter past 65535 resets the counter to zero. 16?31 reserved, should be cleared.
deserial serial peripheral interface (dspi) freescale semiconductor 25-13 pxr40 microcontroller reference manual, rev. 1 only valid in conjunction with master mode. see section 25.4.5, combined serial interface (csi) configuration , for more details. in continuous clock mode, only t dt is supported for tsb. however, in tsb non continuous clock mode, both the pdt and dt delays are valid. address: dspi_base + 0xc?dspi_base + 0x28 access: r/w 0 1 2 3 4 5 6 7 8 9 10 1112131415 r dbr fmsz cpo l cpha lsbfe pcssck pasc pdt pbr w reset011110 0 0 0 0 0 00000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset000000 0 0 0 0 0 00000 figure 25-5. dspi clock and transfer attributes register 0?7 (dspi_ctar0?dspi_ctar7)
deserial serial peripheral interface (dspi) 25-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 25-7. dspi_ctar n field descriptions field descriptions 0 dbr double baud rate. the dbr bit doubles the effect ive baud rate of the serial communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the serial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in ta b l e 2 5 - 8 . see the br[0:3] field description for details on how to compute the baud rate. if the overall baud rate is divide by two or divide by three of the system clock then neither the continuous sck enable or the modified timing format enable bits should be set. 0 the baud rate is computed normally with a 50/50 duty cycle 1 the baud rate is doubled with the duty cycle depending on the baud rate prescaler 1?4 fmsz frame size. the fmsz field selects the number of bi ts transferred per frame. the fmsz field is used in master mode and slave mode. ta bl e 2 5 - 9 lists the frame size encodings. when operating in tsb configuration, detailed in section 25.4.9, timed serial bus (tsb), the fmsz defines the point with in the 32-bit (maximum length) frame where control of the cs switches from the dspi_dsicr to the dspi_dsicr1 register. the cr oss over point must range between 4 bits and 16 bits and is encoded per table 25-9 . the remaining frame after the cross over point, regardless of how many bits are remaining, will be controlled by the dspi_dsicr1 register. 5 cpol clock polarity. the cpol bit selects the inactive state of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock po larities. when the continuo us selection format is selected, switching between clock polarities with out stopping the dspi can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high 6 cpha clock phase. the cpha bit selects which edge of sck causes data to change and which edge causes data to be captured. this bit is used in both master and sl ave mode. for successful communication between serial devices, the devices must have identical clock phase settings. continuous sck is only supported for cpha=1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge 7 lsbfe lsb first. the lsbfe bit selects if the lsb or msb of the frame is transferred first. this bit is only used in master mode. when operating in tsb configuration, this bit should be always 1. 0 data is transferred msb first 1 data is transferred lsb first 8?9 pcssck pcs to sck delay prescaler. the pcssck field selects the prescaler value for the delay between assertion of pcs and the first edge of the sck. th is field is only used in master mode. the table below lists the prescaler values. see the cssck[0:3] field description for details on how to compute the pcs to sck delay. pcssck pcs to sck delay prescaler value 00 1 01 3 10 5 11 7
deserial serial peripheral interface (dspi) freescale semiconductor 25-15 pxr40 microcontroller reference manual, rev. 1 10?11 pasc after sck delay prescaler. the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. this field is only used in master mode. the table below lists the prescaler values. see the asc[0:3] field description for details on how to compute the after sck delay. 12?13 pdt delay after transfer prescaler. the pdt field selects the prescaler value for the delay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. the pdt field is only used in master mode. the table below lists the prescaler values. see the dt[0:3] field description for details on how to compute the delay after transfer. 14?15 pbr baud rate prescal. the pbr field selects the prescale r value for the baud rate. this field is only used in master mode. the baud rate is the frequency of the serial communications clock (sck). the system clock is divided by the prescaler value before the baud rate selection takes place. the baud rate prescaler values are listed in the table below. see the br[0:3] field description for details on how to compute the baud rate. table 25-7. dspi_ctar n field descriptions (continued) field descriptions pasc after sck delay prescaler value 00 1 01 3 10 5 11 7 pdt delay after transfer prescaler value 00 1 01 3 10 5 11 7 pbr baud rate prescaler value 00 2 01 3 10 5 11 7
deserial serial peripheral interface (dspi) 25-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 16?19 cssck pcs to sck delay scaler. the cssck field selects the scaler value for the pcs to sck delay. this field is only used in master mode. the pcs to sck delay is the delay between the assertion of pcs and the first edge of the sck. table 25-10 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is comput ed according to the following equation: eqn. 25-1 see section 25.4.6.2, pcs to sck delay (tcsc) , for more details. 20?23 asc after sck delay scaler. the asc field selects the sca ler value for the after sck delay. this field is only used in master mode. the after sck delay is the delay between the last edge of sck and the negation of pcs. table 25-11 list the scaler values.the after sck delay is a multiple of the system clock period, and it is computed according to the following equation: eqn. 25-2 see section 25.4.6.3, after sck delay (tasc) , for more details. 24?27 dt delay after transfer scaler. the dt field selects the de lay after transfer scaler. this field is only used in master mode. the delay after transfer is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. table 25-12 lists the scaler values. in the continuous serial communications clock operation the dt value is fixed to one tsck, except when the tsbc bit from dspi_dsicr regist er is enabling the tsb configuration. see detailed information on section 25.4.9, timed serial bus (tsb) . the delay after transfer is a multiple of the system clock period and it is computed according to the following equation: eqn. 25-3 see section 25.4.6.4, dela y after transfer (tdt) , for more details. 28?31 br baud rate scaler. the br field selects the scaler value for the baud rate. this field is only used in master mode. the prescaled system clock is divided by the baud rate scaler to generate the frequency of the sck. table 25-13 lists the baud rate scaler values.the baud rate is computed according to the following equation: eqn. 25-4 see section 25.4.6.1, baud rate generator , for more details. table 25-8. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 table 25-7. dspi_ctar n field descriptions (continued) field descriptions t csc 1 f periph --------------- pcssck cssck ? ? = t asc 1 f periph --------------- pasc ? asc ? = t dt 1 f periph --------------- pdt ? dt ? = sck baud rate f periph pbr --------------- 1 dbr + br --------------------- ? =
deserial serial peripheral interface (dspi) freescale semiconductor 25-17 pxr40 microcontroller reference manual, rev. 1 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 25-9. dspi transfer frame size fmsz framesize fmsz framesize 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 table 25-10. dspi pcs to sck delay scaler cssck pcs to sck delay scaler value cssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 25-11. dspi afte r sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 table 25-8. dspi sck duty cycle (continued) dbr cpha pbr sck duty cycle
deserial serial peripheral interface (dspi) 25-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.3.2.4 dspi status register (dspi_sr) the dspi_sr contains status and fl ag bits. the bits reflect the stat us of the dspi and indicate the occurrence of events that can generate interrupt or dma requests. software can clear flag bits in the dspi_sr by writing a ?1? to it. writing a ?0? to a flag bit has no effect. this re gister may not be writable in mdis mode due to the us e of power saving mechanisms. 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 25-12. dspi delay after transfer scaler dt delay after transfer scaler value dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 25-13. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 table 25-11. dspi after sck delay scaler (continued) asc after sck delay scaler value asc after sck delay scaler value
deserial serial peripheral interface (dspi) freescale semiconductor 25-19 pxr40 microcontroller reference manual, rev. 1 address: dspi_base + 0x2c access: r/w 0 1 2 3 4 5 6 7 8 9 101112131415 r tcf txrxs 0 eoqf tfuf 0 tfff 00 0 0 0 rfof 0 rfdf 0 w reset0 0 0 0 001000 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset0 0 0 0 000000 0 0 0 0 0 0 figure 25-6. dspi status register (dspi_sr) table 25-14. dspi_sr field descriptions field description 0 tcf transfer complete flag. the tcf bit indicates that all bits in a frame have been shifted out. the tcf bit is set at the end of the frame transfer. t he tcf bit remains set until cleared by software. 0 transfer not complete 1 transfer complete 1 txrxs tx & rx status. the txrxs bit refl ects the status of the dspi. see section 25.4.2, start and stop of dspi transfers , for information on how what causes this bit to be negated or asserted. 0 tx and rx operations are disabled (dspi is in stopped state) 1 tx and rx operations are enabled (dspi is in running state) 2 reserved, should be cleared. 3 eoqf end of queue flag. the eoqf bit indicates that transmission in pr ogress is the last entry in a queue. the eoqf bit is set when tx fifo entry has the eoq bit set in the command halfword and the end of the transfer is reached. the eoqf bit remains set until cleared by software. when the eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executing command 1 eoq bit is set in the executing spi command 4 tfuf transmit fifo underflow flag. the tfuf bit indicates that an underflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for dspi blocks operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in spi slave mode is empty, and a transfer is initiated by an external spi master. the tfuf bit remains set until cleared by software. 0 tx fifo underflow has not occurred 1 tx fifo underflow has occurred 5 reserved, should be cleared. 6 tfff transmit fifo fill flag. the tfff bit provides a me thod for the dspi to request more entries to be added to the tx fifo. the tfff bit is set while the tx fifo is not full. the tfff bit can be cleared by host software or an acknowledgement from the dma controller when the tx fifo is full. 0 tx fifo is full 1 tx fifo is not full 7?11 reserved, should be cleared.
deserial serial peripheral interface (dspi) 25-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.3.2.5 dspi dma/interrupt request select and enable register (dspi_rser) the dspi_rser serves two purposes. it enables flag bits in the dspi_sr to generate dma requests or interrupt requests. the dspi _rser also selects the type of request to be generated. see the individual bit descriptions for information on the types of requests the bits support. the user must not write to the dspi_rser while the dspi is in the running state. 12 rfof receive fifo overflow flag. the rfof bit indicate s that an overflow condition in the rx fifo has occurred. the bit is set when the rx fifo and shift re gister are full and a transfer is initiated. the bit remains set until cleared by software. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred 13 reserved, should be cleared. 14 rfdf receive fifo drain flag. the rfdf bit provides a method for the dspi to request that entries be removed from the rx fifo. the bit is set while t he rx fifo is not empty. the rfdf bit can be cleared by host software or an acknowledgemen t from the dma controlle r when the rx fifo is empty. 0 rx fifo is empty 1 rx fifo is not empty 15 reserved, should be cleared. 16?20 txctr tx fifo counter. the txctr field indicates the numb er of valid entries in the tx fifo. the txctr is incremented every time the dspi _pushr is wr itten. the txctr is decremented every time a spi command is executed and the spi data is transferred to the shift register. 20?23 txnxtptr transmit next pointer. the txnxtptr field indicate s which tx fifo entry will be transmitted during the next transfer. the txnxtptr field is updated ever y time spi data is transf erred from the tx fifo to the shift register. see section 25.4.10.4, transmit fi fo underflow interrupt request , for more details. 24?27 rxctr rx fifo counter. the rxctr field indicates the nu mber of entries in the rx fifo. the rxctr is decremented every time the dspi _popr is read. the rxctr is incremented every time data is transferred from the shift register to the rx fifo. 28?31 popnxtptr pop next pointer. the popnxtptr field contains a poi nter to the rx fifo entry that will be returned when the dspi_popr is read. the popnxtptr is updated when the dspi_popr is read. see section 25.4.3.5, receive first in fi rst out (rx fifo) buffering mechanism , for more details. table 25-14. dspi_sr field descriptions (continued) field description
deserial serial peripheral interface (dspi) freescale semiconductor 25-21 pxr40 microcontroller reference manual, rev. 1 address: dspi_base + 0x30 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tcf_re 00 eoqf_re tfuf_re 0 tfff_re tfff _dirs 00 0 0 rfof_re 0 rfdf_re rfdf _dirs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 25-7. dspi dm a/interrupt request select and enable register (dspi_rser) table 25-15. dspi_rser field descriptions field description 0 tcf_re transmission complete request enable. the tcf_re bit enables tcf flag in the dspi_sr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled 1?2 reserved, should be cleared. 3 eoqf_re dspi finished request enable. the eoqf_re bi t enables the eoqf flag in the dspi_sr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled 4 tfuf_re transmit fifo underflow request enable. the tf uf_re bit enables the tfuf flag in the dspi_sr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled 5 reserved, should be cleared. 6 tfff_re transmit fifo fill request enable . the tfff_re bit enables the tfff flag in the dspi_sr to generate a request. the tfff_dirs bit selects betw een generating an interrupt request or a dma requests. 0 tfff interrupt requests or dma requests are disabled 1 tfff interrupt requests or dma requests are enabled 7 tfff_dirs transmit fifo fill dma or interr upt request select. the tfff_dirs bit selects between generating a dma request or an interrupt request. when the tfff flag bit in the dspi_sr is set, and the tfff_re bit in the dspi_rser register is set, this bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated 8?11 reserved, should be cleared.
deserial serial peripheral interface (dspi) 25-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.3.2.6 dspi push tx fifo register (dspi_pushr) the dspi_pushr provides a means to write to the tx fi fo. data written to this register is transferred to the tx fifo. see section 25.4.3.4, transmit first in first out (tx fifo) buffering mechanism , for more information. eight or sixteen bit write accesses to the dspi_pushr will transf er 32 bits to the tx fifo. 12 rfof_re receive fifo overflow request enable. the rfof _re bit enables the rfof flag in the dspi_sr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled 13 reserved, should be cleared. 14 rfdf_re receive fifo drain request enable. the rfdf_re bit enables the rfdf flag in the dspi_sr to generate a request. the rfdf_dirs bit selects be tween generating an interrupt request or a dma request. 0 rfdf interrupt requests or dma requests are disabled 1 rfdf interrupt requests or dma requests are enabled 15 rfdf_dirs receive fifo drain dma or interrupt request select. the rfdf_dirs bit selects between generating a dma request or an interrupt request. when the rfdf flag bit in the dspi_sr is set, and the rfdf_re bit in the dspi_rser register is se t, the rfdf_dirs bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated 16?31 reserved, should be cleared. address: dspi_base + 0x34 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r con t ctas eoq ctcn t 0000 pcs 5 pcs 4 pcs 3 pcs 2 pcs 1 pcs 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 25-8. dspi push tx fifo register (dspi_pushr) table 25-15. dspi_rser field descriptions (continued) field description
deserial serial peripheral interface (dspi) freescale semiconductor 25-23 pxr40 microcontroller reference manual, rev. 1 25.3.2.7 dspi pop rx fifo register (dspi_popr) the dspi_popr provides a means to read the rx fifo. see section 25.4.3.5, receive first in first out (rx fifo) buffering mechanism , for a description of the rx fifo op erations. eight or sixteen bit read accesses to the dspi_popr will read from th e rx fifo and update the counter and pointer. table 25-16. dspi_pus hr field descriptions field descriptions 0 cont continuous peripheral chip select enable. the cont bit selects a continuous selection format. the bit is used in spi master mode. the bit enables th e selected pcs signals to remain asserted between transfers. see section 25.4.7.5, contin uous selection format , for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers 1?3 ctas clock and transfer attributes select. the ctas fiel d selects which of the dspi_ctar register is used to set the transfer attributes for the associated spi frame. the field is only used in spi master mode. in spi slave mode dspi_ctar0 is used. the table below shows how the ctas values map to the dspi_ctar registers. the number of dspi_ctar registers is implementation specific. 4 eoq end of queue. the eoq bit provides a means for host software to signal to the dspi that the current spi transfer is the last in a queue. at the end of the transfer the eoqf bit in the dspi_sr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer 5 ctcnt clear spi_tcnt. the ctcnt provides a means for ho st software to clear the spi transfer counter. the ctcnt bit clears the spi_tcnt field in the d spi_tcr register. the spi_ tcnt field is cleared before transmission of the current spi frame begins. 0 do not clear spi_tcnt field in the dspi_tcr 1 clear spi_tcnt field in the dspi_tcr 6?9 reserved, should be cleared 10?15 pcs x peripheral chip select 0?5. the pcs bits select which pcs signals will be asserted for the transfer. 0 negate the pcs[x] signal 1 assert the pcs[x] signal 16?31 txdata transmit data. the txdata field holds spi data to be transferred according to the associated spi command. ctas use clock and transfer attributes from ctas use clock and transfer attributes from 000 dspi_ctar0 100 dspi_ctar4 001 dspi_ctar1 101 dspi_ctar5 010 dspi_ctar2 110 dspi_ctar6 011 dspi_ctar3 111 dspi_ctar7
deserial serial peripheral interface (dspi) 25-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.3.2.8 dspi transmit fifo regist ers 0?3 (dspi_txfr0?dspi_txfr3) the dspi_txfr0 - dspi_txfr3 registers provide vi sibility into the tx fi fo for debugging purposes. each register is an entry in the tx fifo. the registers are read-only and cannot be modi fied. reading the dspi_txfrx registers does not alter the state of the tx fifo. the number of regi sters used to implement the tx fifo is four for this device address: dspi_base + 0x38 access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00 00000000000000 w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset00 00000000000000 figure 25-9. dspi pop rx fifo register (dspi_popr) table 25-17. dspi_popr field descriptions field description 0?15 reserved, should be cleared. 16?31 rxdata received data. the rxdata field contains the spi data from the rx fifo entry pointed to by the pop next data pointer. address: dspi_base+0x3c?dspi _base+0x78 access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtxcmd w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset00 00000000000000 figure 25-10. dspi transmit fifo register 0?15 (dspi_txfr0?dspi_txfr15)
deserial serial peripheral interface (dspi) freescale semiconductor 25-25 pxr40 microcontroller reference manual, rev. 1 25.3.2.9 dspi receive fi fo registers 0?3 (dspi_rxfr0?dspi_rxfr3) the dspi_rxfr0 - dspi_rxf r3 registers provide visi bility into the rx fi fo for debugging purposes. each register is an entry in the rx fifo. th e dspi_rxfr registers are read-only. reading the dspi_rxfrx registers does not alter th e state of the rx fifo. the number of registers used to implement the rx fifo is four for this device. 25.3.2.10 dspi dsi configuration register (dspi_dsicr) the dsi configuration regist er selects various attri butes associated with ds i and csi configurations. the user must not write to the dspi_dsicr while the dspi is in the running state. table 25-18. dspi_txfr n field descriptions field description 0?15 txcmd transmit command. the txcmd field contains the comma nd that sets the transfer attributes for the spi data. see section 25.3.2.6, dspi push tx fifo register (dspi_pushr) , for details on the command field. 16?31 txdata transmit data. the txdata field cont ains the spi data to be shifted out. address: dspi_base + 0x7c?dspi_base + 0xb8 access: read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rxdata w reset0000000000000000 figure 25-11. dspi receive fifo registers 0?15 (dspi_rxfr0?dspi_rxfr15) table 25-19. dspi_rxfr n field descriptions field description 0?15 reserved, should be cleared. 16?31 rxdata receive data. the rxdata field contains the received spi data.
deserial serial peripheral interface (dspi) 25-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 address: dspi_base + 0xbc access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mtoe 0 mtocnt 000 tsbc txss tpol trre cid w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dcont dsictas 0000 0 0 dpcs5 dpcs4 dpcs3 dpcs2 dpcs1 dpcs0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 25-12. dspi dsi confi guration register (dspi_dsicr) table 25-20. dspi_dsicr field descriptions field description 0 mtoe multiple transfer operation enable. the mtoe bi t enables multiple dspis to be connected in a parallel or serial configuration. see section 25.4.4.6, multiple transfer operation (mto) , for more information. 0 multiple transfer operation disabled 1 multiple transfer operation enabled the mtoe feature is not supported in tsb config uration and should be disabled in this mode. 1 reserved, should be cleared. 2?7 mtocnt multiple transfer operation count. the mtocnt field selects number of bits to be shifted out during a transfer in multiple tran sfer operation. the field sets the numb er of sck cycles that the bus master will generate to complete the transfer. the number of sck cycles used will be one more than the value in the mtocnt field. the number of sck cycles defined by mtocnt must be equal to or greater than the frame size. when tsbc is set, mt ocnt is not used, and its value is ignored. 8?10 reserved, should be cleared. 11 tsbc timed serial bus configuration. the tsbc bit enables the timed serial bus configuration. this configuration allows 32-bit data to be used. it also allows t dt to be programmable. see section 25.4.9, timed serial bus (tsb) , for detailed information. 0 timed serial bus configuration disabled 1 timed serial bus configuration enabled if this bit is 0 the dspi_dsicr1 register should not be used. 12 txss transmit data source se lect. the txss bit selects the source of data to be seria lized. the source can be either data from host software written to th e dspi dsi alternate serialization data register (dspi_asdr), or parallel input pin states latched into the dspi dsi serialization data register (dspi_sdr). 0 source of serialized data is the dspi_sdr 1 source of serialized data is the dspi_asdr 13 tpol trigger polarity. the tpol bit selects the active edge of the hardware trigge r input signal (ht). the bit selects which edge will initiate a tr ansfer in the dsi configuration. see section 25.4.4.5, dsi transfer initiation control , for more information. when tsbc bit is set, bits tpol bit is used for both dsicr and dsicr1 registers. 0 falling edge will initiate a transfer 1 rising edge will initiate a transfer
deserial serial peripheral interface (dspi) freescale semiconductor 25-27 pxr40 microcontroller reference manual, rev. 1 25.3.2.11 dspi dsi serializati on data register (dspi_sdr) the dspi_sdr contains the signal stat es of the parallel input signals. th e pin states of the parallel input signals are latched into the dspi _sdr on the rising edge of ever y system clock. the dspi_sdr is read-only. when the txss bit in the dspi_dsicr is negated, the data in the dspi_sdr is the source of the serialized data. 14 trre trigger reception enable. the trre bit enables th e dspi to initiate a transfer when an external trigger signal is received. the bit is only valid in dsi configuration. see section 25.4.4.5, dsi transfer initiation control , for more information. when tsbc bit is set, trre bit is used for both dsicr and dsicr1 registers. 0 trigger signal reception disabled 1 trigger signal reception enabled 15 cid change in data transfer enable. the cid bit enables a change in serialization data to initiate a transfer. the bit is used in master mode in dsi and csi configurations to control when to initiate transfers. when the cid bit is set, serialization is initiated when the current dsi data differs from the previous dsi data shifted out. the dspi_com pr register is compar ed with the dspi_sdr or dspi_asdr register to detect a change in data. refer to section 25.4.4.5, dsi transfer initiation control , for more information. when tsbc bit is set, cid bit is used for both dsicr and dsicr1 registers. 16 dcont dsi continuous peripheral chip select enable. the dcont bit enables the pcs signals to remain asserted between transfers. the dcont bit only af fects the pcs signals in dsi master mode. see section 25.4.7.5, contin uous selection format , for details. when tsbc bit is set, dcont bit is used for both dsicr and dsicr1 registers. 0 return peripheral chip select signals to thei r inactive state after transfer is complete 1 keep peripheral chip select signal s asserted after transfer is complete 17?19 dsictas dsi clock and transfer attributes select. the dsict as field selects which of the dspi_ctar register is used to provide transfer attributes in dsi config uration. the dsictas field is used in dsi master mode. in dsi slave mode, the dspi_ctar1 is always selected. the table below shows how the dsictas values map to the dspi_ctar registers. when tsb configuration is selected the dsictas bits control all 32 bits. 20?25 reserved, should be cleared. 26?31 dpcs x dsi peripheral chip select 0?7. the dpcs bits select which of the pcs signals to assert during a dsi transfer. the dpcs bits only control the asse rtions of the pcs signals in dsi master mode. 0 negate pcs[x] 1 assert pcs[x] table 25-20. dspi_dsicr field descriptions (continued) field description dsictas dsi clock and transfer attributes controlled by dsictas dsi clock and transfer attributes controlled by 000 dspi_ctar0 100 dspi_ctar4 001 dspi_ctar1 101 dspi_ctar5 010 dspi_ctar2 110 dspi_ctar6 011 dspi_ctar3 111 dspi_ctar7
deserial serial peripheral interface (dspi) 25-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the dspi_sdr is a 32-bit register. all 32 bits are used in tsb configuration and only the least significant 16 bits are used in al l other configurations. 25.3.2.12 dspi dsi alternate seria lization data register (dspi_asdr) the dspi_asdr provides a means for host software to write the data to be serialized. when the txss bit in the dspi_dsicr is set, the data in the dspi_asd r is the source of the se rialized data. writes to the dspi_asdr take effect on the next frame boundary. the dspi_asdr is a 32 bits regist er, the upper 16 bits are only used, when tsb is enabled. for non tsb configurations only the leas t 16 significant bits are used. address: dspi_base + 0xc0 access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ser_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ser_data w reset00 00000000000000 figure 25-13. dspi dsi serialization data register (dspi_sdr) table 25-21. dspi_sdr field descriptions field description 0?31 ser_data serialized data. the ser_data field contains th e signal states of t he parallel input signals. address: dspi_base + 0xc4 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r aser_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r aser_data w reset00 00000000000000 figure 25-14. dspi dsi alternate seri alization data register (dspi_asdr)
deserial serial peripheral interface (dspi) freescale semiconductor 25-29 pxr40 microcontroller reference manual, rev. 1 25.3.2.13 dspi dsi transmit comp arison register (dspi_compr) the dspi_compr holds a copy of the last transmit ted dsi data. the dspi_compr is read-only. dsi data is transferred to this register as it is loaded into the tx shift register. the dspi_compr is a 32 bits register, the upper 16 bits are only used, when tsb is enabled. for non tsb configurations only the leas t 16 significant bits are used. 25.3.2.14 dspi dsi de serialization data register (dspi_ddr) the dspi_ddr register holds the signal states for the parallel ou tput signals. the dspi_ddr is read-only and it is memory mapped so that hos t software can read the incoming dsi frames. table 25-22. dspi_asdr field descriptions field descriptions 0?31 aser_data alternate serialized data. the aser_data fiel d holds the alternate data to be serialized. address: dspi_base + 0xc8 access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rcomp_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcomp_data w reset00 00000000000000 figure 25-15. dspi dsi transmit comparison register (dspi_compr) table 25-23. dspi_compr field descriptions field description 0?31 comp_data compare data. the comp_data field holds the last serialized dsi data.
deserial serial peripheral interface (dspi) 25-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.3.2.15 dspi dsi configuratio n register 1 (dspi_dsicr1) the dsi configuration register 1 se lects various attributes associated with tsb configuration. the user must not write to the dspi_dsicr1 while the dspi is in the running state. if tsb configuration is not used the register value is ignored. address: dspi_base + 0xcc access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r deser_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r deser_data w reset00 00000000000000 figure 25-16. dspi deserialization data register (dspi_ddr) table 25-24. dspi_ddr field descriptions field descriptions 0?15 deser_dat a deserialized data. when t sb configuration is set, the deser_d ata field holds deserialized data which is presented as signal states to the paralle l output signals. if tsb is disabled these bits are ignored, and only the lower 16 bits are valid. 16?31 deser_dat a deserialized data. the deser_data field holds des erialized data which is presented as signal states to the parallel output signals. address: dspi_base + 0xd0 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 0 tsbcnt 000000 dse1 dse0 w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00 000000 dpcs1_7 dpcs1_6 dpcs1_5 dpcs1_4 dpcs1_3 dpcs1_2 dpcs1_1 dpcs1_0 w reset00 00000000000000 figure 25-17. dspi dsi configur ation register 1 (dspi_dsicr1)
deserial serial peripheral interface (dspi) freescale semiconductor 25-31 pxr40 microcontroller reference manual, rev. 1 25.4 functional description the deserial serial peripheral interface (dspi) block supports full-dupl ex, synchronous serial communications between mcus and peripheral devices. the dspi can also be used to reduce the number of pins required for i/o by serial izing and deserializing up to 16 pa rallel input/output signals. all table 25-25. dspi_sdr field descriptions field description 0?2 reserved, should be cleared. 3?7 tsbcnt timed serial bus operation count. when tsbc is set, tsbcnt defines the length of the tsb frame. a number between 4 and 32. the tsbcnt field selects number of bits to be sh ifted out during a transfer in tsb operation. the field sets the number of sck cycles that the bus master will generate to complete the transfer. the number of sck cycles used will be one more than t he value in the tsbcnt field. the number of sck cycles defined by tsbcnt must be equal to or greater than the frame size. 8?13 reserved, should be cleared. 14 dse1 data select enable1. when tbsc bit is set, the d se1 bit controls insertion of the zero bit (data select) in the middle of the data frame. the inse rtion bit position is defined by fmsz field of dspi_ctarn register, selected by dsictas field of the dspi_dsicr register. 0 no zero bit inserted in th e middle of the data frame. 1 zero bit is inserted at the middle of the data fr ame. total number of bits in the data frame is increased by 1. 15 dse0 data select enable0. when tbsc bit is set, the d se0 bit controls insertion of the zero bit (data select) in the beginning of the data frame. 0 no zero bit inserted in the beginning of the frame 1 zero bit is inserted at the beginning of the data frame. total number of bits in the data frame is increased by 1. 16?23 reserved, should be cleared. 24?31 dpcs1_ x dsi peripheral chip select 0?7. these bits define the cs to assert for the second part of the dsi frame when operating in tsb configuration with dua l receiver. the dpcs1 bits select which of the pcs signals to assert during the second dsi transfer. the dpcs1 bits only control the assertions of the pcs signals in dsi master mode when in tsb configuration. 0 negate pcs[x] 1 assert pcs[x] tsbcnt framesize 00000 reserved 00001 reserved 00010 reserved 00011 4 00100 5 00101 6 ... ... 11111 32
deserial serial peripheral interface (dspi) 25-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 communications are through a spi-lik e protocol.specifically in the tsb configuration, the dspi can serialize up to 32 parallel input signals or 32 registered bits. the dspi has three configurations: ? spi configuration in which the dspi operates as a basic spi or a queued spi. ? dsi configuration in which the dspi serializes and deserializes parallel input/output signals or bits from memory mapped registers. ? csi configuration in which the dspi comb ines the functionality of the spi and dsi configurations. the dconf field in the dspi m odule configuration register (d spi_mcr) determines the dspi configuration. see table 25-5 for the dspi configuration values. the dspi_ctar0 - dspi_ctar7 regist ers hold clock and transfer attr ibutes. the spi configuration can select which ctar to use on a frame by frame ba sis by setting a field in the spi command. the dsi configuration statically selects which ctar to use. in csi configuration priority logic determines if spi data or dsi data is transferred. the type of data transferred dict ates which ctar register the csi configuration will use. see section 25.3.2.3, dspi clock and transfer attributes registers 0?7 (dspi_ctar0?dspi_ctar7) , for information on the fields of the dspi_ctar registers. the 16-bit shift register in the mast er and the 16-bit shift re gister in the slave ar e linked by the sout and sin signals to form a distributed 32- bit register. the master and slave use 16-bit shift registers regardless the tsbc bit is asserted in the ds pi_dsicr register. when a data tr ansfer operation is performed, data is serially shifted a predetermined number of bit pos itions. because the registers are linked, data is exchanged between the master and the sl ave; the data that was in the mast er?s shift register is now in the shift register of the slave, and vice versa. at the e nd of a transfer, the tcf bit in the dspi_sr is set to indicate a completed transfer. figure 25-18 illustrates how master a nd slave data is exchanged. figure 25-18. spi and dsi serial protocol overview the dspi has eight peripheral chip se lect (pcs) signals that are used to select which of the slaves to communicate with. the three dspi configurations share transfer prot ocol and timing properties so they are described independently of th e configuration in section 25.4.7, transfer formats . the transfer rate and delay settings are described in section 25.4.6, dspi baud rate and clock delay generation . see section 25.4.11, power saving features , for information on the power-s aving features of the dspi. shift register baud rate generator shift register sin sin sout sout sck sck ss pcsx dspi master dspi slave
deserial serial peripheral interface (dspi) freescale semiconductor 25-33 pxr40 microcontroller reference manual, rev. 1 25.4.1 modes of operation the dspi has these distinct modes: ? master mode ? slave mode ? module disable mode ? external stop mode ? debug mode master, slave, and module disable modes are bloc k-specific modes while external stop and debug modes are mcu-specific modes. the block-specific modes are determ ined by bits in the dspi_mcr register. external stop mode and debug mode are modes that the entire mcu can enter in parallel with the dspi being configured in one of its block-specific modes. 25.4.1.1 master mode in master mode the dspi can initia te communications with peripheral devices. the dspi operates as bus master when the mstr bit in the dspi_mcr register is set. the seri al communications clock (sck) is controlled by the master dspi. all three dspi configurations are va lid in master mode. in spi configuration, master mode transfer attributes are controlled by the spi command in the current tx fifo entry. the ctas field in the spi command se lects which of the eight dspi_ctar registers will be used to set the transfer attributes. transfer attribute control is on a frame by frame basis. see section 25.4.3, serial peripheral interface (spi) configuration , for more details. in dsi configuration, master mode transfer attributes are controll ed by the dspi dsi configuration register (dspi_dsicr). the dsisctas field in th e dspi_dsicr selects wh ich of the dspi_ctar registers will be used to set the tr ansfer attributes. transfer attribut es are set up during initialization and should not be changed between frames. see section 25.4.4, deserial serial interface (dsi) configuration , for more details. in csi configuration, the ds i data is transferred usi ng dsi configuration transfer attributes and spi data is transferred using the spi configur ation transfer attributes. in orde r for the bus slave to distinguish between dsi and spi frames, the transfer attributes for the two types of frames must utilize different peripheral chip select signals. see section 25.4.5, combined serial in terface (csi) configuration , for details. 25.4.1.2 slave mode in slave mode the dspi responds to transfers initiated by a spi master. the dspi operates as bus slave when the mstr bit in the dspi_mcr is negated. the dspi slave is selected by a bus master by having the slave?s ss asserted. in slave mode the sck is provided by the bus master. all transfer attributes are controlled by the bus master but cloc k polarity, clock phase and numbers of bits to transfer must still be configured in the dspi sl ave for proper communications.
deserial serial peripheral interface (dspi) 25-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the spi and dsi configurations are va lid in slave mode. in spi slave m ode the slave transfer attributes are set in the dspi_ctar0. in dsi slave mode the sl ave transfer attributes ar e set in the dspi_ctar1. in both spi and dsi confi gurations the dspi in slave mode transf ers data msb first. the lsbfe field of the associated ctar is ignored. 25.4.1.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi can be stopped while in module disable mode.the dspi en ters the module disable mode when the mdis bit in dspi_mcr is set or wh en a request for the dspi to enter doze mode is asserted by an external controller while the doze bit in the dspi_mcr is asserted. logic external to the dspi is needed to implemen t the module disable mode. see section 25.4.11, power saving features , for more details on the module disable mode. 25.4.1.4 external stop mode for devices with low-power modes, the dspi supports the stop mode mechanism. the dspi will not acknowledge the request to enter ex ternal stop mode until it has reached a frame boundary. when the dspi has reached a frame boundary it will halt all operations and indicate that it is ready to have its clocks shut off. the dspi exits external stop mode and resumes normal opera tion once the clocks are turned on. serial communications or register accesses made while in external st op mode are ignored even if the clocks have not been shut off yet. see section 25.4.11, power saving features , for more details on the external stop mode. 25.4.1.5 debug mode the debug mode is used for system development and debugging. if the device enters debug mode while the frz bit in the dspi_mcr is set, the dspi stops a ll serial transfers and enters a stopped state. if the device enters debug mode while the frz bit is negated, the dspi behavior is unaffected and remains dictated by the block-specific mode and configuration of the dspi. th e dspi enters debug mode when a debug request is asserted by an external controller. see figure 25-19 for a state diagram. 25.4.2 start and stop of dspi transfers the dspi has two operating states; stopped and running. the states are independent of dspi configuration. the default state of the dspi is stopped. in the sto pped state no serial transfers are initiated in master mode and no transfers are res ponded to in slave mode. the stopped state is also a safe state for writing the various c onfiguration registers of the dspi without causin g undetermined results. the txrxs bit in the dspi_sr is nega ted in this state. in the running state serial tran sfers take place. the txrxs bit in the dspi_sr is asserted in the running state. figure 25-19 shows a state diagram of the start and stop mechanism. the transitions are described in table 25-26 .
deserial serial peripheral interface (dspi) freescale semiconductor 25-35 pxr40 microcontroller reference manual, rev. 1 figure 25-19. dspi start and stop state diagram state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 25.4.3 serial peripheral in terface (spi) configuration the spi configuration transfers data serially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when the dc onf field in the dspi_mcr is 0b00. the spi frames can be from four to sixteen bits long. the data to be transmitted can come from queues stored in ram external to the dspi . host software or a dma controller can transfer the spi data from the queues to a first-in first-out (fifo) buffer. the re ceived data is stored in entries in the receive fifo (rx fifo) buffer. host software or a dma controller transfer the rece ived data from the rx fifo to memory external to the dspi. the fi fo buffer operations are described in section 25.4.3.4, transmit first in first out (tx fifo) buffering mechanism , and section 25.4.3.5, receive first in first out (rx fifo) buffering mechanism . the interrupt and dma reques t conditions are described in section 25.4.10, interrupts/dma requests . the spi configuration supports two block-specific modes; master mode and slave mode. the fifo operations are similar for th e master mode and slave m ode. the main difference is that in master mode the dspi initiates and controls the tr ansfer according to the fields in th e spi command field of the tx fifo table 25-26. state transitions for start and stop of dspi transfers transition # current state next state description 0 reset stopped generic power-on-reset transition 1 stopped running the dspi is started (dspi tr ansitions to running) when all of the following conditions are true: ? eoqf bit is clear ? debug mode is unselected or the frz bit is clear ? halt bit is clear 2 running stopped the dspi stops (transitio ns from running to stopped) after the current frame for any one of the following conditions: ? eoqf bit is set ? debug mode is selected and the frz bit is set ? halt bit is set reset stopped running power on txrxs=0 txrxs=1 reset 2 1 0
deserial serial peripheral interface (dspi) 25-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 entry. in slave mode the dspi only responds to transf ers initiated by a bus master external to the dspi and the spi command field of th e tx fifo entry is ignored. 25.4.3.1 master mode in spi master mode the d spi initiates the serial transfers by cont rolling the serial communications clock (sck) and the peripheral chip sel ect (pcs) signals. the spi command field in the executing tx fifo entry determines which ctar register s will be used to set the transfer attributes and which pcs signal to assert. the command field also cont ains various bits that help with queue management and transfer protocol. see section 25.3.2.6, dspi push tx fi fo register (dspi_pushr) , for details on the spi command fields. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (sout) pin. in spi master mode, each spi fram e to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. 25.4.3.2 slave mode in spi slave mode the dspi responds to transfers initiated by a spi bus master. the dspi does not initiate transfers. certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with a spi master. the spi slave mode transfer attributes are set in the dspi_ctar0. 25.4.3.3 fifo disable operation the fifo disable mechanisms allo w spi transfers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when th e fifos are disabled. the tx and rx fifos are disabled separately. the tx fifo is disabled by writing a ?1? to the dis_txf bit in the dspi_mcr. the rx fifo is disabled by writing a ?1? to the dis_rxf bit in the dspi_mcr. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the dspi_p ushr and received data is read from the dspi_popr.when the tx fifo is disabled the tfff, tfuf a nd txctr fields in dspi_sr behave as if there is a one-entry fifo but the contents of the dspi_txfr registers a nd txnxtptr are undefined. when the rx fifo is disabled the rfdf, rfof and rxctr fields in the d spi_sr behave as if there is a one-entry fifo but the contents of the dspi_rxfr re gisters and popnxtptr are undefined. 25.4.3.4 transmit first in first ou t (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands fo r transmission. the tx fifo holds four words, each consisting of a co mmand field and a data field. spi co mmands and data are added to the tx fifo by writing to the dspi pu sh tx fifo register (dspi_pushr ). tx fifo entries can only be removed from the tx fifo by being sh ifted out or by flushing the tx fifo. the tx fifo counter field (txctr ) in the dspi status register (dspi_sr) indicates the number of valid entries in the tx fifo. the txctr is updated ev ery time the dspi _pushr is written or spi data is transferred into the shift register from the tx fifo. the txnxtptr field indicates which tx fifo entry will be transmitted during the next transfer. the txnxtptr contains the positive offs et from dspi_txfr0 in number of 32-bit registers. for example,
deserial serial peripheral interface (dspi) freescale semiconductor 25-37 pxr40 microcontroller reference manual, rev. 1 txnxtptr equal to two means that the dspi_txfr2 contains the spi data and command for the next transfer. the txnxtptr field is increm ented every time spi data is transferred from the tx fifo to the shift register. 25.4.3.4.1 filling the tx fifo host software or other intelligent blocks can add (push) entries to the tx fifo by writing to the dspi_pushr. when the tx fi fo is not full, the tx fi fo fill flag (tfff) in the dspi_sr is set. the tfff bit is cleared when tx fifo is full and the dma controller indicates that a wr ite to dspi_pushr is complete or by host so ftware writing a ?1? to the tfff in the dspi_sr. the tfff can generate a dma request or an interrupt request. see section 25.4.10.2, transmit fifo f ill interrupt or dma request , for details. the dspi ignores attempts to push data to a full tx fifo, i.e. the stat e of the tx fifo is unchanged. no error condition is indicated. 25.4.3.4.2 draining the tx fifo the tx fifo entries are removed (drained) by shifting spi data out through the sh ift register. entries are transferred from the tx fifo to the shift register and shifted out as l ong as there are valid entries in the tx fifo. every time an entry is transferred from the tx fifo to the shift regi ster, the tx fifo counter is decremented by one. at the end of a transfer, th e tcf bit in the dspi_sr is set to indicate the completion of a transfer. the tx fifo is flushe d by writing a ?1? to the clr_txf bit in dspi_mcr. if an external bus master initiates a transfer with a dspi slave while th e slave?s dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave?s dspi_sr is set. see section 25.4.10.4, transmit fifo underflow interrupt request , for details. 25.4.3.5 receive first in first ou t (rx fifo) buffering mechanism the rx fifo functions as a buffer for data received on the sin pin. the rx fi fo holds four received spi data frames. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fi fo. spi data are removed (popped) from the rx fifo by reading the dspi pop rx fifo re gister (dspi_popr). rx fifo entr ies can only be removed from the rx fifo by reading the dspi_p opr or by flushing the rx fifo. the rx fifo counter field (rxctr) in the dspi st atus register (dspi_sr) indicates the number of valid entries in the rx fifo. the rxctr is updated ev ery time the dspi _popr is read or spi data is copied from the shift re gister to the rx fifo. the popnxtptr field in the dspi_sr points to th e rx fifo entry that is returned when the dspi_popr is read. the popnxtptr contains the positive offset from dspi_rxfr0 in number of 32-bit registers. for example, popnxtptr equal to two means that the dspi_rxfr2 contains the received spi data that will be retu rned when dspi_popr is read. th e popnxtptr field is incremented every time the dspi_popr is read.
deserial serial peripheral interface (dspi) 25-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.4.3.5.1 filling the rx fifo the rx fifo is filled with the rece ived spi data from the shift regist er. while the rx fifo is not full, spi frames from the shift register are transferred to th e rx fifo. every time a spi frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift regi ster are full and a transfer is initiated, the rfof bit in the dspi_sr is asserted indicating an overflow condition. depend ing on the state of the rooe bit in the dspi_mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. if the rooe bit is asserted, the incoming data is shifted in to the sh ift register. if the rooe bit is negated, the incoming data is ignored. 25.4.3.5.2 draining the rx fifo host software or other intelligent blocks can remove (pop) entries from the rx fifo by reading the dspi pop rx fifo register (dspi_popr). a read of th e dspi_popr decrements the rx fifo counter by one. attempts to pop data from an empty rx fifo are i gnored, the rx fifo counter remains unchanged. the data returned from reading an empty rx fifo is undetermined. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the dspi_s r is set. the rfdf bit is cleared when the rx_fifo is empty and the dma co ntroller indicates that a read from dspi_popr is complete or by host software writing a ?1? to the rfdf. 25.4.4 deserial serial interface (dsi) configuration the dsi configuration supports pin c ount reduction by serializing parallel input signals or register bits and shifting them out in a spi-lik e protocol. the timing and transf er protocol is described in section 25.4.7, transfer formats . the received serial frames are converted to a parallel form (deserialized) and placed on the parallel output sign als or in a register. the various features of the dsi configuration are set in dspi dsi confi guration register (dspi_ds icr). the dspi is in ds i configuration when the dconf field in the dspi_mcr is 0b01. the dsi frames can be from four to sixteen bits long, but four to 32 bits can be used in the tsb configuration (see section 25.4.9, timed serial bus (tsb) , for detailed information). with multiple transfer operation (mto) the dspi s upports serial chaining of dspi bloc ks within a device to create dsi frames consisting of concatenated bi ts from multiple dspis. the dspi also supports parallel chaining allowing several dspis and off-chip spi devices to share the same serial communications clock (sck) and peripheral chip sel ect (pcs) signals. see section 25.4.4.6, multiple transfer operation (mto) , for details on the serial an d parallel chaining support. 25.4.4.1 dsi master mode in dsi master mode the dspi initia tes and controls the dsi transfers. the dsi master has four different conditions that can initiate a transfer: ? continuous ? change in data ? trigger signal
deserial serial peripheral interface (dspi) freescale semiconductor 25-39 pxr40 microcontroller reference manual, rev. 1 ? trigger signal combined with a change in data the four transfer initiation conditions are described in section 25.4.4.5, dsi transfer initiation control . transfer attributes are set during initialization. the dsictas fiel d in the dspi_dsicr determines which of the dspi_ctar registers will control the transfer attributes. 25.4.4.2 dsi slave mode in dsi slave mode the dspi responds to transfers in itiated by a spi or dsi bus master. in this mode the dspi does not initiate dsi transfers. certain transfer attributes such as clock polarity and phase must be set for successful communication with a dsi master. the dsi slave mode tr ansfer attributes are set in the dspi_ctar1. if the cid bit in the dspi_dsicr is set and the data in the dspi_compr differs from the selected source of the serialized data, the slav e dspi will assert the mtrig signal. if the slave?s ht signal is asserted and the trre is set, the slave dspi asserts mtrig . these features are included to support chaining of several dspi. details about the mtrig signal is found in section 25.4.4.6, multiple transfer operation (mto) . 25.4.4.3 dsi serialization in the dsi configuration from four to sixteen bits can be se rialized using two differ ent sources. the txss bit in the dspi_dsicr selects between the dspi ds i serialization data register (dspi_sdr) and the dspi dsi alternate serialization da ta register (dspi_asdr) as the s ource of the serialized data. the dspi_sdr holds the latest parallel input signal values which is sampled at every rising edge of the system clock. the dspi_asdr register is writt en by host software and used as an alternate source of serialized data. a copy of the last 32-bit dsi frame shifted out of the shift register is stored in the dspi dsi transmit comparison register (dspi_compr). th is register provides added visibi lity for debugging and it serves as a reference for transfer initiation control. figure 25-20 shows the dsi serialization logic. figure 25-20. dsi serialization diagram dsi config. sout shift register ht 01 15 clock logic sck txss 0 1 register control logic dsi transmit comparison register pcs dsi serialization data register 32 32 32 dspi alternate serialization data register parallel inputs 32 0 1 16 slave bus interface
deserial serial peripheral interface (dspi) 25-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.4.4.4 dsi deserialization when all bits in a dsi frame have been shifted in, the frame is copied to the dspi dsi deserialization data register (dspi_ddr). this regi ster presents the deserialized data as parallel output signal values. the dspi_ddr is memory mapped to allow host soft ware to read the deserialized data directly. figure 25-21 shows the dsi deserialization logic. figure 25-21. dsi deserialization diagram 25.4.4.5 dsi transfer initiation control data transfers for a master dspi in dsi configuration are initiated by a condition. the transfer initiation conditions are selected by the trre and cid bits in the dspi_dsicr. table 25-27 lists the four transfer initiation conditions. 25.4.4.5.1 continuous control for continuous control the initiation of a transfer is based on the baud ra te at which data is transferred between the dspi and the external device. the baud rate is set in the dspi_ctar register selected by the dsictas field in the dspi_dsicr. a new dsi frame sh ifts out when the previous transfer cycle has completed and the delay after transfer (t dt ) has elapsed. 25.4.4.5.2 change in data control for change in data control a transfer is initiated wh en the data to be seria lized has changed since the transfer of the last dsi frame. a copy of the pr eviously transferred dsi data is stored in the dspi_compr. when the data in the dspi_sdr or th e dspi_asdr is different from the data in the dspi_compr a new dsi frame is transmitted. the tx ss bit in the dspi_dsicr selects which register table 25-27. dsi data transfer initiation control dspi_dsicr bits transfer initiation control trre cid 0 0 continuous 0 1 change in data 1 0 triggered 1 1 triggered or change in data sin shift register 01 n-1 control logic dsi deserialization data register n n parallel outputs in tsb configuration the number of bits n = 32, for non tsb it values 16. slave bus interface
deserial serial peripheral interface (dspi) freescale semiconductor 25-41 pxr40 microcontroller reference manual, rev. 1 the dspi_compr is compared to. the mtrig output signal is asserted ever y time a change in data is detected. 25.4.4.5.3 triggered control for triggered control initiation of a transfer is controlled by the hard ware trigger signal (ht). the tpol bit in the dspi_dsicr selects the active edge of ht . for ht to have any affect, the trre bit in the dspi_dsicr must be set. 25.4.4.5.4 triggered or c hange in data control for triggered or change in data c ontrol initiation of a transfer is c ontrolled by the ht signal or by the detection of a change in data to be serialized. 25.4.4.6 multiple transfer operation (mto) in dsi configuration the mto feature allows for multiple dspis within a device to be chained together in a parallel or serial c onfiguration. the parallel chai ning allows multiple dspis internal to a device and multiple spi devices external to a device to shar e sck and pcs signals there by saving pins. the serial chaining allows bits from multiple dspis to be concatenated into a single dsi frame. mto is enabled by setting the mtoe bit in the dspi_dsicr. in parallel and serial chaining ther e is one bus master and multiple bus slaves. the bus master initiates and controls the transfers, but the dspi slaves generate trigger signals for the bus dspi master when an internal condition in the slave warrants a transfer. th e dspi slaves also propag ate triggers from other slaves to the master. when a dspi slave detects a trigger signal on it s ht input, the slave generates a trigger signal on the mtrig output. serial and parallel chaining require multip lexing of signals external to the dspi. 25.4.4.6.1 parallel chaining note when using the dspi in dsi mode, wi th mto enabled, and clock phase set to leading edge capture (dspix_ctarn [cpha]=0) the first bit shifted out of the master dspi into the slave dspi is read as ?1?, regardless of the actual value. to account for this behavior, the following options are recommended: ? select cpha=1 (following edge capture), if suitab le for external slave devices. ? set the first bit of the transferred data to ?1?, or ignore the first bit. ? externally connect master sout to si n of the first slave, rather than connecting via internal signals. this requires setting siu_disr_sinsel x bits of the first slave dspi to ?00? and configuring the first slav e's sin pin and master sout pin as dspi sin and dspi sout, respectively.
deserial serial peripheral interface (dspi) 25-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 parallel chaining allows multiple dspis internal to a device and multiple spi/dsi devices external to a device to share common sck and pc s signals thereby saving pins. tw o pins are saved per pair of dspi/spi. figure 25-22 shows an example of how the bloc ks can be connected in a device. figure 25-22. example of parallel chaining of dspis the dspi master controls and initiates all transfer, but the dspi slaves have a trigger output signal mtrig that indicates to the master dspi to start a transfer. when the dspi slave has a change in its data to be serialized, it generate s a pulse on the mtrig signal to the master dspi which initiates the transfer. when a dspi slave has its ht signal asserted it also generates a pulse on its mtrig signal thereby propagating trigger signals from other dspi slaves to the dspi master. the mtocnt field in the dspi_dsicr must be written with the number of bits to be transferred. in parallel chaining the num ber written to mtocnt must match the fmsz field in the selected dspi_ctar register. 25.4.4.6.2 serial chaining the serial chaining allows tr ansfers of dsi frames of up to a total of 64 bits, usi ng transfers of smaller dsi frames concatenated toge ther by multiple dspis. figure 25-23 shows an example of how the blocks can be connected in a device. sout sout sin sin pcs[x] ss sck sck dspi master dspi slave ss sck sin sout soc sin sck ss sout mtrig ht spi slave device spi slave device sout sin ss sck dspi slave sin sck ss sout mtrig spi slave device ht
deserial serial peripheral interface (dspi) freescale semiconductor 25-43 pxr40 microcontroller reference manual, rev. 1 figure 25-23. example of serial chaining of dspis the sout of the dspi master is conne cted to the sin of the first dspi slave. the sout of the first dspi slave is connected to the sin input of the second sl ave and so on. the sout of the last dspi slave is connected to the sin of the external spi slave. the sout of the external spi slave is connected to the sin of the dspi master. the dspi master controls and initiates all transfer s, but the slave dspis us e the trigger output signal mtrig to indicate to the dspi master that a trigge r condition has occurred. wh en a dspi slave has a change in data to be serialized it asserts the mtrig signal to the dspi master which initiates the transfer. when a dspi slave has its ht signal asserted it will assert its mtrig signal thereby pr opagating trigger signals from other dspi sl aves to the dspi master. the mtocnt field in the dspi_dsicr must be written with the total number of bits to be transferred. the mtocnt field must equal the sum of all fmsz fi elds in the selected dspi_ctar registers for the dspi master and all dspi slaves. for example if one 16-bit dsi fr ame is created by concatenating eight bits from the dspi master , and four bits fr om each of the dspi slaves in figure 25-23 , the dspi master?s frame size must be set to eight in the fmsz field, and the dspi slaves? frame size must be set to four. the largest dsi frame supported by the mtocnt field is 64 bits. any num ber of dspis can be connected together to concatenate dsi frames , as long as each dspi transfers a minimum of 4 bits and a maximum of 16 bits and the total size of the concatenat ed frame is less than or equal to 64 bits long. 25.4.5 combined serial inte rface (csi) configuration the csi configuration of the dspi is used to s upport spi and dsi functions on a frame by frame basis. csi configuration allows interleaving of dsi data frames from the parallel input signals with spi commands and data from the tx fifo. the data returned from the bus slave is either used to drive the parallel output signals or it is st ored in the rx fifo. the csi confi guration allows serialized data and configuration or diagnos tic data to be transferred to a slave device using only one serial link. the dspi is in csi configuration wh en the dconf field in the dspi_mcr is 0b10. figure 25-24 shows an example sout sout sin sin pcs[x] ss sck sck dspi master dspi slave ss sck sin sout spi slave device soc mtrig ht sout sin ss sck dspi slave mtrig ht
deserial serial peripheral interface (dspi) 25-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 of how a dspi can be used with a deserializing peripheral that s upports spi control for control and diagnostic frames. figure 25-24. example of system using dspi in csi configuration in csi configuration the dspi transfers dsi data ba sed on dsi transfer initiation control. when there are spi commands in the tx fifo, the spi data has priority over the dsi frames . when the tx fifo is empty, dsi transfer resumes. two peripheral chip select signals indicate whether ds i data or spi data is transmitted. the user must configure the dspi so that the two ctar registers associated with dsi data and spi data assert different peripheral chip select signa ls denoted in the figure as pcsx an d pcsy. the csi configuration is only supported in master mode. data returned from the external slave while a dsi fr ame is transferred is placed on the parallel output signals. data returned from the exte rnal slave while a spi fr ame is transferred is moved to the rx fifo. the tx fifo and rx fifo are fully functional in csi mode. 25.4.5.1 csi serialization serialization in the csi configurat ion is similar to serialization in dsi configuration. the transfer attributes for spi frames are determined by the dspi_c tar register selected by th e ctas field in the spi command halfword. the transfer attri butes for the dsi frames are dete rmined by the dspi_ctar register selected by the dsictas field in the dspi_dsicr. figure 25-25 shows the csi serialization logic. shift register sin sin sout sout sck sck ssx pcsx dspi master external slave deserializer ssy pcsy spi frame select logic frame dsi frame shift register spi dsi tx priority control tx fifo
deserial serial peripheral interface (dspi) freescale semiconductor 25-45 pxr40 microcontroller reference manual, rev. 1 figure 25-25. csi serialization diagram the parallel inputs signal states are latched into th e dspi dsi serialization da ta register (dspi_sdr) on the rising edge of every system cl ock and serialized based on the tran sfer initiation control settings in the dspi_dsicr. when spi frames are written to the tx fifo they have priority over dsi data from the dspi_sdr and are transferred at the next frame boundary. a copy of th e most recently transferred dsi frame is stored in the dspi_compr. the transfer priority logic selects the source of the serialized data and asserts the appropriate cs signal. 25.4.5.2 csi deserialization the deserialized frames in csi configuration goes into the dspi_sdr or the rx fifo based on the transfer priority logic. when dsi frames are transferred the returned frames are deserialized and latched into the dspi_ddr. when spi frames are transferred the returned fr ames are deserialized and written to the rx fifo. figure 25-26 shows the csi deserialization logic. figure 25-26. csi deserialization diagram dsi control clock logic register control logic dsi transmit comparison register dsi serialization data register 16 tx fifo parallel pcsx (spi) sout shift register 01 15 16 16 16 logic priority transfer pcsy (dsi) inputs sck (p_in) slave bus interface dsi deserialization data register 16 rx fifo 16 16 parallel sin shift register 01 15 control logic 16 logic priority transfer outputs (p_out) slave bus interface
deserial serial peripheral interface (dspi) 25-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.4.6 dspi baud rate and clock delay generation the sck frequency and the delay values for serial tr ansfer are generated by dividing the system clock frequency by a prescaler and a scaler wi th the option for doubling the baud rate. figure 25-27 shows conceptually how the sck signal is generated. figure 25-27. communications clock prescalers and scalers 25.4.6.1 baud rate generator the baud rate is the frequency of the serial comm unication clock (sck). the system clock is divided by a prescaler (pbr) and scal er (br) to produce sck with the possibi lity of halving the scaler division. the dbr, pbr and br fields in the dspi_ctar regist ers select the frequency of sck by the formula in the br[0:3] field description. table 25-28 shows an example of how to compute the baud rate. 25.4.6.2 pcs to sck delay (t csc ) the pcs to sck delay is the length of time from as sertion of the pcs signal to the first sck edge. see figure 25-29 for an illustration of the pcs to sck delay. the pcssck and cssck fields in the dspi_ctar x registers select the pcs to sck delay by th e formula in the cssck[0:3] bit description. table 25-29 shows an example of how to compute the pcs to sck delay. 25.4.6.3 after sck delay (t asc ) the after sck delay is the length of time between th e last edge of sck and the negation of pcs. see figure 25-29 and figure 25-30 for illustrations of th e after sck delay. the pasc and asc fields in the dspi_ctar x registers select the after sck delay by the formula in the asc[0:3] field description. table 25-30 shows an example of how to compute the after sck delay. table 25-28. baud rate computation example pbr prescaler br scaler dbr f periph baud rate 0b00 2 0b0000 2 0 100 mhz 25 mb/s 0b00 2 0b0000 2 1 20 mhz 10 mb/s table 25-29. pcs to sck delay computation example pcssck prescaler cssck scaler f periph pcs to sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s table 25-30. after sck delay computation example pasc prescaler asc scaler f periph after sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s sck system clock prescaler 1 scaler 1+dbr
deserial serial peripheral interface (dspi) freescale semiconductor 25-47 pxr40 microcontroller reference manual, rev. 1 25.4.6.4 delay after transfer (t dt ) the delay after transfer is the length of time be tween negation of the pcs signal for a frame and the assertion of the pcs signal for the next frame. see figure 25-29 for an illustration of the delay after transfer. the pdt and dt fields in the dspi_ctar x registers select the delay after transfer by the formula in the dt[0:3] field description. table 25-31 shows an example of how to compute the delay after transfer. when in non-continuous clock mode the t dt delay is configurable as outlined in the dspi_ctarx registers. when in continuous clock mode and tsb is not enabled the de lay is fixed at 1 sck period. when in tsb and continuous mode the dela y is programmed as outli ned in the dspi_ctarx registers but in the event that the delay does not coincide with an sck pe riod in duration the delay is extended to the next sck active edge. table 25-32 shows an example of how to compute the delay after transfer with the clock period of sck defined as t sck . the values calculated assume 1 tsck period = 4 ipg_clk. table 25-31. delay after transfer computation example pdt prescaler dt scaler f periph delay after transfer 0b01 3 0b1110 32768 100 mhz 0.98 ms table 25-32. delay after transfer computation example in tsb configuration pdt field t dt 1 (tsck) 0123 dt field 0 2 1234 1 1357 2 2 61014 3 4 12 20 28 4 8 24 40 56 5164880112 6 32 96 160 224 7 64 192 320 448 8 128 384 640 896 9 256 768 1280 1792 10 512 1536 2560 3584 11 1024 3072 5120 7168 12 2048 6144 10240 14336 13 4096 12288 20480 28672 14 8192 24576 40960 57344 15 16384 49152 81920 114688
deserial serial peripheral interface (dspi) 25-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.4.6.5 peripheral chip sele ct strobe enable (pcss ) the pcss signal provides a delay to allow the pcs signals to settle after a transition occurs thereby avoiding glitches. when the dspi is in master mode and pcsse bit is set in the dspi_mcr, pcss provides a signal for an exte rnal demultiplexer to decode the pcs[ 0] -pcs[4] and pcs[6] -pcs[7] signals into as many as 128 glitch-free pcs signals. figure 25-28 shows the timing of the pcss signal relative to pcs signals. figure 25-28. peripheral chip select strobe timing the delay between the assertion of the pcs signals and the assertion of pcss is selected by the pcssck field in the dspi_ctar based on the following formula: eqn. 25-5 at the end of the transf er the delay between pcss negation and pcs negation is selected by the pasc field in the dspi_ctar based on the following formula: eqn. 25-6 table 25-33 shows an example of how to compute the t pcssck delay. table 25-34 shows an example of how to compute the t pasc delay. the pcss signal is not supported when continuous serial communicati on sck is enabled (cont_scke=1). notes: 1 some values are not reachable (i. e. 9, 11, 13, 15, 17, 18, 19...), to calculate these values, please see the equation 25-3 2 the values in this row were rounded to the next integer value table 25-33. peripheral chip select strobe assert computation example pcssck prescaler f periph delay before transfer 0b11 7 100 mhz 70.0 ns table 25-34. peripheral chip select strobe negate computation example pasc prescaler f periph delay after transfer 0b11 7 100 mhz 70.0 ns t pcssck pcss pcsx t pasc t pcssck 1 f periph -------------- pcssck ? = t pasc 1 f periph ------------- - pasc ? =
deserial serial peripheral interface (dspi) freescale semiconductor 25-49 pxr40 microcontroller reference manual, rev. 1 25.4.7 transfer formats the spi serial communication is c ontrolled by the serial communicat ions clock (sck) signal and the pcs signals. the sck signal provided by the master device synchronizes sh ifting and sampling of the data on the sin and sout pins. the pcs signals serv e as enable signals for the slave devices. when the dspi is the bus master, the cpol and cpha bits in the dspi clock and transfer attributes registers (dspi_ctarx) select the pol arity and phase of the serial cl ock, sck. the polarity bit selects the idle state of the sck. the clock phase bit selects if the data on sout is valid before or on the first sck edge. when the dspi is the bus slave, cpol and cpha bits in the dspi_c tar0 (spi) or dspi_ctar1 (dsi) select the polarity and phase of th e serial clock. for spi slaves the dspi_ctar0 is used, and for dsi slaves the dspi_ctar1 is used. even though the bus slave does not control the sck signal, clock polarity, clock phase and number of b its to transfer must be identical for the master device and the slave device to ensure proper transmission. the dspi supports four different transfer formats: ? classic spi with cpha=0 ? classic spi with cpha=1 ? modified transfer format with cpha = 0 ? modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more se tup time. the mtfe bit in the dspi_mcr selects between classic spi format and modified transfer format. th e classic spi format s are described in section 25.4.7.1, classic spi transfer format (cpha = 0) , and section 25.4.7.2, classic spi transfer format (cpha = 1) . the modified transfer form ats are described in section 25.4.7.3, modified spi/ds i transfer format (mtfe = 1, cpha = 0) , and section 25.4.7.4, modified spi/dsi transfer format (mtfe = 1, cpha = 1) . in the spi and dsi configurations , the dspi provides the option of keeping the pcs signals asserted between frames. see section 25.4.7.5, continuous selection format , for details. 25.4.7.1 classic spi transfer format (cpha = 0) the transfer format shown in figure 25-29 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format , the master and slave sample their sin pins on the odd-num bered sck edges and change the data on their sout pi ns on the even-numbered sck edges.
deserial serial peripheral interface (dspi) 25-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 25-29. dspi transfer timing diagram (mtfe=0, cpha=0, fmsz=8) the master initiates the transfer by placing its first data bi t on the sout pin and a sserting the appropriate peripheral chip select signals to th e slave device. the slave responds by placing its first data bit on its sout pin. after the t csc delay has elapsed, the master outputs the first edge of sck. this is the edge used by the master and slave devices to sample the first input data bit on their serial data input signals. at the second edge of the sck the master and slave devices pl ace their second data bit on their serial data output signals. for the rest of the frame the master and the slave sample th eir sin pins on the odd-numbered clock edges and changes the data on their sout pins on th e even-numbered clock edge s. after the last clock edge occurs a delay of t asc is inserted before the master ne gates the pcs signa ls. a delay of t dt is inserted before a new frame transfer ca n be initiated by the master. 25.4.7.2 classic spi transfer format (cpha = 1) this transfer format shown in figure 25-30 is used to communicate with pe ripheral spi slav e devices that require the first sck edge before th e first data bit becomes available on the slave sout pin. in this format the master and slave devices change the data on th eir sout pins on the odd -numbered sck edges and sample the data on their sin pins on the even-numbered sck edges t csc sck master and slave pcsx/ss sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 master sout/ master sin/ t dt t csc t csc = pcs to sck delay t dt = delay after transfer (minimum cs idle time) (cpol = 0) (cpol = 1) t asc slave sin slave sout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sample t asc = after sck delay
deserial serial peripheral interface (dspi) freescale semiconductor 25-51 pxr40 microcontroller reference manual, rev. 1 figure 25-30. dspi transfer timing diagram (mtfe=0, cpha=1, fmsz=8) the master initiates the tran sfer by asserting the pcs signal to the slave. after the t csc delay has elapsed, the master generates the first sck edge and at the same time places valid data on the master sout pin. the slave responds to the first sck edge by pl acing its first data bit on its slave sout pin. at the second edge of the sck the master and slave sa mple their sin pins. for the rest of the frame the master and the slave change the data on their sout pins on the odd-numbered clock edges and sample their sin pins on the even-numbere d clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the pcs signal. a delay of t dt is inserted before a ne w frame transfer can be initiated by the master. 25.4.7.3 modified spi/dsi transfer format (mtfe = 1, cpha = 0) in this modified transfer format both the master a nd the slave sample later in the sck period than in classic spi mode to allow for delays in device pa ds and board traces. these delays become a more significant fraction of the sck period as the sck period decrea ses with increasing baud rates. the master and the slave places data on the sout pins at the assertion of the pcs signal. after the pcs to sck delay has elapsed the first sck edge is generated. the slave samples the master sout signal on every odd numbered sck edge. the slave also places new data on the slave sout on every odd numbered clock edge. t csc t dt sck sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 t csc = pcs to sck delay t dt = delay after transfer (minimum cs negation time) (cpol = 0) (cpol = 1) t asc master sout/ master sin/ slave sin slave sout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pcsx/ss master and slave sample t asc = after sck delay
deserial serial peripheral interface (dspi) 25-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the master places its second data bit on the sout line one system clock af ter odd numbered sck edge. the point where the master samples the slave sout is selected by writing to the smpl_pt field in the dspi_mcr. the smpl_pt field description in table 25-5 lists the number of system clock cycles between the active edge of sck and the master sample point. the master sample point can be delayed by one or two system clock cycles. figure 25-31 shows the modified transfer format for cp ha = 0. only the condition where cpol = 0 is illustrated. the delayed master sample points are indicated with a lighter shaded arrow. figure 25-31. dspi modified transfer format (mtfe=1, cpha=0, f sck = f periph /4) 25.4.7.4 modified spi/dsi transfer format (mtfe = 1, cpha = 1) figure 25-32 shows the modified transfer format for cp ha = 1. only the conditio n where cpol = 0 is described. at the start of a transfer the dspi assert s the pcs signal to the slave device. after the pcs to sck delay has elapsed the master and the slave put data on their sout pins at th e first edge of sck. the slave samples the master sout signal on the even numbered edges of sck. the master samples the slave sout signal on the odd numbere d sck edges starting with the th ird sck edge. the slave samples the last bit on the last edge of the sck. the master samples the last slave sout bit one half sck cycle after the last edge of sc k. no clock edge will be visible on th e master sck pin during the sampling of the last bit. the sck to pcs delay must be greater or equal to half of the sck period. t csc sck system master slave pcs t csc = pcs to sck delay sout master sout sample slave sample sys 1 2 3 4 5 6 clock t asc clk sys clk t asc = after sck delay
deserial serial peripheral interface (dspi) freescale semiconductor 25-53 pxr40 microcontroller reference manual, rev. 1 figure 25-32. dspi modified transfer format (mtfe=1, cpha=1, f sck = f periph /4) 25.4.7.5 continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential se rial transfers. the continuous selecti on format provides the flexibility to handle both cases. the continuous sel ection format is enabled for the spi configuration by setting the cont bit in the spi command. cont inuous selection is enabled for th e dsi configuration by setting the dcont bit in the dspi_dsicr . the behavior of the pcs signals in the two configur ations is identical so only spi configuration will be described. when the cont bit = 0, the dspi drives the asserted ch ip select signals to thei r idle states in between frames. the idle states of the ch ip select signals are selected by the pcsis field in the dspi_mcr. figure 25-33 shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 0. t csc sck system clock master slave pcs slave master sout sout sample sample t csc = pcs to sck delay t asc t asc = after sck delay 1 2 3 4 5 6
deserial serial peripheral interface (dspi) 25-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 25-33. example of non-continuous format (cpha=1, cont=0) when the cont bit = 1, the pcs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt) is not inserted between the transfers. figure 25-34 shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 1. figure 25-34. example of continuous transfer (cpha=1, cont=1) switching ctar registers or changing which pcs si gnals are asserted betw een frames while using continuous selection can cause errors in the transfer . the pcs signal should be negated before ctar is switched or different pcs signals are selected. t csc t dt t csc sck pcsx sck master sout master sin t csc = pcs to sck delay t dt = delay after transfer (minimum cs negation time) (cpol = 0) (cpol = 1) t asc t asc = after sck delay t csc t csc sck pcs sck master sout master sin t csc = pcs to sck delay (cpol = 0) (cpol = 1) t asc (cpol = 0) sck t asc = after sck delay
deserial serial peripheral interface (dspi) freescale semiconductor 25-55 pxr40 microcontroller reference manual, rev. 1 warning during continuous selection mode, to avoid generation of erroneous data, do not change the dspi x _ctar values between frames in the following conditions: ? if dspi x _ctarn[cpha=1] and dspi x _mcr[cont_scke]=0, do not change dspi x _ctarn[cpol, cpha, pcssck or pbr] between frames. ?if dspi x _ctarn[cpha]=0 or dspi x _mcr[cont_scke]=1, do not change any bit field of dspi x _ctarn, except [pbr], between frames. 25.4.8 continuous serial communications clock the dspi provides the option of ge nerating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by setting the cont_sck e bit in the dspi_mcr. co ntinuous sck is valid in all configurations. continuous sck is only s upported for cpha=1. setting cpha=0 will be ignored if th e cont_scke bit is set. continuous sck is supporte d for modified transfer format. clock and transfer attributes fo r the continuous sck mode are set according to the following rules: ? when the dspi is in spi configuration, ctar0 shal l be used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame shall be used. ? when the dspi is in dsi configuration, the ctar specified by the dsicta s field shall be used at all times. ? when the dspi is in csi configuration, the ctar selected by the dsictas field shall be used initially. at the start of a spi frame transfer, th e ctar specified by the ctas value for the frame shall be used. at the start of a dsi frame transfer, the ctar speci fied by the dsictas field shall be used. ? in all configurations, the currently selected ctar shall remain in use until the start of a frame with a different ctar specified, or the continuous sck mode is terminated. it is recommended that the baud rate is the same fo r all transfers made while using the continuous sck. switching clock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into the external stop mode or module disable mode. enabling continuous sck disables the pcs to sck delay and the delay after transfer (t dt ) is fixed at one t sck cycle. when tsb configuration is enabled the t dt is programmable to a minimum of 1xt sck cycles by configuring pdt and dt valu es in the respective ctar register. figure 25-35 shows timing diagram for continuous sck format wi th continuous selection disabled.
deserial serial peripheral interface (dspi) 25-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 25-35. continuous s ck timing diagram (cont=0) if the cont bit in the tx fifo entry is set or the dcont in the dspi_dsicr is set, pcs remains asserted between the transfers. u nder certain conditions, sck can conti nue with pcs asserted, but with no data being shifted out of sout (sout pulled high). this can cause the slave to receive incorrect data. those conditions include: ? continuous sck with cont bit set, but no data in the transmit fifo. ? continuous sck with cont bit set a nd entering stopped state (refer to section 25.4.2, start and stop of dspi transfers ). ? continuous sck with cont bit set and en tering stop mode or module disable mode. figure 25-36 shows timing diagram for continuous sck fo rmat with continuous selection enabled. figure 25-36. continuous s ck timing diagram (cont=1) 25.4.9 timed serial bus (tsb) the dspi can be programmed in timed serial bus configuration by asserting the tsbc bit in the dspi_dsicr register, see section 25.3.2.10, dspi dsi configur ation register (dspi_dsicr) , for t dt sck pcs sck master sout master sin (cpol = 0) (cpol = 1) sck pcs sck master sout master sin (cpol = 0) (cpol = 1) transfer 1 transfer 2
deserial serial peripheral interface (dspi) freescale semiconductor 25-57 pxr40 microcontroller reference manual, rev. 1 details. to work in tsb configurat ion the dspi must be in master m ode and configured as dsi (dconf = 0b01). the tsb allows operating in continuous and non continuous serial communication clock (controlled by bit cont_scke). figure 25-37 shows the signals used in the tsb interface. the sdr and asdr registers are set to 32 bits in this configuration, to allow the micro se cond channel (msc) feature to be performed. in the tsb configuration the dspi manage to send from 4 up to 32 bits data. these bits source data can be either from the dspi dsi alternate serializat ion data register (dspi_ asdr), written by the host software, or from parallel input pi n states latched into the dspi dsi serialization data register (dspi_sdr). figure 25-37. dspi usage in the tsb configuration the same constraints applied to dsi are valid to tsb, but the frame size and the delay after transfer value (t dt ). the tsb configuration a llows from 4 to 32 bits frame size to be used, and t dt can be programmable to a minimum of 1xt sck , allowing a programmable inter-message gap. see table 25-12 and table 25-32 for details on programming the t dt values. the time between the negation of the cs at the end of one frame to the assertion of cs at the next frame is defined by: t dt = p dt * dt / f periph, but delayed until the ne xt active edge of t sck . the gap is only be whole period of tsck and th e pdt and dt fields of the specific ds pi_ctar0-7 register select the delay after transfer. some values will not be possible, see the reference manual for details. sout (downstream frame) sck pcs dsi (master) 32 bit data register (asdr) 32 bit (sdr) serial data gpio or command data writes parallel inputs
deserial serial peripheral interface (dspi) 25-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 25-38. tsb downstream frame the figure 25-38 shows the two types of downstream frames, command frame, and data frame, used in the tsb configuration, refer to section 25.4.9.1, pcs switch over timing , and section 25.4.9.3, tsb data frame format , for detailed information. the command wo rd can be written by software, and the data word consisting of 32 bits words, from the sd r or asdr registers. only the downstream frame is supported in the tsb configuration, the upstream frame can be handled by software using any available serial input. the selection bit, the star t bit for a frame, is not a requirement but could be implemen ted by software. the number of the frame bits can be in th e range of 4 to 32 bits. in this c onfiguration the leas t significant bit of a frame should be transmitted first (lsbfe = 1). 25.4.9.1 pcs switch over timing when in tsb mode it is possible to switch the set of pcs signals that ar e driven during the first part of the frame to a different set of pcs signals during the second part of the frame. the bit at which this switch over occurs is contained in the dsicr register. in order to maximize both the set up and hold time margins on the old and new pcs signals the timing of the switch over occurs on the active edge of the master sck data capture between the last bit of the first part of the frame and the fi rst bit of the second part of the frame. for exam ple, if the first part of the frame is 5 bits and the second part of the frame is 10 bits the pcs signals will switch at the active edge of the master sck in between bits 5 and 6 of the frame as seen by the slave. the exact timing between the external signals sck and pc s signals will not be exac tly aligned due to routing and pad differences. this approach ensures that larger/shorter sck peri ods will result in approximately symmetric increases/decreases of setup and hold margins on th e pcs signals. the setup time for the pcs signals before the first bit of the first part of the frame and the hold time for th e pcs signals after the last bit of the second part of the frame are unchanged in this mode with respect to the other modes and remain controlled by the csc and asc delay fields re spectively when not in continuous sck mode. t dt data frame invalid lsb active phase 0 sck pcs master sout t dt = from 1 to 64 t sck invalid command frame t dt command frame = 4 to 32 bits lsb 1 selection bit data frame = 4 to 32 bits (cpol = 0) active phase
deserial serial peripheral interface (dspi) freescale semiconductor 25-59 pxr40 microcontroller reference manual, rev. 1 25.4.9.2 tsb command frame format in the tsb configuration a command frame is shown in figure 25-39 . figure 25-39. command frame format in the active phase of the command frame, the chip select becomes active va lidating the sout and sck output signals. outside the active phase, chip select is at passive level and invali d data may occur at sout. for tsb configuration, assuming cpol = 0, the sout output and the chip select changes it s state always with the sck rising edge. the sout si gnal must be sampled in the slave device with the falling edge of sck. the clock period of sck is defined as t sck . the length of the command frame passive phase t dt should always be fixed to a minimum of 1x t sck . 25.4.9.3 tsb data frame format a data frame is transmitted from the ts b controller to the receiving devices, figure 25-40 details the frame active and passive phase, for tsb configuration assuming cpol = 0, the sout output and the chip select change their states always with the sck rising edge. the sout signal mu st be sampled in the receiving device with the falling edge of sck. the length of the data frame passive phase t dt can be a minimum of 1xt sck . a data frame can be composed by data bits only or by data bits preceded by a selection bit, see figure 25-40 . a data frame with a selection bit always starts with a low level bit at sout. the number of data bits in the active phase is from 4 to 32 bits, and the le ast significant bit of a data portion is transmitted first (lsbfe = 1). sck pcs master sout invalid command frame t dt command frame = 0 to 32 bits lsb 1 command selection bit (cpol = 0) active phase t dt = from 1 to (pdt * dt / f periph )t sck
deserial serial peripheral interface (dspi) 25-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 25-40. tsb data frame format 25.4.10 interrupts/dma requests the dspi has four conditions that can only generate interrupt requests and two conditions that can generate interrupt or dma request. table 25-35 lists the six conditions. each condition has a flag bit in the dspi status register (dspi_sr) and an request enable bit in the dspi dma/interrupt request select and enable register (dspi_rser). the tx fifo fill flag (tfff) and rx fifo drain flag (rfd f) generate interrupt requests or dma requests dependi ng on the tfff_dirs and rfdf_dirs bits in the dspi_rser. 25.4.10.1 end of queue interrupt request the end of queue request indicates that the end of a transmit queue is reached. the end of queue request is generated when the eoq bit in the executing spi command is asserted and the eoqf_re bit in the dspi_rser is asserted. 25.4.10.2 transmit fifo fill interrupt or dma request the transmit fifo fill reque st indicates that the tx fifo is not fu ll. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, table 25-35. interrupt and dma request conditions condition flag interrupt dma end of queue (eoq) eoqf x tx fifo fill tfff x x transfer complete tcf x tx fifo underflow tfuf x rx fifo drain rfdf x x rx fifo overflow rfof x sck pcs master sout t dt data frame 1 data frame 2 invalid t dt invalid lsb lsb active phase active phase 0 0 data selection bit data frame = 4 to 32 bits t dt = from 1 to (pdt * dt / f periph ) tsck
deserial serial peripheral interface (dspi) freescale semiconductor 25-61 pxr40 microcontroller reference manual, rev. 1 and the tfff_re bit in the dspi_rser is assert ed. the tfff_dirs bit in the dspi_rser selects whether a dma request or an in terrupt request is generated. 25.4.10.3 transfer complete interrupt request the transfer complete request indicates the end of th e transfer of a serial frame. the transfer complete request is generated at the end of each frame tran sfer when the tcf_re bit is set in the dspi_rser. 25.4.10.4 transmit fifo un derflow interrupt request the transmit fifo underflow re quest indicates that an underflo w condition in the tx fifo has occurred. the transmit underflow condi tion is detected only for dspi bl ocks operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in slave mode and spi configuration is empty, and a transfer is initiated from an external spi master. if the tfuf bit is set while the tfuf_re bit in the dspi_rser is asse rted, an interrupt request is generated. 25.4.10.5 receive fifo drai n interrupt or dma request the receive fifo drain request indicates that th e rx fifo is not empty. the receive fifo drain request is generated when the number of entries in th e rx fifo is not zero, and the rfdf_re bit in the dspi_rser is asserted. the rfdf_dirs bit in the dspi_rser selects whether a dma request or an interrupt request is generated. 25.4.10.6 receive fifo o verflow interrupt request the receive fifo overflow request indicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow reque st is generated when rx fifo and shift regi ster are full and a transfer is initiated. the rfof_re bit in the dspi_rser must be set for the interrupt request to be generated. depending on the state of the rooe bit in the dspi_mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift re gister. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. 25.4.11 power saving features the dspi supports three power-saving strategies: ? external stop mode ? module disable mode - clock ga ting of non-memory mapped logic ? clock gating of slave bus signals and clock to memory-mapped logic the external stop mode requires a bl ock external to the dspi to im plement the soc power management and clock gating control. all power saving feat ures require logic external to the dspi. figure 25-41 shows an example on how the dspi power savi ng features can be used in a device.
deserial serial peripheral interface (dspi) 25-62 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 25-41. example of a dspi in a device with a power management block 25.4.11.1 stop mode (external stop mode) the dspi supports the stop mode protocol. when a reque st is made to enter exte rnal stop mode, the dspi block acknowledges the request by negating ipg_stop_ack. when the dspi is ready to have its clocks shut off the ipg_stop_ack signal is asserted. if a serial transfer is in progress, the dspi wa its until it reaches the frame boundary before it asserts ipg_stop_ack. while th e clocks are shut off, the dspi memory-mapped logic is not accessible. the states of the interrupt and dma request signals ca nnot be changed while in external stop mode. 25.4.11.2 module disable mode module disable mode is a block-specif ic mode that the dspi can enter to save power. host software can initiate the module disable mode by writing a ?1? to the mdis bit in the d spi_mcr. the module disable mode can also be initiated by ha rdware. a power management block can initiate module disable mode by asserting the ipg_doze signal while the doze bit in the dspi_mcr is asserted. when the mdis bit is asserted or the ipg_doze signal is asse rted while the doze bit is asserted, the dspi negates ipg_enable_clk at the ne xt frame boundary. if implemented, th e ipg_enable_clk signal can stop the clock to the non-memory mapped logic. when ipg_enable_clk is negated, the dspi is in a dormant state, but the memory mapped register s are still accessible. cert ain read or write opera tions have a different affect when the dspi is in the m odule disable mode. reading the rx fi fo pop register will not change the state of the rx fifo. likewise, wr iting to the tx fifo pu sh register will not ch ange the state of the system clock d q soc power management block non-memory mapped area memory mapped area dspi frame boundary detection logic doze mdis & & & & & & & enable_clk doze stop_ack stop clk addr, byte_en, rwb, wdata module_en clk_s
deserial serial peripheral interface (dspi) freescale semiconductor 25-63 pxr40 microcontroller reference manual, rev. 1 tx fifo. clearing either of the fi fos will not have any af fect in the module disable mode. changes to the dis_txf and dis_rxf fields of the dspi_mcr wi ll not have any affect in the module disable mode. in the module disable mode, all status bits and register flags in the dspi will return the correct values when read, but writing to them will ha ve no affect. writing to the dspi_tcr during module disable mode will not have any af fect. interrupt and dma request signa ls cannot be cleared while in the module disable mode. 25.4.11.3 slave bus signal gating the dspi?s module enable signa l is used to gate slave bus signals su ch as address, byte enable, read/write and data. this prevents toggling slave bus signals from propagati ng through parts of the dspi?s combinational logic and c onsuming power unless it is a dspi acces s. the module enable signal can also be used to gate the clock to the memory-mapped logic. 25.5 initialization/application information 25.5.1 how to change queues this section presents an example of how to change queues for the dspi. the queues are not part of the dspi, but the dspi includes featur es in support of queue management. queues are primarily supported in spi configuration. 1. the last command word from a queue is execute d. the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the tran sfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the dspi_sr is set. 3. the setting of the eoqf flag wi ll disable both serial transmissi on, and serial reception of data, putting the dspi in the stopped state. the txrx s bit is negated to i ndicate the stopped state. 4. the dma will continue to fill tx fifo until it is full or step 5 occurs. 5. disable dspi dma transfers by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clea ring the corresponding dma en able request bits in the dma controller. 6. ensure all received data in rx fifo has been transferred to me mory receive queue by reading the rxcnt in dspi_sr or by checking rfdf in th e dspi_sr after each read operation of the dspi_popr. 7. modify dma descriptor of tx and rx channels for ?new? queues 8. flush tx fifo by writing a ?1? to the clr_tx f bit in the dspi_mcr, flush rx fifo by writing a ?1? to the clr_rxf bit in the dspi_mcr. 9. clear transfer count eith er by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the dspi_tcr. 10. enable dma channel by enabling the dma enable request for th e dma channel assigned to the dspi tx fifo, and rx fifo by setting th e corresponding dma set enable request bit. 11. enable serial transmission and serial reception of data by clearing the eoqf bit.
deserial serial peripheral interface (dspi) 25-64 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 25.5.2 baud rate settings table 25-36 shows the baud rate that is ge nerated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the dspi_ctar regist ers. the values calculated assume a 100 mhz system frequency and the double baud rate dbr bit is clear. 25.5.3 delay settings table 25-37 shows the values for th e delay after transfer (t dt ) and cs to sck delay (t csc ) that can be generated based on the prescaler values and the scaler values set in th e dspi_ctar registers. the values calculated assume a 100 mhz system frequency. this table does not apply for tsb continuous mode. table 25-36. baud rate values baud rate divider prescaler values 2357 baud rate scaler values 2 25.0m 16.7m 10.0m 7.14m 4 12.5m 8.33m 5.00m 3.57m 6 8.33m 5.56m 3.33m 2.38m 8 6.25m 4.17m 2.50m 1.79m 16 3.12m 2.08m 1.25m 893k 32 1.56m 1.04m 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78.1k 55.8k 512 97.7k 65.1k 39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.3k 9.77k 6.98k 4096 12.2k 8.14k 4.88k 3.49k 8192 6.10k 4.07k 2.44k 1.74k 16384 3.05k 2.04k 1.22k 872 32768 1.53k 1.02k 610 436
deserial serial peripheral interface (dspi) freescale semiconductor 25-65 pxr40 microcontroller reference manual, rev. 1 25.5.4 calculation of fifo pointer addresses the user has complete visibility of the tx and rx fifo contents th rough the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is me mory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtptr). for the rx fi fo the first-in pointer is the pop next pointer (popnxtptr). figure 25-42 illustrates the concept of first-in and last-in fifo entries along with the fifo counter. the tx fifo is chosen for the illust ration, but the concepts carry over to the rx fifo. see section 25.4.3.4, transmit first in first out (tx fifo) buffering mechanism , and section 25.4.3.5, receive first in first out (rx fifo) buffering mechanism , for details on the fifo operation. table 25-37. delay values delay prescaler values 1357 delay scaler values 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 ? s 32 320.0 ns 960.0 ns 1.6 ? s2.2 ? s 64 640.0 ns 1.9 ? s3.2 ? s4.5 ? s 128 1.3 ? s3.8 ? s6.4 ? s9.0 ? s 256 2.6 ? s7.7 ? s 12.8 ? s 17.9 ? s 512 5.1 ? s 15.4 ? s 25.6 ? s 35.8 ? s 1024 10.2 ? s 30.7 ? s 51.2 ? s 71.7 ? s 2048 20.5 ? s 61.4 ? s 102.4 ? s 143.4 ? s 4096 41.0 ? s 122.9 ? s 204.8 ? s 286.7 ? s 8192 81.9 ? s 245.8 ? s 409.6 ? s 573.4 ? s 16384 163.8 ? s 491.5 ? s 819.2 ? s 1.1 ms 32768 327.7 ? s 983.0 ? s 1.6 ms 2.3 ms 65536 655.4 ? s 2.0 ms 3.3 ms 4.6 ms
deserial serial peripheral interface (dspi) 25-66 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 25-42. tx fifo pointers and counter 25.5.4.1 address calculation for the firs t-in entry and last-i n entry in the tx fifo the memory address of the first-in entry in th e tx fifo is computed by the following equation: eqn. 25-7 the memory address of the last-in entry in the tx fifo is computed by the following equation: eqn. 25-8 tx fifo base - base address of tx fifo txctr - tx fifo counter txnxtptr - transmit next pointer tx fifo depth - transmit fifo depth, implementation specific 25.5.4.2 address calculation for the firs t-in entry and last-i n entry in the rx fifo the memory address of the first-in entry in th e rx fifo is computed by the following equation: eqn. 25-9 the memory address of the last-in entry in th e rx fifo is computed by the following equation: eqn. 25-10 rx fifo base - base address of rx fifo - - entry a (first in) entry b entry c entry d (last in) - - push tx fifo register transmit next data pointer shift register sout +1 -1 tx fifo counter tx fifo base first-in entry address tx fifo base 4 txnxtptr ? ?? + = last-in entry address tx fifo base 4 modulo tx fifo depth txctr txnxtptr 1 ? + ?? ? + = first-in entry address rx fifo base 4 popnxtptr ? ?? + = last-in entry address rx fifo base 4 modulo rx fifo depth rxctr popnxtptr 1 ? + ?? ? + =
deserial serial peripheral interface (dspi) freescale semiconductor 25-67 pxr40 microcontroller reference manual, rev. 1 rxctr - rx fifo counter popnxtptr - pop next pointer rx fifo depth - receive fifo depth, implement ation specific
deserial serial peripheral interface (dspi) 25-68 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 26-1 pxr40 microcontroller reference manual, rev. 1 chapter 26 enhanced serial communication interface (esci) 26.1 introduction the esci block is an enhanced sci block with a lin master interface layer and dma support. the lin master layer complies with the specifica tions lin 1.3, lin 2.0, lin 2.1, and sae j2602/1. 26.1.1 bibliography ? lin specification package revision 1.3; december 12, 2002 ? lin specification package revision 2.0; september 23, 2003 ? lin network for vehicle appli cations, sae j2602/1, september 1, 2005 ? lin specification package re vision 2.1; november 24, 2006 26.1.2 acronyms and abbreviations table 26-1 contains acronyms and abbreviations used in this document. 26.1.3 glossary table 26-1. acronyms and abbreviations term description esci enhanced sci block with lin support and dma support sci serial communications interface lin local interconnect network - a protocol for low-cost automobile networks lin pe lin protocol engine, finite state machine to control logic of the lin hardware. mclk module clock, defined in section 26.4.3.1, module clock tclk transmitter clock, defined in section 26.4.3.2, transmitter clock rclk receiver clock, defined in section 26.4.3.3, receiver clock rsc receiver sample counter, defined in section 26.4.3.3, receiver clock table 26-2. glossary term definition logic level one the voltage that corresponds to boolean true (1) state. logic level zero the voltage that corresponds to boolean false (0) state.
enhanced serial communication interface (esci) 26-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.1.4 overview the esci block allows asynchronous serial communica tions with peripheral devi ces and other cpus. it includes special support to in terface to lin slave devices. set to set a bit or bits means to establish logic level one on the bit or bits. clear to clear a bit or bits means to establish logic level zero on the bit or bits. asserted a signal that is asserted is in its active state. an active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one. preamble the term preamble describes an idle character which is transmitted by the esci module. bit time duration of a single bit in a transmitted byte field or character, equivalent to the duration of one transmitter clock cycle defined in section 26.4.3.2, transmitter clock frame entity that cons ists of the start bit followed by payload bits followed by one ore more stop bits lin byte field special instance of a frame sci frame special instance of a frame lin frame sequence of break charac ter followed by lin byte fields lin tx frame a lin frame with the frame header, data byte fields, and checksum field transmitted by the esci module lin rx frame a lin frame with the header field transmitted by the esci module and the data byte fields and checksum field received by the esci module table 26-2. glossary (continued) term definition
enhanced serial communication interface (esci) freescale semiconductor 26-3 pxr40 microcontroller reference manual, rev. 1 figure 26-1. esci block diagram 26.1.5 features the esci block includes these distinctive features: ? full-duplex operation ? standard mark/space non-return-to-zero (nrz) format ? 13-bit baud rate selection ? programmable frame, payl oad, and character format ? support of 2 stop bits in receiver path ? hardware parity generation and checking ? programmable even or odd parity ? programmable polarity of rxd pin ? separately enabled tr ansmitter and receiver ? two receiver wake up methods: ? idle line wake-up ? address mark wake-up ? interrupt-driven operation with eight flags: ? transmitter empty ? transmission complete ? receiver full receive shift register ? 16 rxd polarity control baud rate generator receive data register txd transmit data register transmit shift register internal data bus receive control wakeup control frame format control transmit control internal data bus interrupt generation loop control cpu irq rx dma channel dma ctrl tx dma channel dma ctrl lin pe tclk rclk bus clk
enhanced serial communication interface (esci) 26-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error ? receiver framing error detection ? 1/16 bit-time noise detection ? 2 channel dma interface ? lin support ? lin master node functionality (master and slave task) ? compatible with lin slaves from re visions 1.x and 2.0 of the lin standard ? detection of bit errors, physical bus errors and checksum errors ? all status bit can generate maskable interrupts ? application layer crc support ? programmable crc polynom ? detection and generatio n of wakeup characters ? programmable wakeup delimiter time ? programmable slave timeout ? can be configured to incl ude header bits in checksum ? lin dma interface 26.1.6 modes of operation the esci module has two functiona l operational modes, sci and lin mode, and low power modes. the availability of register bi ts and fields depends on the selected operational mode. 26.1.6.1 sci mode the sci mode is the default functional operational mode and is described in section 26.4.5, sci mode . 26.1.6.2 lin mode the lin mode is the second functional operational mode and is described in section 26.4.6, lin mode . 26.1.6.3 disabled mode in the disabled mode the esci m odule indicates to the clocking system , that all module clocks can be turned off. the esci module is in the disabled mode, if the mdis bit in the control register 2 (esci_cr2) is set.
enhanced serial communication interface (esci) freescale semiconductor 26-5 pxr40 microcontroller reference manual, rev. 1 26.1.6.4 stop mode when the esci module is in stop mode, it is inactive and indicates to the system, that all clocks to the esci modules can be turned off. the system requests the esci module to enter the st op mode by asserting the sy stem stop signal. when this happens, the esci module perf orms a shut down of th e ongoing transmission or reception as described in section 26.1.6.4.1, entering st op mode from sci mode , and section 26.1.6.4.3, if th e esci module is in stop mode and the system stop signal is de-asserte d and the lin bit and the mdis bit are 0, the esci module will enter the sci mode. the tr de flag will bet set. no data will be transmitted as long as new data provided by the application. if the receiver is still enabled, it starts the detection of the start bit.entering stop mode from lin mode . the system requests the esci module to leave the stop mode by de-assert ing the system stop signal. when this happens, the esci module then enters the operational m ode configured by the lin bit and the mdis bit. the related sequence is described in section 26.1.6.4.2, leaving stop mode into sci mode , and section 26.1.6.4.4, leaving stop mode into lin mode . 26.1.6.4.1 entering st op mode from sci mode if the esci module is in sci mode and the system st op signal is asserted while a sci frame or character transmission is running, the esci m odule performs a shut down of the tr ansmit process. therefore, it continues the ongoing frame or character transmission until the last bit of the sci frame or character has been transmitted. after the end of the transmission, all pendi ng transfer requests ar e cleared and no more data will be transmitted. none of the transmitter related register flags will be set if the esci module is in sci mode and the system st op signal is asserted while a sci frame or character reception is running, the module stops the reception immedi atley. none of the receiver related register flags will be set. if the esci module is in sci mode and the system stop signal is assert ed and no transmis sion or reception is running, the esci module will enter the stop mode. 26.1.6.4.2 leaving stop mode into sci mode 26.1.6.4.3 if the esci module is in stop mode and the system stop signa l is de-asserted and the lin bit and the mdis bit are 0, the esci module wi ll enter the sci mode. the trde flag will bet set. no data will be transmitted as long as new data provided by the application. if the receiver is still enabled, it starts the detection of the start bit. entering stop mode from lin mode if the esci module is in li n mode and the system stop signal is asse rted while a lin byte field or character transmission is running, the esci m odule performs a shut down of the tr ansmit process. therefore, it continues the ongoing lin byte field or character transm ission until the last bit of the lin byte field or character has been transmitted. after the end of the transmission, all pending tran sfer requests are cleared and no more data will be transmitted. none of th e transmitter related register flags will be set.
enhanced serial communication interface (esci) 26-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if the esci module is in li n mode and the system stop signal is asse rted while a lin byte field or character reception is running, the esci module aborts the rece ption immediatley. none of the receiver related register flags will be set. if the esci module is in lin mode and the system stop signal is asse rted and no transm ission or reception is running, the esci module resets the li n protocol engine to it s idle state, resets th e write access counter of the lin transmit register (esci_ltr) and enters the stop mode. 26.1.6.4.4 leaving stop mode into lin mode if the esci module is in stop mode and the system stop signal is de-assert ed and the lin bit is set and the mdis bit is 0, the esci module will enter the lin mode. the txrdy flag will bet set. no data will be transmitted as long as new lin frame header data provided by the application. if the receiver is still enabled, it starts the detection of the start bit. 26.2 external signal description the esci module is connected two a total of two external pins. 26.2.1 detailed signal descriptions 26.2.1.1 esci transmit pin (txd) this pin serves as transmit data output and as the receive data input of esci. 26.2.1.2 esci receive pin (rxd) this pin serves as receive data input of the esci. 26.3 memory map and register definition this section provides the memory map and a detail ed description of the memory mapped registers. 26.3.1 memory map table 26-3 provides a 32-bit view of the esci?s memory ma p. this table gives the register offset w.r.t. module base address esci_base. table 26-3. esci 32-bit memory map offset register 0x0000 baud rate register (esci_brr) control register 1 (esci_cr1) 0x0004 control register 2 (esci_cr2) sci data register (esci_dr) 0x0008 interrupt flag and status register 1 (esci_ifsr1) interrupt flag and status register 2 (esci_ifsr2)
enhanced serial communication interface (esci) freescale semiconductor 26-7 pxr40 microcontroller reference manual, rev. 1 table 26-4 provides a key for regist er figures and tables. 26.3.2 register descriptions this section consists of re gister descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. writes to a reserved register location do not have any effect and reads of these locations return a zero. details of register bit and field function follow the register diagrams, in bit order. 0x000c lin control register 1 (esci_lcr1) lin control register 2 (esci_lcr2) 0x0010 lin transmit register (esci_ltr) reserved 0x0014 lin receive register (esci_lrr) reserved 0x0018 lin crc polynomial register (esci_lpr) control register 3 (esci_cr3) 0x001c reserved table 26-4. register conventions convention description depending on its placement in the read or write row, in dicates that the bit is not readable or not writeable. fieldname identifies the field. its presen ce in the read or write row indicate s that it can be read or written. register field types rwm a read/write bit that may be modified by a es ci module in some fashion other than by a reset. w1c write one to clear. a flag bit that can be read, is cleared by writing a one, writing 0 has no effect. reset values 0 resets to zero. 1 resets to one. table 26-3. esci 32-bit memory map (continued) offset register
enhanced serial communication interface (esci) 26-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.3.2.1 baud rate register (esci_brr) this register provides the control value for the serial baud rate. the baud rate and clock generation is specified in section 26.4.3, baud rate and clock generation . a byte write access to only th e upper byte of this regist er (esci_brr[0:7] ) will not change the content of the register, instead, the wr itten byte is stored internally into a shadow register. a s ubsequent byte write access to only the lower byte of this register (e sci_brr[8:15]) updates the lower byte and copies the content of the shadow register into the upper byte. a byte write access to only the lower byte of this re gister (esci_brr[8:0]) wit hout a preceding byte write access to only the upper byte copies a value of all zero into the upper byte. a word write access to this register updates both the lower and upper byte immediately and is the recommended write access type for this register. 26.3.2.2 control register 1 (esci_cr1) this register provides bits to conf igure the functionality of the module , provides the interrupt enable bits for the interrupt flags provided in interrupt flag and status register 1 (esci_ifsr1) and provides the control bits for the transmitter and receiver. esci_base + 0x0000 write: anytime 0123456789101112131415 r r sbr w reset0000000000000100 figure 26-2. baud rate register (esci_brr) table 26-5. esci_brr field descriptions field description r reserved. these bits are reserved. they are read as 0. application must not write 1 to these bits. sbr serial baud rate. this field provides the baud rate control value sbr. esci_base + 0x0002 write: anytime 0123456789101112131415 r loops r rsrc m wake ilt pe pt tie tcie rie ilie te re rwu sbk w rwm reset0000000000000000 figure 26-3. control register 1 (esci_cr1)
enhanced serial communication interface (esci) freescale semiconductor 26-9 pxr40 microcontroller reference manual, rev. 1 table 26-6. esci_cr1 field descriptions field description loops loop mode select. this control bit together with the rsrc control bit defines the receiver source mode. the mode coding is defined in ta b l e 2 6 - 7 and the modes are described in section 26.4.5.3.2, re ceiver input mode selection . r reserved. this bit is reserved. it is read as 0. application must not write 1 to these bits. rsrc receiver source control. this control bit together wi th the loops control bit defines the receiver source mode. the mode coding is defined in ta b l e 2 6 - 7 and the modes are described in section 26.4.5.3.2, receiver input mode selection . m frame format mode. this control bi t together with the m2 bit of the control register 3 (esci_cr3) controls the frame format used. the supported frame form ats and the related settings are defines in section 26.4.2, frame formats . wake receiver wake-up condition. this control bit defines the wake-up condition for the receiver. the receiver wake-up is described in section 26.4.5.5, multiprocessor communication . 0 idle line wake-up. 1 address mark wake-up ilt idle line type. this control bit defines the type of idle line detection for the receiver wake-up. the two types are described in section 26.4.5.5.1, idle-line wakeup . 0 idle line detection starts after reception of a low bit. 1 idle line detection starts after reception of the last stop bit. pe parity enable. this control bit enables the parity bit gen eration and checking. the location of the parity bits is shown in section 26.4.2, frame formats . 0 parity bit generation and checking disabled. 1 parity bit generation and checking enabled. pt parity type. this control bit defines whether even or odd parity has to be used. 0 even parity (even number of ones in character clears the parity bit). 1 odd parity (odd number of ones in character clears the parity bit). tie transmitter interrupt enable. this bit controls the esci_ifsr1[trde] inte rrupt request generation. 0 tdre interrupt request generation disabled. 1 tdre interrupt request generation enabled. tcie transmission complete interrupt enable. this bit c ontrols the esci_ifsr1[tc] interrupt request generation. 0 tc interrupt request generation disabled. 1 tc interrupt request generation enabled. rie receiver full interrupt enable. this bit controls the esci_ifsr1[rdrf] interrupt request generation. 0 rdrf interrupt request generation disabled. 1 rdrf interrupt request generation enabled. ilie idle line interrupt enable. this bit controls theesci_ifsr1[idle] interrupt request generation. 0 idle interrupt request generation disabled. 1 idle interrupt request generation enabled. te transmitter enable. this control bit enables and disables the transmitter. the control features of the transmitter are described in section 26.4.5.2.1, transmitter states and transitions . 0 transmitter disabled. 1 transmitter enabled. re receiver enable.this control bit enables and disables the receiver. the control features of the receiver are described in section 26.4.5.3.1, receiv er states and transitions . 0 receiver disabled. 1 receiver enabled.
enhanced serial communication interface (esci) 26-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.3.2.3 control register 2 (esci_cr2) this register provides bits to conf igure the functionality of the module, and interrupt enable bits for the interrupt flags provided in interrupt flag and status register 1 (esci_ifsr1) and control bits for the transmitter and receiver. rwu receiver wake-up mode. this bit controls and indica tes the receiver wake-up mode, which is described in section 26.4.5.5, multiprocessor communication . 0 normal receiver operation. 1 receiver is in wake-up mode. note: this bit should be set in sci mode only. sbk send break character. this bit controls the transmission of break characters, which is described in section 26.4.5.2.7, break character transmission . 0 no break characters will be transmitted. 1 break characters will be transmitted. note: this bit should be set in sci mode only. table 26-7. receive source mode selection loops rscr receiver input mode 0 0 dual wire mode 01 reserved 1 0 loop mode 1 1 single wire mode esci_base + 0x0004 write: anytime 0123456789101112131415 r mdis fbr bstp berrie rxdma txdma brcl txdir besm bestp rxpol pmsk orie nfie feie pfie w reset0010000000000000 figure 26-4. control register 2 (esci_cr2) table 26-8. esci_cr2 field descriptions field description mdis module disabled mode. this bit controls the m odule mode of operation, which is described in section 26.1.6, modes of operation 0 module is not in disabled mode. 1 module is in disabled mode. fbr fast bit error detection. this bit controls the bit error detection mode. 0 standard bit error detection performed as described in section 26.4.6.5.3, standard bit error detection . 1 fast bit error detection performed as described in section 26.4.6.5.4, fast bit error detection . note: this bit is used in lin mode only. table 26-6. esci_cr1 field descriptions (continued) field description
enhanced serial communication interface (esci) freescale semiconductor 26-11 pxr40 microcontroller reference manual, rev. 1 bstp dma stop on bit error or physical bus error. this bi t controls the transmit dma requests generation in case of bit errors or physical bus errors. bit errors are indicated by the berr flag in the interrupt flag and status register 1 (esci_ifsr1) and physical bus errors are in dicated by the pberr flag in the interrupt flag and status register 2 (esci_ifsr2) . 0 transmit dma requests generated regardless of bit errors or physical bus errors. 1 transmit dma requests are not generated if esci_ifsr1[berr] flag or esci_ifsr2[pberr] flags are set. note: this bit is used in lin mode only. berrie bit error interrupt enable. this bit controls the berr interrupt request generation. 0 berr interrupt request generation disabled. 1 berr interrupt request generation enabled. rxdma receive dma control. this bi t enables the receive dma feature. 0 receive dma disabled. 1 receive dma enabled. txdma transmit dma control. this bit enables the transmit dma feature. 0 transmit dma disabled. 1 transmit dma enabled. brcl break character length. this bit is used to define the length of the break character to be transmitted. the settings are specified in section 26.4.2.2, break character formats . txdir txd pin output enable. this bit determines whether the txd pin is used as an output. 0 txd pin is not used as output. 1 txd pin is used as output. note: this bit is used in single wire mode only. besm fast bit error detect ion sample mode. this bit defi nes the sample point for the fa st bit error de tection mode. 0 sample point is rs9. 1 sample point is rs13. note: this bit is used in lin mode only. bestp transmit stop on bit error. if this control bit is set, the esci stops driving the lin bus immediately when a bit error has been detected, i.e. esci_i fsr1[berr]=1. additionally, the esci will not start a new byte transmission as long the berr interrupt flag is set. 0 transmission is not stopped on bit error. 1 transmission is stopped on bit error. note: this bit is used in lin mode only. rxpol rxd pin polarity. this bit contro ls the polarity of the rxd pin. see section 26.4.2.1.1, inverted data frame formats 0 normal polarity. 1 inverted polarity. pmsk parity bit masking. this bit defines whether the received parity bit is presented in the related bit position in the sci data register (esci_dr) . 0 the received parity bit is presented in the bit position related to the parity bit. 1 the value 0 is presented in the bit position related to the parity bit. orie overrun interrupt enable. this bit controls the esci_ifsr1[or] interrupt request generation. 0 or interrupt request generation disabled. 1 or interrupt request generation enabled. nfie noise interrupt enab le. this bit controls the esci_ifs r1[nf] interrupt request generation. 0 nf interrupt request generation disabled. 1 nf interrupt request generation enabled. table 26-8. esci_cr2 field descriptions (continued) field description
enhanced serial communication interface (esci) 26-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.3.2.4 sci data register (esci_dr) this register is used to provide transmit data and retrieve received data in sci mode. in lin mode any write access to this register is ignor ed and any read access returns all 0. in case of data transmission this register is used to provide a part of the transmit data. in case of data reception this register provides a part of the received data and related erro r information.if the applic ation writes to the lowe r byte of this register (esci_dr[8:15]), the internal commit flag icmt, which is not visible to the application, is set to indicate that the register has been updated and ready to transmit new data. if the application reads from the lower byte of this register (esci_dr[8:15]), a signal is send to the internal receiver unit to indi cate that the register was r ead and is ready to receive new data. the read access will not change the content of any register. feie frame error interrupt enable. this bit controls the esci_ifsr1[fe] inte rrupt request generation. 0 fe interrupt request generation disabled. 1 fe interrupt request generation enabled. pfie parity error interrupt enable. this bit contro ls the esci_ifsr1[pf] interrupt request generation. 0 pf interrupt request generation disabled. 1 pf interrupt request generation enabled. esci_base + 0x0006 write: anytime 0123456789101112131415 rrn tn err 0 rd[11:8] rd[7] rd[6:0] w td[7] td[6:0] reset0000000000000000 figure 26-5. sci data register (esci_dr) table 26-9. esci_dr field descriptions field description rn received most significant bit. the semantic of this bit depends on the frame format selected by esci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=1,pe=0]: value of received data bit 8 or address bit. [m2=0,m=1,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. [m2=1,m=0,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. [m2=1,m=1,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. it is 0 for all other frame formats. tn transmit most significant bit. the semantic of this bit depends on the frame format selected by esci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=1,pe=0]: value to be transmitted as data bit 8 or address bit. it is not used for all other frame formats. err receive error bit. this bit indicates the occurrence of the errors selected by the control register 3 (esci_cr3) during the reception of the frame presented in sci data register (esci_dr) . in case of an overrun error for subsequent frames this bit is set too. 0 none of the selected errors occured. 1 at least one of the selected errors occured. table 26-8. esci_cr2 field descriptions (continued) field description
enhanced serial communication interface (esci) freescale semiconductor 26-13 pxr40 microcontroller reference manual, rev. 1 26.3.2.5 interrupt flag and status register 1 (esci_ifsr1) this register provides inte rrupt flags that indicate the occurrence of module events. the related interrupt enable bits are located in control register 1 (esci_cr1) and control register 2 (esci_cr2) . rd[11:8] received data. the semantic of this field depends on the frame format selected by esci_cr3[m2] and esci_cr1[m]. [m2=1,m=1]: value of the received data bits 11:8. (rx=bitx). it is all 0 for all other frame formats. rd[7] received bit 7. the semantic of this bit depends on the format select ed by esci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=0,pe=0]: value of received bit7 or addr bit. [m2=0;m=0,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. for all other frame formats it is the value of received bit7. td[7] transmit bit 7. the semantic of this bit depends on the format selected by es ci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=0,pe=0]: value of transmit bit7 or addr bit. [m2=0;m=0,pe=1]: not used. parity bit is generated internally before transmission. for all other frame formats it is the value of transmit bit7. rd[6:0] received bits 6 to 0. value of received bitx is shown in bit rx td[6:0] transmit bits 6 to 0. value of bit tx is transmitted in bitx. esci_base + 0x0008 write: anytime 0123456789101112131415 r tdre tc rdrf idle or nf fe pf berr tact ract w w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 26-6. interrupt flag and status register 1 (esci_ifsr1) table 26-10. esci_ifsr1 field descriptions field description tdre transmit data register empty interrupt flag. this interrupt flag is set when the content of the sci data register (esci_dr) was transferred into internal shift register. note: this flag is set in sci mode only. tc transmit complete interrupt flag. this interrupt flag is set when a frame, break or idle character transmission has been completed and no data were written into sci data register (esci_dr) after the last setting of the tdre flag and the sbk bit in control register 1 (esci_cr1) is 0. this flag is set in lin mode, if the preamble wa s transmitted after the enabling of the transmitter. rdrf receive data register full interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the sci data register (esci_dr) . note: this flag is set in sci mode only. idle idle line interrupt flag. this interrupt flag is set when an idle character was detected and the receiver is not in the wakeup state. note: this flag is set in sci mode only. table 26-9. esci_dr field descriptions (continued) field description
enhanced serial communication interface (esci) 26-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.3.2.6 interrupt flag and st atus register 2 (esci_ifsr2) this register provides interrupt fl ags that indicate the occurrence of lin related events. the related interrupt enable bits are located in lin control register 1 (esci_lcr1) and lin control register 2 (esci_lcr2) . all interrupt flags in this regist er will be set in lin mode only. or overrun interrupt flag. this interrupt flag is se t when an overrun was detected as described in section 26.4.5.3.11, receiver overrun . note: this flag is set in sci mode only. nf noise interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the sci data register (esci_dr) or lin receive register (esci_lrr) and the receiver has detected noise during the reception of that frame, as described in section 26.4.5.3.13, bit sampling . fe framing error interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the sci data register (esci_dr) or lin receive register (esci_lrr) and the receiver has detected a framing error during the reception of that frame, as described in section 26.4.5.3.18, stop bit verification . pf parity error interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the sci data register (esci_dr) and the receiver has detected a parity error for the character, as described in section 26.4.5.4, reception error reporting . note: this flag is set in sci mode only. berr bit error interrupt flag. this flag is set when a bit error was detected as described in section 26.4.6.5.3, standard bit er ror detection . note: this flag is set in lin mode only. tact transmitter active. the status bit is set as long as the transmission of a frame or special character is ongoing. 0 no transmission in progress. 1 transmission in progress. ract receiver active. the bit will be set 3 receiver clock (rcl k) cycles after the successful qu alification of a start bit. this bit will be cleared, when an idle character was detected. 0 no reception in progress. 1 reception in progress. esci_base + 0x000a write: anytime 0123456789101112131415 r rxrdy txrdy lwake sto pberr cerr ckerr frc000000ureqovfl w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 26-7. interrupt flag and status register 2 (esci_ifsr2) table 26-10. esci_ifsr1 field descriptions (continued) field description
enhanced serial communication interface (esci) freescale semiconductor 26-15 pxr40 microcontroller reference manual, rev. 1 26.3.2.7 lin control register 1 (esci_lcr1) this register provides control bits to control and c onfigure the lin hardware. this register provides the interrupt enable bits for the interrupt flags in interrupt flag and status register 2 (esci_ifsr2) . table 26-11. esci_ifsr2 field descriptions field description rxrdy receive data ready interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the lin receive register (esci_lrr) . txrdy transmit data ready interrupt flag. this in terrupt flag is set when the content of the lin transmit register (esci_ltr) was process by the lin pe either to generate a frame header or to transmit frame data. lwake lin wakeup received interrupt flag. this interrupt flag is set when a lin wakeup character was received, as described in section 26.4.6.6, lin wakeup . sto slave timeout interrupt flag. this interrupt flag is set when a slave-not-resp onding-error is detected. a detailed description is given in section 26.4.6.5.5, slave-not-responding-error detection . pberr physical bus error interrupt flag. this interrupt flag is set when the receiver input remains unchanged for at least 31 rclk clock cycles after t he start of a byte transm ission, as described in section 26.4.6.5, lin error reporting . cerr crc error interrupt flag. this interrupt flag is set when an incorrect crc pattern was detected for a received lin frame. ckerr checksum error interrupt flag. this interrupt flag is set when a checksum error was detected for a received lin frame. frc frame complete interrupt flag. this interrupt flag is set when a lin tx frame has been completely transmitted or a lin rx frame has been completely received. ureq unrequested data received interrupt flag. this in terrupt flag is set when unrequested activity has been detected on the lin bus, as described in section 26.4.6.5, lin error reporting . ovfl overflow interrupt flag. this interrupt flag is set when an overflow as described in section 26.4.6.5.8, overflow detection was detected. esci_base + 0x000c write: anytime 0123456789101112131415 r lres 0 wud 00 prty lin rxie txie wuie stie pbie cie ckie fcie wwu reset0000000000000000 figure 26-8. lin control register 1 (esci_lcr1)
enhanced serial communication interface (esci) 26-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 26-12. esci_lcr1 field descriptions field description lres lin protocol engine reset. this bit cont rols the mode of the lin protocol engine. 0 lin protocol engine in operational mode. 1 lin protocol engine forced into idle state. wu lin bus wake-up trigger. this bit is used to trigger the generation of a wake-up si gnal on the lin bus, as described in section 26.4.6.6, lin wakeup . 0 write has no effect. 1 write triggers the generation of a wakeup signal. wud lin bus wake-up delimiter time. this field determines how long the lin pr otocol engine waits after the end of the transmitted wakeup signal, before starting the next lin frame transmission. 00 4 bit times. 01 8 bit times. 10 32 bit times. 11 64 bit times. prty parity generation control. this bit controls the generation of the two parity bits in the lin header. 0 parity bits generation disabled. 1 parity bits generation enabled. lin lin mode control. this bit controls w hether the device is in sci or lin mode. 0sci mode. 1 lin mode. rxie receive data ready interrupt enable. this bit cont rols the esci_ifsr2[rxrdy] interrupt request generation. 0 rxrdy interrupt request generation disabled. 1 rxrdy interrupt request generation enabled. txie transmit data ready interrupt enable. this bit cont rols the esci_ifsr2[txrdy] interrupt request generation. 0 txrdy interrupt request generation disabled. 1 txrdy interrupt request generation enabled. wuie lin wakeup received interrupt enable. this bit contro ls the esci_ifsr2[lwake] in terrupt reques t generation. 0 lwake interrupt request generation disabled. 1 lwake interrupt request generation enabled. stie slave timeout flag interrupt enable. this bit cont rols the esci_ifsr2[sto] interrupt request generation. 0 sto interrupt request generation disabled. 1 sto interrupt request generation enabled. pbie physical bus error interrupt enable. this bit cont rols the esci_ifsr2[pberr] interrupt request generation. 0 pberr interrupt request generation disabled. 1 pberr interrupt request generation enabled. cie crc error interrupt enable. this bit controls the esci_ifsr2[cerr] interrupt request generation. 0 cerr interrupt request generation disabled. 1 cerr interrupt request generation enabled. ckie checksum error interrupt enable. this bit controls the esci_ifsr2[ckerr] interrupt request generation. 0 ckerr interrupt request generation disabled. 1 ckerr interrupt request generation enabled. fcie frame complete interrupt enable. this bit contro ls the esci_ifsr2[frc] in terrupt request generation. 0 frc interrupt request generation disabled. 1 frc interrupt request generation enabled.
enhanced serial communication interface (esci) freescale semiconductor 26-17 pxr40 microcontroller reference manual, rev. 1 26.3.2.8 lin control register 2 (esci_lcr2) this register provides the interrupt en able bits for the interrupt flags in interrupt flag and status register 2 (esci_ifsr2) . 26.3.2.9 lin transmit register (esci_ltr) this register is used by the appli cation to initiate the lin frame head er generation for bot h lin tx frames and lin rx frames. if a lin tx fram e is generated, this register is us ed to provide the payload data for the lin tx frame. esci_base + 0x000e write: anytime 0123456789101112131415 r000000 uqie ofie 00000000 w reset0000000000000000 figure 26-9. lin control register 2 (esci_lcr2) table 26-13. esci_lcr2 field descriptions field description uqie unrequested data received interrupt enable. this bit controls the esci_ifs r2[ureq] interrupt request generation. 0 ureq interrupt request generation disabled. 1 ureq interrupt request generation enabled. ofie overflow interrupt enable. this bit controls the esci_ifsr2[ovfl] inte rrupt request generation. 0 ovfl interrupt request generation disabled. 1 ovfl interrupt request generation enabled. esci_base + 0x0010 write: anytime 76543210 r 1st w p id 2nd w len 3rd w csm cse crc td (=1) to (ignored) 4th+ w d reset00000000 figure 26-10. lin transmit register (esci_ltr) - lin tx frame generation 76543210 r 1st w p[1:0] id[5:0] 2nd w len 3rd w csm cse crc td (=0) to[11:8] 4th w to[7:0] reset00000000 figure 26-11. lin transmit register (esci_ltr) - lin rx frame generation
enhanced serial communication interface (esci) 26-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if the application initiates a lin tx frame transfer, i. e the td bit is set to 1, the content a nd usage shown in lin transmit register (esci_lt r) - lin tx frame generation applies. the initia tion and transmit of a tx frame is described in section 26.4.6.3, lin tx frame generation . if the application initiates an lin rx frame, i.e the td bit is set to 0, the content and usage shown in lin transmit register (esci_ltr) - lin rx frame generation applies. the initiation and transmit of a rx frame is described in section 26.4.6.4, lin rx frame generation . each write access to this register increments the internal write acce ss counter and enables the writing to the next field. the write acc ess counter is reset if ? the lin pe is in the idle state (esci_lcr1[lres] = 1) ? a lin tx frame was completely transmitted (esci_ifsr1[frc] was set to 1) ? a lin rx frame was completely rece ived (esci_ifsr1[frc] was set to 1) ? module has entered stop mode. table 26-14. esci_ltr field descriptions field description p identifier parity. this field provides the identifier parity which is used to create the protected identifier if the automatic identifier parity generation is disabled, i.e the prty bit in lin control register 1 (esci_lcr1) is 0. id identifier. this field is used for the identifier field in the protected identifier. len frame length. this field defines the number of data bytes to be transmitted or received. csm checksum model. this bit controls the checksum calculation model used. 0 classic checksum model (lin 1.3). 1 enhanced checksum model (lin 2.0). cse checksum enable. this bit control the generation and checking of the checksum byte. 0 no generation and checking of checksum byte. 1 generation and checking of checksum byte. crc crc enable. this bit controls the generation of checki ng standard or enhanced lin frames, which are described in section 26.4.6.2, lin frame formats . 0 standard lin frame generation and checking. 1 enhanced lin frame generation and checking. td transfer direction. this bit control the transfer di rection of the data, crc, and checksum byte fields. 0 data, crc, and checksum byte fields received, described in section 26.4.6.4, lin rx frame generation . 1 data, crc, and checksum byte fields transmitted, described in section 26.4.6.3, lin tx frame generation . to timeout value. the content of the field depends on the transfer direction. rx frame: defines the time available for a complete rx frame transfer, as described in section 26.4.6.5.4, fast bit error detection . tx frame: must be set to 0. d transmit data . data bits for transmission.
enhanced serial communication interface (esci) freescale semiconductor 26-19 pxr40 microcontroller reference manual, rev. 1 26.3.2.10 lin receive register (esci_lrr) this register provides the data bytes of recei ved in case of an lin rx frame was initiated. 26.3.2.11 lin crc polynomia l register (esci_lpr) 26.3.2.12 control register 3 (esci_cr3) this register is used to cont rol the frame formats and the ge neration of the err bit in the sci data register (esci_dr) . esci_base + 0x0014 read only 76543210 rd w reset00000000 figure 26-12. lin receiv e register (esci_lrr) table 26-15. esci_lrr field descriptions field description d receive data . this field provides the data bytes of received lin rx frames. esci_base + 0x0018 write: anytime 0123456789101112131415 r p w reset1100010110011001 figure 26-13. lin crc polynomial register (esci_lpr) this register provides the crc polynom for generation an d processing of crc-enhanced lin frames. table 26-16. esci_lpr field descriptions field description p polynomial bit x p[n] . used to define the lin polynomial. reset value results in x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1, which is the polynomia l used for the can protocol. esci_base + 0x001a write: anytime 0123456789101112131415 r0 0 0 synm eroe erfe erpe m2 00000000 w reset0000000000000000 figure 26-14. control register 3 (esci_cr3)
enhanced serial communication interface (esci) 26-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 26-17. esci_cr3 field descriptions field description 4 synm synchronization mode. this bit controls the synchroni zation mode of the receiver. the synchronization modes are described in section 26.4.5.3.14, bit synchronization . 0 synchronization performed at falling start and data bit edge. 1 synchronization performed at falling start bit edge only. 3 eroe err flag overrun enable. 0 esci_dr[err] flag not affe cted by overrun detection. 1 esci_dr[err] flag is set on overrun detection during frame reception. 2 erfe err flag frame error enable. 0 esci_dr[err] flag not affect ed by frame error detection. 1 esci_dr[err] flag is set on frame error detection for the data provided in esci_dr. 1 erpe err flag parity error enable. 0 esci_dr[err] flag not affected by parity error detection. 1 esci_dr[err] flag is set on parity error detection for the data provided in esci_dr. 0 m2 frame format mode 2. this contro l bit together with the m bit of the control register 1 (esci_cr1) controls the frame format used. the supported frame form ats and the related settings are defines in section 26.4.2, frame formats .
enhanced serial communication interface (esci) freescale semiconductor 26-21 pxr40 microcontroller reference manual, rev. 1 26.4 functional description this section provides a complete functional descripti on of the esci block, detailing the operation of the design from the end user perspect ive in a number of subsections. 26.4.1 module control the operational mode of the module is controlled by the mdis bit in the control register 2 (esci_cr2) . the module can transmit and receives da ta when it is enabled, i.e mdis=0. 26.4.2 frame formats the esci module uses the standard nrz mark/space data format. the esci supports three basic frame types, which are the data frames, br eak characters, and idle characters. 26.4.2.1 data frame formats each data frame contains a character that is surrounded by a start bit, an optional parity or address bit, and one or two stop bits. the supported data frame format s for transmission and reception are specified in table 26-18 . the supported data frame formats fo r reception only are specified in table 26-19 . table 26-18. supported data frame formats for rx and tx control frame content esci_cr3 esci_cr1 start bits payload bits stop bits m2 m pe wake character bits address bits 1 1 the address bit identifies the fr ame as an address character. see section 26.4.5.5, multiprocessor communication . parity bits lin byte fields ( figure 26-15 ) 000018001 sci frames (8 payload bits)( figure 26-16 ) 000018001 000117101 001017011 sci frames (9 payload bits) ( figure 26-17 ) 010019001 010118101 011018011
enhanced serial communication interface (esci) 26-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the structure of the lin frames in normal polarity is shown in figure 26-15 . figure 26-15. lin byte field format the structures of the supported sci frame fo rmats with 8 payload bits are shown in figure 26-16 . figure 26-16. sci frame formats (8 payload bits) the structures of the supported sci frame fo rmats with 9 payload bits are shown in figure 26-17 . figure 26-17. sci frame formats (9 payload bits) the structures of the supported sci frame formats wi th 2 stop bits in normal polarity are shown in figure 26-18 . this frame format is supported for reception only. figure 26-18. sci frame formats (2 stop bits) table 26-19. supported data frame formats for rx only control frame content esci_cr3 esci_cr1 start bits payload bits stop bits m2 m pe wake character bits address bits parity bits sci frames (2 stop bits) (see figure 26-18 ) 101018012 1 110 1 12 0 1 2 bit0 start bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 start bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit0 start bit addr bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 start bit parity bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit0 start bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 start bit addr bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit0 start bit parity bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 start bit parity bit stop bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit0 start bit parity bit stop bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7
enhanced serial communication interface (esci) freescale semiconductor 26-23 pxr40 microcontroller reference manual, rev. 1 26.4.2.1.1 inverted data frame formats the structures of the supported data frame formats in inverted polarity are shown in figure 26-19 . these frame types are supported for recept ion only. the polarity of the rxd pi n is controlled by the rxpol bit in the control register 2 (esci_cr2) . figure 26-19. inverted sci frame formats 26.4.2.2 break character formats the supported break character formats are specified in table 26-20 . the structure and content of the lin break symbols is shown in figure 26-20 . figure 26-20. lin break symbol format the structure and content of the sc i break characters is shown in figure 26-21 . table 26-20. supported break character formats control 1 1 all codings which are not listed are reserved and must not be used. break character content esci_cr3 esci_cr1 esci_cr2 start bit character bits delemit bits m2 m brcl lin break symbol (see figure 26-20 ) 000191 001 1 12 1 sci break character (see figure 26-21 ) 000190 001 1 12 0 010 1 10 0 011 1 13 0 start bit stop bit start bit stop bit stop bit bit0 start bit break delemit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit0 start bit break delemit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11
enhanced serial communication interface (esci) 26-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 26-21. sci break character formats 26.4.2.3 idle character formats an idle character is a sequence of bits with the value 1. the supported id le character formats are specified in table 26-21 . the preamble has the same structure and content as an idle character. the structure and content of the idle characters is shown in figure 26-22 . figure 26-22. idle character formats 26.4.3 baud rate and clock generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value written to the sbr field in the baud rate register (esci_brr) determines the module clock divisor. the baud rate clock is synchronized with the bus clock and drives the receiver. the baud rate clock divided by 16 drives the transmitter. the receiver ha s an acquisition rate of 16 samples per bit time. table 26-21. supported idle character formats control idle character length esci_cr3[m2] esci_cr1[m] idle characters (see figure 26-22 ) 00 10 01 11 10 12 11 16 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit10 bit9 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit10 bit9 bit11 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit10 bit9 bit11 bit12 bit13 bit14 bit14
enhanced serial communication interface (esci) freescale semiconductor 26-25 pxr40 microcontroller reference manual, rev. 1 the baud rate generator is enabled when the te bit or re bit in the control register 1 (esci_cr1) is set to 1 for the first time. the baud rate generator is disabled when sbr = 0. baud rate generation is subject to one source of error: ? integer division of the module clock may not give the exact required target baud rate. figure 26-22 lists some examples of achieving target baud rates with a modul e clock frequency of mclk = 10.2 mhz. 26.4.3.1 module clock the module clock mclk is derived from the system bus clock. it ha s the same phase and frequency. 26.4.3.2 transmitter clock the transmitter clock tclk is used to drive the data to the serial bus via the txd pin. it is derived from the system bus clock by the baud rate generator. the baud rate generator is controlled by the value of the sbr field in the baud rate register (esci_brr) . the frequency of the trans mitter clock is determined by equation 26-1 and defines the length of the transm itted bits, which is denoted as the bit time . eqn. 26-1 26.4.3.3 receiver clock the receiver clock rclk is used to sample the data received on the rxd or txd pin. it is derived from the system bus clock by the baud rate generator. the baud rate generator is controlled by the value of the sbr field in the baud rate register (esci_brr) . the frequency of the receiver sample clock is determined by equation 26-2 . eqn. 26-2 table 26-22. baud rates error example (mclk = 10.2 mhz) esci_brr[sbr] rclk (hz) tclk (hz) target baud rate error (%) 17 600,000.0 37,500.0 38,400 2.3 33 309,090.9 19,318.2 19,200 .62 66 154,545.5 9659.1 9600 .62 133 76,691.7 4793.2 4800 .14 266 38,345.9 2396.6 2400 .14 531 19,209.0 1200.6 1200 .11 1062 9604.5 600.3 600 .05 2125 4800.0 300.0 300 .00 4250 2400.0 150.0 150 .00 5795 1760.1 110.0 110 .00 f tclk f mclk 16 sbr ? ---------------------- = f rt f mclk sbr -------------- - =
enhanced serial communication interface (esci) 26-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the frequency of the receiver cloc k is 16 times the frequency of the transmitter clock, this each bit is sampled with 16 samples. each of the 16 samples of a bit has a sample number assigned, which is defined by the receiver sample counter rsc. the n-th sample is denoted by rs n. the receiver sample counter rsc is updated with each rising edge of the receiver clock rclk. 26.4.4 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiv er baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples rs8, rs9, and rs10 to fall outside the actual stop bit. a noise error will occur if th e stop bit sample rs8, rs9, and rs10 samples are not all the same logical value 1. a framing er ror will occur if the receiver clock is misaligned in such a way that the majority of the rs8, rs9, and rs 10 stop bit samples are a logic zero. 26.4.4.1 faster receiver tolerance in this case the receiver has a higher baud rate than th e transmitter, thus the stop bit sampling starts already in the last transmitted payload bit. to ensure the co rrect, noise and framing error free reception of the stop bit, the samples rs8, rs9, and rs10 must be located in the tr ansmitted stop bi t as shown in figure 26-23 . figure 26-23. faster receiver the maximum tolerance that ensures error free reception ca n be calculated with th e assumption, that rs7 is sampled during the last tr ansmitted payload bit and rs8 is sampled in the stop bit. for an frame with n payload bits the transmitter starts the transmission of the stop bit eqn. 26-3 after the start of the transmission of the start bit. for an frame with n payload bits the receiver sample s the rs8 sample of the stop bit eqn. 26-4 after the successful qualif ication of the start bit. to ensure error free reception of the stop bit, the tr ansmitter must start the transmission of the stop bit before the receiver samples rsc8. eqn. 26-5 rclk start bit rxd start bit qualification 6 7 8 2 1 3 rsc 8 9 10 data voting payload stop bit 6 7 tx stop n1 + ?? =16rt tr ?? rx stop n1 + ?? =16rt re 7rt re ? + ?? tx stop rx stop ?
enhanced serial communication interface (esci) freescale semiconductor 26-27 pxr40 microcontroller reference manual, rev. 1 the maximum percent difference be tween the receiver baud rate a nd the transmitter baud rate is: eqn. 26-6 the maximum percent differences for the supported frames is given in table 26-23 26.4.4.2 slower receiver tolerance in this case the receiver has a slower baud rate than the transmitter, thus the stop bit sampling is still running while the next start bit is al ready transmitted. to en sure the correct, noise and framing error free reception of the stop bit, the samples rs8, rs9, and rs 10 must be located in the transmitted stop bit as shown in figure 26-24 . figure 26-24. slower receiver the maximum tolerance that ensures error free recepti on can be calculated with the assumption, that rs11 is sampled in the transmitted start bit and rs10 is sampled in the last stop bit. for an frame with n payload bits and s stop bits, the transmitter starts th e transmission of the next start bit eqn. 26-7 after the start of the transmis sion of the previous start bit. for an frame with n payload bits a nd s stop bits, the receiver samples th e rs10 sample of the last stop bit eqn. 26-8 after the successful qualif ication of the start bit. to ensure error free reception of the last stop bit, the transmitter must start the tr ansmission of the start bit after the receiver samples rs10. eqn. 26-9 table 26-23. faster receiver maximum tolerance payload bits max baudrate difference tx stop rx stop 8 4.63% 144 151 9 4.19% 160 167 13 3.03% 224 231 baudrate ? rx stop tx stop ? rx stop -------------------------------------- - ?? ?? 100 ? ? tx start ns1 ++ ?? =16rt tr ?? rx stop ns + ?? =16rt re 9rt re ? + ?? rx stop tx start ?
enhanced serial communication interface (esci) 26-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the maximum percent difference be tween the receiver baud rate a nd the transmitter baud rate is: eqn. 26-10 the maximum percent differences for the supported frames is given in table 26-24 26.4.5 sci mode 26.4.5.1 sci mode configuration the application must configure the following bits and fields in orde r to achieve correct sci operation. ? enable sci mode ? lin control register 1 (esci_lcr1) [lin]:= 0 ?select baud rate ? baud rate register (esci_brr) [sbr] ?select receiver input mode ? control register 1 (esci_cr1) [loops] ? control register 1 (esci_cr1) [rsrc] ?select frame format ? control register 1 (esci_cr1) [m] ? control register 1 (esci_cr1) [pe] ? control register 1 (esci_cr1) [wake] ? control register 3 (esci_cr3) [m2] ?select parity type ? control register 1 (esci_cr1) [pt] 26.4.5.2 transmitter the transmitter supports the transmis sion of all frame types defined in table 26-18 , of all break characters defined in table 26-20 , and of all idle characters defined in table 26-21 . 26.4.5.2.1 transmitter states and transitions the transmitter has four basic states which are shown and described in table 26-25 . the state transitions that can triggered by the application commands are shown in table 26-26 . the state transitions that can table 26-24. slower receiver maximum tolerance payload bits stop bits max baudrate difference rx stop tx start 8 1 4.37% 153 160 9 1 3.97% 169 176 9 2 3.57% 185 196 13 2 2.73% 249 256 baudrate ? tx start rx stop ? tx start ------------------------------------------ ?? ?? 100 ? ?
enhanced serial communication interface (esci) freescale semiconductor 26-29 pxr40 microcontroller reference manual, rev. 1 triggered by the module are shown in table 26-27 . the state diagram of the transmitter is shown in figure 26-25 . figure 26-25. transmitter state diagram the current state of the transmitter can be determined by the te control bit in the control register 1 (esci_cr1) and the tact status bit in interrupt flag and status register 1 (esci_ifsr1) . the application triggers a transition described in table 26-26 when it issues a command by writing to the te bit in the control register 1 (esci_cr1) . the transition is triggered only if the conditions are fulfilled. as a result of the transition the state of the transmitter is changed as shown in figure 26-25 and the action given in table 26-26 is executed. the module transition shown in table 26-27 are triggered when the descri bed condition or event occurs. the send break bit sbk in the control register 1 (esci_cr1) is check for the start condition. the internal commit bit icmt, the transmitter active bit tact in the interrupt flag and status register 1 (esci_ifsr1) , the tdre, and the tc flag in the interrupt flag and status register 1 (esci_ifsr1) are changed as a action result of the transition. table 26-25. transmitter states state indication description esci_cr1[te] esci_ifsr1[tact] idle 0 0 transmitter is disabled and no transmission is running ready 1 0 transmitter is enabled and no transmission is running run 1 1 transmitter is enabled and transmission is running stop 0 1 transmitter is disabled and transmission is running table 26-26. transmitter application transitions transition command precond ition action description en esci_cr1[te]:=1 esci_cr1[te]=0 ipre:=1 transmitter is enabled by application command. dis esci_cr1[te]:=0 esci_cr1[te]=1 transmitter is disabled by application command ready en start idle reset_state run stop dis dis en halt done
enhanced serial communication interface (esci) 26-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.4.5.2.2 frame and character transmission the transmitter starts the transmission of a data frame or special character when the condition for the start transition as described in table 26-27 is fulfilled. there are three source for data or character transmission. the priority among these source are specified in table 26-28 . all three sources can be available at one point in time. 26.4.5.2.3 cpu controlled sc i data frame transmission the transmission of a data frame is started when the transmitter is in its ready state and only the commit bit icmt is set. as the first step, the content of the sci data register (esci_dr) is transferred into the internal transmitter shift register. when this transfer is finished, the inte rnal commit bit icmt is cl eared and the transmit data register empty flag tdre in the interrupt flag and status register 1 (esci_ifsr1) is set. if the transmit interrupt enable bit tie in the control register 1 (esci_cr1) is also set, the tdre flag generates a transmitter interrupt request. the transmitter shift register then shifts a frame out through the txd output signal, which is prefaced with a start bit and appended with the parity bit, if configured, and the confi gured number of stop bits. when the last stop bit has been transmitted and the application has not disabl ed the transmitter, the transmitter returns to the ready state via the done transition. if no frame or ch aracter transmit request is pending, the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set. if the application has disabled the transmitter wh ile the frame is transmitted and stop bit has been transmitted, the transmitter goes into the idle state via the halt transition. the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set and the internal co mmit bit icmt is cleared. table 26-27. transmitter module transitions transition condition action description start (state=ready) and (sbk=1 or ipre=1 or icmt=1) tact:=1 start of transmission of data frame or special character when data are available or character transmission request is pending. done state=run and last stop bit transmitted tac t : = 0 tc:= (sbk & ipre & tc) finished transmission of data frame or special character and transmitter still enabled. transmission is complete if no transmit request is pending. halt state=stop and last stop bit transmitted tac t : = 0 tc:=1 icmt:=0 finished transmission of data frame or special character and transmitter was disabled. table 26-28. transmit source priority priority indication tr ansmission source (highest) 0 esci_cr1[sbk]=1 break character. 1 ipre=1 preamble. (lowest) 2 icmt=1 sci data register (esci_dr) frame.
enhanced serial communication interface (esci) freescale semiconductor 26-31 pxr40 microcontroller reference manual, rev. 1 26.4.5.2.4 dma controlled sci data frame transmission in this mode, the esci module handles th e generation of data frames internally. when new data required for transm ission, the module generates the tr ansmit dma reque st and the dma controller delivers the require d data via write accesses to sci data register (esci_dr) . the write access to the low byte of sci data regist er (esci_dr) triggers the transmission of the data. the write access to the high byte of sci data register (esci_dr) triggers no internal operation. the application request the esci module to ente r this mode by setting the txdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and frame transmission. before entering this mode, the application shoul d perform the following actions: 1. configure the module for sci mode. 2. enable the transmitter by setting te in control register 1 (esci_cr1) to 1. 3. setup the dma controller channel and provide frame data in system memory a block diagram which presents an overview of the dma controlled date fram e transmission is shown in figure 26-26 . figure 26-26. dma controlled sci data frame generation 26.4.5.2.5 parity generation the esci module generates the parity bit in transmitted data frame when the parity enable bit pe in the control register 1 (esci_cr1) is set. the parity type bit pt in the control register 1 (esci_cr1) defines whether the odd or even parity is generated. 26.4.5.2.6 preamble transmission the transmission of a preamble is star ted when the transmitter is in ready state, the internal ipre bit, which is not visible to the applic ation, is set, a nd the sbk in the control register 1 (esci_cr1) is clear. dma controller esci tx dma channel data 2 data n system memory data 1 data n sci data frame data 1
enhanced serial communication interface (esci) 26-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 after the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter returns to the ready state via the done transition. if no frame or character transmit request is pending, the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set. if the application has disabled the tr ansmitter while the preamble is tran smitted and if the stop bit has been transmitted, the transmitter goes into th e idle state via the halt transition. the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set and the internal co mmit bit icmt is cleared. 26.4.5.2.7 break character transmission the transmission of a break character is started when the transmitter is in ready state and the send break character bit sbk in the control register 1 (esci_cr1) is set. after the transmission of the break character and if the applicat ion has not disabled the tr ansmitter, the transmitter returns to the ready state via the done transition and restarts the transmission. as long as sbk bit remains set, the transmitter continues to send break characters. when the application has cleared the sbk bit or has disabled the transmit ter, the transmitter continues to transmit the current break character and after it has finished the transmission of this break character it transmits a stop bit. the st op bit at the end of a break character sequence guarant ees the recognition of the start bit of the next data frame. after the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter returns to the ready state via the done transition. if no frame or character transmit request is pending, the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set. if the application has disabled the transmitter while the break character is transmitted and if the stop bit has been transmitted, the transmitte r goes into the idle state via the halt transition. the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set and the internal commit bit icmt is cleared. 26.4.5.3 receiver the receiver supports the reception of all data frame types defined in table 26-18 and table 26-19 , of all break character defined in table 26-20 , and of all idle characters defined in table 26-21 . 26.4.5.3.1 receiver st ates and transitions the receiver has four basic states which are shown and described in table 26-26 . the state transitions that can triggered by the application commands are shown in table 26-26 . the state transitions that can triggered by the module are shown in table 26-27 . the state diagram of the transmitter is shown in figure 26-25 .
enhanced serial communication interface (esci) freescale semiconductor 26-33 pxr40 microcontroller reference manual, rev. 1 figure 26-27. receiver state diagram the current state of the receiver can be determined by the re and rwu bit in the control register 1 (esci_cr1) and the ract status bit in interrupt flag and status register 1 (esci_ifsr1) . the application triggers a transition described in table 26-30 when it issues a command by writing to the re bit in the control register 1 (esci_cr1) . the transition is triggered only if the conditions are fulfilled. as a result of the transition the state of the receiver is changed as shown in figure 26-27 and the action given in table 26-30 is executed. the module transition shown in table 26-31 are triggered when the described event occurs. table 26-29. receiver states state indication description re ract rwu idle 0 0 0 receiver is disabled and no reception is running ready 1 0 0 receiver is enabled and no reception is running run 1 1 0 receiver is enabled and reception is running wakeup 1 - 1 receiver is in wakeup mode table 26-30. receiver application transition transition command condition action description en re:=1 re=0 receiver is enabled by application command. dis re:=0 re=1 receiver is disabled by application command slp rwu:=1 re=1 receiver is set into wakeup mode ready en start idle reset_state dis dis done run wakeup slp slp wake0 wake1
enhanced serial communication interface (esci) 26-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.4.5.3.2 receiver in put mode selection this section describes the three receiver input modes supported by the esci module. the modes are selected by the loops and rsrc control bits in the control register 1 (esci_cr1) . 26.4.5.3.3 dual wire mode in dual wire mode, the esci uses the txd pin fo r transmitting and the rxd pin for data receiving. figure 26-28. dual wire mode 26.4.5.3.4 single wire mode in single wire mode, the rxd pin is disconnected from the esci module and the txd pin is used for both receiving and transmitting. figure 26-29. single wire mode table 26-31. receiver module transition transition condition action description start (state=ready,run) and (start bit received) ract:=1 start of reception of data frame or break character. done (state=run) and (idle character received) ract:=0 idle character received. wake0 (state=wakeup) and (idle character received) rwu:=0 wakeup idle character received. wake1 (state=wakeup) and (address frame received) rwu:=0 wakeup address frame received. rxd transmitter receiver txd transmitter receiver rxd txd
enhanced serial communication interface (esci) freescale semiconductor 26-35 pxr40 microcontroller reference manual, rev. 1 the txdir bit (esci_cr2[1]) determin es whether the txd pin is going to be used as an input (txdir = 0) or an output (txdir = 1) in this mode of operation. 26.4.5.3.5 loop mode in loop mode, the input of the rece iver is driven by the output of the transmitter. the rxd pin is disconnected from the esci module. figure 26-30. loop mode 26.4.5.3.6 frame and character reception the receiver is started when it is in ready or wa keup state and on the selected receiver input (see section 26.4.5.3.2, receiver input mode selection ) an active signal is sampled. the receiver enters the run or wakeup state. the received bits ar e recovered by the bit sampling described in section 26.4.5.3.13, bit sampling . during the reception, the received bits are sh ifted into the internal shift register. 26.4.5.3.7 break character detection the receiver does not prov ide any means to detect the reception of a break character. instead, break characters are processed as data fr ames. due to the received 0 at the stop bit location, the reception of a break character causes at least a framing error. the error reporting is performed as described in section 26.4.5.4, reception error reporting . 26.4.5.3.8 idle character detection the start point of the idle charact er detection is controlled by the idle line type bit ilt in the control register 1 (esci_cr1) . if the ilt bit is 0, the idle character detection starts always immediately after th e reception of a bit with the value 0. in this mode, a data frame with a payload section of all ones will be erroneously detected as an idle character. if the ilt bit is 1, the idle character detection starts after the recepti on of the last stop bit. 26.4.5.3.9 cpu controlled sci data frame reception this section describes the reception proce ss when the receiver is in the run state. when the required number of frame bits have been re ceived, the payload bits of the received frame are transferred into sci data register (esci_dr) if the rdrf flag is 0. the re ceive data register full flag rdrf in interrupt flag and status register 1 (esci_ifsr1) is set. if the receive interrupt enable bit rie in the interrupt flag and status register 1 (esci_ifsr1) is set, the rdrf interrupt request is generated. transmitter receiver rxd txd
enhanced serial communication interface (esci) 26-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if an idle character has been detected, the idle flag in the interrupt flag and status register 1 (esci_ifsr1) is set. if the idle line interrupt enable bit ilie in the control register 1 (esci_cr1) is set, the idle interrupt request is generated. if any of the receiver errors described in section 26.4.5.4, reception error reporting , have been occurred, that corresponding flags will be set. if the application disabled the receiver by clearing the receiver en able bit re in the interrupt flag and status register 1 (esci_ifsr1) the current frame is discarded and no flags will be updated. 26.4.5.3.10 dma controlled sci data frames reception in this mode, the esci module contro ls the reception of sci data fram es automatically and utilizes the connected dma channels. a block di agram which presents an overview of the dma controlled sci data frame reception is shown in figure 26-31 . the rx dma channel is used to transfer the received frame data into the memory. when new data was received, the module generates the receive dma request and the dma controller retrieves the provided data from the sci data register (esci_dr) . the read access fr om the low byte of the sci data register (esci_dr) signals the end of the dma cycle fo r the current data and triggers the reception of new data. th e read access from the sci data register (esci_dr) triggers no internal action. the application request the esci module to ente r this mode by setting the rxdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and frame transmission and reception. befo re entering this mode, the appli cation should perform the following actions: 1. configure the module for sci mode. 2. enable the receiver by setting re in control register 1 (esci_cr1) to 1. 3. setup the dma c ontroller channel. figure 26-31. dma controlled sci data frame reception dma controller esci system memory data 1 data n sci data frame rx dma channel data 2 data n data 1
enhanced serial communication interface (esci) freescale semiconductor 26-37 pxr40 microcontroller reference manual, rev. 1 26.4.5.3.11 receiver overrun when the esci module has received a frame and attempts to transfer the payload data of the received frame into the sci data register (esci_dr) but neither the application nor the dma controller has read the sci data register (esci_dr) since its last update, th e overrun flag or in the interrupt flag and status register 1 (esci_ifsr1) is set. the data contained in sci data register (esci_dr) are not changed and the received data are lost. 26.4.5.3.12 wake-up frame reception this section describes the reception process when the receiver is in the wakeup state. when the required number of frame bits have been re ceived, the payload bits of the received frame are transferred into sci data register (esci_dr) if the rdrf flag is 0. if the address-mark wake-up mode is selected a nd the received frame has the address bit set, the receive data register full flag rdrf in interrupt flag and status register 1 (esci_ifsr1) is set. if the receive interrupt enable bit rie in the interrupt flag and status register 1 (esci_ifsr1) is set, the rdrf interrupt request is generated. the rwu bit is cleared, and the receiver enters th e run state via the wake1 transition. if the idle line wake-up mode is selected and the receiver has detected an idle character, the rwu bit is cleared, and the receiver enters the ready state via the wake0 transition. if any of the receiver errors described in section 26.4.5.4, reception error reporting , have been occurred, that corresponding flags will be set. 26.4.5.3.13 bit sampling the receiver samples the sel ected receiver input (see section 26.4.5.3.2, receiver input mode selection ) with the receiver clock rclk. the sampli ng for start bit detection is shown in figure 26-32 , the sampling for data and stop bit reception is shown in figure 26-33 . the samples indicated by dashed arrows are not used by the receiver. the received data bits are transfer red into the internal shift register after the data strobing. if noise or framing errors were de tected, this is flagged as described in section 26.4.5.4, reception error reporting . 26.4.5.3.14 bit synchronization to adjust for baud rate mismatch, a synchronization of the cyclic samp le counter rsc is performed during start bit reception as described in section 26.4.5.3.15, start bit sampling . additionally, the synchronizat ion of the cyclic sample counter rsc can be configured to be performed during data bit reception as described in section 26.4.5.3.17, data bit synchronization .
enhanced serial communication interface (esci) 26-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.4.5.3.15 start bit sampling figure 26-32. start bit sampling and strobing start bit qualification to adjust for baud rate mismatch, the cyclic sa mple counter rsc is re-synchronized by reset after successful start bit qualification. a start bit is succes sfully qualified, if no rece ption is ongoing and three consecutive high sample s are followed immediately by a low sample. start bit verification after the successful start bit qualification the receiver starts to verify the start bit by a two out of three samples majority voting. a start bit is verified if at least two out of the three sample rsc 3, rsc5, and rsc5 are sampled low. noise is detected when exactly one out of the three samples is high. the resu lts of the start bit verification is summarized in table 26-32 . if the start bit verification was not successful , the receiver resumes the start bit qualification. if the start bit verification was successful , the receiver continues sampling to pe rform noise detection on the samples at rs8, rs9, and rs10. the results of the start bit noise detection is summarized in table 26-33 . table 26-32. start bit verification result [rs3, rs5, rs7] start bit verified noise detected 000 yes no 001 yes yes 010 yes yes 100 yes yes 011 no no 101 no no 110 no no 111 no no sampled value rclk start bit receiver input start bit qualification 1 1 1 11000 0 0 0 0 4 5 6 7 8 1 2 sample counter reset 3 rsc 4 5 6 7 0 8 9 10 11 12 13 14 15 16 1 00 start bit verification noise detection data strobing 01 0 01 000 2 sample counter wrap
enhanced serial communication interface (esci) freescale semiconductor 26-39 pxr40 microcontroller reference manual, rev. 1 26.4.5.3.16 data bit sampling figure 26-33. data and stop bit sampling and strobing to determine the value of a data bit and to detect noi se, a two out of th ree majority voting is performed on the samples rs8, rs9, and rs10. table 26-34 summarizes the results of th e data bit samp le. the receiver detects the number of data bit accord ing to the selected frame format. table 26-33. start bit noise detection [rs8, rs9, rs10] noise detected 000 no 001 yes 010 yes 100 yes 011 yes 101 yes 110 yes 111 yes table 26-34. data bit sampling [rs8, rs9, rs10] data bit value noise detected 000 0 no 001 0 yes 010 0 yes 100 0 yes 011 1 yes 101 1 yes 110 1 yes 111 1 no sampled value rclk data / stop bit receiver input 1 1 1 11000 0 0 0 0 2 3 rsc 4 5 6 7 0 8 9 10 11 12 13 14 15 16 1 00 data voting data strobing 01 0 01 000 2 sample counter wrap 1 12 13 14 15 16 sample counter wrap
enhanced serial communication interface (esci) 26-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.4.5.3.17 data bit synchronization to adjust for baud rate mismatch dur ing the reception of data bits, the cyclic samp le counter rsc can be configured to be synchronized on fa lling edges during data bit reception. this ki nd of synchronization is performed only if the synchroni zation mode bit synm in the control register 3 (esci_cr3) is 0. data bit synchronizatio n (right shifted edges) this kind of sample counter synchr onization happens if the transmitter is slower than the receiver. the reset behavior of the sample counter is shown in figure 26-34 . the sample counter reset condition is: 1. the data bit n-1 is sampled as 1, and 2. the data bit n is sampled as 0, and 3. a falling edge consisting of thr ee consecutive 1-samples and a foll owing 0-sample is detected, and 4. the 0-sample of the falling edge is receiv ed at data bit n sample j, with 1 <= j <= 8. if the condition is fulfilled, the sample counter is re set 16 rclk cycles after the 0 of the falling edge condition was received. the bit counter is not increased. figure 26-34. data bit synchronization (right shifted edges) data bit synchronization (left shifted edges) this kind of sample counter synchroni zation happens if the tran smitter is faster than the receiver. the reset behavior of the sample counter is shown in figure 26-35 . the sample counter reset condition is: 1. the data bit n-1 is sampled as 1, and 2. the data bit n is sampled as 0, and 3. a falling edge consisting of thr ee consecutive 1-samples and a foll owing 0-sample is detected, and 4. the 0-sample of the falling edge is received at data bit n sample j, with 11 <= j <= 16. if the condition is fulfilled, the sample counter is re set 16 rclk cycles after the 0-sample of the falling edge condition was re ceived. the bit counter is increased by 1. voting data rclk rxd 2 3 rsc 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 wrap 1 wrap 3 sample counter reset right shifted falling edge falling edge 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 voting data reset voting data data bit n-1 data bit n data bit n+1
enhanced serial communication interface (esci) freescale semiconductor 26-41 pxr40 microcontroller reference manual, rev. 1 figure 26-35. data bit synchronization (left shifted edges) if the 0-sample of the falling edge condition is received at sample 9 or 10, no sample counter synchronization is performed. 26.4.5.3.18 stop bit verification the reception of a valid st op bit is verified if at least two out of the sample rs8, rs9, and rs10 are sampled high. if this is not that case , a framing error is detected. noise is detected if not all of the samples are of the same value. the results of th e stop bit verification are summarized in table 26-35 . 26.4.5.3.19 parity checking the esci module calculates the parity of a received character and checks is versus the received parity bit in the received data frame when th e parity enable bit pe in the control register 1 (esci_cr1) is set. the parity type bit pt in the control register 1 (esci_cr1) defines whether to check for odd or even parity is generated. if an parity er ror is detected, this is reported as described in section 26.4.5.4, reception error reporting . 26.4.5.4 reception error reporting the receiver can detect four error types: parity erro rs, framing errors, noise er rors, and the overrun error. table 26-35. stop bit verification [rs8, rs9, rs10] stop bit verified fr aming error detected noise detected 000 no yes no 001 no yes yes 010 no yes yes 100 no yes yes 011 yes no yes 101 yes no yes 110 yes no yes 111 yes no no voting data rclk rxd 2 3 rsc 4 5 6 7 8 9 10 11 12 13 14 15 16 1 wrap sample counter reset left shifted falling edge 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 voting data reset voting data databit n-1 falling edge 2 3 4 5 1 databit n+1 databit n
enhanced serial communication interface (esci) 26-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the receiver reports the errors dete cted during frame reception at the end of the reception of the last stop bit of a frame. for error repo rting the receiver utilizes the or, nf, fe, and pf flags in the interrupt flag and status register 1 (esci_ifsr1) . if the receiver has detected an overrun as described in section 26.4.5.3.11, receiver overrun , only the or flag is set. all other error flags are not updated. if the receiver has not detected an overrun and has detected noise as described in section 26.4.5.3.13, bit sampling , the nf flag is set. if the receiver has not detected an overrun and has detected a framing error as described in section 26.4.5.3.13, bit sampling , the fe flag is set. if the receiver has not detected an overrun and has detected a parity error as described in section 26.4.5.3.19, parity checking , the pf flag is set. 26.4.5.5 multiprocessor communication the multiprocessor communication allows one processor to send blocks of frames to other processors on the same serial link. to avoid the rece ived data interrupt for frames not intended for th e processor, the esci receiver can be put into the wakeup stat e. if the receiver is in the wakeup state, the esci will still load the received data into the sci data register (esci_dr) , but will not set the rdrf flag and consequently not request the rdrf interrupt. the receiver leaves the wakeup stat e and clears the rwu bit in the control register 1 (esci_cr1) when the wakeup pattern config ured by wake bit in control register 1 (esci_cr1) is received. the esci module supports two types of wakeup patterns, the idle-line wakup patt ern and the address-mark wakeup pattern. 26.4.5.5.1 idle-line wakeup the idle-line wakeup mode is se lected when the wake bit in control register 1 (esci_cr1) is 0. in this mode, the receiver leaves the wakeup state, when an idle character is det ected as described in section 26.4.5.3.8, idle character detection . the next received fr ame is the address frame that contains address information which can be eval uated by the application. if the application deci des not to receive the frame block, it can set the rwu bit in the control register 1 (esci_cr1) and return the receiver to the wakeup state. figure 26-36. idle-line wakeup format frame block frame block idle character receiver wakeup address frame
enhanced serial communication interface (esci) freescale semiconductor 26-43 pxr40 microcontroller reference manual, rev. 1 26.4.5.5.2 address-mark wakeup the address-mark wakeup mode is selected when the wake bit in control register 1 (esci_cr1) is 1. if the wake bit is set, the address bit is added to the frame format. in this mode, the receiver leaves the wakeup state, when a data frame wi th the address bit value of 1 was received. this frame is the address frame and contains address information which can be evaluated by the applicat ion. if the application decides not to receive the frame bl ock, it can set the rwu bit in the control register 1 (esci_cr1) and return the receiver to the wakeup state. all data frames that belong to the frame block must have the address bit cleared. figure 26-37. address-mark wakeup format 26.4.6 lin mode the esci provides suppor t for the lin protocol. it can be used to automate most tasks of a lin master. in conjunction with the dma interface it is possible to transmit entire lin fra mes and sequences of lin frames as well as to receive data from lin slaves without application interv ention. there is no special support for lin slave mode. 26.4.6.1 lin mode configuration the application must configure the following bits and fields in order to achieve correct lin operation. the configuration of bits and fields not mentioned in th is section depend on the conne cted lin slaves and the current application. ? enable lin mode ? lin control register 1 (esci_lcr1) [lin]:= 1 ?select rxd pin as receiver input ? control register 1 (esci_cr1) [loops]:= 0 ? control register 1 (esci_cr1) [rsrc]:= 0 ?select lin byte fields as used frame format ? control register 1 (esci_cr1) [m]:= 0 ? control register 1 (esci_cr1) [pe]:= 0 ? control register 1 (esci_cr1) [wake]:= 0 ? control register 3 (esci_cr3) [m2]:= 0 ?select break character length of 13 bit as required by lin 2.0 ? control register 2 (esci_cr2) [brcl]:= 1 ? select transmission stop on bit error detection frame block frame block receiver wakeup address frame (addr bit = 1) address frame (addr bit = 1) receiver wakeup ignored idle times
enhanced serial communication interface (esci) 26-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? control register 2 (esci_cr2) [bestp]:= 1 ? select transmission dma stop on bit error detection ? control register 2 (esci_cr2) [bstp]:= 1 ? enable both transmitter and receiver ? control register 1 (esci_cr1) [te]:= 1 ? control register 1 (esci_cr1) [re]:= 1 26.4.6.2 lin frame formats the term lin frame refers to a sequence of lin byte fields preceded by a break character, both are described in section 26.4.2, frame formats . the esci module allows to generate lin frames for lin slaves of lin standards 1.3 and 2.0. 26.4.6.2.1 standard lin frames a standard lin frame, shown in figure 26-38 consists of a break character, a sync field, an id field, zero or more data fields, and a checksum field. the data fields and the checksum fi eld are generated by the lin master for tx lin frames and generated by the lin slave for rx lin frames. the header fields will always be generated by the lin master. figure 26-38. standard lin frame format 26.4.6.2.2 crc e nhanced lin frames the crc enhanced lin frames shown in figure 26-39 contain two additional crc byte fields. these fields are located between the last data field and the checksum field. th e value of the crc is calculated on the same byte fields as the checksum is calculate d on. the polynom used for the crc calculation is defined by lin crc polynomial register (esci_lpr) . the esci module generates the crc fields for tx frames and checks the crc fields fo r rx frames if the crc bit in the lin transmit register (esci_ltr) was written with a value of 1. figure 26-39. crc enhanced lin frame format the crc enhanced lin frames are not part of the lin standard. 26.4.6.3 lin tx frame generation the esci module supports two mode s of lin tx frame generation, th e cpu controlled mode and the dma controlled mode. in the cpu controlled m ode, the application provides the required frame configuration and frame data by s ubsequent cpu write accesses to the lin transmit register (esci_ltr) . in the dma controlled mode, the dma contro ller provides the required frame configuration and frame data in response to dma requests generated by the esci module. break synch identifier data 1 data 2 data n checksum break synch identifier data 1 data 2 data n checksum crc1 crc2
enhanced serial communication interface (esci) freescale semiconductor 26-45 pxr40 microcontroller reference manual, rev. 1 26.4.6.3.1 cpu controlled lin tx frame generation in this mode, the application init iates the generation of an lin tx frame and provides the data to be transmitted by a sequence of subse quent cpu write accesses to the lin transmit register (esci_ltr) . when the esci module has proc essed the data written into lin transmit register (esci_ltr) , the txrdy interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) will be set. the application should clear the txrdy interrupt flag before writing data into the lin transmit register (esci_ltr) because the esci module will set the tx rdy one clock cycle af ter the write access. the first data written to the lin transmit register (esci_ltr) provides the identifier and identifier parity fields. the second data written define s the number of data bytes to be tr ansmitted. the third data written defines the crc and checksum generation. the td bit has to set to 1 in order to invoke the lin tx frame generation. the value of the to field is ignor ed by the esci module for lin tx frames. after the third data was written the generation of a lin tx frame is st arted. firstly, a break field is transmitted, then the synch field a nd the protected identifier field. all subsequent write accesses to the lin transmit register (esci_ltr) provide data bytes to be transmitted via the lin bus. a data byt e field will be transmitted as soon as data are available. after the last data byte, defined by the value written to the len field, was send out, the configured crc and checksum fields will be send out. after the transmission of the checksum field of the lin tx frame, the wr ite access counter for the lin transmit register (esci_ltr) is reset and the frc interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) is set. 26.4.6.3.2 dma controlled lin tx frame generation in this mode, the esci module cont rols the generation of an lin tx frame. when new data required for transmission, the esci module gene rates the transmit dma request an d the dma controller delivers the required data. the application request the esci modul e to enter this mode by setting the txdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and initiates the frame tran smission. before entering this mode, the appl ication should perform the following actions: 1. configure the module for lin mode. 2. enable the transmitter by setting te in control register 1 (esci_cr1) to 1. 3. setup the dma controller channel and provide frame data in system memory a block diagram which presents an overview of the dma controlled lin tx frame is shown in figure 26-40 . the content of the fields in the memory is the same as described in lin transmit register (esci_ltr) - lin tx frame generation .
enhanced serial communication interface (esci) 26-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 26-40. dma controlled lin tx frame generation 26.4.6.4 lin rx frame generation the esci module supports two mode s of lin rx frame generation an d reception, the cpu controlled mode and the dma controlled mode. in the cpu cont rolled mode, the applicat ion provides the required data by subsequent cpu write accesses to the lin transmit register (esci_ltr) and retrieves the received data by subsequent cpu read accesses to the lin receive register (esci_lrr) . in the dma controlled mode, the dma controller provides the required frame confi guration data in response to dma requests generated by the esci module and transfers the received frame data to th e memory in response to dma requests generated by the esci module. 26.4.6.4.1 cpu controlled lin rx frames generation in this mode, the application init iates the generation of an lin rx frame by a sequence of subsequent cpu write accesses to the lin transmit regi ster (esci_ltr) . when the esci module has processed the data written into lin transmit register (esci_ltr) , the txrdy interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) will be set. the application should clear the txrdy interrupt flag before writing data into the lin transmit register (esci_ltr) because the esci module will set the tx rdy one clock cycle af ter the write access. the first data written to the lin transmit register (esci_ltr) provides the identifier and identifier parity fields. the second data written defi nes the number of data bytes requested from the lin slave. the third data written defines the crc and ch ecksum generation. the td bit has to set to 0 to invoke the rx frame generation. the to field defines the upper part of the timeout value. the fourth byte written defines the lower part of the timeout value. after the fourth byte was written the generation of a lin rx frame is started. fi rstly, a break field is transmitted, then the synch field and the protected identifier field. after the transmission of the protected identifier, the esci module starts to receive th e frame data transmitted by th e lin slave. when the module has received a complete byte field, the r eceived data are transferred into the lin receive register dma controller esci csm tx dma channel id[5:0] p[1:0] len 1 cse crc td 2 0 data 1 data 2 data n system memory 1 len must be set to n 2 td must be set to 1 break synch identifier data 1 data n checksum lin tx frame
enhanced serial communication interface (esci) freescale semiconductor 26-47 pxr40 microcontroller reference manual, rev. 1 (esci_lrr) and the receive data ready flag rxrdy in the interrupt flag and status register 2 (esci_ifsr2) is set. the application can retrieve the receive d data by subsequent read access from lin receive register (esci_lrr) after checking the rxrdy fla g. the application should clear the rxrdy flag immediately after reading the lin receive register (esci_lrr) . after the reception of the configured number of data from the slave, the module starts the reception of the configured crc and checksum byte fields. these data are not transferred into the lin receive register (esci_lrr) . the crc and checksum checking is performed inte rnally. in case of errors, they will be reported as described in section 26.4.6.5, lin error reporting . after the reception of the checksum field of the lin rx frame, the frc interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) is set. 26.4.6.4.2 dma controlled li n rx frames generation in this mode, the esci module cont rols the generation of lin rx fram e header and the reception of the frame data automatically and utilizes the two conne cted dma channels. a bloc k diagram which presents an overview of the dma controlled lin rx frame generation and reception is shown in figure 26-40 . the content of the header fields in th e memory is the same as described in lin transmit register (esci_ltr) - lin rx frame generation . the tx dma channel is used the fetch the lin rx frame header and control information. the rx dma channel is used to transfer the received frame data into the memory. when new data required for transm ission, the module generates the tr ansmit dma reque st and the dma controller delivers the required da ta. when new data was received, th e module generates the receive dma request and the dma controller retrieves the provided data. the application request the esci module to ente r this mode by setting the rxdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and frame transmission and reception. befo re entering this mode, the appli cation should perform the following actions: 1. configure the module for lin mode. 2. enable transmitter and receiv er by setting te and re in control register 1 (esci_cr1) to 1. 3. setup the two dma controller channels and pr ovide frame header data in system memory.
enhanced serial communication interface (esci) 26-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 26-41. dma controlled lin rx frame generation and reception 26.4.6.5 lin error reporting this section describes error checking and the signaling of detected errors in lin mode. 26.4.6.5.1 physical bus error detection if the receiver input is sa mpled 0 for at least 31 sample clock cycles after the start of the transmission of a lin frame, the physical bus error flag pberr in the interrupt flag and status register 2 (esci_ifsr2) will be set. 26.4.6.5.2 unrequested activity detection if an unrequested byte is re ceived (i.e. a byte which is not part of an rx frame) which is not recognized as a wakeup or break character, th e bit error flag berr in the interrupt flag and status register 2 (esci_ifsr2) is set. in addition the rxrdy flag will also be set, the linrx register must be read before normal operations can proceed. 26.4.6.5.3 standard bit error detection the standard bit error detection is pe rformed on each byte field transmission. during the transmission of the frame header and frame data, the receiver is running and receives the signal values on the serial bus. after the complete transmis sion of a byte field, the esci compares the data that was transmitted and the data that was received. if they do not match, the bit error flag berr in the interrupt flag and status register 2 (esci_ifsr2) is set. 26.4.6.5.4 fast bit error detection fast bit error detection has been desi gned to allow flagging of lin bit erro rs while they occur, rather than flagging them after a byte tr ansmission has completed (see figure 26-42 ). dma controller esci csm tx dma channel id[5:0] p[1:0] len 1 cse crc td 2 to[11:8] data 1 data 2 data n system memory 1 len must be set to n 2 td must be set to 0 break synch identifier data 1 data n checksum lin rx frame to[7:0] rx dma channel from lin master from lin slave
enhanced serial communication interface (esci) freescale semiconductor 26-49 pxr40 microcontroller reference manual, rev. 1 figure 26-42. fast bit error detection on a lin bus if fast bit error detection bit fbr in the control register 2 (esci_cr2) is set the esci will compare the transmitted and the received data stream while the transmitter is active (not idle). once a mismatch between the transmitted data and the received data is detected the foll owing actions are performed the bit error flag berr will be set. to adjust to different bus loads the sample point at which the incoming bit is compared to the one which was transmitted can be selected with the besm bit in the control register 2 (esci_cr2) . if esci_cr2[besm] = 1, the comparison will be perfor med with sample rs13, otherwise with rs9 (see figure 26-43 ) (also see section 26.4.5.3.13, bit sampling ). figure 26-43. timing diagram fast bit error detection note to calculate the exact position of the samp le point with regard to the rx pin, the delays through the pads and the two bus clock cycle delay through the input synchronizer also needs to be taken into account. txd pin rxd pin lin physical interface synchronizer stage bus clock receive shift register transmit shift register lin bus compare sample point bit error output transmit shift register 12345678910111213141516 input receive shift register esci_cr2[besm] = 0 esci_cr2[besm] = 1 compare sample points
enhanced serial communication interface (esci) 26-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.4.6.5.5 slave-not-responding-error detection the slave-not-responding- error is defined in lin specification package revision 1.3; december 12, 2002 ; 6 error and exception handling. th e lin specification requires that a no_response_error has to be detected if a messa ge frame is not fully completed within the maximum length t frame_max by any slave task upon transmission of the synch and identifier fields. the maximum frame lengt h tframe_max is defined in lin specification package revision 1.3; december 12, 2002 ; 3.3 length of message fram e and bus sleep detect, as eqn. 26-11 where n data is the number of data byte fi elds of the message frame. the sto interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) will be set, if an lin rx frame was not fully received in the amount of time specified in the timeout value field to in the lin transmit register (esci_ltr) . the time period starts wi th the falling edge of the transmitted lin break character and is specified in units of transmit bits. to achieve lin compliant slav e-not-responding-error detection, the timeout value to in the lin transmit register (esci_ltr) field has to be set to t frame_max when a lin rx frame is initiated. 26.4.6.5.6 checksum error detection if the checksum enable bit cse in the lin transmit register (esci_ltr) was set, the checksum checking is performed based on the received checksum byte. th e checksum mode is selected by the csm bit in the lin transmit register (esci_ltr) . if the value received in the checksum bytes did not match the calculated checksum, the check sum error flag ckerr in the interrupt flag and status register 2 (esci_ifsr2) will be set. 26.4.6.5.7 crc error detection the crc checking is performed on the two received crc bytes crc1 and crc2 if the crc enhanced lin frame format was selected by the crc bit in the lin transmit register (esci_ltr) . if the value received in the two crc bytes did not match the calcul ated crc pattern, the crc error flag cerr in the interrupt flag and status register 2 (esci_ifsr2) will be set. 26.4.6.5.8 overflow detection when the receiver has received the next byt e field, which should be transferred into the lin receive register (esci_lrr) , but neither the application nor the rx dma channel have read data from this register since the last update, the recei ved data overflow flag ovfl in the interrupt flag and status register 2 (esci_ifsr2) will be set. in this case the content of the lin receive register (esci_lrr) is not changed. the data received most recently are lost. 26.4.6.6 lin wakeup the section describes the lin wake up behavior of the esci module. t frame_max 10 n data ? 45 + ?? 1.4 ? =
enhanced serial communication interface (esci) freescale semiconductor 26-51 pxr40 microcontroller reference manual, rev. 1 26.4.6.6.1 lin wakeup generation the esci module can cause the li n bus to exit the sleep mode by sending a break character. the application triggers the transmissi on of a break character by writing 1 to the lin bus wakeup trigger wu in the lin control register 1 (esci_lcr1) . after the end of transmission of this break character the transmitter will neither set the txrdy flag in the interrupt flag and status register 2 (esci_ifsr2) nor start the transmission of frame data until the wa keup delimiter period has been expired. the wakeup delimiter period is defined by the wud field in the lin control register 1 (esci_lcr1) . to generate a valid wakeup charact er according to lin 2.0, the esci first needs to be programmed to a baud rate lower than 32 kbaud, then wu can be set. should the applicat ion require a higher baud rate, then this rate can be set once the wakeup character has been transmitted. 26.4.6.6.2 lin wakeup reception if the esci receives a va lid wakeup condition on the selected rece iver input the lin wakeup flag lwake in the interrupt flag and status register 2 (esci_ifsr2) will be set. since each valid wakeup condition violates the byte field structure the frame error flag fe in the interrupt flag and status register 1 (esci_ifsr1) will be set too. the esci detects the following c onditions as valid wakeup conditions: ? reception of a break signal ? reception of a lin 1.x wake up character (80h, 00h or c0h) ? reception of a lin 2.0 wakeup character (low pulse of 250 ms to 5 ms). to detect lin 2.0 wakeup characters, the baud rate must to be set to 32k down to 1.6k baud. 26.4.6.7 lin protoc ol engine reset the lin protocol engine is re set when the lres bit in the lin control register 1 (esci_lcr1) is set to 1. in this case, the lin protocol engine will no longer initiates new transmissions or receptions. however, ongoing byte transmission or reception is not aborted. in order to start the lin pr otocol engine with idle transmitter and receiver proc esses, the lres bit should be asserted for the durat ion of at least one bit. 26.4.7 interrupts this section describes the interrupt s ources and interrupt request generation. 26.4.7.1 interrupt flags and enables all interrupt sources, interrupt flags, a nd interrupt enable bi ts are listed in table 26-36 . this table indicates the operational modes, where the interrupt flags can be set by the esci module.
enhanced serial communication interface (esci) 26-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 26.4.7.2 interrupt request generation the esci module provides one hardware interrupt request signa l to the systems interr upt controller. this interrupt request signal is asserted if and only if at least one of the interrupt flag s and the corresponding interrupt enables are set to 1. otherwise the interrupt line is deasserted. 26.5 application information 26.5.1 sci data frames separated by preamble to separate sci data frame with preambles with minimum idle line time, use this sequence between messages: 1. write to sci data register (esci_dr) ? this sets the internal icmt bit which requests the data transmission 2. wait until tdre in interrupt flag and status register 1 (esci_ifsr1) is set ? this indicates the start of transmission; the icmt bit was cleared table 26-36. esci interrupt flags and interrupt enable bits interrupt source operational mode in terrupt flag interr upt enable bit transmitter sci esci_ifsr1[tdre] esci_cr1[tie] transmitter sci, lin esci_ifsr1[tc] esci_cr1[tcie] receiver sci esci_ifsr1[rdrf] esci_cr1[rie] receiver sci esci_ifsr1[idle] esci_cr1[ilie] receiver sci esci_ifsr 1[or] esci_cr2[orie] receiver sci, lin esci_ ifsr1[nf] esci_cr2[nfie] receiver sci, lin esci_ ifsr1[fe] esci_cr2[feie] receiver sci esci_ifsr1[pf] esci_cr2[pfie] receiver lin esci_ifsr1[berr] esci_cr2[berrie] receiver lin esci_ifsr2[rxrdy] esci_lcr1[rxie] transmitter lin esci_ifsr2[txrdy] esci_lcr1[txie] receiver lin esci_ifsr 2[lwake] esci_lcr1[wuie] receiver lin esci_ifsr2[sto] esci_lcr1[stie] receiver lin esci_ifsr2[pberr] esci_lcr1[pbie] receiver lin esci_ifsr2[cerr] esci_lcr1[cie] receiver lin esci_ifsr2[ckerr] esci_lcr1[ckie] receiver lin esci_ifsr2[frc] esci_lcr1[fcie] receiver lin esci_ifsr2[ureq] esci_lcr2[urie] transmitter, receiver lin esci_ifsr2[ovfl] esci_lcr2[ofie]
enhanced serial communication interface (esci) freescale semiconductor 26-53 pxr40 microcontroller reference manual, rev. 1 3. clear and subsequently set the te bit in control register 1 (esci_cr1) ? this set the internal ipre bit wh ich requests the preamble transmission 4. write to sci data register (esci_dr) ? this sets the internal icmt bit which requests the data transmission the priority scheme of the tran smitter which is described in table 26-28 ensures, that the preamble is transmitted before the data frame.
enhanced serial communication interface (esci) 26-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 27-1 pxr40 microcontroller reference manual, rev. 1 chapter 27 enhanced queued analog-to-digital converter (eqadc) 27.1 overview the enhanced queued analog-to-digital convert er (eqadc) module provi des fast and accurate conversions for a wide range of applications. there are two eq adc modules on the pxr40, eqadc_a and eqadc_b. each eqadc module provides a pa rallel interface to two on-chip, independent analog-to-digital converter cores. eqadc_b has a hardwa re interface to the eight decimation filt er blocks on the pxr40. this allows transferring of conversion and filtered values to and from the eqadc and decimation filters without cpu or dma interaction. each eqadc m odule has 24 dedicated external analog input pins, and 16 pins are shared by each module. the eqadc transfers commands from multiple comm and fifos (cfifos) to the on-chip adcs. the multiple result fifos (rfi fos) can receive data from the on-chi p adcs or from an on-chip dsp module (decimation filters). data from the on-chip adcs can be routed to the side interface, processed by the decimation filters and then routed back through th e side interface to the rf ifos. the eqadc supports software and external hardware tr iggers (via package pins) from ot her blocks (etpu and emios) to initiate transfers of commands from the cfifos to the on-chip adcs. it also monito rs the fill level of the cfifos and rfifos, and accordingly generates dma or interrupt requests to control data movement between the fifos and the system memory.
enhanced queued analog-to-digital converter (eqadc) 27-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.1.1 analog to digital conversion sub-system figure 27-1 shows how two eqadc modules fit into the ove rall analog to digital conversion sub-system. figure 27-1. analog to digital conversion sub-system rfifox cfifox ana0 ana23 an24 an39 vdda_an_a vdda_dig_a vssa_an_a vssa_dig_a vrh_a vrl_a refbypca refbypca1 vdda_an_b vdda_dig_b vssa_an_b vssa_dig_b vrh_b vrl_b refbypcb refbypcb1 adc0 adc1 rfifox cfifox anb0 anb23 cqueue y rqueue y cqueue y rqueue y dma adc0 adc1 system ram eqadc_b eqadc_a etrig1 etrig0 siu decimation filter (8) external trigger temp sensor emios etpu pit/rti absolute ref parallel side interface cpu or 24 24 conversion commands results time stac bus interface stac bus interface 16 16 base
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-3 pxr40 microcontroller reference manual, rev. 1 27.2 block diagram figure 27-2 is the block diagram for an eqadc block ( table 27-1 describes the main sub-blocks). figure 27-2. eqadc block diagram an8/anw an9/anx/tbias an10/any an11/anz an0/dan0+ an1/dan0- an2/dan1+ an3/dan1- an4/dan2+ an5/dan2- an6/dan3+ an7/dan3- priority decoder adc0 adc1 bias gen refbypc cfifox note: x=0, 1, 2, 3, 4, 5 32 bits cqueue y rqueue y system rfifox 16 bits cbuffer0 cbuffer1 eqadc fifo control mux control logic channel vdda vssa vrh vrl ma0 ma1 ma2 y=0, 1, 2, 3, ... dma and requests number adc control interrupt dma transaction done signals unit logic an12/t50pvref an13/t25pvref an15 an14/t75pvref pre-charge ref gen parallel side interface (eqadc psi) eqadc on-chip digital signal processor abort cont abort cont memory result format and calibra- tion etrigx,atrig fil an16/anr an17/ans an19/anu an18/ant an20-39 mux mux (decimation filter) bypassx
enhanced queued analog-to-digital converter (eqadc) 27-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 27-1 shows the primary components inside the eqadc. figure 27-2 also depicts data flow thr ough the eqadc. commands are cont ained in system memory in a user defined data structure. the most likely data structure to be used is a queue (as shown in figure 27-2 1 ). command data is moved from the command queue (cqu eue) to the cfifos by either the host cpu or by the system dma controller. once a cfifo is triggered and becomes th e highest priority cfifo using a certain cbuffer, command data is transferred from the cfifo to th e on-chip adcs. the adc executes the command, and the result is moved through the result format and calibration sub-block to either the side interface or to the rfifo. data from the on- chip companion module (deci mation filter) bypasses the result format and calibration sub-block and is moved directly to its specified rfifo. when data is stored in an rfifo, data is moved from the rfif o by the host cpu or by the system dma controller to a data structure in system memo ry as a result queue (rqueue). if you are familiar with the qadc , the eqadc system upgrades the f unctionality provided by that block. refer to section 27.8.7, eqadc versus qadc , for a comparison between the eqadc and qadc. 27.2.1 features each eqadc block includes these distinctive features (except where noted): table 27-1. eqadc primary component descriptions component function fifo control unit controls the cfifos and the rfifos: ? prioritizes the cfifos to determine which cfifos will have their commands transferred. ? supports software and hardware triggers to start command transfers from a particular cfifo. ? decodes command data from the cfifos and, accordingly, sends these commands to one of the two on-chip adcs. ? decodes result data from on-chip adcs and transfers data to the appropriate rfifo or to the parallel side interface. adc control logic manages the execution of commands bound for on-chip adcs: ? interfaces with the cfifos via two 2- entry command buffers (cbuffers) with abort control and with the rfifos via the result format and calibration sub-block. ? buffers command data for execution. ? decodes command data and, accordingly, generates control signals for the two on-chip adcs. ? detects abort requests, stores abo rted commands and buffers immediate conversion commands. ? formats and calibrates conversion result data coming from the on-chip adcs. ? generates the internal multiplexer control signals and the select signals used by the external multiplexers. eqadc parallel side interface (eqadc psi) allows for a full duplex, synchronous, parallel communication between the eqadc and decimation filters. 1. command and result data can be stored in system memory in any user defined data structure. however, in this document it will be assumed that the data structure of choice is a queue, since it is the mo st likely data structure to be used and because queues are the only type of data structure supported by the dmac.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-5 pxr40 microcontroller reference manual, rev. 1 ? two independent on-chip rsd cyclic adcs ? 8, 10, and 12 bits ad resolution ? selectable common mode convers ion range (0?5v; 0?2.5v; 0?1.25v) ? differential conversions ? differential channels include variable gain amplifier for improved dyna mic range (x1; x2; x4) ? differential channels include programmable pull-up and pull-dow n resistors for biasing and sensor diagnostics (200 k ohms; 100k ohms; 5k ohms) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles ? each conversion result can be marked with an imported timestamp from the etpu, or an independent timestamp ? parallel interface to eq adc cfifos and rfifos ? supports both right-justified unsigned and signed formats for conversion results ? two refbypc pins for each eqadc module: refbypc25 and refbypc75 ? temperature sensor (availabl e only to the primary adc pa ir (eqadc_a?s adc0 and adc1) ? ability to directly measure vdd ? automatic application of adc calibration constants ? parallel side interface allows eqadc_b to rout e conversion results without cpu intervention to the decimation filter bloc k for signal processing ? priority based cfifos ? supports six cfifos with fixed priority. the lower the cfifo num ber, the higher its priority. when commands of distinct cfifos are bound for the same cbuffer, the higher priority cfifo is always served first. ? immediate conversion command feat ure with conversion abort control ? streaming mode operation of cfifo0 to ex ecute defined commands multiple times ? supports software and several hardware tr igger modes to arm a particular cfifo ? generates interrupt when comm and coherency is not achieved ? external (to the eqadc) hardware triggers ? supports rising edge, falling edge, high level and low level triggers ? supports configurab le digital filter ? supports controls to bypass the trigger di gital filters (refer to the siu chapter) ? two triggers operation mode for queue0 ? additional internal trigger (not filtered) called advance trigger that is used to enable the external trigger of queue0 and to control the loop behavior of cfifo0 (only available on eqadc_b) ? supports 4 to 8 external 8-to-1 muxes which ca n expand the input channel number from 40 to 96 27.3 modes of operation this section describes the op eration modes of the eqadc.
enhanced queued analog-to-digital converter (eqadc) 27-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.3.1 normal mode this is the default operational m ode when the eqadc is not in st reaming mode or background debug or stop mode. 27.3.2 streaming mode this mode is characterized by two main aspects: the abort action by cfifo0 in any current conversion process started from another queue, a nd the loop behavior of the cfifo0. in some applications, there may be sequences of identical commands each spaced only by a few microseconds. to reduce the dma data transfer, in th is mode a short command que ue can be stored in cfifo0 and repeatedly be executed based on a timed trigger, but advanc e to the next (repeating) sequence of commands based on anothe r device?s internal trigger. the cfifo0 delivers commands to th e adc as before, but t hose commands are not ?i nvalidated? after they are sent (in fact, they ar e ?invalidated? only because the transfer next data pointer has moved on). when it encounters these repeated commands the cfifo0 onl y fills once, using the dma as usual, until either it is full or a command with end-of-queue is enc ountered. thereafter the sub- queue repeats/wraps. the number of commands loaded is unaffected by the de livery of commands once the streaming mode is configured, since no commands loaded are invalidated even if sent before all the queue is loaded. the number of entries in the cfifo0 is extended to eight (configurable). this is to facilitate the targeted applications. the repeating s ubqueue must be contained with in the eight cfifo0 entries. to maintain compatibility, cfifo0 by default operates as it does before, without streaming and with four entries. streaming, and additional entr ies, can be enabled independently. streaming mode is selected as another mode for queue 0 using the configuration bits in the eqadc_cfcr register. streaming m ode makes use of an additional bit in the conversion command word (ccw); this bit is called ?repeat?. the purpose of this bit is to mark in the command queue, where to start a repeating sequence. streaming mode requires 2 trigger inputs. the standard queue 0 trigger, in this mode referred to as ?repeat trigger? and a second internal trigger input to the eqadc called ?advance? trigger. 27.3.3 debug mode upon a debug mode entry request, eqadc behavior will vary according to the status of the dbg field in the eqadc_mcr. if dbg is programmed to 0b00, the de bug mode entry request is ignored. if dbg is programmed to 0b10 or to 0b11, the eqadc will enter debug mode. during debug mode, the eqadc will not transfer commands from any cfif os, no data will be returned to any rfifo, no hardware trigger event will be capt ured, and all eqadc registers can be accessed as in normal mode. the latter implies that cfifos can st ill be triggered using so ftware triggers, since no scheme is implemented to writ e-protect registers du ring debug mode. dma and interrupt requests continue to be generated as in normal mode. if at the time the debug mode entry request is detecte d, there are commands in the on-chip cbuffers that were already under execution, these comma nds will be completed but the gene rated results, if any, will not
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-7 pxr40 microcontroller reference manual, rev. 1 be sent to the rfifos until debug m ode is exited. commands whose exec ution has not star ted will not be executed until debug mode is exited.the clock associated with an on-chip adc stops, dur ing its low phase, after the adc ceases executing comma nds. the time base counter will only stop after all on-chip adcs cease executing commands. when exiting debug mode, the eqadc relies on the cfifo operation mode s and on the cfifo status to determine the next command entry to transfer. the eqadc?s internal behavior after the debug mode entry request is detect ed differs depending on the status of command transfers. ? no command transfer is in progress. the eqadc immediately halts future command transfers from any cfifo. ? command transfer is in progress. eqadc will complete the transf er and update cfifo status be fore halting future command transfers from any cfifo. comma nd transfers to the internal cbuf fers are considered completed when a command is written to the buffers. 27.3.4 stop mode upon a stop mode entry request detect ion, the eqadc progressive ly halts its operations until it reaches a static, stable state from which it can recover when returning to normal mode. eqadc then asserts an acknowledge signal, indi cating that it is static a nd that the clock input can be stopped.the latter implies that, as long as the platform clock is running, cf ifos can still be triggered us ing software triggers, since no scheme is implemented to write- protect registers during stop mode. if at the time the stop mode entry re quest is detected, there are comma nds in the on-chip cbuffers that were already under execution, these comma nds will be completed but the gene rated results, if any, will not be sent to the rfifos until stop mode is exited. commands whose execution has not started will not be executed until stop mode is exited. after these remaining commands are executed, the clock input to the ad cs and the bias generator circuit is stopped. the adc clock stops duri ng its low phase. the time base counter will onl y stop after all on-chip adcs cease executing comm ands. only then, the stop acknowle dge signal is asserted. when exiting stop mode, the eqadc relies on the cfifo operation modes and on the cfifo status to determine the next command entry to transfer. the eqadc internal behavior after the stop mode entr y request is detected diff ers depending on the status of the command transfer. ? no command transfer is in progress the eqadc immediately halts future command transfers from any cfifo. ? command transfer is in progress eqadc will complete the transf er and update cfifo status be fore halting future command transfers from any cfifo. comma nd transfers to the internal cbuf fers are considered completed when a command is written to the buffers.
enhanced queued analog-to-digital converter (eqadc) 27-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.4 external signal description 27.4.1 overview the following is a list of external pi ns (applies to both eqadc_a and eqadc_b). note at chip integration level, some of th e digital and analog si gnals listed here might share pins or not be available external to the chip. refer to the signals chapter for details. table 27-2. eqadc signals name port function reset state type an0/dan0+ 1 input single-ended analog input / differential analog input positive terminal ?analog an1/dan0- 1 input single-ended analog input / differential analog input negative terminal ?analog an2/dan1+ 1 input single-ended analog input / differential analog input positive terminal ?analog an3/dan1- 1 input single-ended analog input / differential analog input negative terminal ?analog an4/dan2+ 1 input single-ended analog input / differential analog input positive terminal ?analog an5/dan2- 1 input single-ended analog input / differential analog input negative terminal ?analog an6/dan3+ 1 input single-ended analog input / differential analog input positive terminal ?analog an7/dan3- 1 input single-ended analog input / differential analog input negative terminal ?analog an8/anw input single-ended analog input / single-ended analog input from external multiplexers ?analog an9/anx input single-ended analog input / single-ended analog input from external multiplexers ?analog an10/any input single-ended analog input/single-ended analog input from external multiplexers ?analog an11/anz input single-ended analog input / single-ended analog input from external multiplexers ?analog an12 input / output single-ended analog input ? analog an13 input / output single-ended analog input ? analog an14 input / output single-ended analog input ? analog an15 input single-ended analog input ? analog an16/anr 2 input single-ended analog input / single-ended analog input from external multiplexers ?analog an17/ans 2 input single-ended analog input / single-ended analog input from external multiplexers ?analog an18/ant 2 input single-ended analog input / single-ended analog input from external multiplexers ?analog
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-9 pxr40 microcontroller reference manual, rev. 1 27.4.2 detailed signal descriptions an19/anu 2 input single-ended analog input / single-ended analog input from external multiplexers ?analog an20?an39 input single-ended analog inputs ? analog ma0 output external multiplexer control signal 0 digital ma1 output external multiplexer control signal 0 digital ma2 output external multiplexer control signal 0 digital vdda input analog positive power supply ? power vssa input analog negative power supply ? power vrh input voltage reference high ? power vrl input voltage reference low ? power refbypc input external bypass capacitor pin ? power etrig0 input external trigger for cfifo0 ? digital etrig1 input external trigger for cfifo1 ? digital etrig2 input external trigger for cfifo2 ? digital etrig3 input external trigger for cfifo3 ? digital etrig4 input external trigger for cfifo4 ? digital etrig5 input external trigger for cfifo5 ? digital notes: 1 during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pull resistors are disabled when the system clock propagates through the device. 2 can be disabled or not using configuration parameters. table 27-3. eqadc external signals signal name description an0/dan0+ 1 single-ended analog input/differential analog input positive terminal. an0 is a single-ended analog input to the two on-chip adcs. dan0+ is the positive terminal of the differential analog input dan0 (dan0+ - dan0-). an1/dan0- 1 single-ended analog input/differential analog input negative terminal. an1 is a single-ended analog input to the two on-chip adcs. dan0- is the negative terminal of the differential analog input dan0 (dan0+ - dan0-). an2/dan1+ 1 single-ended analog input/differential analog input positive terminal. an2 is a single-ended analog input to the two on-chip adcs. dan1+ is the positive terminal of the differential analog input dan1 (dan1+ - dan1-). an3/dan1- 1 single-ended analog input/differential analog input negative terminal. an3 is a single-ended analog input to the two on-chip adcs. dan1- is the negative terminal of the differential analog input dan1 (dan1+ - dan1-). an4/dan2+ 1 single-ended analog input/differential analog input positive terminal. an4 is a single-ended analog input to the two on-chip adcs. dan2+ is the positive terminal of the differential analog input dan2 (dan2+ - dan2-). table 27-2. eqadc si gnals (continued) name port function reset state type
enhanced queued analog-to-digital converter (eqadc) 27-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 an5/dan2- 1 single-ended analog input/differential analog input negative terminal. an5 is a single-ended analog input to the two on-chip adcs. dan2- is the negative terminal of the differential analog input dan2 (dan2+ - dan2-). an6/dan3+ 1 single-ended analog input/differential analog input positive terminal. an6 is a single-ended analog input to the two on-chip adcs. dan3+ is the positive terminal of the differential analog input dan3 (dan3+ - dan3-). an7/dan3- 1 single-ended analog input/differential analog input negative terminal. an7 is a single-ended analog input to the two on-chip adcs. dan3- is the negative terminal of the differential analog input dan3 (dan3+ - dan3-). an8/anw single-ended analog input/ single-ended analog input from external multiplexers. an8 is a single-ended analog input to the two on-chip adcs. anw is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. an9/anx single-ended analog input/ single-ended analog input from external multiplexers/test bias. an9 is a single-ended analog input to the two on-chip adcs. anx is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. an10/any single-ended analog input/ single-ended analog input from external multiplexers. an10 is a single-ended analog input to the two on -chip adcs. any is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. an11/anz single-ended analog input/ single-ended analog input from external multiplexers. an11 is a single-ended analog input to the two on-chip adcs. anz is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. an12 single-ended analog input/ test 50% vref analog output. an12 is a single-ended analog input to the two on-chip adcs. an13 single-ended analog input/ test 25% vref analog output. an13 is a single-ended analog input to the two on-chip adcs. an14 single-ended analog input/ test 75% vref analog output. an14 is a single-ended analog input to the two on-chip adcs. an15 single-ended analog input. an15 is a single-ended analog inputs to the two on-chip adcs. an16/anr single-ended analog input/ single-ended analog input from external multiplexers. an16 is a single-ended analog input to the two on-chip adcs. anr is a single-ended analog input to one of the on-chip adcs in external multiplexed m ode. the external multiplexing capability is a device option. an17/ans single-ended analog input/ single-ended analog input from external multiplexers. an17 is a single-ended analog input to the two on -chip adcs. ans is a single-ended analog input to one of the on-chip adcs in external multiplexed m ode. the external multiplexing capability is a device option. an18/ant single-ended analog input/ single-ended analog input from external multiplexers. an18 is a single-ended analog input to the two on-chip adcs. ant is a single-ended analog input to one of the on-chip adcs in external multiplexed m ode. the external multiplexing capability is a device option. an19/anu single-ended analog input/ single-ended analog input from external multiplexers. an19 is a single-ended analog input to the two on-chip adcs. anu is a single-ended analog input to one of the on-chip adcs in external multiplexed m ode. the external multiplexing capability is a device option. table 27-3. eqadc external signals (continued) signal name description
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-11 pxr40 microcontroller reference manual, rev. 1 27.5 pin mapping to channel mapping table 27-4 shows the pin mapping to channel mapping to show which signals go to which adc. for internal and external multipl exing channel assignments, see table 27-42 . an20-an39 single-ended analog input. an20 through an39 are single-ended analog inputs to the two on-chip adcs. ina_adc0_0 - ina_adc0_9 (not external to the chip) single-ended analog input. ina_adc0_0 through ina_adc0_9 are single-ended analog inputs to the on-chip adc0. ina_adc1_0 - ina_adc1_9 (not external to the chip) single-ended analog input. ina_adc1_0 through ina_adc1_9 are single-ended analog inputs to the on-chip adc1. ma0-ma2 external multiplexer control signals. ma0, ma1, and ma2 combined form a select signal associated with external multiplexers. vrh, vrl voltage reference high and voltage reference low. vrh and vrl are voltage references for the adcs. v rh is the highest voltage reference, while vrl is the lowest voltage reference. vdda, vssa 5v vdd and vss for the 5v analog components. vdda is the positive power supply pin for the adcs and vssa is the negative power supply pin for the adcs. refer to electrical specifications. refbypc reference bypass capacitor the refbypc pin is used to connect an external bypass capacitor betwe en refbypc and vrl. the value of this capacitor should be 100nf. this bypass capacitor is used to provide a stable reference voltage for the adc. etrig0-etrig5 external trigger the external trigger signals are for hardware triggering. the eqadc can detect rising edge, falling edge, high level and low level on each of the extern al trigger signals. etri gx triggers cfifox. the eqadc also uses digital filters for these external trigger signals. notes: 1 during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pull resistors are disabled when the system clock propagates through the device. table 27-4. pin mapping to channel mapping analog input pin 416 package function adc number eqadc_a channel number eqadc_b channel number eqadc_a eqadc_b ana0?ana23 1 single ended conversion 0, 1 ? 0?23 ? anb0?anb23 single ended conversion ? 0,1 ? 0?23 an24?an39 single ended conversion 0, 1 0, 1 24?39 24?39 ? vrh 0, 1 0, 1 40 40 ? vrl 0, 1 0, 1 41 41 ? 50% (vrh?vrl) 2 0, 1 0, 1 42 42 ? 75% (vrh?vrl) 0, 1 0, 1 43 43 ? 25% (vrh?vrl) 0, 1 0, 1 44 44 table 27-3. eqadc external signals (continued) signal name description
enhanced queued analog-to-digital converter (eqadc) 27-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? local band gap 1220mv 0, 1 ? 45 45 ana8 anwa 3 0, 1 0, 1 64?71 ? anb8 anwb 3 ? 0, 1 ? 64?71 ana9 anxa 3 0, 1 ? 72?79 ? anb9 anxb 3 ? 0, 1 ? 72?79 ana10 anya 3 0, 1 ? 80?87 ? anb10 anyb 3 ? 0, 1 ? 80?87 ana11 anza 3 0, 1 ? 88?95 ? anb11 anzb 3 ? 0, 1 ? 88?95 ana0 and ana1 dana0+ and dana0- 0, 1 ? 96 ? anb0 and anb1 danb0+ and danb0- ? 0, 1 ? 96 ana2 and ana3 dana1+ and dana1- 0, 1 ? 97 ? anb2 and anb3 danb1+ and danb1- ? 0, 1 ? 97 ana4 and ana5 dana2+ and dana2- 0, 1 ? 98 ? anb4 and anb5 danb2+ and danb2- ? 0, 1 ? 98 ana6 and ana7 dana3+ and dana3- 0, 1 ? 99 ? anb6 and anb7 danb3+ and danb3- ? 0, 1 ? 99 ? temperature sensor 0, 1 ? 128 ? ? pmc band gap 0.62 v 4 0 ? 145 ? ? vdd 0 ? 146 ? ? internal 1.2 v regulator 0 ? 147 ? ? vddeh1 50% 0 ? 162 ? ? vddeh3 50% 0 ? 163 ? ? vddeh4 50% 0 ? 164 ? ? vddeh5 50% 0 ? 165 ? ? vddeh6 50% 0 ? 166 ? ? vddeh7 50% 0 ? 167 ? ? 1.2 v lvd vdd 0 ? 180 ? ? 3.3 v internal regulator 0 ? 181 ? ? 3.3 v lvd vddsyn 0 ? 182 ? ? 5.0 v lvd vddreg 0 ? 183 ? ? standby regulator out 1 ? 194 ? ? standby source bias 1 ? 195 ? table 27-4. pin mapping to channel mapping (continued) analog input pin 416 package function adc number eqadc_a channel number eqadc_b channel number eqadc_a eqadc_b
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-13 pxr40 microcontroller reference manual, rev. 1 27.6 memory map/register definition this section provides memory maps and detailed de scriptions of all registers. da ta written to or read from reserved areas of the memory map is undefined. 27.6.1 eqadc memory map this section provides memory maps for the eqadc block. ? 4.75 v lvd vdda (adc band gap) 1 ? 196 ? ana16 anra 3 0, 1 ? 224?231 ? anb16 anrb 3 ? 0, 1 ? 224?231 ana17 ansa 3 0, 1 ? 232?239 ? anb17 ansb 3 ? 0, 1 ? 232?239 ana18 anta 3 0, 1 ? 240?247 ? anb18 antb 3 ? 0, 1 ? 240?247 ana19 anua 3 0, 1 ? 248?255 ? anb19 anub 3 ? 0, 1 ? 248?255 notes: 1 an x 8?an x 11 and an x 16?an x 19 have alternate functions when used with an external multiplexer. 2 after calibration, the 50% reference point will read approximately 20 mv below 50%(vrh - vrl). the 50% reference point should not be used to calibrate the eqadc. use the 25% and 75% reference points to calibrate the eqadc. 3 this function is when using an external multiplexer. 4 refer to the pmc chapter. table 27-5. eqadc memory map address offset 1 register bits access reset value section/page 0x0000 eqadc_mcr?eqadc module configuration register 32 r/w 0x0000_0000 27.6.2.1/16 0x0004 reserved ? 0x0008 reserved ? 0x000c eqadc_etdfr?eqadc external trigger digital filter register 32 r/w 0x0000_0000 27.6.2.2/17 0x0010 eqadc_cfpr0?eqadc cfifo push register 0 32 w 0x0000_0000 27.6.2.3/18 0x0014 eqadc_cfpr1?eqadc cfifo push register 1 32 w 0x0000_0000 0x0018 eqadc_cfpr2?eqadc cfifo push register 2 32 w 0x0000_0000 0x001c eqadc_cfpr3?eqadc cfifo push register 3 32 w 0x0000_0000 0x0020 eqadc_cfpr4?eqadc cfifo push register 4 32 w 0x0000_0000 0x0024 eqadc_cfpr5?eqadc cfifo push register 5 32 w 0x0000_0000 0x0028 reserved ? table 27-4. pin mapping to channel mapping (continued) analog input pin 416 package function adc number eqadc_a channel number eqadc_b channel number eqadc_a eqadc_b
enhanced queued analog-to-digital converter (eqadc) 27-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x002c reserved ? 0x0030 eqadc_rfpr0?eqadc result fifo pop register 0 32 r 0x0000_0000 27.6.2.4/19 0x0034 eqadc_rfpr1?eqadc result fifo pop register 1 32 r 0x0000_0000 0x0038 eqadc_rfpr2?eqadc result fifo pop register 2 32 r 0x0000_0000 0x003c eqadc_rfpr3?eqadc result fifo pop register 3 32 r 0x0000_0000 0x0040 eqadc_rfpr4?eqadc result fifo pop register 4 32 r 0x0000_0000 0x0044 eqadc_rfpr5?eqadc result fifo pop register 5 32 r 0x0000_0000 0x0048 reserved ? ? 0x004c reserved ? ? 0x0050 eqadc_cfcr0-1?eqadc cfifo control register 0 and 1 32 r/w 0x0000_0000 27.6.2.5/19 0x0054 eqadc_cfcr2-3?eqadc cfifo control register 2 and 3 32 r/w 0x0000_0000 0x0058 eqadc_cfcr4-5?eqadc cfifo control register 4 and 5 32 r/w 0x0000_0000 0x005c reserved ? ? 0x0060 eqadc_idcr0?eqadc interrupt and dma control register 0 32 r/w 0x0000_0000 27.6.2.6/22 0x0064 eqadc_idcr1?eqadc interrupt and dma control register 1 32 r/w 0x0000_0000 0x0068 eqadc_idcr2?eqadc interrupt and dma control register 2 32 r/w 0x0000_0000 0x006c reserved ? ? 0x0070 eqadc_fisr0?eqadc fi fo and interrupt status register 0 32 r/w 0x0200_0000 27.6.2.7/25 0x0074 eqadc_fisr1?eqadc fi fo and interrupt status register 1 32 r/w 0x0200_0000 0x0078 eqadc_fisr2?eqadc fi fo and interrupt status register 2 32 r/w 0x0200_0000 0x007c eqadc_fisr3?eqadc fifo and interrupt status register 3 32 r/w 0x0200_0000 0x0080 eqadc_fisr4?eqadc fi fo and interrupt status register 4 32 r/w 0x0200_0000 0x0084 eqadc_fisr5?eqadc fi fo and interrupt status register 5 32 r/w 0x0200_0000 0x0088 reserved ? ? 0x008c reserved ? ? 0x0090 eqadc_cftcr0?eqadc cfifo transfer counter register 0 32 r/w 0x0000_0000 27.6.2.8/29 0x0094 eqadc_cftcr1?eqadc cfifo transfer counter register 1 32 r/w 0x0000_0000 0x0098 eqadc_cftcr2?eqadc cfifo transfer counter register 2 32 r/w 0x0000_0000 0x009c reserved ? ? table 27-5. eqadc memory map (continued) address offset 1 register bits access reset value section/page
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-15 pxr40 microcontroller reference manual, rev. 1 0x00a0 eqadc_cfssr0?eqadc cfifo status snapshot register 0 32 r 0x0000_7800 27.6.2.9/30 0x00a4 eqadc_cfssr1?eqadc cfifo status snapshot register 1 32 r 0x0000_7800 0x00a8 reserved ? ? 0x00ac eqadc_cfsr?eqadc cfifo status register 32 r 0x0000_0000 27.6.2.10/32 0x00b0?0x 00cc reserved ? ? 0x00d0 eqadc_redlccr?eqadc red line client configuration register 32 0x0000_0000 27.6.2.11/33 0x00d4?0x 00fc reserved ? ? 0x0100?0x0 10c eqadc_cf0rw?eqadc cfifo0 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.12/34 0x0110?0x0 11c eqadc_cf0erw?eqadc cfifo0 extension registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.13/37 0x0120 ?0x013c reserved ? ? 0x0140?0x0 14c eqadc_cf1rw?eqadc cfifo1 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.13/37 0x0150?0x0 17c reserved ? ? 0x0180?0x0 18c eqadc_cf2rw?eqadc cfifo2 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.13/37 0x0190?0x0 1bc reserved ? ? 0x01c0?0x 01cc eqadc_cf3rw?eqadc cfifo3 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.13/37 0x01d0?0x 01fc reserved ? ? 0x0200?0x0 20c eqadc_cf4rw?eqadc cfifo4 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.13/37 0x0210?0x0 23c reserved ? ? 0x0240?0x0 24c eqadc_cf5rw?eqadc cfifo5 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.13/37 0x0250?0x0 2fc reserved ? ? 0x0300?0x0 30c eqadc_rf0rw?eqadc rfifo0 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.14/37 0x0310?0x0 33c reserved ? ? 0x0340?0x0 34c eqadc_rf1rw?eqadc rfifo1 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.14/37 0x0350?0x0 37c reserved ? ? table 27-5. eqadc memory map (continued) address offset 1 register bits access reset value section/page
enhanced queued analog-to-digital converter (eqadc) 27-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.2 eqadc register descriptions 27.6.2.1 eqadc module configur ation register (eqadc_mcr) the eqadc module configuration re gister (eqadc_mcr) contains bi ts used to control how the eqadc responds to a debug mode entry request. 0x0380?0x0 38c eqadc_rf2rw?eqadc rfifo2 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.14/37 0x0390?0x0 3bc reserved ? ? 0x03c0?0x 03cc eqadc_rf3rw?eqadc rfifo3 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.14/37 0x03d0?0x 03fc reserved ? ? 0x0400?0x0 40c eqadc_rf4rw?eqadc rfifo4 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.14/37 0x0410?0x0 43c reserved ? ? 0x0440?0x0 44c eqadc_rf5rw?eqadc rfifo5 registers (w=0, .., 3) 32 r 0x0000_0000 27.6.2.14/37 0x0450?0x0 7fc reserved ? ? notes: 1 eqadc_a_base = 0xfff8_0000 eqadc_b_base = 0xfff8_4000 address: 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0000 0000000 w reset000000000 0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 icea0 icea1 00 0 dbg w reset000000000 0000000 figure 27-3. eqadc module conf iguration regist er (eqadc_mcr) table 27-5. eqadc memory map (continued) address offset 1 register bits access reset value section/page
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-17 pxr40 microcontroller reference manual, rev. 1 27.6.2.2 eqadc external tr igger digital filter register (eqadc_etdfr) the eqadc external trigger digita l filter register (eqad c_etdfr) is used to set the minimum time a signal must be held in a logic state on the cfifo tr iggers inputs to be recogni zed as an edge or level gated trigger. the digital filter le ngth field specifies the minimum numbe r of platform clocks that must be counted by the digital filter count er to recognize a logic state change . this filter does not work when the trigger is an internal signal (see siu chapter), but should be considered when the trigger is an external one. table 27-6. eqadc_mcr field descriptions field description 0?23 reserved 24?25 icea n immediate conversion command enable adc n ( n =0,1). icea n enables the eqadc to abort on-chip adc n current conversion and to start the immediate conversi on command from cfifo0 in the requested adc n . 0 disable immediate conversion command request. 1 enable immediate conversion command request. 2?29 these bits are reserved and must always be 0b00. 30?31 dbg debug enable. the dbg field defines the eqadc response to a debug mode entry request. 00 do not enter debug mode. 01 reserved 1x enter debug mode. address: 0x000c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 dfl w reset00000000000000000000000000000000 figure 27-4. eqadc external trigger di gital filter register (eqadc_etdfr)
enhanced queued analog-to-digital converter (eqadc) 27-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.2.3 eqadc cfifo push registers (eqadc_cfpr) the eqadc cfifo push registers (eqadc_cfpr) pr ovide a mechanism to fill the cfifos with command messages from th e cqueues. refer to section 27.7.4, eqadc command fifos , for more information on the cfifos and to section 27.7.2.2, message format in eqadc , for a description on command message formats. table 27-7. eqadc_etdfr field description field description 0?27 reserved 28?31 dfl digital filter length. the dfl field specifies the minimum number of platform clocks t hat must be counted by the digital filter counter to recognize a logi c state change. the count sp ecifies the sample period of the digital filter which is calculated according to the following equation: minimum clock counts for which an etrig signal needs to be st able to be passed through the filter are shown below. refer to section 27.7.4.5, hardware trigger event detection , for more information on the digital filter. note: the dfl field must only be written when the modex of all cfifos are configured to disabled.when the digital filter is bypassed (i.e. for on-chip triggers), the dfl is not considered and the trigger input signal is not filtered. filterperiod s ? ystemclockperiod 2 dfl ? ? 1 s ? ystemclockperiod ? + = dfl[0:3] minimum clock count minimum time (ns) (platform clock = 120 mhz) 0b0000 2 16.66 0b0001 3 25.00 0b0010 5 41.66 0b0011 9 75.00 0b0100 17 141.66 0b0101 33 275.00 0b0110 65 541.66 0b0111 129 1075.00 0b1000 257 2141.66 0b1001 513 4275.00 0b1010 1025 8541.66 0b1011 2049 17075.00 0b1100 4097 34141.00 0b1101 8193 68275.00 0b1110 16385 136541.66 0b1111 32769 273075.00
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-19 pxr40 microcontroller reference manual, rev. 1 27.6.2.4 eqadc result fifo pop registers (eqadc_rfpr) the eqadc result fifo pop regi sters (eqadc_rfpr) provide a mech anism to retrieve data from rfifos. 27.6.2.5 eqadc cfifo contro l registers (eqadc_cfcr) the eqadc cfifo control registers (eqadc_cfcr) contain bits that aff ect cfifos. these bits specify the cfifo operation mode and can invalidate all of the cfifo contents. address: 0x0010, 0x0014, 0x0018, 0x001c, 0x0020, 0x0024 access: user write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 000 00 w cf_push x reset00000000000000000000000000000000 figure 27-5. eqadc cfifo push register x (eqadc_cfpr x ) table 27-8. eqadc_cfpr x field description field description 0?31 cf_push x cfifo push data x. when cfifo x is not full, writing to the whole word or any bytes of eqadc_cfpr x will push the 32-bit cf_push x value into cfifo x . writing to this field also increments the corresponding eqadc_fisr[cfctr x ] value by one. when the cfifo x is full, the eqadc ignores any write to the cf_push x . reading eqadc_cfprx always returns zero. note: only whole words must be written to eqadc_cfpr. wr iting half-words or bytes to eqadc_cfpr will still push the whole 32-bit cf_push field into the correspond ing cfifo, but undefined da ta will fill the areas of cf_push that were not specifically desig nated as target locations for the write. address: 0x0030, 0x0034, 0x0038, 0x003c, 0x0040, 0x0044 access: user read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000 rf_pop x w reset00000000000000000000000000000000 figure 27-6. eqadc rfifo pop register x (eqadc_rfpr x ) table 27-9. eqadc_rfpr x field description field description 0?15 reserved 16?31 rf_pop x result fifo pop data x . when rfifox is not empty, the rf_popx contains the next unread entry value of rfifox. reading a word, a half-word, or any bytes from eqadc_rfprx will pop on e entry from rfifox and cause the eqadc_fisr[rfctrx] field to be decremented by one. when the rfifox is empty, any read on eqadc_rfprx returns undefined data value and does not decrement the rfctrx value. writing to eqadc_rfprx has no effect.
enhanced queued analog-to-digital converter (eqadc) 27-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 address: 0x0050 (cfifo0) 0x0052 (cfifo1) 0x0054 (cfifo2) 0x0056 (cfifo3) 0x0058 (cfifo4) 0x005a (cfifo5) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 cfe ee0* str me0* 000 modex amode0* w ssex cfinvx reset000000 0 000000000 * only available for cfifo0 figure 27-7. eqadc cfifo contro l register x (eqadc_cfcrx) table 27-10. eqadc_cfcr x field description field description 0?2 reserved 3 cfeee0 cfifo0 entry number extension enable. the cfeee0 bit is used to enable the extension of the cfifo0 entries. when in extended mode, the cfifo0 total entries is the sum of normal entries plus the defined value for extension. for more details, refer to section 27.7.4.2, cfifo0 st reaming mode description . 1 enable the extension of cfifo0 entries. 0 cfifo0 has a normal value of entries. 4 strme0 cfifo0 streaming mode operation en able. the strme0 bit is used to enable the streaming mode of operation of cfifo0. in this case, it is possible to repeat some sequence of commands of this fifo without having to load new commands from a command queue. for more details, refer to section 27.7.4.2, cfifo0 streaming mode description . 1 enable the streaming mode of cfifo0. 0 streaming mode of cfifo0 is disabled. 5 ssex cfifo single-scan enable bit x. the ssex bit is used to set the eqad c_fisr[sssx] bit. writing a ?1? to ssex will set the eqadc_fisr[sssx] field if the cfifo is in single-scan mode. when eqadc_fisr[sssx] is already asserted, writing a ?1? to ssex has no ef fect. if the cfifo is in continuous-scan mode or is disabled, writing a ?1? to ssex will not set eqadc_fisr[sssx]. writing a ?0? to ssex has no effect. ssex always is read as ?0?. 0no effect. 1 set the sssx bit. 6 cfinvx cfifo invalidate bit x . the cfinv x bit causes the eqadc to invalidate all entries of cfifo x . writing a ?1? to cfinvx will reset the value of eqadc_fisr[cfctr x ]. writing a ?1? to cfinv x also resets the push next data pointer, transfer next data pointer to the first entry of cfifox in figure 27-49 . cfinvx always is read as ?0?. writing a ?0? has no effect. 0 no effect.1invalidate all of the entries in the corresponding cfifo. note: writing cfinv x only invalidates commands stored in cfifo x ; previously transferred commands that are waiting for execution, that is commands stored in th e cbuffers, will still be executed, and results generated by them will be stored in the appropriate rfifo. note: cfinv x must not be written unless the modex is config ured to disabled, and cfifo status is idle. 7 reserved
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-21 pxr40 microcontroller reference manual, rev. 1 8?11 mode x cfifo operation mode x . the mode x field selects the cfifo operation mode for cfifo x . refer to section 27.7.4.6, cfifo scan trigger modes , for more information on cfifo trigger mode. note: if mode x is not disabled, it must not be changed to any other mode besides disabled. if mode x is disabled and the cfifo status is idle, mode x can be changed to any other mode. table 27-10. eqadc_cfcr x field description (continued) field description mode x [0:3] cfifo operation mode 0b0000 disabled 0b0001 software trigger, single scan 0b0010 low level gated external trigger, single scan 0b0011 high level gated external trigger, single scan 0b0100 falling edge external trigger, single scan 0b0101 rising edge external trigger, single scan 0b0110 falling or rising edge external trigger, single scan 0b0111? 0b1000 reserved 0b1001 software trigger, continuous scan 0b1010 low level gated external trigger, continuous scan 0b1011 high level gated external trigger, continuous scan 0b1100 falling edge external trigger, continuous scan 0b1101 rising edge external trigger, continuous scan 0b1110 falling or rising edge external trigger, continuous scan 0b1111 reserved
enhanced queued analog-to-digital converter (eqadc) 27-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.2.6 eqadc interrupt and dma control registers (eqadc_idcr) the eqadc interrupt control regi sters (eqadc_idcr) contain bits to enable the generation of interrupt or dma requests when the corresponding flag bits are set in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) . 12?15 amode0 cfifo0 advance trigger operation mode 0. the amode0 field selects the tr igger mode for the atrig0 trigger signal in streaming mode. the use of reserved values drives to unknown behavior of the block. note: if amode0 is not disabled, it must not be changed to any other mode besides disabled if amode0 is disabled and the cfifo0 status is idle, am ode0 can be changed to any other mode. note: for the streaming mode of operation when the atri g0 is used to enable the etrig0 or to advance the command queue, the normal mode of operation is external trigger single scan. other settings are not fully tested. address: 0x0060 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ncie0 torie0 pie0 eoqie0 cfuie0 0 cffe0 cffs0 0000 rfoie0 0 rfde0 rfds0 w reset0 0 0 0 0 00 00000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncie1 torie1 pie1 eoqie1 cfuie1 0 cffe1 cffs1 0000 rfoie1 0 rfde1 rfds1 w reset0 0 0 0 0 00 00000000 0 figure 27-8. eqadc interrupt and dma control register 0 (eqadc_idcr0) table 27-10. eqadc_cfcr x field description (continued) field description amode 0 [0:3] cfifo0 advance trigger operation mode 0b0000 disabled 0b0001 software trigger, single scan 0b0010 low level gated external trigger, single scan 0b0011 high level gated external trigger, single scan 0b0100 falling edge external trigger, single scan 0b0101 rising edge external trigger, single scan 0b0110 falling or rising edge external trigger, single scan 0b0111?0b1111 reserved
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-23 pxr40 microcontroller reference manual, rev. 1 address: 0x0064 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ncie2 torie2 pie2 eoqie2 cfuie2 0 cffe2 cffs2 0000 rfoie2 0 rfde2 rfds2 w reset0 0 0 0 0 00 00000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncie3 torie3 pie3 eoqie3 cfuie3 0 cffe3 cffs3 0000 rfoie3 0 rfde3 rfds3 w reset0 0 0 0 0 00 00000000 0 figure 27-9. eqadc interrupt and dma control register 1 (eqadc_idcr1) address: 0x0068 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ncie4 torie4 pie4 eoqie4 cfuie4 0 cffe4 cffs4 0000 rfoie4 0 rfde4 rfds4 w reset0 0 0 0 0 00 00000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncie5 torie5 pie5 eoqie5 cfuie5 0 cffe5 cffs5 0000 rfoie5 0 rfde5 rfds5 w reset0 0 0 0 0 00 00000000 0 figure 27-10. eqadc interrupt and dm a control register 2 (eqadc_idcr2) table 27-11. eqadc_idcr field description field description 0 16 ncie x non-coherency interrupt enable x. nciex enables the eqadc to generate an interrupt request when the corresponding eqadc_fisr [ncfx] is asserted. 0 disable non-coherency interrupt request. 1 enable non-coherency interrupt request. 1 17 torie x trigger overrun interrupt enable x. toriex enables the eqadc to generate an interrupt request when the corresponding eqadc_fisr[torfx] is asserted. apart from generating an independent interrupt request fo r a cfifox trigger overrun event, the eqadc also provides a combined interrupt at which the result fi fo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interr upt requests of all cfif os are ored. when rfoiex, cfuiex, and toriex are all asserted, th is combined interrupt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 27.7.8, eqadc dma/interrupt request , for details. 0 disable trigger overrun interrupt request. 1 enable trigger overrun interrupt request. 2 18 pie x pause interrupt enable x. piex enables the eqadc to generate an interrupt request when the corresponding eqadc_fisr[pfx] is asserted. 1 enable pause interrupt request. 0 disable pause interrupt request.
enhanced queued analog-to-digital converter (eqadc) 27-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 3 19 eoqie x end of queue interrupt enable x. eoqiex enables th e eqadc to generate an interrupt request when the corresponding eqadc_fisr[eoqfx] is asserted. 0 disable end of queue interrupt request. 1 enable end of queue interrupt request. 4 20 cfuie x cfifo underflow interrupt enable x. cfuiex enables the eqadc to generate an interrupt request when the corresponding eqadc_fisr[cfufx] is asserted. apart from generating an independent interrupt request for a cfifox underflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt reques t is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 27.7.8, eqadc dma/interrupt request , for details. 0 disable underflow interrupt request. 1 enable underflow interrupt request. 5 21 reserved 6 22 cffex cfifo fill enable x. cffex enables t he eqadc to generate an interrupt request (cffsx is asserted) or dma request (cffsx is negated) when eqadc_fisr[cfffx] is asserted. 0 disable cfifo fill dma or interrupt request. 1 enable cfifo fill dma or interrupt request. note: cffex must not be negated while a dma transaction is in progress. 7 23 cffsx cfifo fill select x. cffsx selects if a dma or interrupt request is generated when eqadc_fisr[cfffx] is asserted. if cffex is asserted, the eqadc generates an interrupt request when cffsx is negated, or it generates a dma request if cffsx is asserted. 0 generate interrupt request to move dat a from the system memory to cfifox. 1 generate dma request to move data from the system memory to cfifox. note: cffsx must not be negated while a dma transaction is in progress. 8?11 24?27 reserved 12 28 rfoie x rfifo overflow interrupt enable x. rfoiex enables the eqadc to generate an interrupt request when the corresponding eqadc_fisr[rfofx] is asserted. apart from generating an independent interrupt request for an rfifox overflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt reques t is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 27.7.8, eqadc dma/interrupt request , for details. 0 disable overflow interrupt request. 1 enable overflow interrupt request. 13 29 reserved table 27-11. eqadc_idcr field description (continued) field description
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-25 pxr40 microcontroller reference manual, rev. 1 27.6.2.7 eqadc fifo and interrupt status registers (eqadc_fisr) the eqadc fifo and interrupt status registers (eqa dc_fisr) contain flag and status bits for each cfifo and rfifo pair. write ?1? to a flag bit to clear it. writing ?0? has no effect. status bits are read only. these bits indicate the st atus of the fifo itself. 14 30 rfde x rfifo drain enable x. rfdex enables the eqadc to gener ate an interrupt request (rfdsx is asserted) or dma request (rfdsx is negated) when eqadc_fisr[rfdfx] is asserted. 0 disable rfifo drain dma or interrupt request. 1 enable rfifo drain dma or interrupt request. note: rfdex must not be negated while a dma transaction is in progress. 14 31 rfds x rfifo drain select x. rfdsx select s if a dma or interrupt request is generated when eqadc_fisr[rfdfx] is asserted. if rfdex is asserted, the eqadc generates an interrupt request when rfdsx is negated, or it generates a dma request when rfdsx is asserted. 0 generate interrupt request to move data from rfifox to the system memory. 1 generate dma request to move data fr om rfifox to the system memory. note: rfdsx must not be negated while a dma transaction is in progress. address: 0x0070, 0x0074, 0x0078, 0x007c, 0x0080, 0x0084 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ncfx torfx pfx eoqfx cfufx sssx cfffx 0 0000 rfofx 0 rfdfx 0 w reset0 0 0 0 0 0 1 0 0000 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfctrx tnxtptrx rfctrx popnxtptrx w reset0 0 0 0 0 0 0 0 0000 0 0 0 0 figure 27-11. eqadc fifo and interrupt status register x (eqadc_fisrx) table 27-11. eqadc_idcr field description (continued) field description
enhanced queued analog-to-digital converter (eqadc) 27-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 27-12. eqadc_fisrx field description field description 0 ncfx non-coherency flag. ncfx is set whenever a command sequence being transferred through cfifox becomes non coherent. if eqadc_idcr[nciex] and ncf x are asserted, an interrupt request will be generated. write ?1? to clear ncfx. writing a ?0? has no ef fect. for more information refer to section 27.7.4.7.5, command sequence non-coherency detection . 0 command sequence being transferred by cfifox is coherent. 1 command sequence being transferred by cfifox became non-coherent. 1 torfx trigger overrun flag for cfifox. torfx is set when trigger overrun occurs for the specified cfifo in edge or level trigger mode. trigger overrun occurs when an alr eady triggered cfifo receives an additional trigger. when eqadc_idcr[torie x ] and torf x are asserted, an interrupt request will be generated. apart from generating an independent interrupt request fo r a cfifox trigger overrun event, the eqadc also provides a combined interrupt at which the result fi fo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun inte rrupt requests of all cfif os are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interr upt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 27.7.8, eqadc dma/interrupt request , for details. write ?1? to clear the torf x bit. writing a ?0? has no effect. 0 no trigger overrun occurred. 1 trigger overrun occurred. note: the trigger overrun flag will not set for cfif os configured for software trigger mode. 2 pfx pause flag x. pf behavior changes according to the cfif o trigger mode. in edge trigger mode, pfx is set when the eqadc completes the transfer of an entry with an asse rted pause bit from cfifox. in level trigger mode, when cfifox is in triggered status, pfx is set when cfif o status changes from trigge red due to the detection of a closed gate. an interrupt routine, generated due to the asserted pf, can be used to verify if a complete scan of the cqueue was performed. if a closed gate is detected while no command transfers are taking place, it will have immediate effect on the cfifo status. if a closed gate is detected while a command transfer to an on-chip cbuffer is taking place, it will only af fect the cfifo stat us when the transfer completes. the transfer of entries bound for the on-chip adcs is considered complete d when they are stored in the appropriate cbuffer. if eqadc_idcr[pie x ] and pfx are asserted, an interrupt will be generated. write ?1? to clear the pf x . writing a ?0? has no effect. refer to section 27.7.4.7.3, pause status , for more information on the pause flag. 0 entry with asserted pause bit was not transferred from cfifox (cfifo in edge trigge r mode), or cfifo status did not change from triggered due to detection of a closed gate (cfifo in level trigger mode). 1 entry with asserted pause bit was transferred from cfif ox (cfifo in edge trigger mode), or cfifo status changes from triggered due to detection of a closed gate (cfifo in level trigger mode). note: in edge trigger mode, an asserted pfx only implies t hat the eqadc has finished transferring a command with an asserted pause bit from cfifox. it does not impl y that result data for the current command and for all previously transferred commands ha s been returned to the appropriate rfifo. note: in software or level trigger mode, when the eqadc comp letes the transfer of an ent ry from cfifox with an asserted pause bit, pfx will not be set and tr ansfer of commands will continue without pausing.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-27 pxr40 microcontroller reference manual, rev. 1 3 eoqfx end of queue flag x. eoqfx indicates t hat an entry with an asserted eoq bit was transferred from cfifox to the on-chip adcs - see section 27.7.2.2, message format in eqadc , for details about command message formats. when the eqadc completes the transfer of an entry with an asserted eoq bit from cfifox, eoqfx will be set. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer. if the eqadc_idcr[eoqiex] and eoqfx are asserted, an inte rrupt will be generated. write ?1? to clear the eoqfx bit. writing a ?0? has no effect. refer to section 27.7.4.7.2, cqueue completion status , for more information on the end of queue flag. 1 entry with asserted eoq bit was transferred from cfifox. 0 entry with asserted eoq bit was not transferred from cfifox. note: an asserted eoqfx only implies t hat the eqadc has finished transferring a command with an asserted eoq bit from cfifox. it does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate rfifo. 4 cfufx cfifo underflow flag x. cfufx indicate s an underflow event on cfifox. cfufx is set when cfifox is in triggered state and it becomes empty. no commands will be transferred from an underflowing cfifo, nor will command transfers from lower priority cfifos be blocked. when eqadc_idcr[cfuiex] and cfufx are both asserted, the eqadc generates an interrupt request. apart from generating an independent interrupt request for a cfifox underflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt reques t is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 27.7.8, eqadc dma/interrupt request , for details. write ?1? to clear cfufx. writing a ?0? has no effect. 0 no cfifo underflow event occurred. 1 a cfifo underflow event occurred. 5 sssx cfifo single-scan status bit x. an asserted sssx bit enables the detection of trigger events for cfifos programmed into single-scan level- or edge-trigger mode, and works as trigger for cfifos programmed into single-scan software-trigger mode. refer to section 27.7.4.6.2, single-scan mode , for further details. the sssx bit is set by writing a ?1? to eqadc_cfcr[ssex] . the eqadc clears the sssx bi t when a command with an asserted eoq bit is transferred from a cfifo in single- scan mode, when a cfifo is in single-scan level-trigger mode and its status changes from trigg ered due to the detection of a closed gate, or when the value of the cfifo operation mode (eqadc _cfcr[modex]) is changed to disabled. writing to sssx has no effect. sssx has no effect in continuous-scan or in disabled mode. 0 cfifo in single-scan level- or edge-trigger mode wi ll ignore trigger events, or cfifo in single-scan software-trigger mode is not triggered. 1 cfifo in single-scan level- or edge-trigger mode will detect a trigger event, or cfifo in single-scan software-trigger mode is triggered. table 27-12. eqadc_fisrx fi eld description (continued) field description
enhanced queued analog-to-digital converter (eqadc) 27-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 6 cfffx cfifo fill fl ag x. cfffx is set when the cfifox is no t full. when eqadc_idcr[cffe x ] and cfffx are both asserted, an interrupt or a dma request will be generated depending on the status of the cffsx bit. when cffsx is negated (interrupt requests selected), software clears cf ffx by writing a ?1? to it. writing a ?0? has no effect. when cffsx is asserted (dma reques ts selected), cfffx is automatically cleared by the eqadc when the cfifo becomes full. 0 cfifox is full. 1 cfifox is not full. note: writing ?1? to cfffx when cffsx is assert ed (dma requests selected) is not allowed. note: when generation of interrupt requests is selected (cff sx=0), cfffx must only be cleared in the isr after the cfifox push regi ster is accessed. 7?11 reserved 12 rfofx rfifo overflow flag x. rfofx indicates an overflow event on rfifox. rfof x is set when rfifox is already full, and a new data is received from the on- chip adcs. the rfifox will not overwrite older data in the rfifo, and the new data will be ignored. when eqadc_idcr[rfoiex] and rfofx are both asserted, the eqadc generates an interrupt request. apart from generating an independent interrupt request for an rfifox overflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt reques t is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 27.7.8, eqadc dma/interrupt request , for details. write ?1? to clear rfofx. writing a ?0? has no effect. 0 no rfifo overflow event occurred. 1 an rfifo overflow event occurred. 13 reserved 14 rfdf x rfifo drain flag x. rfdfx in dicates if rfifox has valid entries or not. rfdfx is set when the rfifox has at least one valid entry in it. when eqadc_idcr[rfdex] and rfdfx are both asserted, an interrupt or a dma request will be generated depending on the status of th e rfdsx bit. when rfdsx is negated (interrupt requests selected), software clears rfdfx by writing a ?1? to it . writing a ?0? has no effect. when rfdsx is asserted (dma requests selected), rfdfx is automatically cleared by the eq adc when the rfifo becomes empty. 0 rfifox is empty. 1 rfifox has at least one valid entry. note: writing ?1? to rfdfx when rfdsx is assert ed (dma requests selected) is not allowed. note: when the generation of interrupt requests is selected (rfdsx=0), rfdfx must only be cleared in the isr after the rfifox pop register is accessed. 15 reserved 16?19 cfctrx cfifox entry counter. cfctrx indi cates the number of commands stor ed in the cfifox. when the eqadc completes transferring a piece of new data from the cfif ox, it decrements cfctrx by one. writing a word or any bytes to the corresponding eqadc_cfpr increments cfct rx by one. writing any value to cfctrx has no effect. table 27-12. eqadc_fisrx fi eld description (continued) field description
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-29 pxr40 microcontroller reference manual, rev. 1 27.6.2.8 eqadc cfifo transfer c ounter registers (eqadc_cftcr) the eqadc cfifo transfer counter registers (e qadc_cftcr) record the number of commands transferred from a cfifo. the eqadc_cftcr suppor ts the monitoring of command transfers from a cfifo. 20?23 tnxtptrx cfifox transfer next pointer. tnxtpt rx indicates the index of the next entry to be removed from cfifox when it completes a transfer. when tnxtptrx is zero, it poi nts to the entry wit h the smallest memory-mapped address inside cfifox. tnxtptrx is only updated when a command tr ansfer is completed. if the maximum index number (cfifo depth minus one) is reached, tnxtptrx is wrapped to zero, else, it is incremented by one. for details refer to section 27.7.4.1, cfif o basic functionality . writing any value to tnxtptrx has no effect. 24?27 rfctrx rfifox entry counter. rfctrx indica tes the number of data items stor ed in the rfifox. when the eqadc stores a piece of new data into rfifox , it increments rfctrx by one. reading the whole word, half-word or any bytes of the corresponding eqadc_rfpr decrements rfctrx by one. writin g any value to rfctrx itself has no effect. 28?31 popnxt ptrx rfifox pop next pointer. popnxt ptrx indicates the index of the entry that will be returned when eqadc_rfprx is read. when popnxtptrx is zero, it points to the entry with the smallest memory-mapped address inside rfifox. popnxtptrx is updated when eq adc_rfprx is read. if the maximum index number (rfifo depth minus one) is reached, popnxtptrx is wrapped to zero, else, it is incremented by one. for details refer to section 27.7.5.1, rfif o basic functionality . writing any value to popnxtptrx has no effect. address: 0x0090 access: user read/write 0123456789101112131415 r00000 tc_cf0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 tc_cf1 w reset0000000000000000 figure 27-12. eqadc cfifo transfer counter register 0 (eqadc_cftcr0) address: 0x0094 access: user read/write 0123456789101112131415 r00000 tc_cf2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 tc_cf3 w reset0000000000000000 figure 27-13. eqadc cfifo transfer counter register 1 (eqadc_cftcr1) table 27-12. eqadc_fisrx fi eld description (continued) field description
enhanced queued analog-to-digital converter (eqadc) 27-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.2.9 eqadc cfifo status snap shot registers (eqadc_cfssr) the eqadc cfifo status snapshot registers (eq adc_cfssr) contain status fields to track the operation status of each cfifo and th e transfer counter of the last cfif o to initiate a command transfer to the internal cbuffers. eqadc_cf ssr0-1 are related to the on-chip cb uffers (cbuffer0-1). all fields of a particular eqadc_cfssr regi ster are captured at the beginni ng of a command transfer to the cbuffer associated with that register . note that captured status register values are associat ed with previous command transfer. this means that the cfssr register s capture the status regi sters before the status registers change because of the tran sfer of the current comm and that is about to be popped from the cfifo. the eqadc_cfssr registers are read only. writi ng to the eqadc_cfssr re gisters has no effect. address: 0x0098 access: user read/write 0123456789101112131415 r00000 tc_cf4 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 tc_cf5 w reset0000000000000000 figure 27-14. eqadc cfifo transfer counter register 2 (eqadc_cftcr2) table 27-13. eqadc_cftcrx field descriptions field description 0?4 16?20 reserved 5?15 21?31 tc_cfx transfer counter for cfifox. tc_cfx counts the number of commands which have been completely transferred from cfifox. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer. the eqadc increments the tc_cfx value by one after a command is transferred. tc_cfx resets to zero after eqadc completes transferring a comm and with an asserted eoq bit. writing any value to tc_cfx sets the counter to that written value. note: if cfifox is in triggered state when its modex fiel d is programmed to disabled, the exact number of entries transferred from the cfifo unt il that point - tc_cfx - is only known after the cfifo status changes to idle, as indicated by cfsx. for details refer to section 27.7.4.6.1, disabled mode .
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-31 pxr40 microcontroller reference manual, rev. 1 address: 0x00a0 access: user read/write 0123456789101112131415 rcfs0_tcb0cfs1_tcb0cfs2_tcb0cfs3_tcb0cfs4_tcb0cfs5_tcb00000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 lcftcb0 tc_lcftcb0 w reset0111100000000000 figure 27-15. eqadc cfifo status snapshot register 0 (eqadc_cfssr0) address: 0x00a4 access: user read/write 0123456789101112131415 rcfs0_tcb1cfs1_tcb1cfs2_tcb1cfs3_tcb1cfs4_tcb1cfs5_tcb10000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 lcftcb1 tc_lcftcb1 w reset0111100000000000 figure 27-16. eqadc cfifo status snapshot register 1 (eqadc_cfssr1) table 27-14. eqadc_cfssrx field descriptions field description 0?11 cfsx_tcb n cfifo status at transfer to cbuffer n (n=0,1). cfsx_tcb n indicates the cfifox status of previously completed command transfer. cfsx_tcb n is a copy of the corresponding cfsx in the section 27.6.2.10, eqadc cfifo status re gister (eqadc_cfsr) , captured at the time a current command transfer to cbuffer n is initiated. 12?16 reserved
enhanced queued analog-to-digital converter (eqadc) 27-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.2.10 eqadc cfifo status register (eqadc_cfsr) the eqadc cfifo status register (eqadc_cfsr ) contains the current cfifo status. the eqadc_cfsr registers is read only. writing to the eqadc_cfsr register has no effect. 17?20 lcftcb n last cfifo to transfer to cbuffer n (n=0,1). lcftcb n holds the cfifo number to have completed a previous command transfer to cbuffer n . 0000 last command was transferred from cfifo0 0001 last command was transferred from cfifo1 0010 last command was transferred from cfifo2 0011 last command was transferred from cfifo3 0100 last command was transferred from cfifo4 0101 last command was transferred from cfifo5 0110?1110 reserved 1111 no command was transferred to cbuffer n 21?31 tc_lcftcb n transfer counter for last cfifo to transfer commands to cbuffer n. tc_lcftcb n indicates the number of commands which have been completely transferred from cfifox when a current command transfer from cfifox to cbuffer n is initiated. tc_lcftcb n is a copy of the corresponding tc_cfx in the section 27.6.2.8, eqadc cfifo transfer counter registers (eqadc_cftcr) , captured at the time a current command transfer from cfifox to cbuffer n is initiated. this field has no meaning when lcftcb n is 0b1111. address: 0x00ac access: user read only 0123456789101112131415 rcfs0 cfs1 cfs2 cfs3 cfs4 cfs5 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 27-17. eqadc cfifo status register (eqadc_cfsr) table 27-14. eqadc_cfssrx fiel d descriptions (continued) field description
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-33 pxr40 microcontroller reference manual, rev. 1 27.6.2.11 eqadc red line client configurati on register (eqadc_redlccr) the eqadc red line client confi guration register (eqad c_redlccr) contains bi ts used to control which stac bus server data slot the eqadc selects to apply an exte rnal timestamp from either etpu module to an adc sample. two server data slots are specified in the eqadc_redlccr register, and which is used is specified in the on-chip adc0/1 contro l registers, see section 27.6.3.1, adc0/1 control registers (adc0_cr and adc1_cr) . the register also allows selectio n of which 16 bits are used from the 24 bit external time base value. the serv er and bit selection ap plies to both adc0/1. figure 27-18. eqadc red line client configuration register (eqadc_redlccr) table 27-15. eqadc_cfsr field descriptions field description 0?11 cfsx cfifo status. cfsx indicates t he current status of cfifox. 00 idle: cfifo is disabled. cfifo is in single-scan edge or level trigger mode and does not have sss asserted. eqadc completed the transfer of the last entry of the cqueue in single-scan mode. 01 reserved 10 waiting for trigger: cfifo mode is modified to continuous-scan edge or level trigger mode. cfifo mode is modified to single-scan edge or level trigger mode and sss is asserted. cfifo mode is modified to single-scan software trigger mode and sss is negated. cfifo is paused. eqadc transferred the last entry of the queue in continuous-scan edge trigger mode. 11 triggered: cfifo is triggered. 12?31 reserved address: eqadc_base+0x0d0 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r redbs2 srv2 redbs1 srv1 w reset0000000000000000
enhanced queued analog-to-digital converter (eqadc) 27-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.2.12 eqadc cfifo registers (eqa dc_cfxrw) (x=0, ..,5; w=0, .., 3) the eqadc cfifo registers (eqadc_cf xrw) (x=0, .., 5; w=0, .., 3) provide visibility of the contents of a cfifo for debugging purposes. e ach cfifo has four registers which are uniquely mapped to its four 32-bit entries. refer to section 27.7.4, eqadc command fifos , for more information on cfifos. these registers are read only. data writ ten to these registers is ignored. table 27-16. eqadc_redl ccr field descriptions field description 0?15 reserved 16?19 24?27 redbs m red line timebase bits selection m ( m =1,2)?selects 16 bits from the total of 24 bits that are received from the red line interface as desc ribed in below. consi der tbasem[0:23] the sele cted time base from slot srvm: 20?23 28?31 srv m red line server data slot selector m ( m =1,2)?indicates the slot number that contains the desired time base value sent by the red line server. this value selects which etpu timebase on the stac bus is used to timestamp an adc sample. redbs m [0:3] selected bits 0b0000 tbase m [0:15] 0b0001 tbase m [1:16] 0b0010 tbase m [2:17] 0b0011 tbase m [3:18] 0b0100 tbase m [4:19] 0b0101 tbase m [5:20] 0b0110 tbase m [6:21] 0b0111 tbase m [7:22] 0b1000 tbase m [8:23] others reserved srv m [0:3] etpu timebase 0b0000 etpua tcr1 0b0001 etpub tcr1 0b0010 etpua tcr2 0b0011 etpub tcr2 0b0100 - 0b1111 reserved
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-35 pxr40 microcontroller reference manual, rev. 1 address: 0x0100, 0x0104, 0x0108, 01010c access: user read only 0123456789101112131415 rcfifo0_dataw w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcfifo0_dataw w reset0000000000000000 figure 27-19. eqadc cfifo0 registers (eqadc_cf0rw) (w=0, .., 3) address: 0x0140, 0x0144, 0x0148, 01014c access: user read only 0123456789101112131415 rcfifo0_dataw w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcfifo0_dataw w reset0000000000000000 figure 27-20. eqadc cfifo1 registers (eqadc_cf1rw) (w=0, .., 3) address: 0x0180, 0x0184, 0x0188, 01018c access: user read only 0123456789101112131415 rcfifo2_dataw w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcfifo2_dataw w reset0000000000000000 figure 27-21. eqadc cfifo2 registers (eqadc_cf2rw) (w=0, .., 3)
enhanced queued analog-to-digital converter (eqadc) 27-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 address: 0x01c0, 0x01c4, 0x01c8, 0101cc access: user read only 0123456789101112131415 rcfifo3_dataw w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcfifo3_dataw w reset0000000000000000 figure 27-22. eqadc cfifo3 registers (eqadc_cf3rw) (w=0, .., 3) address: 0x0200, 0x0204, 0x0208, 01020c access: user read only 0123456789101112131415 rcfifo4_dataw w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcfifo4_dataw w reset0000000000000000 figure 27-23. eqadc cfifo4 registers (eqadc_cf4rw) (w=0, .., 3) address: 0x0240, 0x0244, 0x0248, 01024c access: user read only 0123456789101112131415 rcfifo5_dataw w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcfifo5_dataw w reset0000000000000000 figure 27-24. eqadc cfifo5 registers (eqadc_cf5rw) (w=0, .., 3)
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-37 pxr40 microcontroller reference manual, rev. 1 27.6.2.13 eqadc cfifo0 extension regi sters (eqadc_cf0erw) (w=0, .., 3) the eqadc cfifo0 extension regi sters (eqadc_cf0erw) (w=0, .., 3) provide visibility of the contents of the extended portion of cfifo0 for de bugging purposes. there are f our registers which are uniquely mapped to its four 32-bit entries. refer to section 27.7.4, eqadc command fifos , for more information on cfifos. these registers are read onl y. data written to these registers is ignored. 27.6.2.14 eqadc rfifo registers (eqadc _rfxrw) (x=0, .., 5; w=0, .., 3) the eqadc rfifo registers (eqadc_rf xrw) (x=0, .., 5; w=0, .., 3) provide visibility of the contents of a rfifo for debugging purposes. e ach rfifo has four registers which are uniquely mapped to its four 16-bit entries. refer to section 27.7.5, eqadc result fifos , for more information on rfifos. these registers are read only. data writ ten to these registers is ignored. table 27-17. eqadc_cfxrw field description field description 0?31 cfifox_dataw[ cfifox data w (w = 0, .., 3). reading cfifox_dataw returns the value stored on the w th entry of cfifox. each cfifo is composed of four 32 -bit entries, with register 0 being mapped to the one with the smallest memory mapped address. address: 0x0110, 0x0114, 0x0118, 01011c access: user read only 0123456789101112131415 r cfifo0_edataw w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo0_edataw w reset0000000000000000 figure 27-25. eqadc cfifo0 extension registers (eqadc_cf0erw) (w=0, .., 3) table 27-18. eqadc_cf0erw field description field description 0?31 cfifo0_edataw cfifox extension data w (w = 0, .., 3). reading cfifo0_edataw returns the value stored on the w th entry of cfifo0?s extended portion.
enhanced queued analog-to-digital converter (eqadc) 27-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 address: 0x0300, 0x0304, 0x0308, 01030c access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrfifo0_dataw w reset0000000000000000 figure 27-26. eqadc rfifo0 registers (eqadc_rf0rw) (w=0, .., 3) address: 0x0340, 0x0344, 0x0348, 01034c access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrfifo1_dataw w reset0000000000000000 figure 27-27. eqadc rfifo1 registers (eqadc_rf0rw) (w=0, .., 3) address: 0x0380, 0x0384, 0x0388, 01038c access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrfifo2_dataw w reset0000000000000000 figure 27-28. eqadc rfifo2 registers (eqadc_rf0rw) (w=0, .., 3)
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-39 pxr40 microcontroller reference manual, rev. 1 address: 0x0380, 0x0384, 0x0388, 01038c access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrfifo2_dataw w reset0000000000000000 figure 27-29. eqadc rfifo2 registers (eqadc_rf0rw) (w=0, .., 3) address: 0x03c0, 0x03c4, 0x03c8, 0103cc access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrfifo3_dataw w reset0000000000000000 figure 27-30. eqadc rfifo3 registers (eqadc_rf0rw) (w=0, .., 3) address: 0x0400, 0x0404, 0x0408, 01040c access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrfifo4_dataw w reset0000000000000000 figure 27-31. eqadc rfifo4 registers (eqadc_rf0rw) (w=0, .., 3)
enhanced queued analog-to-digital converter (eqadc) 27-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.3 on-chip adc registers this section describes a list of registers that c ontrol on-chip adc operation. the adc registers are not part of the cpu accessible memo ry map. these registers can only be accessed indirectly through configuration commands. ther e are a set of non-memory mapped regist ers per adc, plus a set of registers shared by both adcs. the address, usage, and a ccess privilege of each register is shown in table 27-20 . data written to or read from reserved areas of the memory map is undefined. their assigned addresses are the values used to set the adc_reg_ address field of the read/write configurations commands bound for the on-chip adcs. these are half-word addresses. further, the following restrictions apply when accessing these registers: ? registers adc0_cr, adc0_gccr, adc0_o ccr, adc0_agr1/2 and adc0_aor1/2 can only be accessed by configurati on commands sent to cbuffer0. ? registers adc1_cr, adc1_gccr, adc1_o ccr, adc1_agr1/2 and adc1_aor1/2 can only be accessed by configurati on commands sent to cbuffer1. ? registers adc_tscr, adc_tbcr, adc_acr1- 8 and adc_pudcr0-7 can be accessed by configuration commands sent to cb uffer0 or to cbuffer1. a data write to any of these registers through a configuration command sent to cbuffer0 will write the same memory location as when writing to it through a configurat ion command sent to cbuffer1. note simultaneous write accesses from cbu ffer0 and cbuffer1 to any of the shared registers are not allowed. address: 0x0440, 0x0444, 0x0448, 01044c access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrfifo5_dataw w reset0000000000000000 figure 27-32. eqadc rfifo5 registers (eqadc_rf0rw) (w=0, .., 3) table 27-19. eqadc_cfxr w field descriptions field description 0?15 reserved 16?31 rfifox_dataw rfifox data w (w = 0, .., 3). reading rfif ox_dataw returns the value stored on the w th entry of rfifox. each rfifo is composed of four 16-bit en tries, with register 0 being mapped to the one with the smallest memory mapped address.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-41 pxr40 microcontroller reference manual, rev. 1 table 27-20. on-chip adc memory map adc address use access 0x00 adc0/adc1 1 conversion command for standard configuration (see conversion command format for the standard configuration ) write 0x01 adc0/adc1 configuration control register (adc0_cr, adc1_cr) write/read 0x02 time stamp control re gister (adc_tscr) write/read 0x03 time base counter register (adc_tbcr) write/read 0x04 adc0/adc1 gain calibration constant register (adc0_gccr, adc1_gccr) write/read 0x05 adc0/adc1 offset calibration constant register (adc0_occr, adc1_occr) write/read 0x06? 0x07 reserved ? 0x08 adc0/adc1 conversion command fo r alternate configuration 1 (see conversion command format for alternate configurations ) write 0x09 adc0/adc1 conversion command fo r alternate configuration 2 (see conversion command format for alternate configurations ) write 0x0a adc0/adc1 conversion command for alternate configuration 3 (see conversion command format for alternate configurations ) write 0x0b adc0/adc1 conversion command for alternate configuration 4 (see conversion command format for alternate configurations ) write 0x0c adc0/adc1 conversion command fo r alternate configuration 5 (see conversion command format for alternate configurations ) write 0x0d adc0/adc1 conversion command fo r alternate configuration 6 (see conversion command format for alternate configurations ) write 0x0e adc0/adc1 conversion command for alternate configuration 7 (see conversion command format for alternate configurations ) write 0x0f adc0/adc1 conversion command for alternate configuration 8 (see conversion command format for alternate configurations ) write 0x10?0x2f reserved ? 0x30 alternate configuration 1 control register (adc_acr1) write/read 0x31 adc0/adc1 alternate gain 1 regist er (adc0_agr1, adc1_agr1) write/read 0x32 adc0/adc1 alternate offset 1 regi ster (adc0_aor1, adc1_aor1) write/read 0x33 reserved ? 0x34 alternate configuration 2 control register (adc_acr2) write/read 0x35 adc0/adc1 alternate gain 2 regist er (adc0_agr2, adc1_agr2) write/read 0x36 adc0/adc1 alternate offset 2 regi ster (adc0_aor2, adc1_aor2) write/read 0x37 reserved ? 0x38 alternate configuration 3 control register (adc_acr3) write/read 0x39 reserved ? 0x3a reserved ? 0x3b reserved ?
enhanced queued analog-to-digital converter (eqadc) 27-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.3.1 adc0/1 control regi sters (adc0_cr and adc1_cr) the adc0/1 control registers (adc0/1_c r) is used to define the standa rd configuration of the adc. in the standard configuration, the para meters contained in the alternat e configuration control registers (adc_acr1-8) are fixed at their reset value. a conve rsion uses the standard configuration when the 0x3c alternate configuration 4 control register (adc_acr4) write/read 0x3d reserved ? 0x3e reserved ? 0x3f reserved ? 0x40 alternate configuration 5 control register (adc_acr5) write/read 0x41 reserved ? 0x42 reserved ? 0x43 reserved ? 0x44 alternate configuration 6 control register (adc_acr6) write/read 0x45 reserved ? 0x46 reserved ? 0x47 reserved ? 0x48 alternate configuration 7 control register (adc_acr7) write/read 0x49 reserved ? 0x4a reserved ? 0x4b reserved ? 0x4c alternate configuration 8 control register (adc_acr8) write/read 0x4d?0x6f reserved ? 0x70 pull up/down control register0 (adc_pudcr0) write/read 0x71 pull up/down control register1 (adc_pudcr1) write/read 0x72 pull up/down control register2 (adc_pudcr2) write/read 0x73 pull up/down control register3 (adc_pudcr3) write/read 0x74 pull up/down control register4 (adc_pudcr4) write/read 0x75 pull up/down control register5 (adc_pudcr5) write/read 0x76 pull up/down control register6 (adc_pudcr6) write/read 0x77 pull up/down control register7 (adc_pudcr7) write/read 0x78?0x97 reserved for adc_pudcr8 to adc_pudcr39 ? 0x98?0xff reserved ? notes: 1 throughout the table, adc0/adc1 indicates that if the comm and is stored in cbuffer0 it will be applied to adc0 and if in cbuffer1 it applies to adc1. if this indication is omitted the register app lies for both adc0 and adc1, independent of the cbuffer used. table 27-20. on-chip adc memory map (continued)
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-43 pxr40 microcontroller reference manual, rev. 1 conversion command (with th e standard format) is written to a ddress 0x00 of the on-chip adc memory map. refer to conversion command format for the standard configuration . adc0 register address: 0x01 0123456789101112131415 r adc0 _en 000adc0 _em ux 00000adc0 _clk _ sel adc0_clk_ps w reset0000000000011111 adc1 register address: 0x01 0123456789101112131415 r adc1 _en 000adc1 _em ux 00000adc1 _clk _ sel adc1_clk_ps w reset0000000000011111 figure 27-33. adc0/1 cont rol registers (adc0/1_cr)
enhanced queued analog-to-digital converter (eqadc) 27-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 27-21. eqadc_cfxr w field descriptions field description 0 adc0/1_en enable bit for adc0/1. adc0/1_en enables adc0/1 to perform a/d conversions. refer to section 27.7.6.1, enabling and disabling the on-chip adcs , for details. 0 adc is disabled. clock supply to adc0/1 is stopped. 1 adc is enabled and ready to perform a/d conversions. note: the bias generator circuit inside the adc hard macro ceases functioning when both adc0_en and adc1_en bits are negated. note: conversion commands sent to the cbuffer of a disabled adc are ignored by the adc control hardware. note: when the adc0/1_en status is changed from assert ed to negated, the adc clock will not stop until it reaches its low phase. 1?3 reserved 4 adc0/1_emux external multiplexer enable for adc0/1. when adc0/ 1_emux is asserted, the ma pins will output digital values according to the number of the external chan nel being converted for selecting external multiplexer inputs. refer to section 27.7.7, internal/external multiplexing , for a detailed description about how adc0/1_emux affects channel number decoding. 0 external multiplexer disabled; no external multiplexer channels can be selected. 1 external multiplexer enabled; external multiplexer channels can be selected. note: both adc0 and adc1 of an eqadc module pair must be enabled before calibrating or using either adc0 or adc1 of the pair. failure to enable both a dc0 and adc1 of the pair can result in inaccurate conversions. note: both adc0/1_emux bits must not be asserted at the same time. note: the adc0/1_emux bit must only be written w hen the adc0/1_en bit is negated. adc0/1_emux can be set during the same wr ite cycle used to set adc0/1_en. 5?9 reserved 10 adc0/1_clk_sel clock selector for adc0/1. the adc0/1_clk_sel is used to select between the platform clock signal or the prescaler output signal. the prescaler provides the platform clock signal divided by a even factor from 2 to 64. this is required to permit the adc to run as fast as possible when the device is in low power active mode and platform clock is around 1 mhz. 0 prescaler output clock is selected. 1 platform clock is selected - maximum frequency. note: the adc0/1_clk_sel bits must only be wr itten when the adc0/1_en bit is negated. adc0/1_clk_sel can be set during the same write cycl e used to set adc0/1_en. 11?15 adc0/1_clk_ps clock prescaler field for adc0/1. the adc0/1_clk_ps field controls the platform clock divide factor for the adc0/1 clock as in table 27-22 . see section 27.7.6.2, adc clock and conversion speed, for details about how to set adc0/1_clk_ps. note: the adc0/1_clk_ps field must only be written wh en the adc0/1_en bit is negated. this field can be configured during the same write cycle used to set adc0/1_en.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-45 pxr40 microcontroller reference manual, rev. 1 table 27-22. platform clock divide factor for adc clock adc0/1_clk_ps[0:4] platform clock divide factor 0b00000 2 0b00001 4 0b00010 6 0b00011 8 0b00100 10 0b00101 12 0b00110 14 0b00111 16 0b01000 18 0b01001 20 0b01010 22 0b01011 24 0b01100 26 0b01101 28 0b01110 30 0b01111 32 0b10000 34 0b10001 36 0b10010 38 0b10011 40 0b10100 42 0b10101 44 0b10110 46 0b10111 48 0b11000 50 0b11001 52 0b11010 54 0b11011 56 0b11100 58 0b11101 60 0b11110 62 0b11111 64
enhanced queued analog-to-digital converter (eqadc) 27-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.3.2 adc time stamp control register (adc_tscr) the adc time stamp control register (adc_tscr) cont ains a platform clock divide factor used in the making of the time base counter clock. it dete rmines at what frequency the time base counter will run. adc_tscr can be accessed by configuration commands sent to cbuffer0 or to cbuffer1. a data write to adc_tscr through a configurat ion command sent to cbu ffer0 will write the same memory location as when writing to it through a conf iguration command sent to cbuffer1. note simultaneous write accesses from cbuffer0 and cbuffer1 to adc_tscr are not allowed. adc0/1 register address: 0x02 0123456789101112131415 r000000000000 tbc_clk_ps w reset0000000000000000 figure 27-34. adc time stamp control register (adc_tscr) table 27-23. adc_tscr field descriptions field description 0?11 reserved 12?15 tbc_clk_ps time base counter clock prescaler. the tbc_clk_ps field contains the platform clock divide factor for the time base counter. it controls the accuracy of the time stamp. the prescaler is disabled when tbc_clk_ps is set to 0b0000. table 27-24. clock divide factor for time stamp tbc_clk_ps[0:3] platform clock divide factor clock to time stamp counter for a 120 mhz platform clock (mhz) 0b0000 disabled disabled 0b0001 1 120 0b0010 2 60 0b0011 4 30 0b0100 6 20 0b0101 8 15 0b0110 10 12 0b0111 12 10 0b1000 16 7.5 0b1001 32 3.75 0b1010 64 1.88 0b1011 128 0.94 0b1100 256 0.47
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-47 pxr40 microcontroller reference manual, rev. 1 note if tbc_clk_ps is not set to disabled, it must not be changed to any other value besides disabled. if tbc_clk_ps is set to disabled it can be changed to any other value. 27.6.3.3 adc time base coun ter registers (adc_tbcr) the adc time base counter register (adc_tbcr) contains the current value of th e time base counter. adc_tbcr can be accessed by configur ation commands sent to cbuffer0 or to cbuffer1. a data write to adc_tbcr through a confi guration command sent to cbuffer0 will write the same memory location as when writing to it through a conf iguration command sent to cbuffer1. note simultaneous write accesses from cb uffer0 and cbuffe r1 to adc_tbcr are not allowed. 27.6.3.4 adc0/1 gain ca libration constant re gisters (adc0_gccr and adc1_gccr) the adc0/1 gain calibration consta nt register (adc0/1_gccr) contains the gain calibration constant used to fine-tune the adc0/1 conversion results. refer to section 27.7.6.6, adc calibration feature , for details about the calibration scheme used in the eqadc. 0b1101 512 0.23 0b1110 - 0b1111 reserved ? adc0/1 register address: 0x03 0123456789101112131415 r tbc_value w reset0000000000000000 figure 27-35. adc time base counter register (adc_tbcr) table 27-25. adc_tscr field descriptions field description 0?15 tbc_value time base counter value. the tbc_value field cont ains the current value of the time base counter. reading tbc_value returns the current value of time base counter. writes to tbc_value register load the written data to the counter. the time base counter counts from 0x0000 to 0xffff and wraps when reaching 0xffff. table 27-24. clock divide factor for time stamp (continued)
enhanced queued analog-to-digital converter (eqadc) 27-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.3.5 adc0/1 offset calibration constant re gisters (adc0_occr and adc1_occr) the adc0/1 offset calibration c onstant register (adc0/1_occr) contains the offset calibration constant used to fine-tune of adc0/1 conversion results. the offs et constant is a signed 14-bit integer value. refer to section 27.7.6.6, adc calibration feature , for details about the calibration scheme used in the eqadc. adc0 register address: 0x04 0123456789101112131415 r0 gcc0 w reset0100000000000000 adc1 register address: 0x04 0123456789101112131415 r0 gcc1 w reset0000000000000000 figure 27-36. adc0/1 gain calibrati on constant registers (adc0/1_gccr) table 27-26. adc0/1_gcc r field descriptions field description 0 reserved 1?14 gcc0/1 gain calibration constant for adc0/1. gcc0/1 contai ns the gain calibration constant used to fine-tune adc0/1 conversion results. it is a unsigned 15-bit fi xed pointed value. the gain calibration constant is an unsigned fixed point number expressed in the gcc_int .gcc_frac binary format. the integer part of the gain constant (gcc_int) contains a single binary di git while its fractional part (gcc_frac) contains fourteen digits. for details about the gcc data format refer to section 27.7.6.6.2, mac unit and operand data format . adc0 register address: 0x05 0123456789101112131415 r0 0 occ0 w reset0000000000000000 adc1 register address: 0x05 0123456789101112131415 r 0 0 occ1 w reset0000000000000000 figure 27-37. adc0/1 offset calibratio n constant regist ers (adc0/1_occr)
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-49 pxr40 microcontroller reference manual, rev. 1 27.6.3.6 alternate configuration 1-8 control registers (adc_acr1-8) the alternate configuration cont rol registers (adc_acr1-8) are us ed to configure the alternate configurations of the adc. there ar e 8 possible alternate configurations , each one associated with one of the adc_acr1-8 registers. all altern ate configurations shar e the same standard c onfiguration parameters from the adc0/1_cr registers, pl us additional configuration parame ters contained in the adc_acr1-8. a conversion uses one of the altern ate configurations when the conve rsion command (with the alternate configuration format) is written to an address in the range 0x08-0x0f of the on-chip adc memory map. refer to conversion command format for alternate configurations . table 27-27. adc0/1_occ r field descriptions field description 0?1 reserved 2?15 occ0/1 offset calibration constant of adc0/1. occ0/1 contains the offset calibration constant used to fine-tune adc0/1 conversion results. negative values shou ld be expressed using the two?s complement representation. adc0/1 register address: 0x30, 0x34, 0x38, 0x3c , 0x40, 0x44, 0x48, 0x4c access: user read only 0123456789101112131415 r ret_ inh 0 dest fmta 0 ressel 0000 pre_gain w reset0000000000000000 figure 27-38. alternate configurati on 1-8 control registers (adc_acr1-8)
enhanced queued analog-to-digital converter (eqadc) 27-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 27-28. adc_acr1-8 field descriptions field description 0 ret_inh result transfer inhibit / decimation filter pre-fill. this bit is used to inhibit the transfer of the result data from the peripheral module to the result queue. when th e module is a decimation filter, this bit sets the filter in a special mode (pre-fill) in which it does not generate decimated samples out from the conversion results received from the eqadc block, but the conversion samples are used by the filter algorithm. this feature allows a proper initializat ion of the decimation filt er without generating any decimated result. or this bit is useful for sending th e result of the adc to the stac bus master but not putting the result in the result queue. 0 result transfer to result queue / decimation filter in filtering mode 1 no result transfer to result queue / decimation filter pre-fill mode 1reserved 2?5 dest conversion result destination select ion. the dest[0:3] field selects the decimation filter destinations of the conversion result generated by the alternate conv ersion command. this field also affects the behavior of the fmta bit and the ffmt bit of the conver sion command for alternate configurations (see conversion command format for alternate configurations ). note: decimation filter h is only accessible from the cpu, and cannot be accessed by eqadc_b dest[0:3] description 0000 the conversion result is sent to the rfifos. the data format is specified by the ffmt bit in the conversion command. 0001 the conversion result is sent to decimation filter block a. 0010 the conversion result is sent to decimation filter block b. 0011 the conversion result is sent to decimation filter block c. 0100 the conversion result is sent to decimation filter block d. 0101 the conversion result is sent to decimation filter block e. 0110 the conversion result is sent to decimation filter block f. 0111 the conversion result is sent to decimation filter block g. 1000 the conversion result is sent to decimation filter blocks a and e. 1001 the conversion result is sent to decimation filter blocks b and e. 1010 the conversion result is sent to decimation filter blocks c and e. 1011 the conversion result is sent to decimation filter blocks d and e. 1100 the conversion result is sent to decimation filter blocks a and g. 1101 the conversion result is sent to decimation filter blocks b and g. 1110 the conversion result is sent to decimation filter blocks c and g. 1111 the conversion result is sent to decimation filter blocks d and g.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-51 pxr40 microcontroller reference manual, rev. 1 27.6.3.7 adc0/1 alternate gain registers (adc0_agr1-2 and adc1_agr1-2) the alternate gain registers (adc0_agrx and adc1_agrx, x=1-2) contain the gain calibration constants used to fine-tune the adc s conversion results for alternate configurations 1 or 2. a conversion from an adc uses the corresponding adc0_agrx or adc1_agrx register when the conversion command (with the alternate configur ation format) is written to an address in the range 0x08-0x09 of the on-chip adc memory map. refer to section 27.7.6.6, adc calibration feature , for details about the calibration scheme used in the eqadc. 6 fmta conversion data format for alternate configuration. if the dest field is not 0b000, the fmta bit specifies how the 12-bit conversion data returned by the adcs is formatted into the 16-bit data which is sent to the parallel side interface. 0 right justified unsigned 1 right justified signed 7reserved 8?9 ressel adc resolution selection. 00 adc set to 12-bits resolution 01 adc set to 10-bits resolution 10 adc set to 8-bits resolution 11 reserved 10?13 reserved 14?15 pre_gain adc pre-gain control. the pre_gain[0:1] controls the gain of the adc in put stage by changing the internal adc iterations in the gain stage. 00 x1 gain 01 x2 gain 10 x4 gain 11 reserved adc0 register address: 0x31, 0x35 0123456789101112131415 r0 altgcc0x w reset0100000000000000 adc1 register address: 0x31, 0x35 0123456789101112131415 r0 altgcc1x w reset0000000000000000 figure 27-39. adc0/1 alternate x gain register (adc0/1_agrx, x=1-2) table 27-28. adc_acr1-8 field descriptions (continued) field description
enhanced queued analog-to-digital converter (eqadc) 27-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.6.3.8 adc0/1 alternate offset regi ster (adc0_aor1-2 and adc1_aor1-2) the alternate offset registers (adc0_aorx and ad c1_aorx, x=1-2) contain the offset calibration constants used to fine-tune adcs conversion results for alternate c onfigurations 1 and 2. the offset constants are signed 14-bit integer values. refer to section 27.7.6.6, adc calibration feature , for details about the calibration sche me used in the eqadc. 27.6.3.9 adc pull up/down control register x (adc_pudcrx, x =0-7) the adc pull up/dow n control register x (adc_pudcr x ) contains configurati on bits for pull up and pull down resistors present at adc input channels x , x =0 to 7. table 27-29. adc0/1_agr x field de scriptions field description 0reserved 1?15 altgcc0/1x alternate gain calibration constant. altgcc0/1x[0:14] contain the gain calibration constants used to fine-tune adc0/1 conversion results for alternate conf igurations 1 and 2. the gain calibration constants are 15-bit unsigned fixed point numbers expressed in the gcc_int.gcc_frac binary format. the integer part of the gain constants (gcc_int) contain a single binary digit while their fractional part (gcc_frac) contain fourteen digits. for details about the gcc data format refer to section 27.7.6.6.2, mac unit and operand data format . adc0 register address: 0x32, 0x36 0123456789101112131415 r0 0 altocc0x w reset0000000000000000 adc1 register address: 0x31, 0x35 0123456789101112131415 r0 0 altocc1x w reset0000000000000000 figure 27-40. adc0/1 alternate x offset registers (adc0/1_aorx, x=1-2) table 27-30. adc0/1_aorx field descriptions field description 0?1 reserved 2?15 altocc0/1x alternate offset calibration const ant.altocc0/1x[0:13] contain the offset calibration constants used to fine-tune adcs conversion results for alternate configur ations 1 or 2. negative values should be expressed using the two?s complement representation.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-53 pxr40 microcontroller reference manual, rev. 1 27.7 functional description 27.7.1 overview the eqadc provides a parallel interface to two on-chip adcs and a pa rallel side interface to an on-chip companion module, like a decimation filter. the two on- chip adcs are architected to allow access to all the analog channels. initially, command data is contained in system memory in a user de fined data structure which is likely to be a queue as depicted in figure 27-2 1 . command data is moved between the cqueues and cfifos by the host cpu or by the dmac which re spond to interrupt and dma request s generated by the eqadc. the eqadc supports software and hardware triggers from other blocks or exte rnal pins to initiate transfers of commands from the multiple cf ifos to the on-chip adcs. adc0/1 register address: 0x 70?0x77 access: user read/write 0123456789101112131415 r0 0 ch_pull x 00 pull_str x 00000000 w reset0000000000000000 figure 27-41. adc pull up /down control register x (adc_pudcr x , x =0-7) table 27-31. adc_pudcr x field descriptions field description 0?1 reserved 2?3 ch_pullx channel x pull up/down control bits. the ch_pullx[0:1] field controls the pull up/down configuration of the channel x. 00 no pull resistors connected to the channel 01 pull up resistor connected to the channel 10 pull down resistor connected to the channel 11 pull up and pull down resistors connected to the channel 4?5 reserved 6?7 pull_strx pull up/down strength control bits of channel x. the pull_strx[0:1] bit field def ines the strength of the channel x pull up or down resistors. 00 reserved 01 200 kohm pull resistor 10 100 kohm pull resistor 11 5 kohm (approx.) pull resistor (not available for ch_pull_ x = 0b11) 8?15 reserved 1. command and result data can be stored in the system memory in any user defined data structure. however, in this document it will be assumed that the data st ructure of choice is a queue, since it is the most likely data structure to be used and because queues are the only type of data structure supported by the dmac.
enhanced queued analog-to-digital converter (eqadc) 27-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 cfifos can be configured in si ngle-scan or continuous-scan mode. when a cfifo is configured in single-scan mode, the eqadc scan s the cqueue one time. the eqad c stops transferring commands from the triggered cfif o after detecting the eoq bit set in the last transfer. af ter an eoq bit is detected, software involvement is required to rearm the cf ifo so that it can detect new trigger events. when a cfifo is configured for continuous-scan mode, the whole cque ue is scanned multiple times. after the detection of an asserted eoq bit in the la st command transfer, comma nd transfers can continue or not depending on the mode of operation of the cfifo. cfifo0 has a special configurati on option to allow a repetitive sequence of conversion commands (streaming mode) with high priority characteristics (abort operation) or not . this feature is useful with the immediate conversion command featur e that allows the immediate exec ution of a convers ion command or a sequence of commands with critical timing even with the possibility of abortion of some current adc conversion in progress. the aborted command is stored and executed again as soon as the critical timing commands have been finished. the multiple result fifos (rfifos) can receive data from the on-chip adcs or from an on-chip companion module (decimation filter). data from the on-chip adcs can be routed to the side interface, processed by the on-chip companion module (decimati on filter) and then routed back through the side interface to the rfifos. 27.7.2 data flow in eqadc 27.7.2.1 overview and basic terminology figure 27-42 shows how command data fl ows inside the eqadc system . a command message is the predefined format at which command data is stored in the cqueues. a comma nd message has 32 bits and is composed of two parts: a cf ifo header and an adc command. command messag es are moved from the cqueues to the cfifos by the host cpu or by the dmac as they respond to interrupt and dma requests generated by the eqadc. the eqadc generate s these requests whenever a cfifo is not full. the fifo control unit will only transfer to a cbuffer the adc command part of the command message. information in the cfifo header together with the upper bit of the adc command is used by the fifo control unit to arbitrate which triggered cfifo wi ll be transferring the next command.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-55 pxr40 microcontroller reference manual, rev. 1 figure 27-42. command flow during eqadc operation adc commands sent to the on-chip cb uffers are executed in a first-in-fir st-out basis with exception when the immediate conversion command func tion is enabled. three types of resu lts can be expected: data read from an adc register, a convers ion result, or a time stamp. note while the eqadc pops commands out fr om a cfifo, it also is checking the number of entries in the cfifo and generating requests to fill it. the process of pushing and popping comma nds to and from a cfifo can occur simultaneously. however, this is not true for cfifo0 when configured to operate in streaming mode for popping. the fifo control unit expects all incoming results to be shaped in a predefined re sult message format. figure 27-43 shows how result data flows inside the eq adc system. results generated on the on-chip adcs are adjusted considering the se lected resolution of the adc and ar e formatted into result messages inside the result format and calibration sub-block . this result message can be routed directly to one of the rfifos or to an on-chip compan ion module (decimation filter ) via the parallel side interface. after the data is processed by the companion module, it can be routed back to one of the rfifos via the side interface with the correct format. a result message is composed of an rfifo header and an adc result. the fifo control unit decodes the information c ontained in the rfifo header to determine the rfifo to which the adc result should be sent. once in an rfifo, the adc result is moved to the corresponding rqueue by the host cpu or by the dmac as they respond to interrupt and dma requests generated by the eqadc. the eqadc generates these requests whenever an rfifo has at least one entry. priority cfifox note: x=0, 1, 2, 3, 4, 5 32 bits cqueuey cbuffer inside eqadc fifo control to adcs command message cfifo header adc command host cpu or dmac 32 bits dma or interrupt requests adc y=0, 1, 2, 3, ... system memory dma transaction done signals unit abort cont
enhanced queued analog-to-digital converter (eqadc) 27-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note while conversion re sults are returned, the eq adc is checking the number of entries in the rfifo and generating requests to empty it . the process of pushing and popping adc results to and from an rfifo can occur simultaneously. figure 27-43. result flow during eqadc operation 27.7.2.2 message format in eqadc this section explains the command and result message formats used for on-chip adc operation. a command message is the predefined format at wh ich command data is stored in the cqueues. a command message has 32 bits and is composed of two parts: a cfifo header and an adc command. the size of the cfifo header is fixed to 6 bits, and it works as inputs to the fifo control unit . it controls when a cqueue ends, when it pauses, when a loop starts (only for cfifo0 in streaming mode), if commands are sent to internal or exte rnal buffers, and if it can abort a serial data transmission. information contained in the cfifo header, together with th e upper bit of the adc command is used by the fifo note: x=0, 1, 2, 3, 4, 5 inside eqadc host cpu or dmac adc y=0, 1, 2, 3, ... system memory decoder rqueue y rfifox 16 bits 16 bits result message rfifo header adc result dma or interrupt requests dma transaction done signals fifo control unit result format and calibration sub-block on-chip companion eqadc psi module resolution adjust
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-57 pxr40 microcontroller reference manual, rev. 1 control unit to arbitrate which triggered cfifo will tr ansfer the next command. adc commands are encoded inside the leas t significant 26 bits of the command message. a result message is com posed of an rfifo header and an adc result. the fifo control unit decodes the information contained in the rfifo header to determine the rfifo to which the adc result should be sent. an adc result is always 16 bits long. 27.7.2.2.1 message formats for on-chip adc operation this section describes the co mmand/result message formats used for on-chip adc operation. conversion command format for the standard configuration figure describes the format for conversion commands wh en interfacing with the on-chip adcs in the standard configuration. the standard configuration is selected when the least significant byte (bits 24-31) of the conversion command is set to zero. in the sta ndard configuration, the conversion result is always routed to one of the rfifos. a time stam p information can be optionally requested. conversion command format for the standard configuration 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r eoq pau s e rep reserved eb (0b0) bn cal message_tag lst tsr fmt w cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r channel_number 0 0 0 0 0 0 0 0 w adc command table 27-32. field descriptions field description 0 eoq end of queue bit. the eoq bit is asserted in the la st command of a cqueue to indicate to the eqadc that a scan of the cqueue is comple ted. eoq instructs the eqadc to reset its current cfifo transfer counter value (tc_cf) to zero. depending on the cfif o mode of operation, the cfifo status will also change upon the detection of an asserted eoq bit on the last transferred command - see section 27.7.4.6, cfifo scan trigger modes , for details. 0 not the last entry of the cqueue. 1 last entry of the cqueue. note: if both the pause and eoq bits are asserted in the same command message the respective flags are set, but the cfifo status changes as if only the eoq bit were asserted. 1 pau s e pause bit. the pause bit allows software to create sub-queues within a cqueue. when the eqadc completes the transfer of a command with an asse rted pause bit, the cfifo enters the waiting for trigger state. refer to section 27.7.4.7.1, cf ifo operation status , for a description of the state transitions. the pause bit is only valid when cfifo operation mode is configured to single or continuous-scan edge trigger mode. 0 do not enter waiting for trigger state afte r transfer of the current command message. 1 enter waiting for trigger state after tr ansfer of the current command message. note: if both the pause and eoq bits are asserted in the same command message the respective flags are set, but the cfifo status changes as if only the eoq bit were asserted.
enhanced queued analog-to-digital converter (eqadc) 27-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 2 rep repeat/loop start point indication bit. the rep bit is asserted in the command to indicate where is the start point of the sub-queue to be repeated when the streaming mode is enabled. the pause bit indicates the end point of the sub-qu eue. therefore, both can occur in the same command or in separated ones. if two or more rep bits are read before a pause bit, this is an error case and the intermediary rep bits are ignored. 0 it is not the start point of a loop. 1 indicates the start point of the sub-queue to be repeated. 3?4 reserved 5 eb external buffer bit. a negated eb bit indicates that the command is sent to an internal cbuffer. 0 command is sent to an internal buffer. 1 reserved. 6 bn buffer number bit. bn indicates which buffer the message will be stored in. 1 message stored in buffer 1. 0 message stored in buffer 0. 7 cal calibration bit. cal indicates if the retu rning conversion result must be calibrated. 1 calibrate conversion result. 0 do not calibrate conversion result. 8?11 message_tag message_tag field. the message_ tag allows the eqadc to sepa rate returning results into different rfifos. wh en the eqadc transfers a co mmand, the message_tag is in cluded as part of the command. eventually the on-chip adc returns the result with the same message_tag. the eqadc separates incoming messages into different rfifos by decoding the message_tag of the incoming data. 0000 result is sent to rfifo 0 0001 result is sent to rfifo 1 0010 result is sent to rfifo 2 0011 result is sent to rfifo 3 0100 result is sent to rfifo 4 0101 result is sent to rfifo 5 0110?0111 reserved 1000 null message received 1001 reserved for customer use (see note) 1010 reserved for customer use (see note) 1011?1111 reserved note: these messages are treated as null messages. 12?13 lst long sampling time. these two bits determine the duration of the sa mpling time in adc clock cycles. table 27-32. field descriptions (continued) field description lst[0:1] sampling cycles (adc clock cycles) 0b00 2 0b01 8 0b10 64 0b11 128
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-59 pxr40 microcontroller reference manual, rev. 1 conversion command format for alternate configurations figure 27-44 describes the format for conversion commands when interfacing with the on-chip adcs in one of the 8 alternate confi gurations. an alternate conf iguration is selected when the least significant byte (bits 24-31) of the conversion comm and is set to a value in the range 0x08-0x0f. each value in this range selects one of the 8 alternate conf iguration (0x08 selects alternate conf iguration 1, 0x0f selects alternate configuration 8). in the al ternate configurations, the conversion result can be rout ed to one of the rfifos or to the parallel side interface to communicate with an on-chip companion modul e (decimation filter). a bit field in the corresponding alternate configuration control register selects the internal rfifo or parallel side interface as the destination for th e conversion result. time stamp information can be optionally requested. note all fields, except ffmt and alt_conf ig_sel, are identical to the ones in the standard configuration format. only the fields which are different from the standard format will be described here. figure 27-44. conversion command fo rmat for alternate configurations 14 tsr time stamp request. tsr indicates the request for a time stamp. when tsr is asserted, the on-chip adc control logic returns a time stamp for the current conversion command after the conversion result is sent to the rfifos. see section 27.7.6.3, time stamp feature , for details. 0 return conversion result only. 1 return conversion time stamp after the conversion result. 15 fmt conversion data format. fmt specifies to the eqadc how to format the 12-bit conversion data returned by the adcs into the 16-bit format which is sent to the rfifos. see section , adc result format for on-chip adc operation , for details. 0 right justified unsigned. 1 right justified signed. 16?23 channel_ number channel number field. the channel_number field selects the analog input channel. the software programs this field with the channel number corresponding to the analog input pin to be sampled and converted. see section 27.7.7.1, channel assignment , for details. 24?31 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 eoq pau s e rep reserved eb (0b0) bn cal message_tag lst tsr ffmt cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 channel_number alt_config_sel adc command table 27-32. field descriptions (continued) field description
enhanced queued analog-to-digital converter (eqadc) 27-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 27-33. field descriptions field description 0 eoq end of queue bit. the eoq bit is asserted in the la st command of a cqueue to indicate to the eqadc that a scan of the cqueu e is completed. eoq instructs the eqadc to reset its current cfifo transfer counter value (tc_cf) to zero. depending on the cf ifo mode of operation, the cfifo status will also change upon the detection of an asserted eo q bit on the last transferred command - see section 27.7.4.6, cfifo scan trigger modes , for details. 0 not the last entry of the cqueue. 1 last entry of the cqueue. note: if both the pause and eoq bits are asserted in the same command message the respective flags are set, but the cfifo status changes as if only the eoq bit were asserted. 1 pau s e pause bit. the pause bit allows software to cr eate sub-queues within a cqueue. when the eqadc completes the transfer of a command with an asse rted pause bit, the cfifo enters the waiting for trigger state. refer to section 27.7.4.7.1, cf ifo operation status , for a descripti on of the state transitions. the pause bit is only valid when cfifo operation mode is configured to single or continuous-scan edge trigger mode. 0 do not enter waiting for trigger state afte r transfer of the current command message. 1 enter waiting for trigger state after transfer of the current command message. note: if both the pause and eoq bits are asserted in the same command message the respective flags are set, but the cfifo status changes as if only the eoq bit were asserted. 2 rep repeat/loop start point indication bit. the rep bit is asserted in the command to indicate where is the start point of the sub-queue to be repeated when the streaming mode is enabled. the pause bit indicates the end point of the sub-queue. therefore, both can occur in the same command or in separated ones. if two or more rep bits are read before a pause bit, this is an error case and the intermediary rep bits are ignored. 0 it is not the start point of a loop. 1 indicates the start point of the sub-queue to be repeated. 3?4 reserved 5 eb external buffer bit. a negated eb bit indicates that the command is sent to an internal cbuffer. 0 command is sent to an internal buffer. 1 reserved. 6 bn buffer number bit. bn indicates which buffer the message will be stored in. 1 message stored in buffer 1. 0 message stored in buffer 0. 7 cal calibration bit. cal indicates if the returning conversion result must be calibrated. 1 calibrate conversion result. 0 do not calibrate conversion result.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-61 pxr40 microcontroller reference manual, rev. 1 8?11 message_tag message_tag field. the message_tag allows the eqadc to separate re turning results into different rfifos. w hen the eqadc transfers a co mmand, the message_tag is included as part of the command. eventually the on-chip adc returns the result with t he same message_tag. the eqadc separates incoming messages into different rfifos by decoding the message_tag of the incoming data. 0000 result is sent to rfifo 0 0001 result is sent to rfifo 1 0010 result is sent to rfifo 2 0011 result is sent to rfifo 3 0100 result is sent to rfifo 4 0101 result is sent to rfifo 5 0110?0111 reserved 1000 null message received 1001 reserved for customer use (see note) 1010 reserved for customer use (see note) 1011?1111 reserved note: these messages are treated as null messages. 12?13 lst long sampling time. these two bits determine the duration of the sampling time in adc clock cycles. 14 tsr time stamp request. tsr indicates the request for a time stamp. when tsr is asserted, the on-chip adc control logic returns a time stamp for the current conversi on command after the conversion result is sent to the rfifos. see section 27.7.6.3, time stamp feature , for details. 0 return conversion result only. 1 return conversion time stamp after the conversion result. 15 ffmt conversion data format. fmt specifies to the eqadc ho w to format the 12-bit conversion data returned by the adcs into the 16-bit format which is sent to the rfifos. see section , adc result format for on-chip adc operation , for details. 0 right justified unsigned. 1 right justified signed. table 27-33. field descriptions (continued) field description lst[0:1] sampling cycles (adc clock cycles) 0b00 2 0b01 8 0b10 64 0b11 128
enhanced queued analog-to-digital converter (eqadc) 27-62 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 write configuration command format for on-c hip adc operation figure 27-45 describes the command message format for a write configuration co mmand when interfacing with the on-chip adcs. a write confi guration command is used to set the control re gisters of the on-chip adcs. no conversion data will be returned for a write configurat ion command. write configuration commands are differentiated from read configuration co mmands by a negated r/w bit. figure 27-45. write configuration command format for on-chip adc operation 16?23 channel_ number channel number field. the channel_number field selects the analog input channel. the software programs this field with the channel number corresponding to the analog input pin to be sampled and converted. see section 27.7.7.1, channel assignment , for details. 24?31 alt_config_sel alternate configuration selection. this field selects one of the alternate configurations. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 eoq pau s e rep reserved eb (0b0) bn r/w (0b0) adc_register high byte cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc_register low byte adc_reg_address adc command table 27-33. field descriptions (continued) field description alt_config_sel[0:7] alter nate configuration 0x08 1 0x09 2 0x0a 3 0x0b 4 0x0c 5 0x0d 6 0x0e 7 0x0f 8
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-63 pxr40 microcontroller reference manual, rev. 1 read configuration command forma t for on-chip adc operation figure 27-46 describes the command message format for a read configuration comm and when interfacing with the on-chip adcs. a read conf iguration command is used to read the contents of the on-chip adc registers which are only accessible via comma nd messages. read configuration commands are differentiated from write configuration commands by an asserted r/w bit. figure 27-46. read configuration command format for on-chip adc operation table 27-34. field descriptions field description 0 eoq end of queue bit 1 pau s e pause bit 2 rep repeat/loop start point indication bit 3?4 reserved 5 eb must be 0b0 6 bn buffer number bit. refer to section , conversion command format for the standard configuration. 7 r/w read/write bit. a negated r/w indica tes a write configuration command. 0 write1read 8?15 adc_register_ high_byte adc register high byte field. register_high_byte is the value to be written into the most significant 8 bits of control/configuration re gister when the r/w bit is negated. 16?23 adc_register_ low_byte adc register low byte field. register_low_byte is the value to be written into the least significant 8 bits of a control/configuration re gister when the r/w bit is negated. 24?31 adc_reg_ address adc register address. the adc_reg_address field sele cts a register on the a dc register set to be written or read. only half-word addresses can be used. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 eoq pau s e rep reserved eb (0b0) bn r/w (0b1) message_tag reserved cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved adc_reg_address adc command
enhanced queued analog-to-digital converter (eqadc) 27-64 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 adc result format for on -chip adc operation when the fifo control unit receives a return data message, it decodes the message_tag field and stores the 16-bit data into the appropria te rfifo. this section describes the adc result portion of the result message returned by the on-chip adcs. the 16-bi t data stored in the rfifos can be: ? data read from an adc register with a read configuration command. in this case, the stored 16-bit data corresponds to the contents of the adc register that was read. ? a time stamp. in this case, the stored 16-bit data is the value of the time base counter latched when the eqadc detects the end of the analog input voltage sampling. for details see section 27.7.6.3, time stamp feature . ? a conversion result, coming directly from the adcs. in this case, the stored 16-bit data contains a right justified 14-bit result data . the conversion result can be calibrated or not depending on the status of cal bit in the comma nd that requested the conversion 1 . when the cal bit is negated, this 14-bit data is obtained by ex ecuting a 2-bit left-shift on the 12-bit data resultant from the resolution adjustment on the 8 or 10 or 12-bit data received from the adc. the resolution adjustment consists of changing the conversion resu lt input from 8, 10 or 12 bits right aligned to a 12-bit word left al igned - refer to section 27.7.6.5, adc resoluti on selection feature , for details. when the cal bit is asserted, this 14-bit data is the result of the calculations performed in the table 27-35. field descriptions field description 0 eoq end of queue bit 1 pau s e pause bit 2 rep repeat/loop start point indication bit 3?4 reserved 5 eb must be 0b0 6 bn buffer number bit. refer to section , conversion command format for the standard configuration. 7 r/w read/write bit. an asserted r/w bit i ndicates a read configuration command. 0 write1read 8?11 message_ tag message_tag field. refer to section , conversion command format for the standard configuration . 12?23 reserved 24?31 adc_reg_ address adc register address. the adc_reg_address field sele cts a register on the a dc register set to be written or read. only half-word addresses can be used. 1. in case the conversion result is routed through an on-chip dsp via side interface, the calibration is applied before the data is sent to the dsp.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-65 pxr40 microcontroller reference manual, rev. 1 eqadc mac unit using the 12-bit data result of the resolution adjustment and the calibration constants gcc and occ, or al tgcc and altocc - refer to section 27.7.6.6, adc calibration feature , for details. then, this 14-bit data is further formatted in to a 16-bit format according to the status of the fmt bit in conversion command of the standard configurati on or ffmt bit in the conversion command of the alternate configurations 1 . when fmt/ffmt is asserted, the 14-bit result data is reformatted to look as if it was measured against an imaginary ground at vref/2 (the msb bit of the 14-bit result is inverted), a nd is sign-extended to a 16-bit format as in figure 27-47 . when fmt/ffmt is negated, the eq adc zero-extends the 14-bit result data to a 16-bit format as in figure 27-48 . correspondence between the analog voltage in a channel and the calculated digital values is shown in table 27-37 . figure 27-47. adc result format when fmt=1 (right justified signed) figure 27-48. adc result format when fmt=0 (right justified unsigned) 1. for simplicity, the following text will refer to fmt only, but when using alternate configurations, refer to conversion command format for alternate configurations . 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sign_ext resolution adjusted conversion_result (with inverted msb bit) adc result 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 resolution adjusted conversion_result adc result
enhanced queued analog-to-digital converter (eqadc) 27-66 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 27-36. field descriptions field description 0?1 sign_ext sign extension field. sign_ext only has meaning when fmt is asserted. sign_ext is 0b00 when conversion_result is positive, and 0b11 when conversion_result is negative. 2?15 conversion_ result conversion result field. conversion_result is a digital value corresponding to the analog input voltage in a channel when the conversion command was initiated. the two?s co mplement representation is used to express negative values. table 27-37. correspondence between analog voltages and digital values 1, 2 voltage level on channel (v) corresponding 8-bit conversion result returned by the adc 3 corresponding 10-bit conversion result returned by the adc 4 corresponding 12-bit conversion result returned by the adc 5 16-bit result sent to rfifos (fmt=0) 6 16-bit result sent to rfifos (fmt=1) 6 single- ended conversions 5.12 ? ? 0xfff 0x3ffc 0x1ffc ? 0x3ff ? 0x3ff0 0x1ff0 0xff ? ? 0x3fc0 0x1fc0 5.12 ? lsb ? ? 0xfff 0x3ffc 0x1ffc ? 0x3ff ? 0x3ff0 0x1ff0 0xff ? ? 0x3fc0 0x1fc0 ... ... ... ... ... ... 2.56 ? ? 0x800 0x2000 0x0000 ? 0x200 ? 0x2000 0x0000 0x80 ? ? 0x2000 0x0000 ... ... ... ... ... ... 1 lsb ? ? 0x001 0x0004 0xe004 ? 0x001 ? 0x0010 0xe010 0x01 ? ? 0x0040 0xe040 0 0x00 0x000 0x000 0x0000 0xe000 differential conversions 2.56 ? ? 0xfff 0x3ffc 0x1ffc ? 0x3ff ? 0x3ff0 0x1ff0 0xff ? ? 0x3fc0 0x1fc0 2.56 - lsb ? ? 0xfff 0x3ffc 0x1ffc ? 0x3ff ? 0x3ff0 0x1ff0 0xff ? ? 0x3fc0 0x1fc0 ... ... ... ... ... ... 0 ? ? 0x800 0x2000 0x0000 ? 0x200 ? 0x2000 0x0000 0x80 ? ? 0x2000 0x0000 ... ... ... ... ... ... 2.56 ? lsb ? ? 0x001 0x0004 0xe004 ? 0x001 ? 0x0010 0xe010 0x01 ? ? 0x0040 0xe040 ?2.56 0x00 0x000 0x000 0x0000 0xe000
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-67 pxr40 microcontroller reference manual, rev. 1 27.7.3 command/result queues each cqueue entry is a 32-bit comm and message.the last entry of a cq ueue has the eoq bit asserted to indicate that it is the last entry of th e cqueue. rqueue entr y is a 16-bit data. see section 27.7.2.1, overview and basic terminology , for a description of the message formats and their flow in eqadc. refer to section 27.8.5, cqueue and rqueues usage , for examples of how cqueues and rqueues can be used. 27.7.4 eqadc command fifos 27.7.4.1 cfifo basic functionality there are six prioritized cfifos lo cated in the eqadc. each cfifo is four entries deep, except cfifo0 that can be configured to eight entries deep in extended mode, and each cfifo entry is 32 bits long. a cfifo serves as a temporary storage location for th e command messages stored in the cqueues in the system memory. when a cfifo is not full, the eqadc sets the corresponding cfff bit in eqadc_fisr. if cffe is asserted in eqadc_ idcr, the eqadc generates requests for more commands from a cqueue. an interrupt request, served by the hos t cpu, is generated when cffs is negated, and a dma request, served by the dmac, is generated when cffs is asserted. the host cpu or the dmac respond to these requests by writing to the eqadc_cfpr to fill the cfifo. note the dmac should be configured to write a single command (32-bit data) to the cfifo push registers for every asserted dma request it acknowledges. refer to section 27.8.2, eqadc/dmac interface , for dmac configuration guidelines. notes: 1 vref=vrh-vrl=5.12v. resulting in one 12-bit count (lsb) =1.25mv. 2 the two?s complement representation is used to express negative values. 3 for non-corner voltages (voltages different from v rl and v rh ), the maximum quantization error is lsb. first code transition (from 0x000 to 0x001 for unsigned values) happens at +0.5 lsb (v) while the last one (from 0xffe to 0xfff for unsigned values) happens at v ref - 1.5 lsb (v). 4 for non-corner voltages (voltages different from v rl and v rh ), the maximum quantization error is lsb. first code transition (from 0x000 to 0x001 for unsigned values) happens at +0.5 lsb (v) while the last one (from 0xffe to 0xfff for unsigned values) happens at v ref - 1.5 lsb (v). 5 for non-corner voltages (voltages different from v rl and v rh ), the maximum quantization error is lsb. first code transition (from 0x000 to 0x001 for unsigned values) happens at +0.5 lsb (v) while the last one (from 0xffe to 0xfff for unsigned values) happens at v ref - 1.5 lsb (v). 6 assuming uncalibrated conversion results. 0.5 ? 0.5 ? 0.5 ?
enhanced queued analog-to-digital converter (eqadc) 27-68 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note cfifo0 can be configured to work in an alternative wa y called streaming mode. this mode is very different from the mode described here because it maintains some stored commands to ex ecute them several times in sequence and in loop. note only whole words must be written to eqadc_cfpr. writing half-words or bytes to eqadc_cfpr will still push the whol e 32-bit cf_push field into the corresponding cfifo, but undefi ned data will fill the areas of cf_push that were not specifically designated as target locations for writing. figure 27-49 describes the important components in the cfif o. each cfifo is implemented as a circular set of registers to avoid the need to move all en tries at each push/pop opera tion. the push next data pointer points to the next availa ble cfifo location for storing data written into the eqadc command fifo push register. the transfer ne xt data pointer points to the next entry to be removed from cfifox when it completes a transfer. the cfifo transfer counter control logic counts the number of entries in the cfifo and generates dma or in terrupt requests to fill the cfifo. tnxtptr in eqadc_fisr, indicates the index of the entry that is currently being addressed by the transfer next data pointer, and cfctr, in the same register, provides the number of entries stored in the cfifo. using tnxtptr and cfctr, the absolute addresses for th e entries indicated by the transfer next data pointer and by the push next data pointer can be calcula ted using the following formulas: transfer next data pointer addres s = cfifox_base_address + tnxtptrx*4 push next data pointer address = cfifox_base_address + [(tnxtptrx+cfctrx) mod cfifo_depth] * 4 where ? a mod b returns the remainder of the division of a by b . ? cfifox_base_address is the smallest memory mapped address allocated to a cfifox entry. ? cfifo_depth is the number of entries containe d in a cfifo - four in this implementation. when cfs x in eqadc_cfsr is triggered, the eqadc ge nerates the proper cont rol signals for the transfer of the entry pointed by tr ansfer next data pointer. cfufx in eqadc_fisr is set when a cfifox underflow event oc curs. a cfifo underflow occurs when the cfifo is in triggered state and it becomes empty. no commands will be transferred from an unde rflowing cfifo, nor will command transfers from lower priority cfifos be blocked. cfifox is empty when the transfer next data pointer x equals the push next data pointe r x and cfctrx is zero. cfifox is full when the transfer next data pointer x equals the push next data pointer x and cfctrx is not zero. when the eqadc completes the transfer of an entr y from cfifox: the transf erred entry is popped from cfifox, the cfifo counter cfctr in the eqadc_fisr is decremented by one, and transfer next data pointer x is incremented by one (or wr apped around) to point to the next entry in the cfifo. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-69 pxr40 microcontroller reference manual, rev. 1 when the eqadc_cfprx is written and cfifox is not full, the cfif o counter cfctrx is incremented by one, and the push next data poin ter x then is incremen ted by one (or wrapped ar ound) to point to the next entry in the cfifo. when the eqadc_cfprx is written but cfifox is full, the eqadc will not increment the counter value and will not overwrite any entry in cfifox. figure 27-49. cfifo diagram the detailed behavior of the push next data pointer and transfer next data pointer is described in the example shown in figure 27-50 where a cfifo with 16 entries is s hown for clarity of explanation, the actual hardware implementa tion has only four entries. in this exam ple, cfifox with 16 entries is shown in sequence after pushing and transferring entries. 32-bit entry 1 32-bit entry 2 -------------------- -------------------- push next data pointer * transfer next data pointer * cfifo push register cfifo control logic dma done interrupt/dma request control signals transfer counter * all cfifo entries are memory mapped and the entries addressed by these pointers can have their absolute addresses calculated using tnxtptr and cfctr. write to slave-bus interface by cpu or dma
enhanced queued analog-to-digital converter (eqadc) 27-70 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-50. cfifo entry pointer example 27.7.4.2 cfifo0 streaming mode description cfifo0 can be configured to operate in streaming mode to allow repetition of a group of commands several times without the need of re filling the registers as in the norma l mode of operation of cfifos. this mode makes use of the ad ditional bit in the convers ion command word (ccw) cal led ?repeat? (rep bit). push transfer cfifox first in after reset or invalidation next data pointer next data pointer last in valid entry empty entry push transfer cfifox some entries pushed but none executed next data pointer next data pointer transfer cfifox no entries pushed but some executed next data pointer first in last in push next data pointer push cfifox entries pushed until full and none executed next data pointer cfifox no entries pushed but some executed transfer cfifox some entries pushed and some executed next data pointer first in last in push next data pointer transfer next data pointer first in last in push next data pointer transfer next data pointer first in last in note: x=0, 1, 2, 3, 4, 5
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-71 pxr40 microcontroller reference manual, rev. 1 the purpose of this bit is to mark in the command queue, where to start a repeating seque nce. this location is stored in an additional pointer ?repeat pointer?. streaming mode requires 2 tr igger inputs. the standard que ue 0 trigger, in this mode referred to as repeat trigger and a new internal trigger input to the e qadc called advance trigger (no filter available). cfifo0 is configured to operate in streaming mode by setting th e bit strme0 as described in section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) . cfifo0 is eight entries deep in extended mode by setting th e bit cfeee0 in the same eqadc_cfcr register, and each entry is 32 bits long. this cfifo0 serves as a local storage of a few commands that need to be executed sequentially as in a fifo but can contain sub-queues that need to be executed several times. the cfff0 bit in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) , is used to assure the cfifo0 is not full and command messages are stored from address 0x0 to 0x7. 27.7.4.2.1 cfifo0 operat ion in streaming mode in streaming mode, the cfifo0 is filled with ccws using the dma ex actly the same as existing modes. the cfifo executes commands as per the existing m odes until it executes a conversion command word with the repeat bit set. when this ccw is executed, the repeat pointer is set to point to this fifo location and from this ccw onwards, cfifo0 entries is not inva lidated, that is, the repeat pointer prevents this and subsequent entries from being overwritten. the queue continues to exec ute until a ccw with an asserted pause bit is completed; then the queue stops and enters the pause state, waiting for a tri gger. this is the same as normal behavior. the pause state is exited in one of two ways: repeat trigge r or repeat trigger with advance trigger. the repeat trigger with no advance trigger causes the transf er next data pointer to be loaded with the repeat pointer location and ccws are then executed from the repeat pointer back to the pause bit. this means that a section of the cfifo0 is repeatedly executed every time a repeat trigger occurs. the repeat trigger with the advance trigger pending causes al l ccws from the repeat pointer to the pause bit to be invalidated and the ccw af ter the pause bit to be executed. th is is achieved by invalidating the repeat pointer. the effect is that the queue adva nces beyond the repeating section of the cfifo0 to execute new ccws. note that the advance trigger can occur at any time between repeat triggers, but is only actioned when the next repeat trigger occurs. prior to that it is pending. in a typical application, the queue is made of so me configuration commands to the adc (to flush the decimator or turn on pad pull-up/down) followed by a repeating section of adc conversions on one or more adc channels from one or more sensors; fo llowed by a few more configuration commands; then more repeating adc conversions, until the entire engine cycle is comp lete; when the que ue is restarted. the mechanism described permits any number of repe ating sub-queues to be loaded and executed, interspersed by configuration commands. 27.7.4.2.2 triggering descri ption in streaming mode the additional advance-trigger signal atrig0 is detected by a separate circuit that is configured by the bit field amode0 as described in section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) . this trigger signal is used as an advance control of pop pointer of cfif o0. in addition, it is used as the
enhanced queued analog-to-digital converter (eqadc) 27-72 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 enable trigger for the repeat trigger. this means it is necessary to have an advance trigger first to enable the detection of the repeat trigger. when the repeat trigger is enabled, the advance trigger is used to advance the pop pointer beyond some loop sub-queue. and it is to disa ble the repeat trigger by executing a pause without a previous rep bit. a typical sequence of events is presented below to describe the relationship between the triggers. in streaming mode, the cfifo0 is filled with cc ws using the dma as usua l. the two triggers are configured to positive e dge and single scan mode. the sss bit is asserted and the trigger detector of the repeat trigger is disabled in the start of the queue. it is necessary to receive the first advance trigger to enable the detector of the other trigger. this enable is useful when the repeat trigger is received all the ti me and the trigger signal can be disabled when it is not desired. the advance trigger is received and de tected and the repeat trigger det ector is enabled. no commands are executed until now. the repeat trigger is detected and the commands start to be executed in sequence. if a re p bit is decoded with the pause bit, the loop is configured and th e cfifo0 commands stop to be executed. the next repeat trigger is waited to start th e execution of the loop again, or the advance trigger can be detected to break the loop and advance the queue in cfifo 0. the repeat trigger detector remains enabled. if the advance trigger is received and the next command in the cfifo0 does not present the rep bit set, this means the cfifo0 is not starting a new loop. in th is case (outside a loop) if a pause bit is decoded, this means to disable the re peat trigger detector. this can be useful if the repeat trigge r is not required for some interval of time. the repeat trigger detector is enabled again when the next advance trigger event is detected. 27.7.4.2.3 cfifo0 diagram d escription in streaming mode figure 27-51 represents the main componen ts of cfifo0 in streaming mode. however, some signals behave in a different way from the common operation. the push next data pointer points to the next available cfifo0 location for storing data writte n into the eqadc command fifo push register. the transfer next data pointer points to the next entry to be transferred to cbuffer. the repeat pointer points to the first entry of the re peating sub-queue. tnxtptr in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) , indicates the index of the entry that is curren tly being addressed by the transfer next data pointer, and cfctr, in the same register, provides the number of entries stored in the cfifo. when cfs0 in section 27.6.2.10, eqadc cfifo stat us register (eqadc_cfsr) , is triggered, the eqadc generates the proper control signals for the tran sfer of the entry pointed by transfer next data pointer. cfuf0 in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) , is set when cfifo0 underflow event occurs. a cfifo underf low occurs when the cfifo is in triggered state and it is empty. no commands will be tran sferred from an underflowing cfifo, nor will command transfers from lower priority cfifos be blocked. cfifo0 is empty when cfctr0 is zero. cfifo0 is full when (cfctr0 mod cfifo_depth) is zero but cfctr0 is not zero. when the eqadc completes the transfer of an entry from cfifo0 in loop conditi on: the transferred entry is not popped from cfifo0, th e cfifo counter cfctr in the section 27.6.2.7, eqadc fifo and
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-73 pxr40 microcontroller reference manual, rev. 1 interrupt status re gisters (eqadc_fisr) , is not decremented by one, and transfer next data pointer 0 is incremented by one (or wrapped around) to point to the next entry in the cfifo0. figure 27-51. cfifo0 in streaming mode diagram the detailed behavior of the push next data pointer and transfer next data pointer is described in the example shown in figure 27-52 where a cfifo with 16 entries is s hown for clarity of explanation, the actual hardware implementation has onl y four/eight entries. in this ex ample, cfifo0 with 16 entries is shown in sequence after pushi ng and transferring entries. 32-bit entry 1 32-bit entry 2 -------------------- -------------------- push next data pointer * transfer next data pointer * cfifo push register cfifo control logic dma done interrupt/dma request control signals data to external device or to on-chip adcs transfer counter * all cfifo entries are memory mapped and the entries addressed by these pointers can have their absolute addresses calculated using tnxtptr and cfctr. repeat pointer 32-bit entry n, rep write to slave-bus interface by cpu or dma
enhanced queued analog-to-digital converter (eqadc) 27-74 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-52. cfifo0 in streaming mode entry pointer example push transfer cfifo0 first in after reset or invalidation next data pointer next data pointer last in valid entry empty entry push transfer cfifo0 some entries pushed but none executed next data pointer next data pointer transfer cfifo0 no entries pushed but some executed next data pointer last in push next data pointer transitory state. repeat trigger with no entries pushed but not repeat pointer repeat pause up to pause bit - waiting for trigger repeat pause repeat pointer transfer cfifo0 next data pointer last in push next data pointer repeat pause repeat pointer advance trigger causes loop execution. transfer cfifo0 next data pointer last in push next data pointer repeat pause repeat pointer transitory state. repeat trigger and with advance trigger causes execution of next entry after pause. repeat full and not executed. transfer cfifo0 next data pointer last in push next data pointer pause repeat pointer repeat first in non repeat command followed by 5 repeat commands pending. no trigger.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-75 pxr40 microcontroller reference manual, rev. 1 figure 27-53. cfifo0 in streaming mode entry pointer example (cont.) 27.7.4.2.4 streaming mode error conditions in the repeat state, the existing error conditions stil l apply, but now there are new ways to trigger them. now, the ccws are not being invalida ted so the dma is not able to lo ad more ccws into those locations. so a queue overflow becomes more likely, and occurs if the repeat loop is longe r than 8 entries. if all ccws in the cfifo0 are executed and no pause bit or eoq bit is detected, th e eqadc will signal an underflow error. in pr actice this may limit a repeating queue to 7 entries since otherw ise an underflow will occur at the point a repeat with advance trigger occurs, and there is no command in the cfifo0 to execute. the exception is a final co mmand with both a pause and an eoq bit set. the end of queue bit eoq continues to operate as in normal mode, unless the repeat mode is enabled. in this case the pause bit takes precedence and a repeat trigger causes the ju mp back described. a rep eat trigger with advance trigger causes the queue to end. another error condition occur when th e repeat trigger is in the triggered state a nd a new repeat trigger is received. in this case, a trigger overflow occurs but the cfifo0 is defined to not restart the loop. the trigger in this case is not used in th e cfifo0, but the overflow is indicated. 27.7.4.3 cfifo common prioriti zation and command transfer the cfifo priority is fixed according to the cfif o number. a cfifo with a smaller number has a higher priority. when commands of distinct cfifos are bound for the same destination (cbuffer), the higher no entries pushed. last in push transfer cfifo0 entries pushed. fi fo full. waiting next data pointer next data pointer repeat pointer repeat pause transfer cfifo0 next data pointer last in push next data pointer pause repeat pointer repeat entries executed to pause bit. pending trigger. at pause bit for repeat trigger or advance & repeat trigger.
enhanced queued analog-to-digital converter (eqadc) 27-76 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 priority cfifo is always served first. a tr iggered, not-underflowing cfifo will start the transfer of its commands when: ? its commands are bound for an internal cbuffer that is not full, and it is the highest priority triggered cfifo sending co mmands to that cbuffer. a triggered cfifo with commands bound for a certain cbuffer consecutively tran sfers its commands to it until: ? an asserted end of qu eue bit is reached, or; ? an asserted pause bit is encountered and the cf ifo is configured for edge trigger mode, or; ? cfifo is configured for level trigger mo de and a closed gate is detected, or; ? in case its commands are bound for an internal cbuffer, a highe r priority cfifo that uses the same internal cbuffer is triggered, or; the prioritization logic of the eqadc, depicted in figure 27-54 , is composed of two independent sub-blocks: one prioritizing cfifos with commands bound for cbuffer0 and another prio ritizing cfifos with commands for cbuffer1. as th ese sub-blocks are inde pendent, simultaneous wr ites to cbuffer0 and cbuffer1. the hardware identifies the destination of a command by decoding the bn bit in the command message - see section 27.7.2.2, message format in eqadc , for details. note triggered but empty cfifos, underflowi ng cfifos, are not considered for prioritization. no da ta from these cfifos will be sent to the cbuffers and nor will they stop lowe r priority cfifos from transferring commands. whenever cbuffer0 is able to receive new entries, the prioritization sub-block selects the highest-priority triggered cfifo with a command bound for cbuffer0, and writes its comm and into the buffer. in case cbuffer0 is able to receive new entries but there are no triggered cfifos with commands bound for it, nothing is written to the buffer. the sub-block prio ritizing cbuffer1 usage behaves in the same way.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-77 pxr40 microcontroller reference manual, rev. 1 figure 27-54. cfifo prioritization logic 27.7.4.4 cfifo prioriti zation in abort mode the cfifo priority does not change when the eqad c is configured to allow abortion of conversion execution in on-chip adc analog blocks. however, cfif o0 is the only one that can be enabled to abort conversions. this feature is necessary when the timing of some conversion is very im portant. in normal priority scheme, when cfifo0 is triggered, its conversion comman d can be put behind 2 pending conversion commands in the cbuffer due to the queue structure. consid ering that these 2 pending commands are from lower priority cfifos and that the dela y between the trigger and the sampling of the command from cqueue0 can be unacceptable, eqadc can be configured to permit immediate conversion commands from cfifo0 with abort function. when cfifo0 is triggered and abort is enabled, up to 2 commands in cbuf fer0 or cbuffer1 are stored in a side register. the abort request signal is genera ted to adc0 or adc1 and the confirmation of adc reset/ready is waited to send the command from cfifo0 to the decoded cbuffer. after the transfer of all commands from cfifo0, the recovery phase restores the up to 2 commands that were in cbuffer when the abort occurred. after this re covery phase, it is established the normal process of prioritization of comm ands from cfifos. cfifo3 command cfifo4 command cfifo5 command cfifo0 command cfifo1 command cfifo2 command adc1 cbuffer1 adc0 for cbuffer0 prioritization 6 x command command (2 entries) command eqadc prioritization logic cbuffer0 (2 entries) usage for cbuffer1 prioritization usage abort cont0 abort cont1
enhanced queued analog-to-digital converter (eqadc) 27-78 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.7.4.5 hardware trigger event detection on this device, the on-chip triggers bypass the filter and the off-chip etrig tri ggers are always filtered and subject to the minimum filter length of 2 clocks. when the filt er is bypassed, the etrig input signal is not filtered and the logic after the filter receives a copy of th is input trigger signal. the digital filter length field in section 27.6.2.2, eqadc external tri gger digital filter register (eqadc_etdfr) , specifies the minimum number of platform clocks that the etrig 0-5 signals must be held at a logic level to be recognized as valid. al l etrig signals are filtere d. a counter for each queue trigger is implemented to detect a transition between logic levels. the c ounter counts at the platform clock rate. the corresponding count er is cleared and restarted each time the signal transitions between logic levels. when the corresponding counter matches the valu e specified by the digital filter length field in section 27.6.2.2, eqadc external trigger di gital filter regi ster (eqadc_etdfr) , the eqadc considers the etrig logic level to be valid and passe s that new logic level to the rest of the eqadc. the filter is only for filtering the etrig signal. logic after the filter checks for transitions between filtered values, such as for detecting the transi tion from a filtered logic le vel zero to a filter l ogic level one in rising edge external trigger mode. the eq adc can detect rising edge, falli ng edge, or level gated external triggers. the digital filter will always be active independen tly of the status of the mode x field in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) , but the edge, leve l detection logic is only active when modex is set to a value different from disabled, and in case modex is set to single scan mode, when the sss bit is asserted. note that the time necessary for a external trigger event to result into a cfifo status change is not sole ly determined by the dfl field in the section 27.6.2.2, eqadc external trigger digital fi lter register (eqadc_etdfr) . after being synchroni zed to the platform clock and filtered, a trigger event is checked agains t the cfifo trigger mode. only then, after a valid trigger event is detected, the eqadc accor dingly changes the cfifo status. refer to figure 27-55 for an example. figure 27-55. etrig event propagation example 27.7.4.6 cfifo scan trigger modes the eqadc supports two different scan modes, single-scan and cont inuous-scan. refer to table 27-38 for a summary of these two scan m odes. when a cfifo is triggered, the eqadc scan mode determines whether the eqadc will stop comma nd transfers from a cfifo, and wa it for software intervention to platform clock external trigger signal filtered external cfifo status trigger signal signal state at input pin modex idle waiting for trigger triggered disabled continuous scan high l evel gated external trigger trigger detection delay trigger synchronization and filtering delay 1 ) notes: 1. this delay is about 2 clocks when the filter by pass control is asserted.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-79 pxr40 microcontroller reference manual, rev. 1 rearm the cfifo to detect new trigger events, upon detection of an as serted eoq bit in the last transfer. refer to section 27.7.2.2, message format in eqadc , for details about command formats. cfifos can be configured in si ngle-scan or continuous-scan mode. when a cfifo is configured in single-scan mode, the eqadc scans the cqueue one time. the eqadc stops future command transfers from the triggered cfifo af ter detecting the eoq bit se t in the last transfer. af ter a eoq bit is detected, software involvement is required to rearm the cf ifo so that it can detect new trigger events. when a cfifo is configured for continuous-scan mode, no software in volvement is necessary to rearm the cfifo to detect new trigger events after an as serted eoq is detected. in continuous-scan mode the whole cqueue is scanned multiple times. the eqadc also supports different triggering mech anisms for each scan mode. the eqadc will not transfer commands from a cfifo until the cfifo is triggered. the combination of scan modes and triggering mechanisms allows the s upport of different requirements for scanning input channels. the scan mode and trigger mechanism are confi gured by programming the modex field in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) . enabled cfifos can be triggered by software or extern al trigger events. the elap sed time from detecting a trigger to transferring a command is a function of clock frequency, tri gger synchronization, trigger filtering or not, programmable trigger events, command transfer, cfifo prioritization, cbuffer availability, etc. fast and predic table transfers can be achieved by ensuring that the cfifo is not underflowing and that the target cbuffer is not full when the cfifo is triggered. 27.7.4.6.1 disabled mode the mode x field in section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) , for all of the cfifos can be changed from any ot her mode to disabled at any ti me. no trigger event can initiate command transfers from an cfifo which has its mode field programmed to disabled. note if modex is not disabled, it must not be changed to any other mode besides disabled. if modex is disabled and the cfifo status is idle, modex can be changed to any other mode. if mode x is changed to disabled: ? the cfifo execution status will change to idle. the timing of this change depends on whether a command is being transferred or not: ? when no command transfer is in progress, th e eqadc switches the cfifo to idle status immediately. ? when a command transfer to an on-chip cbuffer is in progress, the eqadc will complete the transfer, update tc_cf, and switch cfifo status to idle. command tran sfers to the internal cbuffers are considered completed when a command is written to the buffers. ? the cfifos are not invalidated automatically. the cfifo still can be invalidated by writing a ?1 to the cfinvx bit in section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) . certify that cfs has changed to idle before setting cfinvx. ? the tc_cfx value also is not reset automatical ly, but it can be reset by writing ?0? to it.
enhanced queued analog-to-digital converter (eqadc) 27-80 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? the sss bit in section 27.6.2.7, eqadc fifo and interrupt status regist ers (eqadc_fisr) , is negated. the sss bit can be set even if a ?1? is wr itten to the sse bit in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) , in the same write that th e modex field is changed to a value other than disabled. ? the trigger detection hardware is reset. if mo dex is changed from disabled to an edge trigger mode, a new edge, matching that edge trigger mode , is needed to trigger the command transfers from the cfifo. note cfifo fill requests, which generate d when cfff is asserted, are not automatically halted when modex is changed to disabled. cfifo fill requests will still be generate d until cffe is cleared in section 27.6.2.6, eqadc interrupt and dma cont rol registers (eqadc_idcr) . 27.7.4.6.2 single-scan mode in single-scan mode, a single pass through a sequence of command messages in a cqueue is performed. in single-scan software trigger mode , the cfifo is triggere d by an asserted single-scan status bit (sss) in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) . the sss bit is set by writing ?1? to the single-scan enable bit (sse) in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) . in single-scan edge- or level-trigge r mode, the respective triggers are only detected when the sss bit is asserted. when the sss bit is negated, all trigger ev ents for that cfifo are ignored. writing a ?1? to the sse bit can be done during the same write cycle that the cfifo operation mode is configured. only the eqadc can clear the sss bit. once sss is asserted, it remains asserted until the eqadc completes the cqueue scan, or th e cfifo operation mode (modex) in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) , is changed to disabled. the sss x bit will be negated while mode x is disabled. single-scan software trigger when single-scan software trigger m ode is selected, the cfifo is trig gered by an asserted sss bit. the sss bit is asserted by writing ?1? to the sse bit. writ ing to sse while sss is al ready asserted will not have any effect on the state of the sss bit, nor will it cause a trigger overrun event. the cfifo commands start to be tr ansferred when the cfif o becomes the highest priority cfifo using a not-full on-chip cbuffer. when an asserted eoq bit is encountered, the eqadc will clear the sss bit. setting the sss bit is required for the eqad c to start the next scan of the queue. the pause bit has no effect in si ngle-scan software trigger mode. single-scan edge trigger when sss is asserted and an edge triggered mode is selected for a cfifo, an appropriate edge on the associated trigger signal causes the cfifo to become triggered. fo r example, if rising-edge trigger mode is selected, the cfifo becomes triggered when a rising edge is sensed on the trigger signal.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-81 pxr40 microcontroller reference manual, rev. 1 the cfifo commands start to be tr ansferred when the cfif o becomes the highest priority cfifo using a not-full on-chip cbuffer or an not-full external cbuffer. when an asserted eoq bit is en countered, the eqadc clears sss and stops command transfers from the cfifo. an asserted sss bit and a s ubsequent edge trigger ev ent are required to start the next scan for the cfifo. when an asserted pause bi t is encountered, the eqadc stops co mmand transfers from the cfifo, but sss remains set. another edge tr igger event is required for command transfers to continue. a trigger overrun happens when the cfifo is in triggered state and an e dge trigger event is detected. single-scan level trigger when sss is asserted and a level gated trigger mode is selected, the input level on the associated trigger signal puts the cfifo in triggered state. when the cfifo is asserted to hi gh-level gated trigger, a high level signal opens the gate, and a low level closes the gate. when the cfifo is set to low-level gated trigger mode, a low level signal opens the gate, and a high level closes the gate. if the corresponding level is already present, setting the sss bit triggers the cfifo. the cfifo commands start to be transferred when the cfifo becomes the highest priority cfif o using a not-full on-chip cbuffer or a not -full external cbuffer. the eqadc clears the sss bit and stops transferri ng commands from a triggered cfifo when an asserted eoq bit is encountered or when cfifo status changes from triggered due to the detection of a closed gate. command transfers will restart from the point they have stopped. the pause bit has no effect in single-scan level-trigger mode. 27.7.4.6.3 continuous-scan mode in continuous-scan mode, multiple passes looping th rough a sequence of command messages in a cqueue are executed. when a cfifo is programmed fo r a continuous-scan mode, the sse bit in the section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) , does not have any effect. continuous-scan software trigger when a cfifo is programmed to continuous-scan so ftware trigger mode, th e cfifo is triggered immediately. the cfifo commands star t to be transferred when the cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer. when a cfifo is programmed to run in continuous-scan software trigger mode, the eqadc wi ll not halt transfers from the cfifo until the cfifo operation mode is modified to disabled or a hi gher priority cfifo preempts it. al though command transfers will not stop upon detection of an asserted eoq bi t, the eoqf is set and, if enabled, an eoq interrupt request is generated. the pause bit has no effect in cont inuous-scan software trigger mode. continuous-scan edge trigger when rising, falling, or either e dge trigger mode is selected for a cfifo, a corresponding edge on the associated etrig signal places th e cfifo in triggered state. th e cfifo commands start to be transferred when the cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer.
enhanced queued analog-to-digital converter (eqadc) 27-82 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 when an eoq or a pause is enc ountered, the eqadc halts command tr ansfers from the cfifo and, if enabled, the appropriate interrupt requests are genera ted. another edge trigger ev ent is required to resume command transfers but no software involvement is requi red to rearm the cfifo in order to detect such event. a trigger overrun happens when the cfifo is already in triggered st ate and a new edge trigger event is detected. continuous-scan level trigger when high or low level gated trigge r mode is selected, the input leve l on the associated trigger signal places the cfifo in triggered state. when high-le vel gated trigger is sele cted, a high-level signal opens the gate, and a low level closes the gate. the cfifo commands start to be transferred when the cfifo becomes the highest priority cfifo usi ng a not-full on-chip cbuffer. although command transfers will not stop upon detection of an asserted eoq bit at the e nd of a command transfer, the eoqf is asserted and, if enabled, an eo q interrupt request is generated. the eqadc stops transferring comm ands from a triggered cfifo wh en cfifo status changes from triggered due to the detec tion of a closed gate. if a closed gate is detected while no command transfers are taking place and the cfifo stat us is triggered, the cfifo stat us is immediately changed to waiting for trigger and the pf fl ag is asserted.command transfers will restart as the gate opens. the pause bit has no effect in c ontinuous-scan level-trigger mode. 27.7.4.6.4 cfifo scan trigge r mode start/stop summary table 27-38 summarizes the start and stop conditions of command transfers from cfifos for all of the single-scan and contin uous-scan trigger modes. table 27-38. cfifo scan trigger mode - command transfer start/stop summary trigger mode requires asserted sss to recognize trigger events? command transfer start/restart condition stop on asserted eoq bit 1 ? stop on asserted pause bit 2 ? other command transfer stop condition 3 4 single scan software don?t care asserted sss bit. yes no none. single scan edge yes a corresponding edge occurs. yes yes none. single scan level yes gate is opened. yes no eqadc also stops transfers from the cfifo when cfifo status changes from triggered due to the detection of a closed gate. 5 continuous scan software no cfifo starts automatically after being configured into this mode. no no none. continuous scan edge no a corresponding edge occurs. yes yes none.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-83 pxr40 microcontroller reference manual, rev. 1 27.7.4.7 cfifo and trigger status 27.7.4.7.1 cfifo operation status each cfifo has its own cfifo status fiel d. cfifo status (cfs) can be read from section 27.6.2.10, eqadc cfifo status register (eqadc_cfsr) . figure 27-56 and table 27-39 indicate the cfifo status switching c ondition. refer to figure 27-17 for the meaning of each cfif o operation status. the last cfifo to transfer a command to an on-ch ip cbuffer can be read from the lcftcb n (n=0,1) fields in the section 27.6.2.9, eqadc cfifo status sn apshot registers (eqadc_cfssr) . the last cfifo to transfer a command to a specific ex ternal cbuffer can be identified by reading the lcftssi and ecbni fields in the section 27.6.2.9, eqadc cfifo status sn apshot registers (eqadc_cfssr) . continuous scan level no gate is opened. no no eqadc also stops transfers from the cfifo when cfifo status changes from triggered due to the detection of a closed gate. 5 notes: 1 refer to section 27.7.4.7.2, cqueue completion status , for more information on eoq. 2 refer to section 27.7.4.7.3, pause status , for more information on pause. 3 eqadc always stops command transfers from a cf ifo when the cfifo operation mode is disabled. 4 eqadc always stops command transfers from a cfifo w hen a higher priority cfifo is triggered. refer to section 27.7.4.3, cfifo common prioritization and command transfer , for information on cfifo priority. 5 if a closed gate is detected while no command transfers are taking place, it will have immediate effect on the cfifo status. if a closed gate is detect ed during the serial transmission of a command to the external device, it will have no effect on the cfifo st atus until the transmission completes. table 27-38. cfifo scan trigger mode - command transfer start/stop summary (continued) trigger mode requires asserted sss to recognize trigger events? command transfer start/restart condition stop on asserted eoq bit 1 ? stop on asserted pause bit 2 ? other command transfer stop condition 3 4
enhanced queued analog-to-digital converter (eqadc) 27-84 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-56. state machine of cfifo status table 27-39. command fifo status switching condition no. from current cfifo status (cfs) to new cfifo status (cfs) status switching condition 1 idle (00) idle (0b00) ? cfifo mode is programmed to disabled, or ? cfifo mode is programmed to single-scan edge or level trigger mode and sss is negated. 2 waiting for trigger (0b10) ? cfifo mode is programmed to continuous-scan edge or level trigger mode, or ? cfifo mode is programmed to single-scan edge or level trigger mode and sss is asserted, or ? cfifo mode is programmed to single-scan software trigger mode. 3 triggered (0b11) ? cfifo mode is programmed to continuous-scan software trigger mode 4 waiting for trigger (10) idle (0b00) ? cfifo mode is modified to disabled mode. 5 waiting for trigger (0b10) ? no trigger occurred. 6 triggered (0b11) ? appropriate edge or level trigger occurred, or ? cfifo mode is programmed to single-scan software trigger mode and sss bit is asserted. idle waiting for trigger triggered 2 1 3 4 5 6 7 8 9
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-85 pxr40 microcontroller reference manual, rev. 1 27.7.4.7.2 cqueue completion status the end of queue flag (eoqf) in section 27.6.2.7, eqadc fifo and in terrupt status registers (eqadc_fisr) , is asserted when the eqadc completes the tr ansfer of a cfifo entr y with an asserted eoq bit. software sets the eoq bit in the last command message of a cq ueue to indicate that this entry is the end of the cqueue - see section 27.7.2.2, message format in eqadc , for information on command message formats. the transfer of entries bound for the on-chi p adcs is considered completed when they are stored in the appropriate cbuffer. the command with a eoq bit a sserted is valid and will be transferred. when eoqie in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) , and eoqf are asserted, the eqadc will generate an end of queue interrupt request. in single-scan modes, command transfers from the corresponding cfifo will cease when eqadc completes the transfer of a entry w ith an asserted eoq. software i nvolvement is required to rearm the cfifo so that it can de tect new trigger events. 7 triggered (11) idle (0b00) ? cfifo in si ngle-scan mode, eqadc detects the eoq bit asserted at end of command transfer, and cfifo mode is not modified to disabled.or ? cfifo, in single-scan level trigger mode, and the gate closes while no commands are being transferred from the cfifo, and cfifo mode is not modified to disabled. or ? cfifo, in single-scan level trigger mode, and eqadc detects a closed gated at end of command transfer, and cfifo mode is not modified to disabled. or ? cfifo mode is modified to di sabled mode and cfifo was not transferring commands. ?cfifo mode is modified to disabled mode while cfifo was transferring commands, and cfifo completes or aborts the transfer. 8 waiting for trigger (0b10) ? cfifo in single or continuous-scan edge trigger mode, eqadc detects the pause bit asse rted at the end of command transfer, the eoq bit in the same command is negated, and cfifo mode is not modified to disabled, or ? cfifo in continuous-scan edge trigger mode, eqadc detects the eoq bit asserted at the end of command transfer, and cfifo mode is not modified to disabled, or ? cfifo, in continuous-scan level trigger mode, and the gate closes while no commands are being transferred from the cfifo, and cfifo mode is not modified to disabled, or ? cfifo, in continuous-scan level trigger mode, and eqadc detects a closed gated at end of command transfer, and cfifo mode is not modified to disabled. 9 triggered (0b11) ? no event to switch to idle or waiting for trigger status has happened. table 27-39. command fifo status switching condition (continued) no. from current cfifo status (cfs) to new cfifo status (cfs) status switching condition
enhanced queued analog-to-digital converter (eqadc) 27-86 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note an asserted eoqfx only implies that eqadc has finished transferring a command with an asserted eoq bit fr om cfifox. it does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate rfifo. 27.7.4.7.3 pause status in edge trigger mode, when the eqadc completes the transfer of a cfifo entry with an asserted pause bit, the eqadc will stop future command transfers from the cfifo and set th e corresponding pause flag (pf) in section 27.6.2.7, eqadc fifo and interrupt status regist ers (eqadc_fisr) . refer to section 27.7.2.2, message format in eqadc , for information on command message formats. the eqadc ignores the pause bit in command messages in any software and external level trigger mode. the eqadc sets the pf flag upon detection of an asserted pause bit only in single or continuous-scan edge trigger mode. when the pf flag is set for a cfifo in single-scan edge trigger mode, the sss bit will not be cleared in section 27.6.2.7, eqadc fifo and interru pt status registers (eqadc_fisr) . in level trigger mode, the definition of the pf flag ha s been redefined. in level trigger mode, when cfifox is in triggered status, pfx is set when cfifo st atus changes from trigge red due to detection of a closed gate. the pause flag interrupt routine can be used to verify if the a complete scan of the cqueue was performed. if a closed gate is detected while no command transfers are taking place, it will have immediate effect on the cfifo status. when pie in section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) , and pf are asserted, the eqadc will generate a pause interrupt request. note in edge trigger mode, an asserted pfx only implies that the eqadc finished transferring a command with an asserted pause bi t from cfifox. it does not imply that result data for the cu rrent command and for all previously transferred commands has been returned to the appropriate rfifo. note in software or level trigger mode, wh en the eqadc completes the transfer of an entry from cfifox wi th an asserted pause bit, pfx will not be set and command transfers will c ontinues without pausing. 27.7.4.7.4 trigger overrun status note when a cfifo is configured for edge- or level-trigger mode an d is in triggered state, an additional trigger occurring for the same cfifo results in a trigge r overrun. the trigge r overrun bit for the corresponding cfifo will be set (torf x = 1) in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) . when torie in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) , and torf are asserted, the eqadc gene rates a trigger overrun interrupt request. for cfifos configured for level-trig ger mode, a trigger overrun does not occur.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-87 pxr40 microcontroller reference manual, rev. 1 note the trigger overrun flag will not set for cfifos configured for software trigger mode. 27.7.4.7.5 command sequence n on-coherency detection the eqadc provides a mechanism to indicate if a command sequence has been completely executed without interruptions. a command se quence is defined as a group of consecutive commands bound for the same cbuffer and it is expected to be executed wi thout interruptions. a comma nd sequence is coherent if its commands are executed in order without interr uptions. since commands are stored in the cbuffers before being executed in the eqadc, a command se quence is coherent if, wh ile it is transferring commands to a cbuffer, the buffer is only fed with commands from th at sequence without ever becoming empty. a command sequence starts when: ? a cfifo in triggered state transf ers its first command to cbuffer. ? the cfifo is constantly transferring comma nds and the previous command sequence ended. ? the cfifo resumes command tran sfers after being interrupted. and a command sequence ends when: ? an asserted eoq bit is detected on the last transferred command. ? cfifo is in edge-trigger mode and asserted pause bit is detected on the last transferred command. ? the cbuffer to which the next command is bound is different from the one to which the last command was transferred. figure 27-57 shows examples of how the eqadc would de tect command sequences when transferring commands from a cfifo to a cbuffer. the smalle st possible command sequence can have a single command as shown in example 3 of figure 27-57 .
enhanced queued analog-to-digital converter (eqadc) 27-88 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-57. command sequence examples the ncf flag is used to indicate command sequence non- coherency. when the ncfx flag is asserted, it indicates that the command seque nce being transferred through cfif ox became non-coherent. the ncf flag only becomes asserted fo r cfifos in triggered state. a command sequence is non-coherent when, after tran sferring the first comma nd of a sequence from a cfifo to a cbuffer, it cannot successi vely send all the other commands of the sequence before any of the following conditions are true: cf5_cb1_cm0 cf5_cb1_cm1 cf5_cb1_cm2 cf5_cb1_cm3 (pause =1) cf5_cb1_cm4 cf5_cb1_cm5 cf5_cb1_cm6 (eoq =1) cf5_cb1_cm0 cqueue with a three cf5_cb1_cm1 cf5_cb1_cm2 cf5_cb0_cm3 cf5_cb0_cm4 cf5_cb1_cm5 cf5_cb1_cm6 (eoq =1) command sequences cf5_cb1_cm0 cqueue with a seven cf5_cb2_cm1 cf5_cb3_cm2 cf5_cb1_cm3 cf5_cb0_cm4 cf5_cb2_cm5 cf5_cb1_cm6 (eoq =1) command sequences example 3 example 1 example 2 cqueue with a two command sequences assuming that these commands are tr ansferred by a cfifo configured for edge trigger mode and the command transfers are never interrupted, the eqadc would check for non-coher ency of two command sequences: one formed by commands 0, 1, 2, 3, and the other by commands 4, 5, 6. assuming that command transfers from the cfifo are never interrupted, the eqadc would check for non-c oherency of three command sequences. the first being formed by commands 0, 1, 2, the second by commands 3, 4 and the third by commands 5, 6. note that even when the commands of this cqueue are transferred through a cfifo in continuous-scan mode, the first three commands and the last two commands of this cqueue would still constitute two distinct co mmand sequences, although they are all bound for the same cbuffer, since an asserted eoq ends a command sequence. the eqadc would check for non-coherency of seven command sequences, all containing a single co mmand, but ncf would never get set. cf x _cb a _cm n - command n in cfifo x bound for cbuffer a
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-89 pxr40 microcontroller reference manual, rev. 1 ? the cfifo through which commands are being tr ansferred is preempted by a higher priority cfifo which sends commands to the same cbuffer . the ncf flag becomes asserted immediately after the first command tran sfer from the preempting cfifo, that is the highe r priority cfifo, to the cbuffer in use is completed. see figure 27-58 . once command transfers restart/cont inue, the non-coherency hardware will behave as if the command sequence started fr om that point. figure 27-59 depicts how the non-coherency hardware will behave when a non-coherency event is detected. note if modex is changed to disabled wh ile a cfifo is transferring commands, the ncf flag for that cfifo will not become asserted.
enhanced queued analog-to-digital converter (eqadc) 27-90 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-58. non-coherency event when different cfifos use the same cbuffer * tnxtptr - transfer next data pointer tnxtptr * cf5_cb1_cm0 0 cf5_cb1_cm1 1 cf5_cb1_cm2 2 cf5_cb1_cm3 3 cf0_cb1_cm0 0 cf0_cb1_cm1 1 cf0_cb1_cm2 2 cf0_cb1_cm3 3 tnxtptr * empty 0 empty 1 cbuffer1 cfifo5 cfifo0 tnxtptr * sent 0 sent 1 cf5_cb1_cm2 2 cf5_cb1_cm3 3 cf0_cb1_cm0 0 cf0_cb1_cm1 1 cf0_cb1_cm2 2 cf0_cb1_cm3 3 tnxtptr * cf5_cb1_cm0 0 cf5_cb1_cm1 1 cbuffer1 cfifo5 cfifo0 tnxtptr * sent 0 sent 1 cf5_cb1_cm2 2 cf5_cb1_cm3 3 sent 0 cf0_cb1_cm1 1 cf0_cb1_cm2 2 cf0_cb1_cm3 3 tnxtptr * cf5_cb1_cm1 0 cf0_cb1_cm0 1 cbuffer1 cfifo5 cfifo0 (a) cfifo0 and cfifo5 both have commands to be sent to cbuffer1, and both are not triggered (b) cfifo5 becomes triggered and transfers two commands to cbuffer1 (c) cfifo0 becomes triggered and transfers a command to cbuffer1. the sequence sent through cf x _cb a _cm n - command n in cfifo x bound for cbuffer a cfifo5 becomes non-coherent.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-91 pxr40 microcontroller reference manual, rev. 1 figure 27-59. non-coherency detection when transfers from a command sequence are interrupted 27.7.5 eqadc result fifos 27.7.5.1 rfifo basic functionality there are six rfifos located in th e eqadc. each rfifo is four entr ies deep, and each rfifo entry is 16 bits long. each rfifo serv es as a temporary storage location for the one of the rque ues allocated in system memory. result data is saved in the rfifos before being moved into the system rqueues. when an rfifo is not empty, the eqadc sets the co rresponding rfdf bit in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) . if rfde is asserted in section 27.6.2.6, eqadc interrupt and dma control registers (eqadc_idcr) , the eqadc generates a request so that an rfifo entry is moved to the rqueue. an interrupt request, served by the host cpu, is generate d when rfds is negated, and a dma request, served by the dm ac, is generated when rfds is asserted. the host cpu or the dmac responds to these requests by reading section 27.6.2.4, eqadc result fifo pop registers (eqadc_rfpr) , to retrieve data from the rfifo. note the dmac should be configured to read a single result (16-bit data) from the rfifo pop registers for every a sserted dma request it acknowledges. refer to section 27.8.2, eqadc/dmac interface , for dmac configuration guidelines. note reading a word, a half-word, or any bytes from eqadc_rfprx will pop an entry from rfifox, and the rfctrx field will be decremented by one. figure 27-60 describes the important components in the rfif o. each rfifo is implemented as a circular set of registers to avoid the need to move all entries at each push/po p operation. the pop next data pointer always points to the next rfifo message to be re trieved from the rfifo wh en reading eqadc_rfpr. cf5_cb1_cm0 cf5_cb1_cm1 cf5_cb1_cm2 cf5_cb1_cm3 cf5_cb1_cm4 cf5_cb1_cm5 cf5_cb1_cm6 cf5_cb1_cm7 cf5_cb1_cm8 cf5_cb1_cm9 cf5_cb1_cm10 cf5_cb1_cm11 cf5_cb1_cm12 cf5_cb1_cm13 command sequence became non-c oherent before command 4 was transferred. once command tr ansfers are resumed, eqadc will only check for coherency after command 4. command sequence became non-coherent before command 11 was transferred. once command transfers are resumed, eqadc will only check for coherency after command 11.
enhanced queued analog-to-digital converter (eqadc) 27-92 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the receive next data pointer point s to the next available rfifo locat ion for storing the next incoming message from the on-chip adcs. the rfifo counter logic counts the number of entries in rfifo and generates interrupt or dma requests to drain the rfifo. popnxtptr in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) , indicates which entry is cu rrently being addressed by the pop next da ta pointer, and rfctr, in the same register, provides the number of entries stored in the rfifo. using popnxtptr and rfctr, the absolute addresses for pop next data pointer and recei ve next data pointer can be calculated using the following formulas: pop next data pointer address= rfifox_base_addre ss + popnxtptrx*4 receive next data pointer a ddress = rfifox_base_address + [(popnxtptrx+rfctrx) mod rfifo_depth] * 4 where ? a mod b returns the remainder of the division of a by b . ? rfifox_base_address is the smallest memory mapped address allocated to an rfifox entry. ? rfifo_depth is the number of entries containe d in a rfifo - four in this implementation. when a new message arrives and rfifox is not full, th e eqadc copies its contents into the entry pointed by the receive next data pointer. the rfifo counter rfctrx in section 27.6.2.7, eqadc fifo and interrupt status re gisters (eqadc_fisr) , is incremented by one, and the re ceive next data pointer x is also incremented by one (or wrapped ar ound) to point to the next empty entry in rfifox. however, if the rfifox is full, the eqadc sets the rfof in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) . the rfifox will not overwrite the older data in the rfifo, the new data will be ignored, and the receive next data pointer x is not incremented or wrapped around. rfifox is full when the receive next data pointer x equals the pop next data pointer x and rfctrx is not zero. rfifox is empty when the receive next data pointer x equals the p op next data poin ter x and rfctrx is zero. when the eqadc rfifo pop register x is read an d the rfifox is not empty, the rfifo counter rfctrx is decremented by one, and the pop next data pointer is increm ented by one (or wrapped around) to point to the next rfifo entry. when the eqadc rfifo pop register x is read and rfifox is empty, eqadc will not decrement the counter value and the pop next da ta pointer x will not be updated. the read value will be undefined.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-93 pxr40 microcontroller reference manual, rev. 1 figure 27-60. rfifo diagram the detailed behavior of the pop ne xt data pointer and receive next data pointer is described in the example shown in figure 27-61 where an rfifo with 16 entries is shown for clarity of explanation, the actual hardware implementa tion has only four entries. in this exam ple, rfifox with 16 entries is shown in sequence after popping or receiving entries. data entry 2 data entry 1 -------------------- -------------------- pop next data pointer * receive next data pointer * rfifo pop register data from rfifo counter control logic dma done interrupt/dma request on-chip adcs or from control signals * all rfifo entries are memory mapped and the entries addressed by these pointers can have their ab solute addresses calculated using popnxtptr and rfctr. parallel side interface read from slave-bus interface by cpu or dma
enhanced queued analog-to-digital converter (eqadc) 27-94 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-61. rfifo entry pointer example 27.7.5.2 distributing resu lt data into rfifos data to be moved into the rfifos can come from these sources: adc0, adc1, or the on-chip companion module through the psi. all result data comes with a message_tag field and a dest field defining receive pop rfifox first in after reset or invalidation next data pointer next data pointer last in valid entry empty entry receive pop rfifox some entries received but none popped next data pointer next data pointer pop rfifox no entries received but some popped next data pointer first in last in receive next data pointer receive rfifox entries received until full and none popped next data pointer rfifox no entries received but some popped pop rfifox some entries received and some popped next data pointer first in last in receive next data pointer pop next data pointer first in last in receive next data pointer pop next data pointer first in last in note: x=0, 1, 2, 3, 4, 5
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-95 pxr40 microcontroller reference manual, rev. 1 what should be done with the received data. th e eqadc hardware decodes the message_tag and dest fields and: ? stores the 16-bit data into the appropriate rf ifo if the message_tag indicates a valid rfifo number and dest value is zero, or; ? sends the 16-bit data, the me ssage_tag and the non-zero dest data through the psi to an on-chip companion module (as a decimation filter), or; ? ignores the data in case of a null or ?reserved for customer us e? message_tag and dest value is zero. in general received data is moved into rfifos as they become avai lable, while an exception happens when multiple results from different sources become availabl e at the same time. in that case, result data from adc0 is processed first, result data from adc1 is only process after all adc0 data is processed, and finally returned data from the companion module is pr ocessed (after all data fr om adc0/1 is processed). when time-stamped results return from the on-chip adcs, the conversion result and the time stamp are always moved to the rfifos in cons ecutive clock cycles in order to gua rantee they are always stored in consecutive rfifo entries. 27.7.6 on-chip adc configuration and control 27.7.6.1 enabling and disabling the on-chip adcs the on-chip adcs have an enable bit (adc0/1_en) in the section 27.6.3.1, adc0/1 control registers (adc0_cr and adc1_cr) , which allows the enabling of the adcs only when necessary. when the enable bit for an adc is negated, the clock input to that adc is st opped. the adcs are disabled out of reset - adc0/1_en bits are negated - to allow for their safe configurati on. the adc must only be configured when its enable bit is negated. once the en able bit of an adc is a sserted, clock input to is started. note conversion commands sent to the cbuf fer of a disabled adc are ignored by the adc control hardware. note a 8ms wait time from vdda power up to enabling adc is required to pre-charge the external 100nf capacit or on refbypc pin. this time must be guaranteed by crystal startup time plus reset duration or user. the adc internal bias generato r circuit will start up after 10us upon vrh/vrl and vdda/vssa power up and produces a stab le/required bias current to the pre-charge circuit, but the current to other analog circuits are disabled until adcs are enabled. as soon as the adcs ar e enabled, the bias currents to all of analog circuits will be enabled.
enhanced queued analog-to-digital converter (eqadc) 27-96 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note due to legacy reasons, the eqadc will always wait 120 adc clocks before issuing the first conversion command following the enabling of one of on-chip adcs, or the exiting of st op mode. there are two independent counters checking for this delay: one clocked by adc0_clk and another by adc1_clk. conversion commands can start to be executed whenever one of these counters comple tes counting 120 adc clocks. 27.7.6.2 adc clock and conversion speed the clock input to the adcs is defined by sett ing the adc0/1_clk_sel and the adc0/1_clk_ps fields in the adc0_cr and adc1_cr. when the ad c0/1_clk_sel is set, the adc clock frequency is the same as the platform clock, but it has the i nverted phase. when it is clear, the adc0/1_clk_ps field selects the clock divide fa ctor by which the platform clock will be divided as showed in table 27-22 . the adc clock frequency is calculated as below and should be lower than the maximum value specified to the adc analog block. this is also the maximum frequency of platform clock when the adc0/1_clk_sel is asserted. figure 27-62 depicts how the adc clocks fo r adc0 and adc1 are generated. figure 27-62. adc0/1 clock generation adcclockfrequency platformclockfrequency mhz ?? platformclockdividefactor ------------------------------------------------------------------------------------- - adcclockfrequency 15 mhz ? ?? ; = divide by: 2, 4, 6, .. , 60, 62, 64 adc0 control register adc0_clk_ps to adc0 platform clock divider platform clock adc0clock sel adc0_clk_sel divide by: 2, 4, 6, .. , 60, 62, 64 adc1 control register adc1_clk_ps to adc1 platform clock divider platform clock adc1clock sel adc1_clk_sel
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-97 pxr40 microcontroller reference manual, rev. 1 the adc conversion speed (in k sa mples per second - ksps ) is calculated by the following formula. t he number of sampling cycles is determined by the lst bits in the command message ? see conversion command format for the standard configuration ? and it can take one of the following values: 2, 8, 64, or 128 adc clock cycles. the number of ad conversion cycles is 13 for differential conversions and 14 for single-ended conversions (12 bits resolution and unitary input gain). the maximum conversion speed is achieved when the adc clock frequency is set to its maximum, the number of sampling cycles set to its minimum (2 cycles), and the resolution is also se t to the minimum (8 bits) with input unitary gain. table 27-40 shows an example of how the adc0/1_clk_ps can be set when usi ng a 120 mhz platform clock and the corresponding conversion speeds for all possible adc clock frequencies. the table also shows that according to the platform clock frequency, certain clock divide fact ors are invalid (2, 4, 6, 8 clock divide factors in the example) since their use would result in a adc clock fre quency higher than the maximum one supported by the adc. in this example, the maximum adc clock frequency is 15 mhz (12 bits resolution conversions with unitary input gain). table 27-40. adc clock configuration example (platform clock frequency=120 mhz) adc0/1_clk_ps[0:4] platform clock divide factor adc clock (platform clock = 120 mhz) differential conversion speed with default sampling time (2 cycles) single-ended conversion speed with default sampling time (2 cycles) 0b00000 2 n/a n/a n/a 0b00001 4 n/a n/a n/a 0b00010 6 n/a n/a n/a 0b00011 8 15.0 mhz 1.0 msps 938 ksps 0b00100 10 12.0 mhz 800 ksps 750 ksps 0b00101 12 10.0 mhz 667 ksps 625 ksps 0b00110 14 8.57 mhz 571 ksps 536 ksps 0b00111 16 7.5 mhz 500 ksps 469 ksps 0b01000 18 6.67 mhz 444 ksps 417 ksps 0b01001 20 6.0 mhz 400 ksps 375 ksps 0b01010 22 5.45 mhz 364 ksps 341 ksps 0b01011 24 5.0 mhz 333 ksps 313 ksps 0b01100 26 4.62 mhz 308 ksps 288 ksps 0b01101 28 4.29 mhz 286 ksps 268 ksps 0b01110 30 4.0 mhz 267 ksps 250 ksps 0b01111 32 3.75 mhz 250 ksps 234 ksps 0b10000 34 3.53 mhz 235 ksps 221 ksps 0b10001 36 3.33 mhz 222 ksps 208 ksps 0b10010 38 3.16 mhz 211 ksps 198 ksps 0b10011 40 3.0 mhz 200 ksps 188 ksps 0b10100 42 2.86 mhz 190 ksps 179 ksps 0b10101 44 2.73 mhz 182 ksps 170 ksps adcconversionspeed adcclockfrequency mhz ?? numberofsamplingcycles numb erofadconversioncycles + ?? ------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------- =
enhanced queued analog-to-digital converter (eqadc) 27-98 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.7.6.3 time stamp feature the on-chip adcs can provide a time stamp for the conversions they execute. a time st amp is the value of the time base counter latched when the eqadc detects the end of the analog input voltage sampling. a time stamp for a conversion co mmand is requested by setting the tsr bit in the corresponding command. when tsr is negated, that is a time stamp is not requeste d, the adc returns a single result message containing the conversion resu lt. when tsr is asserted, that is a time stamp is requested, the adc returns two result messages; one containing the conversion result, and afterwards another containing the time stamp for that conversion. the result messages are sent in th is order to the rfifos and both messages are sent to the same rfifo was specifi ed in the message_tag field of the executed conversion command. the time base counter is a 16-bit up counter that wraps after reaching 0xf fff. it is disabled after reset and it is enabled according to the setting of tbc_clk_ps field in section 27.6.3.2, adc time stamp control register (adc_tscr) . tbc_clk_ps defines if the counter is enabled or disabled, and, if enabled, at what frequency it is incremented. th e time stamps are returned regardless of whet her the time base counter is enabled or disabled. th e time base counter can be reset by writing 0x0000 to the section 27.6.3.3, adc time base counter registers (adc_tbcr) , with a write configuration command. 27.7.6.4 adc pre-gain feature each adc can be configured to have a selectable input gain as defined in section 27.6.3.6, alternate configuration 1-8 contro l registers (adc_acr1-8) . this means the input si gnal is sampled and the result is amplified by factor 2, or 4 before the conversion phase. in present implementation of this feature, the conversion is 1 or 2 adc clock cycles longer for gain 2 or gain 4, respectively. 27.7.6.5 adc resolution selection feature the adcs conversion resolutions can be 8 bi ts, 10 bits or 12 bits as described in section 27.6.3.6, alternate configuration 1-8 co ntrol registers (adc_acr1-8) . for conversions at a resolution less than 12, the adc is executing less operations a nd the conversion time is smaller. in this adc, it is verified that 0b10110 46 2.61 mhz 174 ksps 163 ksps 0b10111 48 2.5 mhz 167 ksps 156 ksps 0b11000 50 2.4 mhz 160 ksps 150 ksps 0b11001 52 2.31 mhz 154 ksps 144 ksps 0b11010 54 2.22 mhz 148 ksps 139 ksps 0b11011 56 2.14 mhz 143 ksps 134 ksps 0b11100 58 2.07 mhz 138 ksps 129 ksps 0b11101 60 2.0 mhz 133 ksps 125 ksps 0b11110 62 1.94 mhz 129 ksps 121 ksps 0b11111 64 1.88 mhz 125 ksps 117 ksps table 27-40. adc clock configuration example (p latform clock frequenc y=120 mhz) (continued) adc0/1_clk_ps[0:4] platform clock divide factor adc clock (platform clock = 120 mhz) differential conversion speed with default sampling time (2 cycles) single-ended conversion speed with default sampling time (2 cycles)
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-99 pxr40 microcontroller reference manual, rev. 1 there is 1 adc clock cycle for each bit of resolution. therefore, for the same adc clock frequency, the adc sample frequency is higher for lower resolutions. 27.7.6.6 adc calibration feature 27.7.6.6.1 overview there are three sets of calibration coefficients for ea ch adc. each set is composed by a gain factor and an offset factor: gccn/occn, altgccn1/altg ccn1, and altgccn2/altgccn2, where n is the adc number 0 or 1. the pair gccn/occn is selected when it is used the normal configuration or the alternate configurations 3 to 8. the pair altg ccn1/altgccn1 is used onl y when the alternate configuration 1 is selected. and the pair altgccn2/altgccn2 is for the alternate configuration 2. the description below is for a generi c pair of gain/offset gcc/occ. the eqadc provides a calibrati on scheme to remove the ef fects of gain and offset errors from the results generated by the on-chip adcs. only results genera ted by the on-chip adcs are calibrated. the results generated by adcs on the external device are directly sent to rfifos unchanged. the main component of calibration hardware is a multip ly-and-accumulate (mac) unit, one pe r on-chip adc, that is used to calculate the following transfer f unction which relates a calibrated re sult to a raw, uncalibrated one. cal_res = gcc * raw_res + occ+2; where: ? cal_res is the calibrated resu lt corresponding the input voltage v i . ? gcc is the gain calibration constant. ? raw_res is the raw, uncalibrated result with resolution adjustment corresponding to an specific input voltage v i . ? occ is the offset calibration constant. ? the addition of two reduces the maximu m quantization error of the adc. see section 27.8.6.3, quantization error reduc tion during calibration . calibration constants gcc and occ are determined by taking two samples of known reference voltages and using these samples to calculate the values for the constants. for details and an example about how to calculate the calibration constants and us e them in result calibration refer to section 27.8.6, adc result calibration . once calculated, gcc is stored in the section 27.6.3.4, adc0/1 gain calibration constant registers (adc0_gccr and adc1_gccr) , and occ in section 27.6.3.5, adc0/1 offset calibration constant registers ( adc0_occr and adc1_occr) , from where their values are fed to the mac unit. the alternate gain values are stored in section 27.6.3.7, adc0/1 alternate gain registers (adc0_agr1-2 and adc1_agr1-2) , and the alternate offset values in section 27.6.3.8, adc0/1 alternate offset register (adc0_aor1-2 and adc1_aor1-2) . since the analog characteristics of each on-chip adcs differs, each adc has an i ndependent pair of calibration constants. a conversion result is calibrated ac cording to the status of cal bit in the command that initiated the conversion. if the cal bit is asserte d, the eqadc will automati cally calculate the calibrated result before sending the result to the appropriate rfifo or companion module. if the cal bit is negate d, the result is not calibrated, it bypasses the calibration hardware, and is directly sent to th e appropriate rfifo or companion module.
enhanced queued analog-to-digital converter (eqadc) 27-100 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.7.6.6.2 mac unit and operand data format the mac unit diagram is shown in figure 27-63 . each on-chip adc has a sepa rate mac unit to fine-tune its conversion results. the descripti on below considers the general calibra tion constant registers but it is the same for the alternate calibration constants. the occ0/1 operand is a 14-bit signed value stored in the section 27.6.3.5, adc0/1 offset calibration constant registers (a dc0_occr and adc1_occr) . the raw_res operand is the raw uncalibrated result, and it is the direct output from the on-chip adcs but passing through the resolution adjustment block. the gcc0/1 operand is a 15-bit fixe d point unsigned value stored in the section 27.6.3.4, adc0/1 gain calibration constant regi sters (adc0_gccr and adc1_gccr) . the gcc is expressed in the gcc_int.gcc_frac binary format. the intege r part of the gcc (gcc_int= gcc[1]) contains a single binary digit while its fractional part (g cc_frac=gcc[2:15]) cont ains 14 bits - see figure 27-64 . the gain constant equivalent decimal value ranges fro m 0 to 1.999938..., as shown in table 27-41 . two is always added to the mac output - see section 27.8.6.3, quantization erro r reduction during calibration . cal_res output is the calibrated result, and it is a 14-bit unsigned value. cal_res is truncated to 0x3fff, in case of a overflow, and to 0x0000, in case of an underflow. figure 27-63. mac unit diagram gcc_int - integer part of the gain calibration constant for adc0/1 gcc_int is the integer part of the gain calibration constant for adc0/1. gcc_frac[1:14] - fractional part of th e gain calibration constant for adc0/1 gcc_frac is the fractional part of the gain calibration constant for adc0/1. gcc_frac can expresses decimal values ranging from 0 to 0.999938... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 gcc_int gcc_frac gcc[1] gcc[2:15] figure 27-64. gain calibration constant format mac unit calibrated result (cal_res) (14-bit unsigned value) raw uncalibrated result (raw_res) (12-bit unsigned value) gain calibration constant (gcc0/1) (15-bit fixed point unsigned value from adc0/1_gccr register) offset calibration constant (occ0/1) (14-bit signed value from adc0/1_occr register) + 2
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-101 pxr40 microcontroller reference manual, rev. 1 27.7.6.7 adc control logic overview and command execution figure 27-65 shows the basic logic blocks involved in the adc control and how they interact. cfifos/rfifos interact with cbuffers/ abort cont / result message return logic through the fifo control unit . the eb and bn bits in the command message uniquely identify the cbuffer to which a command should be sent. the fifo control unit decodes these bits and se nds the adc command to the proper cbuffer. other bl ocks of logic are the resolution adjustment , result format and calibration sub-block , the time stamp logic, and the mux control logic . the resolution adjustment sub-block receives the 12-bit data bus directly from th e adc and changes the received conversion results fr om right aligned format of adc to the left aligned format depending on the selected resolution of the conversi on. this operation helps the calibratio n processing to us e the calibration coefficients always with the same format. the result format and ca libration sub-block formats the returning data in to result messages and sends them to the rfifos 1 . the returning data can be da ta read from an adc regist er, a conversion result, or a time stamp. the formatting and calibration of conversi on results also take place inside this sub-block. the time stamp logic latches the value of the time base counter when detecting the end of the analog input voltage sampling, and sends it to the result format and calibration sub-block as time stamp information. the mux control logic generates the proper mux control signa ls and, when the adc0/1_emux bits are asserted, the ma signals based on the channel numbers ex tracted from the adc command. when the on-chip adc abort feature is not enabled, ad c commands are stored in the cbuffers as they come and they are executed in the first-in-first-out basis. after the execution of a command in entry1 finishes all commands are shifted one entry. after the shift, entry0 is always empty and ready to receive a new command. execution of confi guration commands only start when they reach entry1. consecutive conversion commands are pi pelined and their execution can start while in entry0. this is explained below. table 27-41. binary and decimal representations of the gain constant gain constant (gcc_int.gcc_frac binary format) corresponding decimal value 0.0000_0000_0000_00 0 ... ... 0.1000_0000_0000_00 0.5 ... ... 0.1111_1111_1111_11 0.999938... 1.0000_0000_0000_00 1 ... ... 1.1100_0000_0000_00 1.75 ... ... 1.1111_1111_1111_11 1.999938... 1. the result messages may also be routed to an on-chip companion module via the side interface, and then fed back to the rfifos.
enhanced queued analog-to-digital converter (eqadc) 27-102 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ad conversion accuracy can be affected by the settling time of the input channel mult iplexers. some time is required for the channel multiplexe rs internal capacitances to settle after the channel number is changed. if the time prior to sampling is not long enough to absorb this settling, then the settling time will take from adc sampling time which may result in inaccurate samp ling and ultimately compromise conversion result accuracy - see figure 27-66 (a). the eqadc attempts to compensate for this settling time by switching the multiplexers in preparation for the next conversion command's sampling while performing the previous conversion ( figure 27-66 (b)). in eqadc, this is done in the following way; when a conversion command is in buffer entry1 and another conversion command is id entified in entry0, then the channel number of entr y0 is sent to the mux control logic some cycles before the sampling phase of the command in entry0 starts. in this way, sampli ng for the next command can promptly start after the current conversion finishes because th e internal capacitance of the multiplexers will be settled by that time, allowing for more accurate sampling. this is special ly important for applications that require high conversion speeds, that is with the adc running at maximum clock fr equency and with the analog input voltage sampling time set to a minimum (2 adc cloc k cycles), when the shor t sampling time does not allow the multiplexers to completely settle. the s econd advantage of pipelini ng conversion commands is to provide precise conversion intervals, which me ans the time intervals between two consecutive conversions are the same. this is important for any digita l signal process application. when the on-chip adc abort feature is enabled, adc commands from cfifo0 should be considered immediately, even stopping the execu tion of some command that is al ready in entry1. when the abort request is sent to the adc, the alr eady stored commands in the cbuffers are copied in a temporary set of registers. the first adc command from cfifo0 is sent after the abort acknow ledge indication from adc. the process is the same as usual unt il the transfer of the last comma nd from cfifo0. then the temporarily stored commands that were postpone d by the abortion are reco vered and they are pi pelined for execution. after the last command from this te mporary memory is transferred, the next commands are pipelined from the cfifos.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-103 pxr40 microcontroller reference manual, rev. 1 figure 27-65. on-chip adc control scheme channel_number1 mux 40:1 adc0 adc1 cfifox rfifox mux 40:1 bias gen mux an0-an39 refbypc control 16 bits time stamp result1 time stamp 0 result0 tsr0 message_tag1; fmt1, cal1 emux1 tbc_clk_ps 32 bits ma0, ma1, ma2 entry1 entry0 configuration entry1 entry0 tsr1 addr or/and data addr or/and data register data 0/1 channel_number0 time stamp1 registers cbuffer1 cbuffer0 logic logic fifo control unit emux0 register field words in shaded boxes represent configuration register fields adc1_result1 adc0_result0 lst1 lst0 note: x=0, 1, 2, 3, 4, 5 result format message_tag0; fmt0, cal0 pre-charge ref gen psi abort cont abort cont resolution adjust resolution adjust
enhanced queued analog-to-digital converter (eqadc) 27-104 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-66. overlapping consecutive conversion commands 27.7.7 internal/external multiplexing 27.7.7.1 channel assignment the internal analog multiplexers select one of the 40 analog input pins for conversion, based on the channel_number field of a command message. th e analog input pin cha nnel number assignments and the pin definitions vary depending on how the adc0/1_emux are configure d. allowed combinations of adc0/1_emux bits are shown in table 27-42 together with references to tables indicating how channel_number field of each conversion comma nd must be set to avoid channel selection conflicts.in addition to this master multiplexer, each adc is equi pped with a secondary multiplexer that are used to monitor signals internal to the chi p. these analog input pins are also selected by the channel_number field. channel # change and sample start (a) command execution sequence for two non-overlapped commands (b) command execution sequence for two overlapped commands minimum time necessary to perform a single conversion after channel number is changed channel # change and sample start ad conversion mux settle time and sampling ad conversion mux settle time and sampling conversion starts imm ediately after channel # change.adc sample time should compensate for mux internal capacitance settling and for the sampling on the sampling capacitor. if sample time is not long enough, this can lead to inaccurate conversion results. ad conversion change channel # mux settle time and sampling channel # change and sample start ad conversion sampling sample start channel # changes before sampling starts leading to more time for mux internal capacitance to settle. mux settle time
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-105 pxr40 microcontroller reference manual, rev. 1 during differential conversions the analog multiplexer passes differenti al signals to both the positive and negative terminals of the adc. th e differential conversions can only be initiated on fo ur channels: dan0, dan1, dan2, and dan3. for each value of chann el_number, this table lists the adcs you can use to perform conversions for that channel (which you specify using bn ), whether external multiplexing (specified by adcx_cr[emux]) must be disabled or enabled to access the channel, and the assigned analog input signal and conversion type. ? more than one adc can access the sa me analog input, but not at the same time. ? when one adc is performing a differen tial conversion on a pair of pins, another adc must not access either of those two pins as single-ended channels. table 27-42. multiplexed and non-multiplexed channel assignments channel_number adcs (bn) adcx_cr[emux] analog input signal conversion type (b) (d) 0000_0000 0 0, 1 x an0 (accessible when dan0+ and dan0? are not being accessed) single-ended 0000_0001 1 0, 1 x an1 (accessible when dan0+ and dan0? are not being accessed) single-ended 0000_0010 2 0, 1 x an2 (accessible when dan1+ and dan1? are not being accessed) single-ended 0000_0011 3 0, 1 x an3 (accessible when dan1+ and dan1? are not being accessed) single-ended 0000_0100 4 0, 1 x an4 (accessible when dan2+ and dan2? are not being accessed) single-ended 0000_0101 5 0, 1 x an5 (accessible when dan2+ and dan2? are not being accessed) single-ended 0000_0110 6 0, 1 x an6 (accessible when dan3+ and dan3? are not being accessed) single-ended 0000_0111 7 0, 1 x an7 (accessible when dan3+ and dan3? are not being accessed) single-ended 0000_1000 8 0, 1 x an8 (see also anw) single-ended 0000_1001 9 0, 1 x an9 (see also anx) single-ended 0000_1010 10 0, 1 x an10 (see also any) single-ended 0000_1011 11 0, 1 x an11 (see also anz) single-ended 0000_1100 to 0000_1111 12 to 15 0, 1 x an12 to an15 single-ended 0001_0000 16 0, 1 x an16 (see also anr) single-ended 0001_0001 17 0, 1 x an17 (see also ans) single-ended 0001_0010 18 0, 1 x an18 (see also ant) single-ended 0001_0011 19 0, 1 x an19 (see also anu) single-ended
enhanced queued analog-to-digital converter (eqadc) 27-106 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0001_0100 to 0010_0111 20 to 39 0, 1 x an20 to an39 single-ended 0010_1000 40 0, 1 x vrh single-ended 0010_1001 41 0, 1 x vrl single-ended 0010_1010 42 0, 1 x 50% ? (vrh ? vrl) (do not use for calibration) single-ended 0010_1011 43 0, 1 x 75% ? (vrh ? vrl) (used for calibration) single-ended 0010_1100 44 0, 1 x 25% ? (vrh ? vrl) (used for calibration) single-ended 0010_1101 45 0 x ina_adc0_0 (see table 27-4 ) single-ended 0010_1101 45 1 x ina_adc1_0 (see table 27-4 ) single-ended 0010_1110 to 0011_1111 46 to 63 (reserved) 0100_0xxx 64 to 71 0, 1 1 anw (the ma2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an8) single-ended 0100_1xxx 72 to 79 0, 1 1 anx (the ma2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an9) single-ended 0101_0xxx 80 to 87 0, 1 1 any (the ma2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an10) single-ended 0101_1xxx 88 to 95 0, 1 1 anz (the ma2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an11) single-ended 0110_0000 96 0, 1 x dan0+ and dan0? (accessible when a0 and a1 are not being accessed) differential 0110_0001 97 0, 1 x dan1+ and dan1? (accessible when a2 and a3 are not being accessed) differential 0110_0010 98 0, 1 x dan2+ and dan2? (accessible when a4 and a5 are not being accessed) differential 0110_0011 99 0, 1 x dan3+ and dan3? (accessible when a6 and a7 are not being accessed) differential 0110_0100 to 0111_1111 100 to 127 (reserved) 1000_0000 128 0 x ina_adc0_1 (see table 27-4 ) single-ended 1000_0000 128 1 x ina_adc1_1 (see table 27-4 ) single-ended 1000_0001 129 0 x ina_adc0_2 (see table 27-4 ) single-ended 1000_0001 129 1 x ina_adc1_2 (see table 27-4 ) single-ended table 27-42. multiplexed and non-multiplexed channel assignments (continued) channel_number adcs (bn) adcx_cr[emux] analog input signal conversion type (b) (d)
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-107 pxr40 microcontroller reference manual, rev. 1 27.7.7.2 external multiplexing the eqadc can use from one to eight external mult iplexer chips to expand th e number of analog signals that may be converted. up to 64 analog channels can be converted through external multiplexer selection. 1000_0010 to 1000_1111 130 to 143 (reserved) 1001_0000 144 0 x ina_adc0_9 (see table 27-4 ) single-ended 1001_0000 144 1 x ina_adc1_9 (see table 27-4 ) single-ended 1001_0001 to 1010_0001 145 to 161 (reserved) 1010_0010 162 x 0 ina_adc0_3 (see table 27-4 ) single-ended 1010_0011 163 x 0 ina_adc0_4 (see table 27-4 ) single-ended 1010_0100 164 x 0 ina_adc0_5 (see table 27-4 ) single-ended 1010_0101 165 x 0 ina_adc0_6 (see table 27-4 ) single-ended 1010_0110 166 x 0 ina_adc0_7 (see table 27-4 ) single-ended 1010_0111 167 x 0 ina_adc0_8 (see table 27-4 ) single-ended 1010_1000 to 1100_0001 168 to 193 (reserved) 1100_0010 194 x 0 ina_adc1_3 (see table 27-4 ) single-ended 1100_0011 195 x 0 ina_adc1_4 (see table 27-4 ) single-ended 1100_0100 196 x 0 ina_adc1_5 (see table 27-4 ) single-ended 1100_0101 197 x 0 ina_adc1_6 (see table 27-4 ) single-ended 1100_0110 198 x 0 ina_adc1_7 (see table 27-4 ) single-ended 1100_0111 199 x 0 ina_adc1_8 (see table 27-4 ) single-ended 1100_1000 to 1101_1111 200 to 223 (reserved) 1110_0xxx 224 to 231 0, 1 1 anr (the ma 2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an16) single-ended 1110_1xxx 232 to 239 0, 1 1 ans (the ma2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an17) single-ended 1111_0xxx 240 to 247 0, 1 1 ant (the ma2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an18) single-ended 1111_1xxx 248 to 255 0, 1 1 anu (the ma 2?ma0 pins act as the selector inputs for an external 8-to-1 mux; see also an19) single-ended table 27-42. multiplexed and non-multiplexed channel assignments (continued) channel_number adcs (bn) adcx_cr[emux] analog input signal conversion type (b) (d)
enhanced queued analog-to-digital converter (eqadc) 27-108 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the externally multiplexed channels are automati cally selected by the channel_number field of a command message, in the same way done with internal ly multiplexed channels. the software selects the external multiplexed mode by setting the ad c0/1_emux bit in eith er adc0_cr or adc1_cr depending on which adc will perform the conversion. table 27-43 shows the channel number assignments for the multiplexed mode. there are 4 di fferential pairs, 39 single-ended, and, at most, 64 externally multiplexed channels which can be selecte d. only one adc can have it s emux bit asserted at a time. figure 27-67 shows the maximum configuration of eight ex ternal multiplexer chips connected to the eqadc. the external multip lexer chip selects one of eight analog inputs and c onnects it to a single analog output, which is fed to a specific input of the eqadc. the eqadc provides three multiplexed address signals, ma0, ma1, and ma2, to select one of eight inputs. these thr ee multiplexed address signals are connected to all eight external multiplexer chips. th e analog output of the eight multiplex chips are each connected to eight separate e qadc inputs, anr, ans, ant, anu, anw, anx, any, and anz. the ma pins correspond to the three least significant bits of th e channel number that se lects anr, ans, ant, anu, anw, anx, any, and anz with ma0 be ing the most significant bit - see table 27-43 . when the external multiplexed mode is selected for either adc, the eqadc automatically creates the ma output signals from channel_ number field of a command me ssage. the eqadc also converts the proper input channel (anr, ans, ant, anu, anw, anx, any, and anz) by interpreting the channel_number field. as a result, up to 64 exte rnally multiplexed channels appear to the conversion queues as dire ctly connected signals. table 27-43. encoding of ma pins 1 notes: 1 ?0? means pin is driven low and ?1? that pin is driven high. channel number selecting anr, ans, ant, anu, anw, anx, any, anz (decimal) ma0 ma1 ma2 anr ans ant anu anw anx any anz 224 232 240 248 64 72 80 88 0 0 0 225 233 241 249 65 73 81 89 0 0 1 226 234 242 250 66 74 82 90 0 1 0 227 235 243 251 67 75 83 91 0 1 1 228 236 244 252 68 76 84 92 1 0 0 229 237 245 253 69 77 85 93 1 0 1 230 238 246 254 70 78 86 94 1 1 0 231 239 247 255 71 79 87 95 1 1 1
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-109 pxr40 microcontroller reference manual, rev. 1 figure 27-67. example of external multiplexing ma0 ma1 ma2 mux an64 an65 an66 an67 an68 an69 an70 an71 mux an72 an73 an74 an75 an76 an77 an78 an79 mux an80 an81 an82 an83 an84 an85 an86 an87 mux an88 an89 an90 an91 an92 an93 an94 an95 anw anx any anz 4 an0-an7 32 40 mux 40:1 mux 40:1 adc0 adc1 mux control channel number0/1 eqadc an12-an15 note: limited availability of pins may result in the sharing of adc inputs and mux outputs. mux an224 an225 an226 an227 an228 an229 an230 an231 mux an232 an233 an234 an235 an236 an237 an238 an239 mux an240 an241 an242 an243 an244 an245 an246 an247 mux an248 an249 an250 an251 an252 an253 an254 an255 anr ans ant anu 4 an20-an39
enhanced queued analog-to-digital converter (eqadc) 27-110 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.7.8 eqadc dma/interrupt request table 27-44 lists methods to generate in terrupt requests in the eqadc queuing control and triggering control. the dma/interrupt request select bits a nd the dma/interrupt enable bits are described in section 27.6.2.6, eqadc interrupt and dm a control registers (eqadc_idcr) , and the interrupt flag bits are described in section 27.6.2.7, eqadc fifo and interr upt status registers (eqadc_fisr) . table 27-68 depicts all interrupts and dma requests gene rated by the eqadc.the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo tr igger overrun interrupt requests of all cfifos are ored to generate single interrupt request from the eqadc. this combined interrupt request is assert ed whenever one of the following flag s becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). table 27-45 describes a list of methods to generate dma requests in the eqadc. table 27-44. eqadc fifo interrupt summary 1 notes: 1 for details refer to section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) , and section 27.6.2.6, eqadc interrupt a nd dma control registers (eqadc_idcr) . interrupt condition clearing mechanism non coherency interrupt nciex = 1 ncfx = 1 clear ncfx bit by writing a ?1? to the bit. result fifo overflow interrupt 2 2 apart from generating an independent interrupt reques t for when a rfifo overflow interrupt, a cfifo underflow interrupt, and a cfifo trigger overrun inte rrupt occurs, the eqadc also provides a combined interrupt request at which these requests from all cfifos are ored. refer to figure 27-68 for details. rfoiex = 1 rfofx = 1 clear rfofx bit by writing a ?1? to the bit. command fifo underflow interrupt 2 cfuiex = 1 cfufx = 1 clear cfufx bit by writing a ?1? to the bit. result fifo drain interrupt rfdex = 1 rfdsx = 0 rfdfx = 1 clear rfdfx bit by writing a ?1? to the bit. command fifo fill interrupt cffex = 1 cffsx = 0 cfffx = 1 clear cfffx bit by writing a ?1? to the bit. end of queue interrupt eoqiex = 1 eoqfx = 1 clear eoqfx bit by writing a ?1? to the bit. pause interrupt piex = 1 pfx =1 clear pfx bit by writing a ?1? to the bit. trigger overrun interrupt 2 toriex = 1 torfx =1 clear torfx bit by writing a ?1? to the bit. table 27-45. eqadc fifo dma summary 1 dma request condition clearing mechanism result fifo drain dma request rfdex = 1 rfdsx = 1 rfdfx = 1 the eqadc automatically clea rs the rfdfx when rfifox becomes empty. writing ?1? to the rfdfx bit is not allowed. command fifo fill dma request cffex = 1 cffsx = 1 cfffx = 1 the eqadc automatically clears the cfffx when cfifox becomes full. writing ?1? to the cfffx bit is not allowed.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-111 pxr40 microcontroller reference manual, rev. 1 notes: 1 for details refer to section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) , and section 27.6.2.6, eqadc interrupt a nd dma control registers (eqadc_idcr) .
enhanced queued analog-to-digital converter (eqadc) 27-112 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-68. eqadc dma and interrupt requests nciex ncfx toriex torfx piex pfx cffex cfffx cfifo fill interrupt request eoqiex eoqfx cfuiex cfufx rfoiex rfofx non coherency interrupt request pause interrupt request end of queue interrupt request trigger overrun interrupt request cfifo underflow interrupt request rfifo overflow interrupt request combined inte rrupt request cffsx rfdex rfdfx rfifo drain interrupt request rfdsx rfdex rfdfx rfifo drain dma request rfdsx dma request generation logic cffex cfffx cfifo fill dma request cffsx dma request generation logic
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-113 pxr40 microcontroller reference manual, rev. 1 27.7.9 analog sub-block 27.7.9.1 analog to digital converter (adc) 27.7.9.1.1 adc architecture figure 27-69. rsd adc block diagram the rsd cyclic adc consists of two main portions, the analog rsd stage, and the digital control and calculation block, as shown in figure 27-69 . to begin an analog to digital conversion, a differential input is passed into the analog rs d stage. the signal is pa ssed through the rsd stage, and then from the rsd stage output, back to its input to be passed again. to complete a 12-bi t conversion, the signal must pass through the rsd stage 12 times. for 10-bit and 8-bit re solution, the signal must pa ss 10 or 8 times through the rsd. each time an input signal is read into the rsd stage, a digital sample is taken by the digital control/calculation block. the digita l control/calculation block uses this sample to tell the analog block how to condition the signal. the digita l block also saves each successive sample and adds them according to the rsd algorithm at the end of the entire conversion cycle. rsd single-stage digital control and calculation pipeline_control sample 12 bit output diff input clock pipeline
enhanced queued analog-to-digital converter (eqadc) 27-114 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.7.9.1.2 rsd overview figure 27-70. rsd stage block diagram on each pass through the rsd stage, the input signal will be multiplied by exactly two, and summed with either -vref, 0, or vref, dependi ng on the logic control. the logic control will determine -vref, 0, or vref depending on the two comp arator inputs. as the logic cont rol sets the summing operation, it also sends a digital value to the rsd adder. e ach time an analog signal passes through the rsd single-stage, a digital value is collected by the rsd a dder. at the end of an entire ad conversion cycle, the rsd adder uses these collected values to calculate the 12-bit/10-bi t/8-bit digital output. figure 27-71 shows the transfer function for the rsd stage. note how the dig ital value (a, b) is dependent on the two comparator inputs. x2 sum vrl vrh input voltage logic control residue voltage + - + - -vref,0,vref digital signal rsd adder
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-115 pxr40 microcontroller reference manual, rev. 1 figure 27-71. rsd stage transfer function in each pass through the rsd stage, the residue will be sent back to be the new input, and the digital signals, a and b, will be stored. for the 12-bit adc, input signal is sampled during the input phase, and after each of the 12 passes throu gh the rsd stage. thus, 13 total a and b values are collected. upon collecting all these values, they will be added according to the rsd algor ithm to create the 12-bit digital representation of the original analog input. the bits are added in the following manner: 27.7.9.1.3 rsd adder the array, s1 to s12,will be the digital output of th e rsd adc with s1 being the msb and s12 being the lsb. vref vref -vref -vref vl vh input voltage residue voltage vres=2vin+vref vres=2vin vres=2vin-vref a=0, b=0 a=0, b=1 a=1, b=0
enhanced queued analog-to-digital converter (eqadc) 27-116 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-72. rsd adder 27.7.9.1.4 variable gain ampl ification (vga) for pre-gain the vga starts after sampling completes. it is enabled by a 2-bit signal pre_gain described in section 27.6.3.6, alternate configuration 1-8 control registers (adc_acr1-8) . the adc takes 2, 8, 64 or 12 8 clock cycles to do sampling which is selected by the lst[0:1] field in the conversion command message. after the sampling, if 2x vga is enabled, there is a 2x gain stage without comparison before the regular conversion cycles. wh en 4x vga is enabled, there are the 2x gain stage without comparison by 2 times before the normal conversion processing. 27.8 initialization/application information 27.8.1 multiple queues control setup example this section provides an example of how to configure multiple cqueues. table 27-46 describes how each cqueue can be used for a differen t application. also documented in th is section are general guidelines on how to initialize the on-chip adcs and the external device, and how to configure the cqueues and the eqadc. table 27-46. application of each cqueue cqueue number cqueue type running speed number of contiguous conversions example 0 very fast burst time-based cqueue every 2 ? s for 200 ? s; pause for 300 ? s and then repeat 2 injector current profiling 1fast hardware-triggered cqueue every 900 ? s 3 current sensing of pwm controlled actuators 2 fast repetitive time-based cqueue every 2 ms 8 throttle position a13 b12 a12 b11 a11 b10 .. .. ... ... a3 b2 a2 b1 ------------- --------------- -------------- s12 s11 s10 ... ... s2 s1 carry +
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-117 pxr40 microcontroller reference manual, rev. 1 27.8.1.1 eqadc initialization the following steps provide an exam ple about how to configure the eqadc controls and how to initialize the on-chip adcs. in this example, all conversi on commands will be tran sferred through cfifo0. 1. load all required configuration commands in the ram in such way that they form a queue; this data structure will be re ferred below as cqueue0. figure 27-73 shows an example of a cqueue able to configure the on-chip adcs at the same time . although, this example uses the dmac to store commands in cfifo0, configurat ion commands could have also been directly written to the cfifo0 push register. 2. select source driving eqadc ha rdware trigger ports (etrig). be fore proceeding to next step, allow some time (minimum of two pl atform clocks - filter period is set to minimum after reset) so that the logic level at the source is filt ered and reaches the eqadc control logic. note etrig ports could be driven by an ex ternal pin or by the output port of other blocks in the device, such as timers. in order to avoid unexpected triggering of cfifos in hardware tr igger modes, the source driving the etrig port must be selected and set to a known logic level before putting the cfifos into the waiting for trigger state. 3. configure section 27.6.2.2, eqadc external trigger digi tal filter register (eqadc_etdfr) . 4. configure the dmac to transfer data from cqueue0 to cf ifo0 in the eqadc. 5. configure section 27.6.2.6, eqadc interrupt and dm a control registers (eqadc_idcr) . a. set cffs0 to configure the eqadc to genera te a dma request to load commands from cqueue 0 to the cfifo0. b. set cffe0 to enable the eqadc to generate a dma request to transfer commands from cqueue0 to cfifo0; command tran sfers from the ram to the cf ifo0 will start immediately. c. set eoqie0 to enable the eqadc to generate an interrupt after transferring all of the commands of cqueue0 through cfifo0. 6. configure section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) . 3 software-triggered cqueue every 3.9 ms 3 command triggered by software strategy 4 repetitive angle-based cqueue every 625 ? s 7 airflow read every 30 degrees at 8000 rpm 5 slow repetitive time-based cqueue every 100 ms 10 temperature sensors table 27-46. application of each cqueue (continued) cqueue number cqueue type running speed number of contiguous conversions example
enhanced queued analog-to-digital converter (eqadc) 27-118 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 a. write 0b0001 to the mode0 field in eqadc_ cfcr0 to program cfifo0 for software single-scan mode. b. write ?1? to sse0 to assert sss0 and trigger cfifo0. 7. since cfifo0 is in single-scan so ftware mode and it is also the highest priority cfifo, the eqadc starts to transfer conf iguration commands to the on-chip adcs and to the external device. 8. when all of the configuration comm ands have been transferred, cf0 in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) , will be set. the eq adc generates a end of queue interrupt. the initializa tion procedure is complete. figure 27-73. example of a cqueue configuring the on-chip adcs/external device the initialization procedure described above does not ge nerate adc clocks that are in phase because the timing at which the adc 0/1_en bits, in the section 27.6.3.1, adc0/1 contro l registers (adc0_cr and adc1_cr) , are set is different. below foll ows an example on how to simulta neously set these bits so that in-phase adc clocks are generated. in this example, adc0/1_clk are c onfigured to the same frequency. 1. push an adc0_cr write configuration comma nd in cfifo0 that enables adc0 (adc0_en=1) and that sets the adc0_clk_ps to an appropriate value. for example, 0x80800801. 2. push an adc1_cr write configuration comma nd in cfifo1 that enables adc1 (adc1_en=1) and that sets the adc1_clk_ps to an appropriate value. for example, 0x82800801. 3. configure cfifo0 and cfifo1 to single scan so ftware trigger mode and simultaneously trigger them by writing 0x04100410 to the eqadc_cfcr0 register - see section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) . 27.8.1.2 configuring eq adc for applications this section provides an exampl e based on the applications in table 27-46 . the example describes how to configure multiple cqueues to be used for those a pplications and provides a st ep-by-step procedure to configure the eqadc and the associated cqueue struct ures. in the example, the ?fast hardware-triggered cqueue?, described on the second row of table 27-46 , will have its commands transferred to cbuffer1; the conversion commands will be executed by adc1. th e generated results will be returned to rfifo3 before being transferred to the rqueues in the ram by the dmac. configuration command to cbuffer0 - ex: write adc0_cr cqueue in 0x0 0x1 0x2 0x3 system memory configuration command to cbuffer2 - ex: writ e to external device configuration register configuration command to cbuffer0 - ex: write adc_tscr configuration command to cbuffer1 - ex: write adc1_cr command address
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-119 pxr40 microcontroller reference manual, rev. 1 note there is no fixed relations hip between cfifos and rfifos with the same number. the results of co mmands being transferred through cfifo1 can be returned to any rfifo, regardless of its number. the destination of a result is determined by the message_tag fiel d of the command that requested the result. see section 27.7.2.2, message format in eqadc , for details. step one: setup the cqueues and rqueues. 1. load the ram with configur ation and conversion commands. table 27-47 is an example of how cqueue1 commands should be set. a. each trigger event will cause four commands to be executed. when the eqadc detects the pause bit asserted, it w ill wait for another trigger to re start transferring commands from the cfifo. b. at the end of the cqueue, the ?e oq? bit is assert ed as shown in table 27-47 . c. results will be returned to rfifo3 as speci fied in the message_tag field of commands. 2. reserve memory space for storing results. table 27-47. example of cqueue commands 1 notes: 1 fields lst, tsr, fmt, and channel_n umber are not showed for clarity. see section , conversion command format for the standard configuration , for details. bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit name eoq paus e rep reserved eb bn reserved message tag adc command cmd 1 0 0 0 0 0 1 0 0b0011 conversion command cmd 2 0 0 0 0 0 1 0 0b0011 conversion command cmd 3 0 0 0 0 0 1 0 0b0011 conversion command cmd 4 0 1 0 0 0 1 0 0b0011 2 2 message_tag field is only defined for read confi guration commands. configure peripheral device for next conversion sequence cmd 5 0 0 0 0 0 1 0 0b0011 conversion command cmd 6 0 0 0 0 0 1 0 0b0011 conversion command cmd 7 0 0 0 0 0 1 0 0b0011 conversion command cmd 8 0 1 0 0 0 1 0 0b0011 2 configure peripheral device for next conversion sequence etc. ........... cmd eoq 1 0 0 0 0 1 0 0b0011 eoq message cfifo header adc command
enhanced queued analog-to-digital converter (eqadc) 27-120 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 step two: configure the dmac to handle data transfers between th e cqueues/rqueues in ram and the cfifos/rfifos in the eqadc. 1. for transferring, set the source a ddress of the dmac to point to the start address of cqueue1. set the destination address of the dmac to point to eqadc_cfpr1. refer to section 27.6.2.3, eqadc cfifo push re gisters (eqadc_cfpr) . 2. for receiving, set the source address of th e dmac to point to eqadc_rfpr3. refer to section 27.6.2.4, eqadc result fifo pop registers (eqadc_rfpr) . set the destination address of the dmac to point to th e starting address of rqueue1. step three: configure th e eqadc control registers. 3. configure section 27.6.2.6, eqadc interrupt and dm a control registers (eqadc_idcr) . a. set eoqie1 to enable the end of queue interrupt request. b. set cffs1 and rfds3 to configure the eqadc to generate dma reque sts to push commands into cfifo1 and to pop result data from rfif03. c. set cfinv1 to invalidate the contents of cfifo1. d. set rfde3 and cffe1 to enable the eqadc to generate dma request s. command transfers from the ram to the cfifo1 will start immediately. e. set rfoie3 to indicate if rfifo3 overflows. f. set cfuie1 to indicate if cfifo1 underflows. 4. configure mode1 to continuous-scan ri sing edge external trigger mode in section 27.6.2.5, eqadc cfifo control registers (eqadc_cfcr) . step four: command transfer to adcs and result data reception. when an external rising edge event occurs fo r cfifo1, the eqadc automatically will begin transferring commands from cfifo1 when it beco mes the highest priority cfifo trying to send commands to cbuffer1. the received results will be placed in rfifo3 and then moved to rqueue1 by the dmac. 27.8.2 eqadc/dmac interface this section provides an overview about the eqadc/dmac interface and general guidelines about how the dmac should be configured in or der for it to correctly transfer data between the queues in system memory and the eqadc fifos. note advanced dmacs provide more functi onality then the ones discussed in this section. 27.8.2.1 cqueue/cfifo transfers in transfers involving cqueues and cfifos, the dm ac moves data from a queued source to a single destination as showed in figure 27-74 . the location of the data to be moved is indicated by the source
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-121 pxr40 microcontroller reference manual, rev. 1 address, and the final destination for that data, by the destination address. the dmac contains a data structure containing these addresses a nd other parameters used in the cont rol of data transfers. for every dma request issued by the eqadc, th e dmac has to be conf igured to transfer a single command (32-bit data) from the cqueue, pointed to by the source address, to the cfif o push register, pointed to by the destination address. after the serv ice of a dma request is completed, the source address has to be updated to point to the next valid comma nd. the destination addres s remains unchanged. when the last command of a queue is transferred one of the following actions is recommende d. refer to the dmac block guide for details about how this functionality is supported. ? the corresponding dma channel shoul d be disabled. this might be desirable for cfifos in single scan mode. ? the source address should be upda ted to point to a valid command which can be the first command in the queue that has just been transferred (c yclic queue), or the firs t command of any other cqueue. this is desirable for cfif os in continuous scan mode, and at some cases, for cfifos in single scan mode. figure 27-74. cqueue/cfifo interface 27.8.2.2 rqueue/rfifo transfers in transfers involving rqueues and rfifos, the dm ac moves data from a single source to a queue destination as showed in figure 27-75 . the location of the data to be moved is indicated by the source address, and the final dest ination for that data, by th e destination address. for every dma request issued by the eqadc, the dmac has to be c onfigured to transfer a single result (16-bit data), pointed to by the source address, from the rfifo pop re gister to the rqueue, pointed to by the destination address. after the service of a dma request is completed, the dest ination address has to be updated to point to the location where the next 16-bit result will be stored. the source addr ess remains unchanged. when the last expected result is written to the rqueue, one of the following actions is recommended. refer to the dmac block guide for details about how this functionality is supported. ? the corresponding dma channel should be disabled. source address command 1 command 2 command 3 ..... command n-1 command n cfprx cqueue in system memory cfifo push register one command transfer per dma request destination address
enhanced queued analog-to-digital converter (eqadc) 27-122 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? the destination address should be updated to point to the next location where new coming results are stored, which can be the first entry of the cu rrent rqueue (cyclic queue ), or the beginning of a new rqueue. figure 27-75. rqueue/rfifo interface 27.8.3 sending immediate command setup example in the eqadc, there is no immedi ate command register for sending a command immediately after writing to that register. however, a cfifo can be configur ed to perform the same function as an immediate command register. the follow ing steps illustrate how to configur e cfifo5 as an immediate command cfifo. the results will be returned to rfifo5. 1. configure the section 27.6.2.6, eqadc interrupt and dm a control registers (eqadc_idcr) . a. clear cfifo fill enable5 (cffe5 = 0) in eqadc_idcr2. b. clear cfifo underflow interrupt en able5 (cfuie5 = 0) in eqadc_idcr2. c. clear rfds5 to configure the eqadc to genera te interrupt requests to pop result data from rfif05. d. set rfifo drain enable5 (r fde5 = 1) in eqadc_idcr2. 2. configure the section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) . a. write ?1? to cfinv5 in eqadc_fcr2. this will invalidate the contents of cfifo5. b. set mode5 to continuous-scan softwa re trigger mode in eqadc_cfcr2. 3. to transfer a command, write it to eqad c cfifo push register 5 (eqadc_cfpr5) with message tag = 0b0101. refer to section 27.6.2.3, eqadc cfifo push registers (eqadc_cfpr) . 4. up to four commands can be queued in cfif o5. check the cfctr5 status in eqadc_fisr5 before pushing another command to a void overflowing the cfifo. refer to section 27.6.2.7, result 1 result 2 result 3 ..... result n-1 result n rfprx rqueue in system memory rfifo pop register one result transfer per dma request source address destination address
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-123 pxr40 microcontroller reference manual, rev. 1 eqadc fifo and interrupt st atus registers (eqadc_fisr) . 5. when the eqadc receives a conve rsion result for rfifo5, it generates an interrupt request. rfifo pop register 5 (eqadc_rfpr5) can be popped to read the result. refer to section 27.6.2.4, eqadc result fifo pop registers (eqadc_rfpr) . 27.8.4 modifying queues more cqueues may be needed than the six supporte d by the eqadc. these additional cqueues can be supported by interrupting command transfers from a co nfigured cfifo, even if it is triggered and transferring, modifying the corresponding cqueue in th e ram or associating another cqueue to it, and restarting the cfifo. more details on disabling a cfifo are described in section 27.7.4.6.1, disabled mode . 1. determine the resumption conditions when later resuming the scan of th e cqueue at the point before it was modified. a. change modex in section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) , to disabled. refer to section 27.7.4.6.1, disabled mode , for a description of what happens when modex is changed to disabled. b. poll cfsx until it becomes idle in section 27.6.2.10, eqadc cfifo status register (eqadc_cfsr) . c. read and save tc_cfx in section 27.6.2.8, eqadc cfifo tran sfer counter registers (eqadc_cftcr) , for later resuming the scan of the queue. the tc_cfx provides the point of resumption. d. since all result data may not have being stor ed in the appropriate rfifo at the time modex is changed to disable, wait for all expected re sults to be stored in the rfifo/rqueue before reconfiguring the dmac to work with the modi fied rqueue. the number of results that must return can be estimated from th e tc_cfx value obtained above. 2. disable the dmac from responding to the dm a request generated by cfffx and rfdfx in section 27.6.2.7, eqadc fifo and interrupt status registers (eqadc_fisr) . 3. write ?0x0000? to the tc_cfx field. 4. load the new configur ation and conversion commands into ram. configure the dmac to support the new cqueue/rqueue, but do not configur e it yet to respond to dma requests from cfifox/rfifox. 5. if necessary, modify section 27.6.2.6, eqadc interrupt and dma control registers (eqadc_idcr) , to suit the modified cqueue. 6. write ?1? to cfinvx in section 27.6.2.5, eqadc cfifo cont rol registers (eqadc_cfcr) , to invalidate the entries of cfifox. perform a ny other modifications to eqadc_cfcr except changing modex from disabled. 7. configure the dmac to respond to dm a requests generated by cfffx and rfdfx. 8. change modex to the modified cfifo operation mode. write ?1? to ssex to trigger cfifox if modex is software trigger.
enhanced queued analog-to-digital converter (eqadc) 27-124 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.8.5 cqueue and rqueues usage figure 27-76 is an example of cqueue and rqueue usag e. it shows the cqueue0 commands requesting results that will be stored in rqueue0 and rqueue1, and cqueue1 comm ands requesting re sults that will be stored only in rqueue 1. some command messages re quest data to be return ed from the on-chip adc, but some only configure th em and do not request returning data. wh en a cqueue contai ns both write and read commands like cqueue0, the cqueue and rque ue entries will not be aligned; as shown in figure 27-76 , the result for the second command of cqueue0 is the first entry of rqueue0. the figure also shows that cqueue and rqueue en tries can also become unaligned even if all commands in a cqueue request data as cqueue1. cqueue1 entries became unaligned to rqueue1 entries because a result requested by the forth cqueue0 comm and was sent to rqueue1. this ha ppens because the system can be configured so that several cqueues can ha ve its results sent to a single rqueue.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-125 pxr40 microcontroller reference manual, rev. 1 figure 27-76. eqadc command and result queues no result cqueue0 write command 0 0x0000 result to rqueue0 cqueue0 read command 1 0x0004 result to rqueue0 cqueue0 conversion command 2 0x0008 result to rqueue1 cqueue0 conversion command 3 0x000c ... ... result to rqueue0 cqueue0 conversion command n 0x001c command queue 0 (cqueue0) result cqueue0 read command 1 0x0000 result cqueue0 conversion command 2 0x0002 ... ... result queue 0 (rqueue0) result to rqueue1 cqueue1 read command 0 0x0000 result to rqueue1 cqueue1 read command 1 0x0004 result to rqueue1 cqueue1 conversion command 2 0x0008 ... ... result to rqueue1 cqueue1 conversion command m 0x001c command queue 1 (cqueue1) result cqueue1 read command 0 0x0000 ... ... result queue 1 (rqueue1) result cqueue1 read command 1 0x0002 result cqueue1 conversion command 2 0x0006 result cqueue0 conversion command 3 0x0004 rqueue0 is not aligned with cqueue0 because the first command of cqueue0 does not request results. rqueue1 is not aligned with cqueue1 because it contains results for cqueue0 and cqueue1 commands. the timing at which the cqueue0 command result is stored in rqueue1 depends on the relative speed at which commands from both cqueues are executed. this is influenced by factors like resource sharing, adc clock frequency, sampling time, and triggering time.
enhanced queued analog-to-digital converter (eqadc) 27-126 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 27.8.6 adc result calibration the adc result calibration process consists of two steps: determini ng the gain and offset calibration constants, and calibrating the raw re sults generated by the on-chip adcs by solving the following equation discussed in section 27.7.6.6, adc calibration feature . cal_res = gcc * raw_res + occ+2; eqn. 27-1 the calibration constants gcc and occ can be ca lculated from equation equation 27-1 provided that two pairs of expected (cal_res) and measured (raw_r es) result values are available for two different input voltages. most li kely calibration points to be used are 25% vref 1 and 75% vref since they are far apart but not too close to the end point s of the full input voltage range. this allows for calculations of more representative calibration constant s. the eqadc provides these volta ges via channel numbers 43 and 44. the raw, uncalibrated results for these input volta ges are obtained by converti ng these channels with conversion commands that have the cal bit negated. the transfer equations for when sa mpling these reference voltages are: cal_res 75%vref = gcc * raw_res 75%vref + occ+2; cal_res 25%vref = gcc * raw_res 25%vref + occ+2; thus; gcc = (cal_res 75%vref ? cal_res 25%vref ) / (raw_res 75%vref ? raw_res 25%vref ); eqn. 27-2 occ = cal_res 75%vref ? gcc*raw_res 75%vref ? 2; eqn. 27-3 or occ = cal_res 25%vref ? gcc*raw_res 25%vref ? 2; eqn. 27-4 after being calculated, the g cc and occ values must be written to adc registers: section 27.6.3.4, adc0/1 gain calibration constant registers (adc0_gcc r and adc1_gccr) , and section 27.6.3.5, adc0/1 offset calibration constant registers (adc0_occr and adc1_occr) , using write configuration commands. the eqadc will automatically calibrate the results, according to equation equation 27-1 , of every conversion command that has its ca l bit asserted using the gcc and occ values stored in the adc calibration registers. 27.8.6.1 mac configuration procedure the following steps illustrate how to configure the calibration hardware, namely , determining the values of the gain and offset cali bration constants, and the wr iting of these constants to the calibration registers. the procedure below should be performed for adc0 and for adc1. 1. convert channel 44 with a comman d that has its cal bi t negated and obtain the raw, uncalibrated result for 25%vref (raw_res 25%vref ). 1. vref=vrh-vrl
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-127 pxr40 microcontroller reference manual, rev. 1 2. convert channel 43 with a comman d that has its cal bi t negated and obtain the raw, uncalibrated result for 75%vref (raw_res 75%vref ). 3. since the expected values for the conve rsion of these volta ges are known (cal_res 25%vref and cal_res 75%vref ), gcc and occ values can be calculated from equations equation 27-2 and equation 27-3 using these values, and the ones determined in steps 1 and 2. 4. reformat gcc and occ to the prope r data formats as specified in section 27.7.6.6.2, mac unit and operand data format . gcc is an unsigned 15-bit fixed poi nt value and occ is a signed 14-bit value. 5. write gcc value to section 27.6.3.4, adc0/1 gain calibrati on constant registers (adc0_gccr and adc1_gccr) , and occ value to section 27.6.3.5, adc0/1 offset calibration constant registers (adc0_occr and adc1_occr) , using write configuration commands. 27.8.6.2 example the raw results obtained when sampling reference voltages 25%vref and 75%vref were, respectively, 3798 and 11592. the results that should have been obt ained from the conversion of these reference voltages are, respectively, 4096 a nd 12288. therefore, using equations equation 27-2 and equation 27-3 , the gain and offset calibration constants are: gcc=(12288-4096)/(11592-3798) = 1.05106492-> 1.05102539 = 0x4388 occ=12288 - 1.05106492*11592 - 2 = 102.06-> 102 = 0x0066 table 27-48 shows, for this particular case, examples of how the result values ch ange according to gcc and occ when result calibration is execute d (cal=1) and when it is not (cal=0). 27.8.6.3 quantization error reduction during calibration figure 27-77 shows how the adc transfer curve changes due to the addition of two to the mac output during the calibration - see mac output equation at section 27.7.6.6.1, overview . the maximum absolute quantization error is reduced by half leading to an increase in accuracy. table 27-48. calibration example input voltage raw result (cal=0) calibrated result (cal=1) hexadecimal decimal hexadecimal decimal 25% vref 0x0ed6 3798 0x1000 4095.794 75% vref 0x2d48 11592 0x3000 12287.486
enhanced queued analog-to-digital converter (eqadc) 27-128 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 27-77. quantization error reduction during calibration 27.8.7 eqadc versus qadc this section describes how the eqadc upgrades the qadc functionality. the s ection also provides a comparison between the eqadc and qadc in terms of th eir functionality. this section targets the users familiar with te rminology in qadc. figure 27-78 is an overview of a qadc. figure 27-79 is an overview of the eqadc system. 0 1/2 lsb lsb input voltage digital value 4 error for adc transfer curve shifted ideal transfer curve transfer curve 0 input voltage - 4 2 quantization error - 2 (12-bit ad resolution) (12-bit ad resolution) 1/2 lsb lsb (14-bit result) error for shifted transfer curve adc transfer curve
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-129 pxr40 microcontroller reference manual, rev. 1 figure 27-78. qadc overview figure 27-79. eqadc system overview the eqadc system consists of these parts: que ues in ram, the eqadc, and on-chip adcs. as compared with the qadc, the eqadc system requires extra hardware. 1. a dma or an mcu is required to move data between the eqadc?s fi fos and queues in the system memory. external triggers result queues command queues analog to digital converter interrupt request digital control logic for analog device trigger and queue control logic external triggers cqueues rqueues dmac/cpu dma/interrupt requests eqadc trigger and fifo control logic system bus analog to digital converter cfifos rfifos
enhanced queued analog-to-digital converter (eqadc) 27-130 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 since there are only fifos inside the eqadc, much of the termi nology or use of the register names, register contents, and signals of the eqadc involve ?fifo? instead of ?queue?. these register names, register contents, and signals ar e functionally equivalent to the ?queue? counterparts in the qadc. table 27-49 lists how the eqadc register, register c ontents, and signals are related to qadc. . the eqadc and qadc also have similar procedures for the confi guration or execution of applications. table 27-50 shows the steps required for the qadc vers us the steps required for the eqadc system. table 27-49. terminology comparison between qadc and eqadc qadc terminology eqadc terminology function ccw command message in the qadc, the hardware only executes conversion command words. in the eqadc, not all commands are conversion commands; some are configuration commands. queue trigger cfifo trigger in the qadc, a trigger event is required to start the execution of a queue. in the eqadc, a trigger event is required to start command transfers from a cfifo. wh en a cfifo is triggered and transferring, commands are contin uously moved from cqueues to cfifos. thus, the trigger event initiates the ?execution of a queue? indirectly. current word pointer queue x (cwpqx) counter value of commands transferred from command fifox (tc_cfx) in the qadc, cwpqx allows the last executed command on queue x to be determined. in the eqadc, the tc_cfx valu e allows the last transferred command on cqueue x to be determined. queue pause bit (p) cfifo pause bit in the qadc, det ecting a pause bit in the ccw will pause the queue execution. in the eqadc, detecting a paus e bit in the command will pause command transfers from a cfifo. queue operation mode (mqx) cfifo operation mode (modex) the eqadc supports all queue operation modes in the qadc except operation modes related to a periodic timer. a timer elsewhere in the system can provide the same functio nality if it is connected to etrigx. queue status (qs) cfifo status (cfsx) in the qadc, th e queue status is read to check whether a queue is idle, active, paused, suspended, or trigger pending. in the eqadc, the cfifo status is read to check whether a queue is idle, waiting for trigger (idle or paused in qadc), or triggered (suspended or trigger pending in qadc). what cfifo is currently ?active? can be determined by reading the lcftcbn field on the eqadc_cfssr registers. table 27-50. usage comparison between qadc and eqadc system procedure qadc eqadc system analog control configuration configure analog device by writing to the qadc registers. program configuration commands into command queues. prepare scan sequence program scan commands into command queues. program scan commands into command queues. queue control configuration write to the qadc contro l registers. write to the eqadc control registers.
enhanced queued analog-to-digital converter (eqadc) freescale semiconductor 27-131 pxr40 microcontroller reference manual, rev. 1 data transferred between queues and buffers not required. program the dmac or the cpu to handle the data transfer. queue execution require software or external trigger events to start queue execution. require software or external trigger events to start command transfers from a cfifo. table 27-50. usage comparison between qadc and eqadc system (continued) procedure qadc eqadc system
enhanced queued analog-to-digital converter (eqadc) 27-132 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 28-1 pxr40 microcontroller reference manual, rev. 1 chapter 28 decimation filter 28.1 overview this document describes the decimation filter block f unctionality for the pxr40 rev 2 device, and is not valid for any other revi sions of this device. there are 12 independent decimation fi lter blocks (a through l) on th e device. each decimation filter block contains a multiply-accumulat e (mac) unit capable of implementin g a 16-bit, 4th or der iir or 8th order fir filter. the d ecimation filter blocks can be cascaded to create larger fi lters. filter output data can be decimated at a programmable rate in the range 1 to 16. each decimation filter has a 32-bit in tegrator unit, which allows the bl ock to accumulate and sum a series of filter outputs. the integrator input can be selected from before or afte r the decimator. the integrator can be enabled and disabled, cleared, and read by software or by hardware tr iggers from cert ain channels of the etpu modules on the device. the integrator cont rol triggers are selected in the siu_decfil1 and siu_decfil2 and siu_decfil3 registers. the data and control registers for each decimation filter bl ock are independently accessed by the cpu. all decimation filters support dma wr ites to the input data register, and dma reads of the output data register. the eqadc_a and eqadc_b blocks have an internal hardwa re link to decimation filters a through l. this allows cpu independent transf er of eqadc_a and eqad c_b analog to digital conversion result data to the decima tion filter input data registers, an d filter output data back to the eqadc_a and eqadc_b c onversion result fifos. each decimation filter block supports 4 combinations of input data source and output result destination: 1. input from eqadc/output to eqadc : in this mode, the decimation filter receives analog to digital conversion data samples from the eqadc block. the output result from the decimation filter is automatically returned to the rfifo in eqadc that was specified in the conversion command for the adc input. 2. input from system ram/output to system ram : in this mode, the input data to the decimation filter is supplied from system ram by the cpu or dma. the filter data and associated commands are written to a memory mapped input register, and the output results are written to a memory mapped register, where they can be read by either cpu or dma. 3. input from eqadc/output to system ram : in this mode, the decimation filters can be configured for input data from eqadc and output result to the system ram (cpu or dma). 4. input from system ra m/output to eqadc : in this mode, the decimati on filter input data from system ram (cpu or dma), and the output re sult is sent to an eqadc result fifo. each decimation filter block can be programmed to generate interrupt requests when input data is received from the eqadc, when the filter result is writt en to the output buffer, if a filter overflow occurs,
decimation filter 28-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 and if either input or output buffer overruns occur. an interrupt can also be generated when an integrator result is ready to be read. figure 28-1 shows a system-level block diagram of a single decimation filter. all decimation filters share the same configurati on, with some differences in the hardwa re trigger sources for the integrator controls.
decimation filter freescale semiconductor 28-3 pxr40 microcontroller reference manual, rev. 1 figure 28-1. decimation filter block diagram an[n] rfifo adc eqadc_b 51-bit mac 4th order decimator rate interrupts coeff decimation filter block cpu interrupt controller peripheral bridge b etpua edma_b edma_a 1 to 16 peripheral bridge a iir 8th order fir -or- integrator 32-bit etpub count value siu tap input buffer regs crossbar switch mpu output buffer
decimation filter 28-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.1.1 features the decimation filter block includes these features: ? selectable 4th order iir filt er, or 8th order fir filter ? 16-bit, two?s complement signed input/output data ? internal taps with 16-bit (feed-f orward taps) and 24-b it (feedback taps) reso lutions (fixed point) for two?s complement signed value ? 24-bit programmable filter coefficients (fix ed point) for two?s complement signed value ? mac unit with 51-bit fixed point accumulator ? convergent rounding methodology ? two?s complement overflow or saturation selection ? 58 system (core frequency divided by tw o) clock cycles to process the input ? direct data input from the on- chip eqadc_a and eqadc_b block ? dma access to input and output data buffers ? cpu accessible status /configuration register s and data input/output ? filter initialization (flush) and stabilization (prefill) commands ? timestamp support ? programmable integer deci mation rates of 1 to 16 ? 32-bit, fixed point, signed or unsigned integr ator unit with hardware triggered windowing ? cascading of two or more blocks to create more complex filters 28.1.2 modes of operation overview this section provides an overview of the operati onal modes of the decimation filter. the modes are selected using the module c onfiguration register fields mdis, fren, and frz (see section 28.2.2.1, decimation filter module configuration re gister (decfilt_x_mcr) . the mode selection is summarized in table 28-1 . 28.1.2.1 normal mode this is the default operational mode of the decimation filter. in this mode, the decimation filter processes each new input in the input buffer according the f ilter, decimator, and integrator configuration. table 28-1. operation mode selection mode mdis fren, frz normal 0 (0,0), (0,1) or (1,0) freeze 0 1, 1 disabled 1 x
decimation filter freescale semiconductor 28-5 pxr40 microcontroller reference manual, rev. 1 28.1.2.2 freeze mode this mode is also known as debug mode . all filter action is frozen. if the filter is processing an input, it enters freeze mode only after the cu rrent processing finishes. more de tails of freeze mode may be found in section 28.3.8, freeze mode . 28.1.2.3 disabled mode each decimation filter block ma y be disabled by setting the decfilt_x_mcr[mdis] bit in the respective block instance. 28.2 memory map and register definition this section provides the memory maps and detailed descriptions of all re gisters. there are eight decimation filter bloc ks on the device. each decimation filter block has its own independent set of registers as defined in section 28.2.2, decimation filter register descriptions . the base address of each decimation filter bl ock is given in table 28-2 . 28.2.1 decimation filter memory map the addresses of the decimation filter registers are specified as offsets from the module?s base address as described in table 28-3 . table 28-2. decimation filter modules base address module address decfilt_a_ base 0xfff8_8000 decfilt_b_ base 0xfff8_8800 decfilt_c_ base 0xfff8_9000 decfilt_d_ base 0xfff8_9800 decfilt_e_ base 0xfff8_a000 decfilt_f_ base 0xfff8_a800 decfilt_g_ base 0xfff8_b000 decfilt_h_ base 0xfff8_b800 table 28-3. block memory map address register bits access reset value section/page decfilt_x_ base + 0x000 decfilter_mcr ? module configuration register 32 r/w 0x0000_0000 28.2.2.1/28-7 decfilt_x_ base + 0x004 decfilter_msr ? module status register 32 r/w 0x0000_0000 28.2.2.2/28-11 decfilt_x_ base + 0x008 decfilter_mxcr ? module extended configuration register 32 r/w 0x0000_0000 28.2.2.3/28-13
decimation filter 28-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 decfilt_x_ base + 0x00c decfilter_mxsr ? module extended status register 32 r/w 0x0000_0000 28.2.2.4/28-16 decfilt_x_ base + 0x010 decfilter_ib ? interface input buffer 32 r/w 0x0000_0000 28.2.2.5/28-19 decfilt_x_ base + 0x014 decfilter_ob ? interface output buffer 32 r 0x0000_0000 28.2.2.6/28-20 decfilt_x_ base + 0x018?0x01f reserved decfilt_x_ base + 0x020 decfilter_coef0 ? filter coefficient 0 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x024 decfilter_coef1 ? filter coefficient 1 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x028 decfilter_coef2 ? filter coefficient 2 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x02c decfilter_coef3 ? filter coefficient 3 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x030 decfilter_coef4 ? filter coefficient 4 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x034 decfilter_coef5 ? filter coefficient 5 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x038 decfilter_coef6 ? filter coefficient 6 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x03c decfilter_coef7 ? filter coefficient 7 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x040 decfilter_coef8 ? filter coefficient 8 32 r/w 0x0000_0000 28.2.2.7/28-20 decfilt_x_ base + 0x044?0x077 reserved decfilt_x_ base + 0x078 decfilter_tap0 ? filter tap 1 0 register 32 r 0x0000_0000 28.2.2.8/28-21 decfilt_x_ base + 0x07c decfilter_tap1 ? filter tap 1 register 32 r 0x0000_0000 28.2.2.8/28-21 decfilt_x_ base + 0x080 decfilter_tap2 ? filter tap 2 register 32 r 0x0000_0000 28.2.2.8/28-21 decfilt_x_ base + 0x084 decfilter_tap3 ? filter tap 3 register 32 r 0x0000_0000 28.2.2.8/28-21 decfilt_x_ base + 0x088 decfilter_tap4 ? filter tap 4 register 32 r 0x0000_0000 28.2.2.8/28-21 decfilt_x_ base + 0x08c decfilter_tap5 ? filter tap 5 register 32 r 0x0000_0000 28.2.2.8/28-21 table 28-3. block memory map (continued) address register bits access reset value section/page
decimation filter freescale semiconductor 28-7 pxr40 microcontroller reference manual, rev. 1 28.2.2 decimation filter register descriptions all registers are 32-bit wide, and each of the eight decimation filters on th e device have the same register interface. 28.2.2.1 decimation filter module conf iguration register (decfilt_x_mcr) the decimation filter m odule configuration regist er provides configuration control bits for the decimation filter internal logic. note do not modify this register?s contents when the status bit bsy is set, except for fields fren, frz and idis. to gua rantee that bsy does not set during the read-modify-write oper ation, it is advisable to set idis=1 and wait for bsy=0 beforehand. decfilt_x_ base + 0x090 decfilter_tap6 ? filter tap 6 register 32 r 0x0000_0000 28.2.2.8/28-21 decfilt_x_ base + 0x094 decfilter_tap7 ? filter tap 7 register 32 r 0x0000_0000 28.2.2.8/28-21 decfilt_x_ base + 0x098?0x0cf reserved decfilt_x_ base + 0x0d0 decfilter_edid ? enhanced debug input data 32 r 0x0000_0000 28.2.2.9/28-22 decfilt_x_ base + 0x0d4?0x0df reserved decfilt_x_ base + 0x0e0 decfilter_fintval ? final integration value register 32 r 0x0000_0000 28.2.2.10/28-23 decfilt_x_ base + 0x0e4 decfilter_fintcnt ? final integration count register 32 r 0x0000_0000 28.2.2.11/28-23 decfilt_x_ base + 0x0e8 decfilter_cintval ? current integration value register 32 r 0x0000_0000 28.2.2.12/28-24 decfilt_x_ base + 0x0ec decfilter_cintcnt ? current integration count register 32 r 0x0000_0000 28.2.2.13/28-24 decfilt_x_ base + 0x0f0?0x1ff reserved 1 the tap register stores, on each filter node, the input sample data and, for the iir type, the filter intermediary results. table 28-3. block memory map (continued) address register bits access reset value section/page
decimation filter 28-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 address: decfilt_x_base + 0x000 access: user read/write 01234567 8 9 101112131415 r mdis fren 0 frz 0 cascd[1:0] iden oden erren 0 ftype[1:0] 0 scal[1:0] w sres reset00000000 0 0 00 0 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r idis sat io_sel[1:0] dec _rate[3:0] sdie dsel ibie obie edme tore tmode w reset10000000 0 0 00 0 000 figure 28-2. decimation filter module configuration register (decfilt_x_mcr) table 28-4. decfilt_x_mcr field descriptions field description 0 mdis module disable?puts the decimation filter in low po wer mode. communication through the eqadc interface is ignored in this mode. writes to the configuration regi ster are allowed with the except ion of writes to the fren and sres bits, which are ignored. writes to the coefficien t registers are allowed. the decimation filter cannot enter freeze mode once in disable mode. 0 normal mode 1 low power mode 1 fren freeze enable?enables the decimation filter to enter freeze mode see section 28.3.8, freeze mode , for more details. 0 freeze mode disabled 1 freeze mode enabled 2 reserved 3 frz freeze mode?controls the freeze mode of the decimation filter. for this bit to take effect the fren freeze enable bit also needs to be asserted. while in freeze mode the mac operations are halted. see section 28.3.8, freeze mode , for more details. 0 normal mode 1 freeze mode 4 sres software-reset bit?a self-negated bit which provides the c apability to initialize the decimation filter interface. this bit always reads as zero. see section 28.3.7, soft reset command , for more details. 0 no action 1 software-reset 5?6 cascd cascade mode configuration?configures the block to work in cascade mode of operation. for more details about the cascade mode, see section 28.3.14, cascade mode . 00 no cascade mode (single block) 01 cascade mode, head block config 10 cascade mode, tail block config 11 cascade mode, middle block config note: any change to this field must follow the procedure described in the section 28.3.14.2, cascade freeze, stop, and configuration change procedures . 7 iden input data interrupt enable?enables the decimation filt er to generate interrupt requests on all new input data written to the interface input buffer register. 0 input data interrupt disabled 1 input data interrupt enabled
decimation filter freescale semiconductor 28-9 pxr40 microcontroller reference manual, rev. 1 8 oden output data interrupt enab le?enables the decimation filter to generate interrupt requests on all new data written to the filter output buffer. this is independent of the io_sel field setting. 0 output data interrupt disabled 1 output data interrupt enabled 9 erren error interrupt enable?enables the decimation filter to generate interrupt requests based on the assertion of the decfilter_msr register error flags ovf, divr, svr, ovr or ivr. 0 error interrupts disabled 1 error interrupts enabled 10 reserved 11?12 ftype filter type selection bits?selects the filter type. 00 filter bypass 01 iir filter - 1 x 4th order 10 fir filter - 1 x 8th order 11 reserved 13 reserved 14?15 scal filter scaling factor?selects the scalin g factor used by the filter algorithm. 00 scaling factor = 1 01 scaling factor = 4 10 scaling factor = 8 11 scaling factor = 16 16 idis input disable?disables the block input, so that writes to the input buffer have no effect and input dma or interrupt requests are not issued. inpu t disabling is needed to change the bl ock configuration to or from cascade mode. 0 input enabled 1 input disabled 17 sat saturation enable?enables the satura tion of the filter output. see section 28.3.11, saturation , for more details. 0 disables saturation 1 enable saturation 18?19 io_sel input data source and output result destination se lection?selects the source of the input data to the decimation filter, and the destination fo r the filter output re sult. the io_sel[1:0] encoding and associated source and destination definitions is given below. note th at when decimation filters are cascaded to form larger filters, the io_sel[1:0] field only is applicable to the in put data source for the head filter in the cascade, and to the output result destination for the tail filter in the casc ade. filters in the middle of the cascade receive input and send output to their adjacent filters in the cascade. regardless of the io_sel setting, the decimation filter input and output buffer registers can be read by the cpu/dma at any time, and th e output buffer register is updated in the case of the eqadc result destination. note t hat the eqadc module has to be configured to send conversion results to a decimation filter in addition to setting the io_sel field. table 28-4. decfilt_x_mcr field descriptions (continued) field description io_sel[1] io_sel[0] input data so urce output result destination 0 0 eqadc a/d conversion result eqadc rfifo 0 1 eqadc a/d conversion result output buffer register (cpu/dma) 1 0 input buffer register (cpu/dma) output buffer register (cpu/dma) 1 1 input buffer register (cpu/dma) eqadc rfifo
decimation filter 28-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 20?23 dec_rate decimation rate selection?selects the decimation rate used by the decimation filter. the decimation rate defines the number of data samples fr om the master block that is required to generate one decimated result in the decimation filter output. 0000 no decimation: one filter output for each sample input 0001?1111 one filter output for eac h (dec_rate+1) sample inputs 24 sdie integrator data interrupt enable?enables output buffer interrupts due to integrator data result being ready. 0 integration ready does not cause an output interrupt. 1 integration ready causes an output interrupt 25 dsel dma selection?determines whether the data transfers ? to the input buffer (write to) and from the output buffer (read from) ? are performed by dma requests or by interrupt requests. 0 interrupt requests are generated 1 dma requests are generated 26 ibie input buffer interrupt request enable?enables the de cimation filter to generate interrupt requests when: ? cpu/dma is selected (io_sel[1]=1), dsel=0, and the input buffer is available to receive new data; ? eqadc input is selected with enhanced debug (io_sel[1]=0, edme=1), dsel=0, and the input buffer has data to be read by the cpu. 0 input buffer interrupt request disabled 1 input buffer interrupt request enabled 27 obie output buffer interrupt request enable?enables the decimation filter interrupt requests when outputs are directed to the cpu/dma and dma requests is not selected (dsel=0). 0 output buffer interrupt request disabled 1 output buffer interrupt request enabled 29 edme enhanced debug monitor enable?defines the enhanced debug monitor when input selection is from eqadc (io_sel[1]=0). 0 enhanced debug monitor disabled 1 enhanced debug monitor enabled 29 tore triggered output result enable?enables an etpu signal to transfer the filter result to its destination, using the mode specified by tmode[1:0]. 0 output buffer transfer by etpu signal disabled 1 output buffer transfer by etpu signal enabled 30?31 tmode trigger mode?selects the way the etpu signal controls the transfer of a new output result 00 result is transferred at t he rising edge of the etpu signal 01 result is transferred while the etpu signal is 0 10 result is transferred at the falling edge of the etpu signal 11 result is transferred while the etpu signal is 1 table 28-4. decfilt_x_mcr field descriptions (continued) field description
decimation filter freescale semiconductor 28-11 pxr40 microcontroller reference manual, rev. 1 28.2.2.2 decimation filter module status register (decfilt_x_msr) address: decfilt_x_base + 0x004 access: user read/write 0 1 2345 6 7 8 9 1011 12 131415 r bsy 0 dec_counter[3:0] 0 0 0 0 0 0 0 0 0 0 w idfc odfc ibic obic divrc ovfc ovrc ivrc reset000000000000 0 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 idf odf 0 ibif obif 0 divr ovf ovr ivr w reset000000000000 0 000 figure 28-3. decimation filter status register (decfilt_x_msr) table 28-5. decfilt_x_msr field descriptions field description 0 bsy decimation filter busy i ndication?the bsy bit indicates th at the decimation filter is actively processing a new input data sample. bsy is not asserted when the filter is disabled (ftype = 00). the bsy bit is asserted when the soft reset is executed. 0 decimation filter idle 1 decimation filter busy 1 reserved 2?5 dec_ counter decimation counter?the dec_counter[3:0] field in dicates the current value of the dec_counter decimation counter, which counts the number of input data samples received by the decimation filter. when the value of this counter matches the dec_rate[3:0] co nfiguration register field, one decimated result is generated and the dec_counter counter is re -initialized at zero. this register is cleared by a soft reset or a flush command. 6 idfc input data flag clear bit?the idfc bit clears the idf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears idf 7 odfc output data flag clear bit?the odfc bit clears the odf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears odf 8 reserved 9 ibic input buffer interrupt request clear bit?the ibic bit clears the ibif flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears ibif 10 obic output buffer interrupt request clear bit?the obic bit clea rs the obif flag bit in t he status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears obif 11 reserved
decimation filter 28-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 12 divrc divr clear bit?the divrc bit clears the divr debug filter input data read overrun indication bit in the status register. this bit is self negated, t herefore it is always read as zero. 0 no action 1 clears divr 13 ovfc ovf clear bit?the ovfc bit clears the ovf output overflow bit in the status register . this bit is self negated, therefore it is always read as zero. 0 no action 1 clears ovf 14 ovrc ovr clear bit?the ovrc bit clears the ovr output overrun bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears ovr 15 ivrc ivr clear bit?the ivrc bit clears the iv r filter input overrun indication bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears ivr 16?21 reserved 22 idf input data flag?the idf bit flag indicates when new data is available at the decfilt_x_ib register or at the decfilt_x_iob register. this flag generates an inte rrupt request if enabled by the iden bit in the configuration register. this flag is cleared by the idfc status bit or by a soft reset of the decimation filter. 0 sample not received 1 new sample received note: obs: this flag is not used for read / write requests. it is used only to announce the input data event. for read / write request flag, refer to ibif. 23 odf output data flag?the odf bit flag indicates when a new decimated sample is availa ble at the decfilt_x_ob register or at the decfilt_x_iob register. this flag ge nerates an interrupt request if enabled by the oden bit in the configuration register. this flag is cleared by th e odfc status bit or by a soft reset of the decimation filter. 0 no new decimated output sample available 1 new decimated output sample available note: obs: this flag is not used for read requests. it is us ed only to announce the output data event. for read request flag, refer to obif. 24 reserved 25 ibif input buffer interrupt request flag?the ibif bit flag indi cates that the input buffer decfilt_x_ib is available to be filled with new data, when enhanced debug monitor is off. in enhanced debug monitor, it indicates the input buffer decfilt_x_ib was filled with a new sample and is ready to be read. 0 no action 1 new sample is requested (io_sel[1] = 1, edme=0) or new sample is available in enhanced debug monitor (io_sel[1]=0, edme=1). 26 obif output buffer interrupt request flag ?the obif bit flag indicates that either a new decimated sample is available at the decfilt_x_ob register. 0 no new decimated output available 1 new decimated output available 27 reserved table 28-5. decfilt_x_msr field descriptions (continued) field description
decimation filter freescale semiconductor 28-13 pxr40 microcontroller reference manual, rev. 1 28.2.2.3 decimation filter module extended configuration register (decfilt_x_mxcr) 28 divr enhanced debug monitor input data read overrun?the divr bit indicates that a received sample in the filter interface input register was overwritten by a new sa mple and was not read by the cpu/dma. this flag generates an interrupt request if enabled by the erren bi t in the configuration register. this flag is cleared by the divrc status bit or by a so ft reset of the decimation filter. 0 input data read overrun did not occur in enhanced debug monitor 1 enhanced debug monitor input data read overrun occurred 29 ovf filter overflow flag?the ovf bit indicates that an over flow occurred in the filtered sample result. this flag generates an interrupt request if enabled by the erren bi t in the configuration register. this flag is cleared by the ovfc status bit or by a so ft reset of the decimation filter. 0 no overflow 1 overflow occurred 30 ovr output interface buffer overrun?th e ovr bit indicates that a decimated sample was overwritten by a new sample in the interface output buffer register. this flag generates an interrupt request if enabled by the erren bit in the configuration register. this flag is clear ed by the ovrc status bit or by a soft reset of the decimation filter. 0 no output overrun 1 filter output overrun occurred 31 ivr input interface buffer overrun?the ivr bit indicates that a received sample in the filter interface input register was overwritten by a new sample. this flag generates an interrupt request if enabled by the erren bit in the configuration register. this flag is cleared by the ivrc status bit or by a soft reset of the decimation filter. 0 input buffer overrun did not occur 1 input buffer overrun occurred note: address: decfilt_x_base + 0x008 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r sdmae ssig ssat scsat 000 0 0000 0 000 w srq szro reset0 0 0 0 000 0 0 0 0 0 0 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sisel 0 szrosel 00 shltsel 0 srqsel 00 sensel w reset0 0 0 0 000 0 0 0 0 0 0 000 figure 28-4. decimation filter extended configuration register (decfilt_x_mxcr) table 28-5. decfilt_x_msr field descriptions (continued) field description
decimation filter 28-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 28-6. decfilt_x_ mxcr field descriptions field description 0 sdmae integrator dma enable?the sdmae bit enables the dma request when an integrator output is available (see section 28.3.13.2, integrator output ). 0 integrator dma request disabled 1 integrator dma request enabled note: the dma channel used is the same one used for filter outputs, and any configuration that generates dma requests from both of those sources is not allowed. 1 ssig integrator signal operation selection?the ssig bit defines how the filtered data signal is treated for integration: 0 integrator input takes the abs olute value of filter output 1 integrator input takes the signed filter output 2 ssat integrator saturated operation selection?the ssat bit defines how the integrator accumulator behaves in case of an overflow. 0 integrator accumulator holds a modulo 2 17 value (considering the 15-bit fractional part) on an overflow. 1 integrator accumulator saturates on an overflow note: in saturated operation the overflown integration sum holds the value 0xffffffff for absolute integration (ssig=0), or values 0x7f ffffff (positive saturation) and 0x8 0000000 (negative saturation) for signed integration (ssig=1). note: non-saturated mode is not supported with signed inte gration, therefore one mu st not configure ssig=1 and ssat=0. 3 scsat integrator counter saturated operation selection?the scsat bit defines how the integrator sample counter behaves in case of an overflow. 0 integrator sample counter holds a modulo 2 32 value on an overflow. 1 integrator sample counter saturates on an overflow, holding a value of 0xffffffff. 4?13 reserved 14 srq integrator output request?the srq bit is used to command the update of the integrator output, reflected in the registers decfilt_x_fintval and decfilt_x_fintcnt. it may also cause a dma or interrupt request, depending on the decfilt_x_mcr bit sdie and decfilt_ x_mxcr bit sdmae. this is a write-only bit, so reads always return 0. for more details see section 28.3.13.2, integrator output . 0 no integrator output update request 1 requests integrator output update 15 szro integrator zero?the szro bit is used to zero the integr ator sum. this is a write- only bit, reads always return 0. for more details see section 28.3.13.3, integrator reset . 0 does not zero integrator sum 1 zeroes integrator sum note: if bits srq and szro are both written 1 at the same time, the integrator is reset only after the registers decfilt_x_fintval and decfilt_x_fintcnt are updated. 16 sisel integrator input selection?the sisel bit selects t he input of the integrator. for more details see section 28.3.13.1, integrator inputs . 0 decimated filter outputs feed the integrator 1 filter outputs before the decimation feed the integrator 17 reserved
decimation filter freescale semiconductor 28-15 pxr40 microcontroller reference manual, rev. 1 18?19 szrosel integrator zero control mode selection?the szrosel fi eld defines the use of the integrator zero hardware input signal. for more details see section 28.3.13.3, integrator reset . 20?21 reserved 22?23 shltsel integrator halt control selection?the shltsel field defines the integrator halting mechanism. when the integrator is halted, the integration accumulator remains unaltered on filter outputs independently of the enabling selected by sensel. fo r more details see section 28.3.13.4, integrator enabling and halting . 24 reserved 25?27 srqsel integrator output read request mode selection?the srq sel field defines the use of the integrator output request hardware input signal. an integrator output request updates the registers decfilt_x_fintval and decfilt_x_fintcnt, also causing a dma or interrupt req uest. note that dma or interrupt requests due to integrator output updates depend on the decfil t_x_mxcr bit sdmae and decfilt_x_mcr bit sdie. when continuous output is on, an in tegrator output request is issued whenever a new filter output is accumulated. for more details see section 28.3.13.2, integrator output . table 28-6. decfilt_x_mxcr field descriptions (continued) field description szrosel[1:0] description 0 0 hardware integrator zero request disabled 0 1 integrator zero on toggle of hardware signal 1 0 integrator zero on rising edge of hardware signal 1 1 integrator zero on falling edge of hardware signal shltsel[1:0] description 0 0 hardware halt control signal disabled 0 1 integrator halted, independently of the hardware signal 1 0 integrator halted when signal is at logical 0 1 1 integrator halted when signal is at logical 1 srqsel[2:0] description 0 0 0 hardware output request disabled 0 0 1 integrator output request on toggle of hardware signal 0 1 0 integrator output request on rising edge of hardware signal 0 1 1 integrator output request on falling edge of hardware signal 1 0 0 reserved 1 0 1 continuous output request on, i ndependently of hardware signal 1 1 0 continuous output request on when signal is at logical 0 1 1 1 continuous output request on when signal is at logical 1
decimation filter 28-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.2.2.4 decimation filter module extended status register (decfilt_x_mxsr) 28?29 reserved 30?31 sensel integrator enable control selection?the sensel field defines the integrator enabling mechanism. when the integrator is enabled, filter outputs selected by the sisel bit are added to the integration accumulator. when the integrator is disabled, the integration accumulator re mains unaltered on filter outputs. for more details see section 28.3.13.4, integrator enabling and halting . address: decfilt_x_base + 0x00c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 0000 0 00000 0 0 0 0 w sdfc ssec scec ssovf c scovf c svrc reset0 0 0000 0 00000 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0000 0sdf0 0ssesce0ssovfscovfsvr w reset0 0 0000 0 00000 0 0 0 0 figure 28-5. decimation filter extended status register (decfilt_x_mxsr) table 28-7. decfilt_x_mxsr field descriptions field description 0?6 reserved 7 sdfc integrator output data flag clear bit?the sdfc bit clear s the sdf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears sdf 8?9 reserved table 28-6. decfilt_x_mxcr field descriptions (continued) field description sensel[1:0] description 0 0 integrator disabled, independently of the hardware enable control signal 0 1 integrator enabled, independent ly of the hardware signal 1 0 integrator enabled when signal is at logical 0 1 1 integrator enabled when signal is at logical 1
decimation filter freescale semiconductor 28-17 pxr40 microcontroller reference manual, rev. 1 10 ssec ssec ? integrator sum exception clear bit?the ssec bit cl ears the sse flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears sse 11 scec integrator count exception clear bit?the scec bit clears th e sce flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears sce 12 reserved 13 ssovfc integrator sum overflow clear bit?the ssovfc bit clears the ssovf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears ssovf 14 scovfc integrator count overflow clear bit?the scovfc bit clea rs the scovf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears scovf 15 svrc svr clear bit?the svrc bit clears the svr integrator data overrun indication bit in the status register. this bit is self negated, therefore it is always read as zero. 0 no action 1 clears svr 16?22 reserved 23 sdf integrator data flag?the sdf bit flag indicates when a new integrator result is available at the decfilt_x_fintval register. this flag generates an interrupt request if enabled by the sdie bit in the configuration register. this flag is cleared by the sdfc status bit or by a soft reset of the decimation filter. 0 no new integrator result available 1 new integrator result available 24?25 reserved 26 sse integrator sum exception flag?the sse bit indicates an e xceptional conditi on of the integrator accumulator. this flag generates an interrupt request if enabled by t he decfilt_x_mcr bit erren, and it is cleared by the ssec bit or by a soft reset. integr ator exceptions are defined in section 28.3.13.5, integrator exceptions . 0 no exception in the integrator accumulator. 1 integrator accumulator exception. 27 sce integrator count exception flag?the sce bit indicates an exceptional condition of the integrator counter. this flag generates an interrupt request if enabled by t he decfilt_x_mcr bit erren, and it is cleared by the scec bit or by a soft reset. integrator exceptions are defined in section 28.3.13.5, integrator exceptions . 0 no exception in the integrator counter. 1 integrator counter exception. 28 reserved table 28-7. decfilt_x_mxsr field descriptions (continued) field description
decimation filter 28-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29 ssovf integrator sum overflow flag?the ssovf bit indicates an overflow of the integrator accumulator. this flag is cleared by the ssovfc bit or by a soft reset. 0 no overflow in the in tegrator accumulator. 1 integrator accumulator overflown. note: the ssovf bit samples the integrator accumulator overflow condition when and only when either registers decfilt__fintval or de cfilt__cintcnt are up dated. therefore, only one of the register pairs (decfilt_x_fintval/decfilt_x_fintcnt and decfilt_x_cintval/ decfilt_x_cintcnt) must be used by the application, in order to avoid races. 30 scovf integrator count overflow flag?the scovf bit flag indica tes an overflow of the internal integrated sample counter. this flag is cleared by the scovfc bit or by a soft reset. 0 no overflow in the integrator sample counter. 1 integrator sample counter overflown. note: the scovf bit samples the integrator accumulator overflow condition when and only when either registers decfilt_x_fintval or de cfilt_x_cintcnt are updat ed. therefore, only one of the register pairs (decfilt_x_fintval/decfilt_x_fintcnt and decfilt_x_cintval/ decfilt_x_cintcnt) must be used by the application, in order to avoid races. 31 svr integrator data overrun?the svr bit indicates that an integration value and count in the registers decfilt_x_fintval and decfilt_x_fintcnt was overwr itten by a new integrator output request and was not read by the cpu or dma. this flag generates an in terrupt request if enabled by the erren bit in the configuration register. this flag is cleared by the svrc bit or by a soft reset. 0 integrator data overrun did not occur. 1 integrator data overrun occurred. table 28-7. decfilt_x_mxsr field descriptions (continued) field description
decimation filter freescale semiconductor 28-19 pxr40 microcontroller reference manual, rev. 1 28.2.2.5 decimation filter interface input buffer register (decfilt_x_ib) the input buffer register provides access to the input buffer of the decimation fi lter when the filter is receiving input data from the cpu/ dma (decfilt_x_mcr[io_sel[1]] = 1). writes to this register are interpreted as requests to the decimation filter to pr ocess new sample data. write s to this register when decfilt_x_mcr[io_sel[1]] = 0 have no effect. address: decfilt_x_base + 0x 010 access: user read/write r000 0 intag[3:0] 000000 pre fill flush w reset000 0 0000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inpbuf[15:0] w reset000 0 0000000000 0 0 figure 28-6. decimation filter interface input buffer register (decfilt_x_ib) table 28-8. decfilt_x_ ib field descriptions field description 0?3 reserved 4?7 intag decimation filter input tag bits ?the inta g[3:0] bit field is defined as a select or signal and it is used to identify different destinations for the inbuf[15:0] data. when the input data source is the cp u/dma and the output destination is an eqadc, intag is used to address the appropriate rfifo in the eqadc block. 8?13 reserved 14 prefill decimation filter prefill/filter cont rol bit?the prefill bit selects the decimation filter operation mode. for more details, see section 28.3.4, filter prefill control . 0 decimation filter normal sample 1 decimation filter prefill sample 15 flush decimation filter flush c ontrol bit?assertion of the flush bit initialize s the decimation filter to a initial state, as defined in section 28.3.6, flush command . this bit is self negated and it is cleared only when the data is read and the flush is executed. 0 no flush request 1 flush request 16?31 inpbuf input buffer data?the inpbuf[15:0] bi t field carries the sample data to be filtered. this data buffer can be written from the eqadc or by the cpu/dma. see section 28.3.1, deci mation filter input , for more details.
decimation filter 28-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.2.2.6 decimation filter interface ou tput buffer register (decfilt_x_ob) 28.2.2.7 decimation filter coeffici ent n register (decfilt_x_coefn) address: decfilt_x_base + 0x014 access: user read only r000000000000 outtag[3:0] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 routbuf[15:0] w reset0000000000000000 figure 28-7. decimation filter interface output buffer register (decfilt_x_ob) table 28-9. decfilt_x_ob field descriptions field description 0?11 reserved 12?15 outtag decimation filter out put tag bits?the outtag[3:0] bit field is def ined as a selector signal and it is used to identify different destinations for the outbuf[15:0] data. when the output result destination is an eqadc, outtag holds the same value as the decfilt_x_ib[intag], which is used to address the destination rfifo. 16?31 outbuf output buffer data?the outpbuf[15:0] bit field is the result data in the decimation filter output buffer. it represents a fixed point signed number in two?s complem ent format and is updated only when a decimated result is ready to be transmitted, meaning it contains the last decimated result from the filter. address: decfilt_x_base + 0x020?0x040 access: user read/write 0123456789101112131415 r 8{coefn[23]} coefn[23:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r coefn[15:0] w reset0000000000000000 figure 28-8. decimation filter coeffi cient n register (decfilt_x_coefn)
decimation filter freescale semiconductor 28-21 pxr40 microcontroller reference manual, rev. 1 28.2.2.8 decimation filter tapn register (decfilt_x_tapn) table 28-10. decfilt_x_coefn field descriptions field description 0?31 coefn coefficient n field?the coefn[23:0] bit fields are the digital filter coeffici ents registers. the coefficients are fractional signed values in two?s complement format, in the range (-1 ? coef < 1). note: reads to this register are sign-extended, meaning t he coefficient?s sign bit is copied to all 8 most significant register bits. note: writing to these fields when bsy=1 is not allowed. address: decfilt_x_base + 0x0 78?0x094 access: user read only 01234567891011121314 15 r 8{tapn[23]} tapn[23:16] w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tapn[15:0] w reset00000000000000 0 0 figure 28-9. decimation filter tapn register (decfilt_x_tapn) table 28-11. decfilt_x_tapn field descriptions field description 0?31 ta p n tapn register?the read-only tapn[23:0] bit fields show s the contents of the digital filter tap registers, as fractional signed values in two?s complement format, in the range (-1 ? coef < 1). the tap registers hold the input data delay line (xn, xn-1,......,xn-7 for 8th order fir). note: reads to this register are sign-extended, meaning t he coefficient?s sign bit is copied to all 8 most significant register bits. note: the content of thes e registers is meaningless when bsy=1.
decimation filter 28-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.2.2.9 decimation filter interface enhanced debug input data register (decfilt_x_edid) the enhanced debug input data register provides read -only access to the sample data received by the decimation filter when the input is selected from an e qadc module (decfilt_x_mcr[io_sel[1]] =0), allowing the monitoring of input data from an eqadc. see section 28.3.15, enhanced debug monitor description for more details, and see section 28.3.12.1.2, input buffer enhanced debug monitor interrupt and section 28.3.12.1.4, input buffer enha nced debug monitor dma request for more information on interrupt and dma reque sts associated with the enhanced debug monitor. writes to this register have no effect. 28.2.2.10 decimation filter final integrat ion value register (decfilt_x_fintval) address: decfilt_x_base + 0x0d0 access: user read only 01234567891011121314 15 r00000000000000 0 0 w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r samp_data[15:0] w reset00000000000000 0 0 figure 28-10. decimation filter interfa ce input buffer register (decfilt_x_edid) table 28-12. decfilt_x_edid field descriptions field description 0?15 reserved 16?31 samp_data conversion sample data?the samp_data[15:0] bit field carries the data that was loaded into the decimation filter input buffer to be processed by the fir/iir sub-bl ock. this value is only updated by input data received from an eqadc (decfilt_x_mcr[io_sel[1]] = 0) , and the enhanced debug monitor is enabled (decfilt_x_mcr[edme] = 1). address: decfilt_x_base + 0x0e0 access: user read only 01234567891011121314 15 r sum_value[31:16] w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sum_value[15:0] w reset00000000000000 0 0 figure 28-11. decimation filter final integration value register (decfilt_x_fintval)
decimation filter freescale semiconductor 28-23 pxr40 microcontroller reference manual, rev. 1 28.2.2.11 decimation filter final in tegration count value register (decfilt_x_fintcnt) table 28-13. decfilt_x_fintval field descriptions field description 0?31 sum_value integration sum value?the sum_value[31:0] field holds the sum of filtered output values. the 17 most significant bits hold the integer part, and the 15 least sign ificant ones the fractional part of the integration value. the control of the integration sum a nd update of this register is determi ned by the register decfilt_x_mxcr (see section 28.2.2.3, decimation filter module ex tended configuration register (decfilt_x_mxcr) ). the register is updated only upon an integration output request. sum_value should be taken as an unsigned number when the integrator is configured for absolute operation (decfilter_mxcr bit ssig=0), and a two?s complement signed number otherwise. note: if ssat=0, decfilt_x_fintval hold s the integration sum modulo 2 17 (considering the 15-bit fractional part). note: if ssat=1, the integration sum is saturated, so that if the accumu lation overflows decfilt_x_fintval holds the value 0xffffffff for absolute integrat ion (ssig=0), or values 0x7fffffff (positive saturation) and 0x80000000 (negative saturation) for signed integration (ssig=1). address: decfilt_x_base + 0x0e4 access: user read only 01234567891011121314 15 r count[31:16] w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r count[15:0] w reset00000000000000 0 0 figure 28-12. decimation filter final integration count value register (decfilt_x_fintcnt) table 28-14. decfilt_x_fi ntcnt field descriptions field description 0?31 count integration count value?the count field holds the coun t of filtered outputs integr ated. the control of the integration sum and update of this register is determ ined by the register decfil t_x_mxcr. the register is updated together with decfilt_x_fintval, only upon an integration output request.
decimation filter 28-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.2.2.12 decimation filter curren t integration value register (decfilt_x_cintval) 28.2.2.13 decimation filter current integration count value register (decfilt_x_cintcnt) address: decfilt_x_base + 0x0e8 access: user read only 01234567891011121314 15 r sum_value[31:16] w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sum_value[15:0] w reset00000000000000 0 0 figure 28-13. decimation filter current integration value register (decfilt_x_cintval) table 28-15. decfilt_x_cintval field descriptions field description 0?31 sum_value integration sum value?the sum_value[31:0] field holds an unsigned number representing the sum of filtered output values, continuously updated as the integrati on proceeds. the control of the integration sum is determined by the register decfilt_x_mxcr (see section 28.2.2.3, decimati on filter module extended configuration register (decfilt_x_mxcr) ). address: decfilt_x_base + 0x0ec access: user read only 01234567891011121314 15 r count[31:16] w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r count[15:0] w reset00000000000000 0 0 figure 28-14. decimation filter current integrat ion count value register (decfilt_x_cintcnt) table 28-16. decfilt_x_ci ntcnt field descriptions field description 0?31 count integration count value?the count fiel d holds the count of filtered out puts integrated. the value is updated only when register decfilt_x_cintval is read, to k eep the coherency between the integration and count values.
decimation filter freescale semiconductor 28-25 pxr40 microcontroller reference manual, rev. 1 28.3 functional description the following subsections describe the functional ope ration of a single block a nd apply to all decimation filter blocks on the device. 28.3.1 decimation filter input the decimation filter receives input data from either the an eqadc block, or from the cpu using the memory mapped decfilt_x_ib register. the data source is selected by the decfilt_x_mcr[io_sel[1]] bit. note that when the decimati on filters are cascade d, filters other than the head filter receive input from the adjacent filter. see section 28.3.14, cascade mode , for more information on cascade operation. an interrupt or dma request can be generated when th e input buffer is empty, and the input data source is the cpu or dma. a dma request is generated when the decfil t_x_mcr[dsel] = 1, and the input buffer becomes empty. if dma is not enabled, an interrupt is generated by setting the decfilt_x_mcr[ibie] = 1. if both an interrupt and dma request are enabled, the dma takes precedence. an interrupt can also be generated when the input buf fer is written with a new value. this interrupt is enabled by the decfilt_x_mcr[iden] bit. when enabled and data is written to the filter input buffer, the decfilt_x_msr[idf] bit is set. the idf flag re mains set, even after the input data has been consumed by the filter and the buffer is free, until idf is cleared by software write to the idfc bit. see section 28.3.12, interrupts and dma overview , for more information on interrupt and dma requests. 28.3.1.1 input buffer overrun an input overrun occurs when the input buffer is holding input data and new data is received by the filter. see section 28.3.1, decima tion filter input , for details of the input buffer. when the decimation filter is idle (decfilt_x_msr[bsy] = 0) the filter can receive two consecutive input buffer writes without input overrun. input buffer overrun is detected and fl agged by the decfilt_x_msr[ivr] bit. the overrun interrupt is enabled by the decfilt_x_mcr[erren] bit. the input buffer overrun can occu r only in the following cases: ? when the input buffer has sa mple data to be proces sed but the filter is bus y and another input (data or timestamp) is received. ? when the input buffer has a timestamp , the internal timestamp register is loaded and the next input data is received. as an example of the input data seque nce, assume that the filter is en abled and not busy, and all registers are empty. then a word of sample data is received followed by a timestamp and another word of sample data. no input overrun occurs in this case, because th e first sample is immediately transferred to the tap input register, the timestam p is immediately transferre d to the internal timestam p storage register, and the second sample can be he ld in the input buffer until the end of the processing of the first sample data by the filter. the input overrun may occur if mo re input is received before the end of the processing, or if the filter is busy at the beginning of the received sequence.
decimation filter 28-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 when the filter is bypassed (decfilt_x_mcr[ftype] = 0b00) or in disable mode, the data from the input buffer is transferred to the output buffer, if it is not already full. if the out put buffer is full, the input buffer is loaded, and another word of input data is sent, then an input overrun occurs. 28.3.2 decimation filter output note decimation filter h is not writeable or readable from the eqadc, only by dma or the cpu. all other decima tion filters have no limitations. the decimation filter can send filtere d results directly to an eqadc, or to the cpu using the memory mapped decfilt_x_ob output buffer register. the output destination for the filter result is determined by the decfilt_x_mcr[io_sel] field. the filter result is wri tten to the output buffe r register when the decimation count is reached (eit her an eqadc or cpu destinati on). the decfilt_x_msr[odf] flag bit is set when the output buffer is updated. when an eqadc is selected for the result destination, the result is automatically tran sferred to an eqadc rfifo when the output buffer is updated. the output buffer is not updated when the d ecimation filter is in prefill mode, so the decfilt_x_msr[odf] flag is not set in that case. an interrupt or dma request can be generated when the output buffer is updated, and the output result destination is the cpu or dma. a dma request is generated when the decfilt_x_mcr[dsel] = 1, and the output buffer is updated. if dma is not enabled, an in terrupt is generated by setting the decfilt_x_mcr[obie] = 1. if both an interrupt and dma request are enabled, the dma takes precedence. when the filter is bypassed (dec filt_x_mcr[ftype]=0b00), and the eqadc is selected as the output destination, the data written into th e input buffer is delayed until the out put buffer is empty and then written to the output buffer. when the filter is bypassed and the memory mapped register is selected as the output destination, the data written into the input buffer is immediately written into the output buffer, and the decfilt_x_msr[odf] flag is set. a soft reset (decfilt_x_msr[sres]) clears the output buffer, and termin ates output data transfer to the output buffer. 28.3.2.1 output buffer overrun an output overrun occurs when the output buffer (decfilt_x_ob) is holding output data (sample or timestamp) that has not been read a nd it is overwritten with subsequent data (sample or ti mestamp). output overruns are flagged by the decfilt_x_msr[ovr] bit. an output buffer overr un interrupt is enabled by the decfilt_x_mcr[erren] bit. the output buf fer empty condition depends on the mode and output selection as follows: ? when the output result destination is an eqadc, the output buffer is considered empty when the filter output transfer to an eqadc rfifo is complete. ? when the output result destination is the cpu/dm a, the output buffer is considered empty after the buffer has been read and the de cfilt_x_msr[odf] flag is cleared. prefill inputs do not cause iir or fir output overrun for either output destination selection.
decimation filter freescale semiconductor 28-27 pxr40 microcontroller reference manual, rev. 1 when bypass mode is selected, an output overrun cannot occur because the data written into the input buffer (decfilt_x_ib) is written into the output buffer (decfilt_x_ob) only when this buffer is empty, but an input over run may still occur (see section 28.3.1.1, input buffer overrun ). 28.3.3 bypass operation bypass operation is configured by setting the field ftype[1:0] of the module configuration register decfilt_x_mcr to 00. in this case, th e input sample is sent to the out put with no change. this behavior is independent of input data source or output result destination select ions. the following applies to the bypass configuration: ? flush is ignored ? prefill is ignored ? decimation is ignored ? bsy bit is not set ? the input flag decfilt_x_msr[idf] and output flag decfilt_x_msr[odf] are set 28.3.4 filter prefill control a prefill indicates that the input data should be accepted by the decimation filter, but no decimated output should be generated while the control field indicates prefill. therefore the prefill function is used in the beginning of the filter operation to initialize and stabilize the deci mation filter without generating decimated samples. in addition, the prefill does not operate when the filter is in bypass (ftype=0b00). when the input data sour ce is an eqadc (decfilt _x_mcr[io_sel[1]] = 0), prefill is enabled/disabled in the eqadc conversion command word (ccw). see section 28.4.1, eqadc configuration for decimation filter operation for more information on an eqadc configuration of decimation filter functionality. when the input data source is the cpu/dma (decfilt_x_mcr[io_ sel[1] = 1]), prefill is controlled by the prefill fiel d in the decfilt_x_ib register. when the prefill control is set, the de cimation filter block operates as follows: ? input data is processed normally by the di gital filter and tap values are updated. ? the decimation counter is maintained in reset value. ? the output buffer is not updated and no output interrupt is generated. ? the accompanying timestamp for the identifi ed prefill conversion data is not bypassed. ? the overflow detector/fla g operates normally and the error in terrupt request is set if enabled.
decimation filter 28-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.3.5 timestamp data transmission 28.3.5.1 timestamp data when the selected input source is the eqadc, the e qadc can be configured to send timestamp data after related sample data for filtering. th e timestamp is sent back to the rf ifo following the respective filter output, using the same mechanism. si nce the decimation filter takes several clock cycles to process a sample, the timestamp is copied into an internal time stamp register until the filt ered output is sent out, therefore freeing the input buf fer for more sample data. timestamp information is not supported when the input data source is the cpu or dma. 28.3.5.2 timestamp management the timestamp data input is automatically sent to the decimation filter by the eqadc when configured to do so in the eqadc conversion command word. however, some add itional conditions are considered: ? the timestamp is additional in formation that accompanies a sa mple conversion data. the eqadc block sends the decimation filter the conversion data with control bits for either prefill or filter operation. this data may optionally be followed by the corresponding timestamp data. when the corresponding conversion data is mark ed for prefill, the timestamp da ta is not sent to the output buffer. this occurs because the filter re sult is not sent to the output buffer. ? similarly, when the filter is decimating the results , the timestamp is only se nt to the output buffer if the corresponding received conversion data has gene rated a filter output that is selected by the decimation counter to be sent to the output buffer. other received ti mestamps that come with data not selected by the decimator are discarded. 28.3.6 flush command the flush signal is used by the decimation filter to execute a partial reset of the filter. this is useful when the same filter is used on a new se t of data samples after finishing th e filtering of another set of data. when the flush control is detected, all filter taps are cleared and the dec_counter[3:0] field in the status register decfilt_x_msr is reset. the flush function does not clear the coefficient registers (dec filt_x_coefn) in the decimation filter, thus it is not required to re-write these registers after a flush. the output buffer also keeps the last result and may be retrieved until the next output is posted. the flush control precedes the input data to be fi ltered. therefore, the corre sponding sample data is processed by the block after the flush. when input is from an eqadc (d ecfilt_x_mcr[io_sel[1] = 0]), the flush command is included in the eqadc conversion command word. see section 28.4.1, eqadc configuration for decima tion filter operation for more information on an eqadc configuration of decimation filter functionality. when input is from the cpu/dm a (decfilt_x_mcr[io_sel[1]] =1), the flush command comes from the flush bit in the decfilt_x_ib register. note that a word of valid sample data can be available at the sa me time the flush signal is asserted. in this case the flush is executed and the sample is processed after the flush. the flush command is ignored when the decimati on filter is disabled (decfilt_x_mcr[mdis]=1).
decimation filter freescale semiconductor 28-29 pxr40 microcontroller reference manual, rev. 1 28.3.7 soft reset command the soft reset command is request ed through the self nega ted bit sres of the decfilt_x_mcr register and provides the cpu with the capability to initializ e the decimation filter. after the software reset is issued, all internal filter tap regist ers, the decimation counter, and the st ate machine are put in to the reset state. the status register decfil t_x_msr is also cleared. the coeffi cient registers are not affected by the soft reset. if the filter is currentl y processing data (the mac is active and decfilt_x_msr[bsy]=1), the proces sing is aborted. in addition, any pending output data transfer to the eqadc rfifo is terminated. the software rese t command has precedence over all other register control bits except the module disable bit. the decfilt_x_msr[bsy] is set on the detection of the assertion of the decfilt_ x_mcr[sres] bit, and remains set until the reset procedure is complete. the configuration register decfilt_x_mcr is also not affected by a soft reset, except for the self-negation of the sres bit. when in debug or freeze mode, the soft reset is execu ted but the filter remain s in debug or freeze mode. 28.3.8 freeze mode the freeze mode operation is entered using the fren and frz bits in the de cfilt_x_mcr register, or when the entire soc enters debug mode. it is not possible to ente r freeze mode when the deci mation filter is disabled. in case of a freeze mode request during the processing of an input sample, the current processing is finished and then the decimation filter block enters freeze mode. access to all memory mapped registers in the de cimation filter remains active in freeze mode. 28.3.9 filter implementation the filter hardware shown in figure 28-15 contains eight taps which may be configured as an iir or fir filter. multiplexer a controls the bypass filter path and multiplexer b c ontrols/selects the filter mode of operation, to either iir mode or fir mode. the selection is controlled by the ftype[1:0] bits in the filter module configuration register. the or der of the filter can be controlle d by setting the appropriate filter coefficients to zero. the iir can be up to 4rd order and the fir up to 8th order.
decimation filter 28-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 28-15. filter configuration paths (fir or 1x4poles iir) 28.3.10 rounding the decimation filter performs rounding operations in two diff erent locations, as shown in figure 28-15 : ? to obtain the filter output result with 16 bits ? to obtain the iir feedback result to be stored in tap4 registers with 24 bits the rounding mechanism implements the c onvergent rounding methodology (also known as round-to-nearest even number), which makes the d ecision on rounding up or down based on the value of the lower portion of data to be rounded (ls_word ). the rounding up/down condition is equal to the traditional rounding except when the ls_word has th e format {1000...00}. in this particular case, the rounding procedure is like the example of figure 28-16 . if the ms_word is odd, the value is rounded up. otherwise the value is rounded down. by-pass fir z -1 z -1 z -1 z -1 + coefficient 2 tap1 coefficient 4 coefficient 3 tap2 tap3 tap0 coefficient 1 x(n) + coefficient 6 ta p 5 coefficient 8 coefficient 7 tap6 ta p 7 ta p 4 coefficient 5 y(n) 01 10 b z -1 z -1 z -1 z -1 round/sat ftype[1:0] round/sat iir 00 a scale factor s register coefficient 0
decimation filter freescale semiconductor 28-31 pxr40 microcontroller reference manual, rev. 1 figure 28-16. convergent rounding methodology 28.3.11 saturation filter output saturation occurs when an overflow or underflow condition of th e filter is detected by dedicated logic, and if it is enab led by the sat control bit of the c onfiguration regist er decfilt_x_mcr. in this condition, the filter output is set to a saturated value equal to the maximum or minimum value that can be represented by the 16-bit output port. also, for the iir filter an equivalent logic is used to assert the saturation for the 24-bit feedback result. 28.3.12 interrupts and dma overview there are several host request events that can be enabled using th e module configurati on register (mcr). an interrupt request can be issued under any of the following conditions: ? when a word of input data is received ? when the input buffer can receive data ? when a word of output data is available ? when an error has occurred. the input data flag decfilt_x_msr[idf] is set when a new input data is received from the cpu or an eqadc. note that this flag is not used to generate read or write requests (as defined in section 28.3.12.1, input buffer interrupt and dma requests ). output data is available and its flag (decfilt_x_m sr[odf]) is set when the input data sample is processed by the filter, the decimation counter matches the decimation rate value, and it is moved to the output buffer. it is not used to gene rate read requests (as defined in section 28.3.12.2, output buffer interrupt and dma requests ). an error event in the decimation filter bl ock is defined as one of these events: ? overflow in the filter, fl agged by decfilt_x_msr[ovf] ? overrun in the decimation filter input, flagged by decfilt_x_msr[ivr] ? overrun in the decimation filter output, flagged by decfilt_x_msr[ovr] xx.......xx.......0010 1 xx.......xx.......00100 xx...xx 1000.....00......00 before rounding xx.......xx.......00100 xx...xx rounded down ms_word ls_word +0 xx...xx 1000.....00......00 before rounding xx.......xx.......00110 xx...xx rounded up +1
decimation filter 28-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? overrun in enhanced debug monitor, flagged by decfilt_x_msr[divr] ? integrator overrun, flagged by decfilt_x_msr[svr] ? integrator value exception, flagged by decfilt_x_msr[sse] ? integrator count exception, flagged by decfilt_x_msr[sce] a filter overflow occurs when the tw o?s-complement result value from the mac accumulator is out of the range of values that can be stored in tap register 4 (iir) or in the output register. an input overrun occurs when the input buffer is holding a word of input data and one more word of data is received by the filter. see section 28.3.1.1, input buffer overrun , for more details. an output overrun occurs when a new word of data is sent to the output buffer but the previous word of data has not been handled yet. see section 28.3.2.1, output buffer overrun , for more details. these flags can be set for input from or output to an eqadc, however they are only cleared by ? the cpu, or ? by the soft reset command (decfilt_x_mcr[sres] ? by the clear flag bits in the decfilt_x_msr register. the dma function for integrator result, input and output buffers is enabled setting the decfilt_x_mcr[dsel] = 1. the dma reque st generally replaces the inte rrupt request that is normally generated by these register s/conditions and is discu ssed in more detail in section 28.3.12.1.3, input buffer dma request , section 28.3.12.2.2, output buffer dma request , and section 28.3.12.3, integrator interrupt and dma requests . 28.3.12.1 input buffer in terrupt and dma requests 28.3.12.1.1 input buffer interrupt this interrupt is enabled by the decfilt _x_mcr[ibie] bit and is asserted only when decfilt_x_mcr[dsel] = 0. if decfilt_x_mcr[dsel] = 1, a dma request is generated instead (see section 28.3.12.1.3, input buffer dma request ). when this request is asserted, the decfilt_x_msr[ibif] bit is set to indicate a pending interrupt. when the input data source is the cpu, the input buffe r interrupt request is asserted when the input buffer is empty, meaning the block is requesting data be wr itten into the input buffer. the interrupt request is cleared when the cpu writes a one to the decfil t_x_msr[ibic] bit, or by a soft reset command. 28.3.12.1.2 input buffer en hanced debug monitor interrupt when the input data source is an eqadc, dma is disabled, and enhanced debug is enabled, the input sample data can be read by the cpu when this interrupt request is asserted. the interrupt is asserted when a new word of sample data is supplied to the filter, a nd gives the application visibility into the input data being from an eqadc. in enhanced debug mode, if the input buffer is overwritten by the next word of sample data , an input read overrun event can occur (the decfilt_x_msr[divr] bi t is asserted) if the interrupt request is not cleared before, or at the same time as, the new sample arrives to set the interrupt. the
decimation filter freescale semiconductor 28-33 pxr40 microcontroller reference manual, rev. 1 decfilt_x_msr[divr] bit is clea red by writing a one to the decfilt_x_msr[divrc] bit. note however, in enhanced debug mode, the set condition has higher pr iority than the clear. this means that if the set condition occurs at the same time the cpu writes the clear bit (dec filt_x_msr[ibic] to clear the interrupt, the interrupt remains asserted. 28.3.12.1.3 input buffer dma request this dma request is enabled by setting the io_s el field and the dsel bit in the decfilt_x_mcr register. when cpu/dma is selected as the input da ta source, the input buffer dma request is asserted when the input buffer is available to receive a convers ion sample (it is not holding a word of data). this dma request is cleared when an input data word is written to the input buffer. therefor e, the dma request is always cleared before it is asserted again. th is dma request can also be cleared by a soft reset. 28.3.12.1.4 input buffer en hanced debug monitor dma request when an eqadc is the input data source, dma is enabled, and enhanced debug is enabled, the input sample data can be read by dma when this dma request is asserted. the request is asserted when a new word of sample data is written into the input buffer to be processed. as th is filter register is overwritten by the next word of sample data, a dma read overrun event can occur (the decf ilt_x_msr[divr] bit is asserted) if the dma request is not cleared before, or at the same time as, a new sample arrives to set the dma request. the decfilt_x_msr[divr] bit is cleared by writing one to the decfilt_x_msr[divrc] bit or by soft reset. 28.3.12.2 output buffer in terrupt and dma requests 28.3.12.2.1 output buffer interrupt this interrupt is enabled by setting the decfilt _x_mcr[obie] bit, and is asserted when the output buffer is updated, cpu is selected for the out put destination, and dma is disabled. the decfilt_x_msr[obif] flag bit is set wh en the interrupt request is asserted. the output buffer interrupt request can also be asserted when decfilt_x_mcr[sdie] = 1, and an integrator result is ready to be read. this cond ition is indicated when the decfilt_x_mxsr[sdf] bit is set. note that both the filter output and integrator output sh are the same interrupt source. this interrupt request is clea red by writing a 1 to the bit decfilt_x_msr[obic] and/or the decfilt_x_mxsr[sdfc] bits, or by a soft reset command. 28.3.12.2.2 output buffer dma request when the cpu is selected as the output destinati on, and dma is enabled, the output buffer can be read using dma. the output buffer dma request is asserted when the output buffer receives a new result from the filter. this dma request is cleared when the output buffer is read by the processor, or a soft reset occurs.
decimation filter 28-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.3.12.3 integrator interrupt and dma requests an interrupt or dma request can be asserted when an integrator output is ready to be re ad or an overflow or error condition occurs in either the integrator su m or count values. integrator interrupt requests are enabled by the decfilt_x_mcr[sdie] bit, and flagge d in the decfilt_x_mxsr[sdf] bit. integrator dma requests are enabled by the decfilt_x_mxcr[sdmae] bit. 28.3.13 integrator the decimation filter output result may be optionall y routed to a dedicated hardware integrator. the integrator may be operated in a windowed mode, cont rolled by signals routed internally from etpu2 channels, or operated in a continuous mode. additionally, the integrat or output may be configured to saturate at the maximum value of the supported range, or permit ted to continue integration. figure 28-17 shows the high level data flows and controls for the integrator. the rfifo and output buffer data paths are shown in this figure to highlight that they are independent of the integrator. note however that the output buffer shares a dma and interrupt reque st with the integrator output value, fintval (decfilter_fintval). figure 28-17. integrator data and control 28.3.13.1 integrator inputs the integrator input can come either directly from the filter output or from the deci mator output, selected by the decfilter_mxcr[sisel] (see section 28.2.2.3, decimation filter module extended configuration regist er (decfilt_x_mxcr) ?). prior to integration a hardware option, controlled by decfilter_mxcr[ssig], is pr ovided to convert the input to its absolute value. note the integrator accumulates input samp les when bypass is selected in the filter. fintcnt fintval cintcnt cintval output buffer decimator filter output start etpu2 channel reset etpu2 channel pause integrator & sample counter integrator & sample counter select select rfifo dma or interrupt dma or interrupt sample count integration value
decimation filter freescale semiconductor 28-35 pxr40 microcontroller reference manual, rev. 1 28.3.13.2 integrator output the integrator output is provided in two sepa rate 32 bit registers: decfilter_fintval and decfilter_cintval. decfilter_fintval is only upda ted when an output re quest is made by an etpu2 channel or by a core or dma access to a configuration register. decfilter_cintval is updated whenever a new integration re sult is available or when a rese t request is made by hardware or software. the output is in one of two forms: ? the 32-bit, fixed point unsigned accumulation of the absolute values from the filter output, when configured for absolute operation (decfilter_m xcr[ssig] = 0). this allows a total of 131071 samples to be integrated before an overflow occurs. ? the 32-bit, fixed point signed two?s complement accumulation of the signed values from the filter output, when configured for signed operation (decfilter_mxcr[ssig] = 1). this allows a total of 65536 samples to be integrated before an overflow occurs the fractional part of the accumulat ion is 15 bits wide in both forms. an accumulation overflow is flagged in decfil ter_mxsr[ssovf] when an output request occurs. the accumulator can overflow in either of th e ways described below, selected through the decfilter_mxcr[ssat]: ? saturated accumulation (ssat=1), so that an ove rflow results in the value of 0xffffffff for absolute value accumulation ( ssig=0), or 0x7fffffff (positive) and 0x80000000 (negative) for signed accumulation (ssig=1). ? non-saturated accumulation (ssat=0), so th at an overflow results in the modulo 2 17 accumulation value. this operation is only allowed in absolute accumulation (ssig=0). note a non-saturated overflow that occurs before ssovf is cleared is still flagged in the next output request. the integrator output value becomes availa ble in register decfilter_fintval (see section 28.2.2.10, decimation filter final integration value re gister (decfilt_x_fintval) ) when an integrator output request is issued. the integrator output reque st can be issued in the following ways: ? by an etpu2 channel; the enabling and selection of the signal request modes is done through the decfilter_mxcr[srqsel] field (see section 28.2.2.3, decimation filter module extended configuration regist er (decfilt_x_mxcr) ), and the channel selection is done through the zseln fields of siu_decfil 1 and siu_decfil2 and siu_de cfil3 registers in the siu module. ? by software, writing 1 to the decfilter_mxcr[srq]; the integrator output request also updates the register decfilter_ fintcnt, which holds the number of samples accumulated into the register decfil ter_fintval. this accumulated sample counter can operate either in a saturated or ?wrapped? count mode, as selected by decfilter_mxcr[scsat]. in both cases, a counter overflow is flagged by decfilter_mxsr[scovf]. note a non-saturated overflow that occurs before an scov f clear is still flagged in the next output request.
decimation filter 28-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 an integrator output update can also issue a dma or interrupt reques t. the interrupt and dma requests are the same ones used for the filter output buffer (see section 28.3.12.2, output buff er interrupt and dma requests , and section 28.3.12.1.3, input buffer dma request ). decfilter_mcr[sdie] is used to enable integrator interrupts, a nd the decfilter_mxcr[sdmae] enable s the dma integrator requests. the integrator dma request uses the same signal as the filter out put dma request, so one must never use any configuration that allows both the integr ator and filter output to make dma requests. integrator output updates are flagged by decfilter_mxs r[sdf]. the integrator overrun is detected in the same way as a filter output buffer overr un, and is flagged by decfilter_mxsr[svr]. an integrator overrun also genera tes an error interrupt if decfilter_mcr[erren] = 1 (see section 28.3.2.1, output buffer overrun ). registers decfilter_cintval a nd decfilter_cintcnt provide a way to poll intermediate integration values and sample counts, respectively (see section 28.2.2.12, decimati on filter current integration value register (decfilt_x_cintval) , and section 28.2.2.13, decimation filter current integration count value re gister (decfilt_x_cintcnt) ). decfilter_cintval is updated whenever the integrator is rese t or a new sample is accumulated. decfilter_cintcnt is updated only when decfilter_cintval is read, so that cohe rency between the value and count values is guaranteed. therefore, the read access order of that pair of registers must be de cfilter_cintval first, followed by decfilter_cintcnt. note the flags ssovf and scovf can also asserted when decfilter_cintval is read. the ssovf and scovf set and clearing rules apply for the decfilter_cintval read the same way as for an integrator output request. 28.3.13.3 integrator reset the integration value is reset to the value of zero, in the following ways: ? by hardware: on hardware reset, or controlled by an etpu2 channe l; the enabling and selection of the zero signal modes is done thr ough decfilter_mxcr[szrosel] (see section 28.2.2.3, decimation filter module extended conf iguration register (decfilt_x_mxcr) ), and etpu2 channel selection is defined by the zseln fiel ds of the siu_decfil1 and siu_decfil2 and siu_decfil3 registers in the siu module. ? by software: on software reset, or wr iting 1 to the decfilter_mxcr bit szro; the integrator reset also zeroes the internal counter of accumulated samples and the internal overflow state (but not ssovf and scovf). software and hardware reset resets all integrator registers immediately. an integrator zero command from an etpu2 channe l or by software (szro) affects the integrator registers and flags as follows: ? decfilter_cintval resets immediately; ? decfilter_cintcnt does not reset im mediately; it is updated only upon a decfilter_cintval read, loaded with the numbe r of integrated samples occurred after the reset;
decimation filter freescale semiconductor 28-37 pxr40 microcontroller reference manual, rev. 1 ? decfilter_fintval and decfilter_fintcnt do not reset immediately; being updated only upon a new output request (see section 28.3.13.2, integrator output ); if a integrator software zero command (through szro bit) a nd an integrator output request (through srq bit) are made at the same time, the register s decfilter_fintval and de cfilter_fintcnt are updated with the last internal values before reset; th e same applies to simultaneous integrator zero command and output reque st by hardware signal; ? all internal overflow flags note an integrator zero request does not negate the ssovf and scovf flags note the integrator reset does not depe nd on the integrator enabling (see section 28.3.13.4, integrator enabling and halting ). 28.3.13.4 integrator enabling and halting two mechanisms, enabling and halting, drive the integr ator accumulation, allowing it to be controlled by a combination of two sources: ? both software ? both hardware (etpu2 channels) ? one hardware (etpu2 ch annel) and other software values are accumulated when the integrator is enabled and not halted. the integrator halt and enable states can be controlled in the following ways: ? by hardware, through etpu2 channels; the enabli ng and the selection of the signal request modes is done through decfilter_mxcr[sensel] and decfilter_mxcr[shltsel] fields, respectively (see section 28.2.2.3, decimation fi lter module extended c onfiguration register (decfilt_x_mxcr) ), and channel selection is done through the siu_decfil1 and siu_decfil2 and siu_decfil3 registers in the siu module. ? by software, through the same decfilter_mxcr[sensel] and decfilter_mxcr[shltsel] fields. note that these fields are in different bytes, so that two distinct, concurrent software ta sks can avoid coherency problems by changing the fields using byte read-modify-write accesses. etpu2 selection for the integrator enable st ate is defined by siu_de cfiln[zseln] fields. etpu2 selection for the integrator halt st ate is defined by siu_decfiln[hseln] fields. note enabling and halting does not affect output requests or integrator reset. 28.3.13.5 integrator exceptions integrator may run into exception states due to overflo w, either of the accumulated value or the sample counter. exceptions are flagged by the decfilter_m xsr bits sse, for sum value exception, and sce,
decimation filter 28-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 for counter exception. these flags generate an error interrupt, if it is enabled (see section 28.3.12, interrupts and dma overview ). the accumulator exception condition de pends on whether it operates in satu rated mode or not, as follows: ? in saturated operation (decfilter_mxcr[ssa t] = 1): a sum exception occurs (sse=1) whenever an overflow is flagged; sse asserts together with ssovf. ? in non-saturated operation (decfilter_mxcr[ss at] = 0): a sum exception occurs (sse=1) when an overflow is flagged and decf ilter_mxsr[ssovf] is already set to 1. ? in non-saturated operation, an accumulator excepti on also occurs if th e accumulator overflows twice without any update of th e final integrator value decfilter_fintval or the current integrator counter decfilter_cintcnt (by a read to the decfilter_cintval register), neither an integrator reset occurs. the ssovf flag does not assert in this situation. note the ssovf flag can only be asserted upon a hardware request, a software request, or when decfilter_cintval is read, based on the internal accumulator overflow state. similarly, the sample counter exce ption condition depends on whether it operates in saturated mode or not, as follows: ? in saturated operation (decfil ter_mxcr[scsat] = 1): a counter exception occurs (sce=1) whenever an overflow is flagged; sce asserts together with scovf. ? in non-saturated operation (decfilter_mxcr[ scsat] = 0): a counter exception occurs (sce=1) when an overflow is fl agged and the decfilter_mxsr bit scovf is already set to 1. ? in non-saturated operation, a counter exception also occurs if the counter overflows twice without any update of the final count decfilter_fin tcnt or the current integrator counter decfilter_cintcnt (by a read to the de cfilter_cintval regi ster), neither an integration reset occurs. the scovf flag does not assert in this situation. note the scovf flag can only be asserted upon a hardware request, a software request, or when decfilter_cin tval is read (also updating decfilter_cintcnt), based on the internal counter overflow state. 28.3.14 cascade mode cascade mode is a configuration of the decimation filters where two or more filters are chained together serially to provide more complex fi ltering functions. all filt ers in the cascade arra ngement are configured to operate in cascade mode using the cascd[ 1:0] field in the de cfilt_x_mcr register. figure 28-18 shows an example of a simple casca ded arrangement. this example shows the eqadc being used for both data input and output, but cascaded filters may also be conf igured to receive data from the cpu/dma. the ?head? receives the raw data to be filtered from the eq adc. the bottom block, or ?tail?, is the last filter block in the chain. it sends the output result to the selected data destination. the blocks in between, or ?middle? blocks, do not exchange data (receive/tra nsmit) with the eqadc (o r cpu/dma), only with the
decimation filter freescale semiconductor 28-39 pxr40 microcontroller reference manual, rev. 1 preceding and following decimation filt er blocks in the cascade. middl e blocks are optional. a minimum of two blocks, one head block feeding one tail block can be used in cascade. note the values passed between cascaded blocks can be monitored using enhanced debug monitor (see section 28.3.15, enhanced debug monitor description ). the following are general considerations for creating and using cascaded filters: ? the block configurations as hea d, tail or middle must respect thei r physical connections such that all the following apply: ? a ?head? block must feed a ?middle? or a ?tail? block ? a ?middle? must feed another ?m iddle? block or a ?tail? block ? a ?tail? feeds no other block, and its output will be either the cpu/dma interface or the eqadc fifos. ? a ?head? is fed by no other block. its input is either the cpu/dma interface or the eqadc. ? cascaded filters must be sequential, that is; fi lter a feeds filter b wh ich feeds filter c etc. ? as a consequence of the conditions above, there must be one and only one ?head? block and one and only one ?tail? block in a cascade. ? more than one group of physically chained blocks can form a cascade. for example, figure 28-19 shows two physical chains, with blocks a and b conf igured as head and tail, respectively, forming one cascaded filter block. two of the remaining blocks form anothe r cascaded filter block starting with block e (head), and e nding with block f (tail). ? blocks not used in a cascaded chain can be used normally by setting the decfilt_x_mcr[cascd] field to 0b00, as shown in section 28.3.14.1. ? the optional connection show fr om block l to block a in sect ion 28.3.14.1 allows block l to be configured as head or middle, feeding block a configured as middle or tail, yielding more flexibility, as in the last example of section 28.3.14.1. ? the input to a cascaded configuration is sele cted by the decfilt_x_mcr [io_sel] bitfield of the head block. the output target of th e cascaded blocks is selected by the decfilt_x_mcr[io_sel] bitfield of the tail block.
decimation filter 28-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.3.14.1 example configurations the following diagrams illustrate some of the po ssible options for using th e decimation filters in a cascaded configuration. in all illu strated examples, the decfilt_x_mcr[i o_sel] bits are set to select the eqadc as the source for input conversion data, and the eqadc rfifos as destination for the outputs of the filter(s). figure 28-18. cascaded filters figure 28-19. multiple cascaded filters eqadc rfifos decfilt_b (middle) decfilt_c (tail) cpu configuration/control data decfilt_a (head) mcr[io_sel]=0b00 mcr[cascd]=0b01 mcr[io_sel]=0b00 mcr[cascd]=0b11 mcr[io_sel]=0b00 mcr[cascd]=0b10 decfilt_a eqadc rfifos cpu data configuration/control data decfilt_b decfilt_e (head) (head) (tail) decfilt_f (tail) mcr[io_sel]=0b00 mcr[cascd]=0b01 mcr[io_sel]=0b00 mcr[cascd]=0b01 mcr[io_sel]=0b00 mcr[cascd]=0b10 mcr[io_sel]=0b00 mcr[cascd]=0b10
decimation filter freescale semiconductor 28-41 pxr40 microcontroller reference manual, rev. 1 figure 28-20. mixed cascaded and single blocks 28.3.14.2 cascade freeze, stop, and configuration change procedures to change a block configuration mode to or from cascade mode, the fo llowing safe procedures must be observed: ? to modify a cascade combo, either to single or any other casc ade combo combination, all the cascade combo blocks must have their inputs disabled (using de cfilt_x_mcr[idis]), in order, from the head to the tail block. after a block idis bit has been set to 1 (one), one must wait for its decfilter_x_msr bit bsy to be 0 (zero) before disabling the input of the next block in the sequence. ? each block in a new cascade com bo must be configured with its input disabled. when the mode configuration is done, the combo blocks must have their inputs enabled in order, from the tail towards the head block. ? a single block must also be rec onfigured the same way, to or from a cascade combo configuration: first disabling its input , and then waiting for a non-busy st ate before writing decfilter_x_mcr field cascd. to take cascade combo blocks to or from freeze or low power modes, a similar procedure must be used: ta i l head middle ta i l single head middle single decfilt_a decfilt_b decfilt_c decfilt_d decfilt_e decfilt_f decfilt_k decfilt_l eqadc rfifos cpu configuration and control mcr[io_sel]=0b00 mcr[cascd]=0b01 mcr[io_sel]=0b00 mcr[cascd]=0b11 mcr[io_sel]=0b00 mcr[cascd]=0b10 head: middle: tail: configurations: single: mcr[io_sel]=0b00 mcr[cascd]=0b00
decimation filter 28-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? take the head to freeze or lo w-power first, wait for decfil ter_x_msr bit bsy=0, and repeat the procedure for the other blocks in the chain in sequence, towards the tail block. take the blocks out of freeze or low-power modes in the inverse sequence, from tail to head. 28.3.15 enhanced debug monitor description this feature is enabled by the edme bit in th e configuration register decfilter_x_mcr. the monitoring operation is applicable only to an eqadc input data source, and a pplies when filters are cascaded. the enhanced debug monito r feature makes the input sample data also available in the decfilter_x_edid register. a dma or interrupt request (selected by decfilt_x_mcr[dsel]) indicates a new input was fed and decfilter_x_edid was updated. the input is processed normally by the filter. an enhanced debug input data register (decfil ter_x_edid) overrun can occur if a sample is not read by the cpu or dma before overw ritten by a new sample. the overrun is indicated in a separate flag divr in the status register decfilter_x_msr. if the erren bit is set in the decfilter_x_mcr configuration register, this overrun asserts the an interrupt request. 28.4 application information the following sections describe common use cases and configurations of the decimation filter block. 28.4.1 eqadc configuration for decimation filter operation 28.4.1.1 eqadc configuration / decimation filter input in normal mode of operation of the decimation filter , filter data inputs are supplied by an eqadc block and the filter output is returned to the specified rfifo in the e qadc. in standard eqadc operation, conversion results are rout ed directly from the converter to one of the local eqadc rfifo buffers. however, by using alternate conversion command word configurations in the eqadc, conversion results can be routed to the decimation filter block. addi tionally, the same eqadc conversion results can be routed to a second decimation filter block specified by an extended alte rnate configuration register. the eqadc can send either conve rsion data or timestamp data. the conversion data is filtered by the decimation filter and the timestam p is bypassed and delayed until ready to be sent back to the eqadc when the relevant conversion da ta is filtered and available. in the eqadc, the alt_config_sel[0:7] field of the conversion command word (ccw) specifies whether an alternate configuration is used for the adc conversion. the values for this field are given in table 28-17 . the eqadc can store up to eight alternate conf igurations, which can be dynamically selected during the adc conversion with th e ccw. when the alt_config_sel field is set to 0x00, no alternate configuration is used, and the adc convers ion is processed according to the ccw.
decimation filter freescale semiconductor 28-43 pxr40 microcontroller reference manual, rev. 1 each eqadc alternate configurati on uses the format specified in figure 28-21 . the ret_inh, dest, and fmta bits/fields in the altern ate configuration register pertain to decimation filter operation, and the ressel and pre_gain fields do not. the ret_in h bit is used by eqadc to set the decimation filter in/out of prefill mode. the dest field determines which de cimation filter the c onversion result is sent to, and the encoding is given in table 28-18 . the fmta bit determines wh ether the data going to the decimation filter is signed or unsigned. the eight alternate config urations are stored in the adc by ex ecuting write commands to the on-chip adc alternate configuration regist ers. the write command is specifi ed in the write configuration command format for on-chip adc operation sec tion of the reference manual. the alternate configuration register a ddresses 0x30 through 0x4c for each adc0/1 converter in an eqadc are given at the top of the register diagram. table 28-17. eqadc alternate configuration selection alt_config_sel[0:7] alternate configuration 0x00 alternate configuration not used 0x08 1 0x09 2 0x0a 3 0x0b 4 0x0c 5 0x0d 6 0x0e 7 0x0f 8 adc0/1 register address: 0x30 , 0x34, 0x38, 0x3c, 0x40, 0x44, 0x48, 0x4c access: user read only 0123456789101112131415 r ret_ inh 0 dest fmta 0 ressel 0000 pre_gain w reset0000000000000000 figure 28-21. alternate configurati on 1-8 control registers (adc_acr1-8)
decimation filter 28-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.4.1.2 eqadc configurat ion / decimator output table 28-18. adc_acr1-8 field descriptions field description ret_inh result transfer inhibit / decimation filter pre-fill?thi s bit is used to inhibit the transfer of the result data from the peripheral module to the result queue. when th e module is a decimation filter, this bit sets the filter in a special mode (pre-fill) in which it does not generate decimated samples out from the conversion results received from the eqadc block, but the conversion samples are used by the filter algorithm. this feature allows a proper initializat ion of the decimation filt er without generating any decimated result. or this bit is useful for sending th e result of the adc to the stac bus master but not putting the result in the result queue. 0 result transfer to result queue / decimation filter in filtering mode 1 no result transfer to result queue / decimation filter pre-fill mode dest[0:3] conversion result destination selection?the dest [0:3] field selects the decima tion filter destinations of the conversion result generated by the alternate conversion command. this field also affects the behavior of the fmta bit and the ffmt bit of the conversion command for alte rnate configurations (see conversion command format for alternate configurations ). fmta conversion data format for alternate configuration? if the dest field is not 0b000, the fmta bit specifies how the 12-bit conversion data returned by the adcs is formatted into the 16-bit data which is sent to the parallel side interface. 0 right justified unsigned 1 right justified signed dest[0:3] description 0000 the conversion result is sent to the rfifos. the data format is specified by the ffmt bit in the conversion command. 0001 the conversion result is sent to decimation filter block a. 0010 the conversion result is sent to decimation filter block b. 0011 the conversion result is sent to decimation filter block c. 0100 the conversion result is sent to decimation filter block d. 0101 the conversion result is sent to decimation filter block e. 0110 the conversion result is sent to decimation filter block f. 0111 the conversion result is sent to decimation filter block g. 1000 the conversion result is sent to decimation filter blocks a and e. 1001 the conversion result is sent to decimation filter blocks b and e. 1010 the conversion result is sent to decimation filter blocks c and e. 1011 the conversion result is sent to decimation filter blocks d and e. 1100 the conversion result is sent to decimation filter blocks a and g. 1101 the conversion result is sent to decimation filter blocks b and g. 1110 the conversion result is sent to decimation filter blocks c and g. 1111 the conversion result is sent to decimation filter blocks d and g.
decimation filter freescale semiconductor 28-45 pxr40 microcontroller reference manual, rev. 1 the rfifo number that receives the filtered data from the decimation fi lter block, or directly from the adc, is specified in the message_tag[8:11] fi eld in the eqadc ccw (see ?conversion command format for the standard configurati on section of the reference manual). 28.5 use cases the following use cases provide examples of how to configure the decimation filter for different modes. one use case describes the mode that filters the conversion re sults that directly tran sferred from the adc. in this case, the appropriate software initialization of the ad c configuration register is described to enable the transfer of an adc result to the decimation filter module wit hout cpu intervention. the second use cases describes the stand-alone mode, where data previously stored in a memory table is transferred into the filter and subsequent fi ltered data extracted using cpu interaction. for all uses cases, the decimation filter is configured as an iir filter, with exampl e filter characteristics. an explanation of the iir configuration and coefficient select ion is give in the next section. 28.5.1 iir filter configuration this section describes the topology of the iir filter that is implemented in the de cimation filter hardware and provides a definition of the co efficients for an elliptical low pass, 4th order iir filter. figure 28-22 shows the filter functional diagram, consisting of 4 feed-forw ard stages and 4 feedba ck stages, to provide a maximum of a 4th order iir filter. ressel[0:1] adc resolution selection. 00 adc set to 12-bits resolution 01 adc set to 10-bits resolution 10 adc set to 8-bits resolution 11 reserved pre_gain[0:1] adc pre-gain control?the pre_gain[0:1] cont rols the gain of the adc input stage by changing the internal adc iterations in the gain stage. 00 x1 gain 01 x2 gain 10 x4 gain 11 reserved table 28-18. adc_acr1-8 field descriptions (continued) field description
decimation filter 28-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 28-22. 1 x 4 poles iir filter functional diagram the generalized difference e quation for the iir filter of figure 28-22 can be written as: eqn. 28-1 where x(n) is the filter input at time n, y(n) is the filter output at time n , n is the number of feed-forward filter coefficients minus one, b i are the feed-forward filter coefficients, m is the number of feed-back filter coefficients, and a j are the feedback filter coefficients. in order to optimize the hardware implementation, the co efficients must be scaled to a maximum range of +1 to -1. taking s caling into account, equation 28-1 can be expressed as: eqn. 28-2 all coefficients are scaled down by s, and the output of the accumulator is multiplied by s. y(n) z -1 z -1 z -1 z -1 + + + + b 0 z -1 z -1 z -1 z -1 + + + + x(n) a 4 a 3 a 2 a 1 b 4 b 3 b 2 b 1 x(n-1) y(n-1) x(n-2) x(n-3) x(n-4) y(n-2) y(n-3) y(n-4) yn ?? b i xn i ? ?? a j yn j ? ?? j1 = m ? + i0 = n ? = yn ?? s b i s ---- - xn i ? ?? i0 = n ? a j s ----- yn j ? ?? j1 = m ? + ?? ?? ?? ?? ?? =
decimation filter freescale semiconductor 28-47 pxr40 microcontroller reference manual, rev. 1 the block diagram shown in figure 28-23 represents the hardware im plementation of the decimation filter, which includes the scale factor hardware that compensates for th e scaling of the coefficients. the scale factor, s, is set by the bit field decfilt_x_mcr[scal]. coefficients b 0 to b 4 correspond to decfilt_x_coef0 to decfilt_x_coef4 coefficients a 1 to a 4 correspond to decfilt_x_coef5 to decfilt_x_coef8. the delay taps labelled tap0 to tap7 correspond to the memory mapped registers decfilt_x_tap0 to decfilt_x_tap7. figure 28-23. fourth order iir filt er implementation block diagram the examples given here implement a filt er with the following characteristics: ? filter type: elliptic/low pass iir ? filter order: 4th order ? input sample rate: 800k sample/s ? passband edge: 100 khz ? stopband edge: 150 khz ? passband attenuation: ? 1 db table 28-19 lists the computed coefficients , in real number notation, to ac hieve the above characteristics. z -1 z -1 z -1 z -1 + b 2 tap1 b 4 b 3 tap2 tap3 tap0 b 0 b 1 x(n) + a 2 tap5 a 4 a 3 tap6 tap7 tap4 scale factor s a 1 y(n) z -1 z -1 z -1 z -1
decimation filter 28-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 since the number range of the comput ed coefficients exceeds the range of the hardware, the coefficients must be scaled, by at least a factor of 4. in this example, a factor of 8 is chosen. table 28-20 below lists the scaled values and their 24 bit signed fractional values, in hexadecimal notation. 28.5.2 initialization procedure specific initialization for tw o different operating modes is provided in th e use case sections that follow this section. the general sequence of steps fo r initializing one decimation filter is: 1. program the configuration re gisters decfilt_x_mcr to configure the input data source and output result destination. 2. write all filter coefficient re gisters decfilt_x_coefn with va lues that define the filter frequency response characteristics. 3. execute a soft reset if the filter was previously configured, by writing decfilt_x_mcr[sres] = 1. table 28-19. computed coefficient values coefficient decimal valu e coefficient decimal value b0 0.0221455 a0 -1.0 b1 0.00445582948893748 a1 2.69772868375858 b2 0.0318517846509088 a2 -3.234056294853 b3 0.00445582948893748 a3 1.92028561712454 b4 0.0221455 a4 -0.47939080709495 table 28-20. coefficient values for decimation filter computed value scaled value (scal=8) filter coefficients deci mal value decimal value hexadecimal values (24 bits) decfilt_x_coef0 = b0/scal 0.0221455 0.00276815891266 0x005ab5 decfilt_x_coef1 = b1/scal 0.00445582948893748 0.00055694580078 0x001240 decfilt_x_coef2 = b2/scal 0.0318517846509088 0.00398147106171 0x008277 decfilt_x_coef3 = b3/scal 0.00445582948893748 0.00055694580078 0x001240 decfilt_x_coef4 = b4/scal 0.0221455 0.00276815891266 0x005ab5 decfilt_x_coef5 = a1/scal 2. 69772868375858 0.33721613883972 0x2b29e6 decfilt_x_coef6 = a2/scal ?3.234056294853 ?0.40425717830658 0xcc414e decfilt_x_coef7 = a3/scal 1.92028561712454 0.24003565311432 0x1eb97d decfilt_x_coef8 = a4/scal ?0.47939080709495 ?0.05992400646210 0xf8546a
decimation filter freescale semiconductor 28-49 pxr40 microcontroller reference manual, rev. 1 4. the module is ready to receive da ta and perform a filtering function. 5. if the input data source is an eqadc, these additional steps must be executed: a) configure and enable the eqadc converter to transfer results to the filter. b) configure and enable the eqadc commands to transfer filtered resu lts to desired rfifo. c) configure and enable a dma ch annel or cpu interrupt handler to transfer result from rfifo to memory. 6. if the input data source is th e cpu/dma, configure a cpu interrupt handler or polling software to input unfiltered data and retrieve the filter data. 28.5.2.1 use case 1 - normal mode, adc conver sion and filtering. the input to filter a is fr om an adc conversion result. filter a is configured as a 4rd order low pass iir. the output from the filter is routed to rf ifo5 and transferred to memory by the dma. decimation is not enabled. saturation is enabled. 28.5.2.1.1 decfilt_a_mcr ? module configurat ion register settings enable iir filter type: ftype=1 scale coefficients to a range of +1 to -1: scal=8 enable saturation of filter output result: sat=1 select ?normal? mode, to transfer data from adc through filter, to rfifo: io_sel[1]=0 select no decimation: dec_rate=0 28.5.2.1.2 decfilt_a_coefn write the filter coefficients given in table 28-20 to the following registers. decfilt_a_coef0 = 0x005ab5 decfilt_a_coef1 = 0x001240 decfilt_a_coef2 = 0x008277 decfilt_a_coef3 = 0x001240 decfilt_a_coef4 = 0x005ab5 decfilt_a_coef5 = 0x2b29e6 decfilt_a_coef6 = 0xcc414e decfilt_a_coef7 = 0x1eb97d decfilt_a_coef8 = 0xf8546a
decimation filter 28-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.5.2.1.3 eqadc configurat ion for decimation filter configure an alternate configuration control register (adc_acr1 to adc_acr8) to select decimation filter a as the destination for an adc convers ion, by setting adc_acrn[dest] = 1. to select a signed format, adc_acrn[fmta]=1. the adc_acrn register format has the form: note that the adc_adrn registers are internal to the adc and can only be acce ssed indirectly by writing a register write command to the eqadc cfifo. to do this the cpu should write a command to any eqadc cfifo with the following format: for example, to update adc_ac r1[dest] = 1, adc_acr1[fmta]=1 ? set the bit field adc_reg_address = 0x30 ? set the bit field adc_register low byte = 0x00 ? set the bit field adc_register high byte = 0x06 28.5.2.1.4 eqadc command to cause the adc conversion to be transferred to the decimation filter select ed by the method described in section 28.5.2.1.3, a conversion command for altern ate configurations must be applied to the eqadc cfifo. the form of the command is as follows: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ret_ inh 0 dest fmta 0 ressel 0 0 atbsel pre_gain w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 eoq pau s e rep reserved eb (0b0) bn r/w (0b0) adc_register high byte cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc_register low byte adc_reg_address adc command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 eoq pau s e rep reserved eb (0b0) bn cal message_tag lst tsr ffmt cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 channel_number alt_config_sel adc command
decimation filter freescale semiconductor 28-51 pxr40 microcontroller reference manual, rev. 1 the alt_config_sel field should be set to select the adc_acrn register that was configured in section 28.5.2.1.3. for example, if adc_acr1 were se lected, then the alt_ config_sel field should be 0x08. 28.5.2.2 use case 2 - input/o utput from/to the cpu/dma, stored data filtering. the input to filter c is through the memory mapped input register. filter c is configured as a 4th order low pass iir. the output from the filter is routed to a memory mapped output register and an interrupt is issued when new data is available. in this example the adc is not used at all, and no adc configuration or comma nds are needed to support the decimation filter operation. decimation is not enabled. saturation is enabled. 28.5.2.2.1 decfilt_c_mcr ? module configurat ion register settings enable interrupt when new filte red data is available: oden=1 enable iir filter type: ftype=1 scale coefficients to a range of +1 to -1: scal=8 enable saturation of filter output result: sat=1 select the cpu/dma as the output destination to transfer data to memory mapped output register: decfilt_x_mcr[io_sel[0:1] = 01 or 10 select no decimation: dec_rate=0 28.5.2.2.2 decfilt_c_coefn write the filter coefficients given in table 28-20 to the following registers. decfilt_c_coef0 = 0x005ab5 decfilt_c_coef1 = 0x001240 decfilt_c_coef2 = 0x008277 decfilt_c_coef3 = 0x001240 decfilt_c_coef4 = 0x005ab5 decfilt_c_coef5 = 0x2b29e6 decfilt_c_coef6 = 0xcc414e decfilt_c_coef7 = 0x1eb97d decfilt_c_coef8 = 0xf8546a
decimation filter 28-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 28.5.2.2.3 cpu interrupt handler all sources of interrupts from the de cimation filters a, b, c and d are routed to separate single vector numbers. each of the remaining deci mation filters has a single interrupt vector for all interrupt sources. decimation filter c uses vector numbers 467 to 469. set intc vector number 468 to the address of de cimation filter c output data interrupt handler. set the priority for the decimati on filter and enable interrupts by lowering the processor priority. when the interrupt occurs, if de cfilt_c_msr[obif] = 1 then this indicates filter output data is available. in this case, read the decfilt_c_ob, then clear the output data interrupt by writing decfilt_c_msr[obic] = 1. note that decfilt_c_msr[ib if] should also be set when the output data interrupt occurs, as a result of the previous write to the input data regist er, so it should be cl eared also by writing decfilt_c_msr[ibic] = 1. the cpu can now also write a new input value to the decfilt_c_ib register. the error flags ovf, ovr and ivr should also be checke d at this point, and clear if set, and remedial action taken, if desire d by the application.
decimation filter freescale semiconductor 28-53 pxr40 microcontroller reference manual, rev. 1
decimation filter 28-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 29-1 pxr40 microcontroller reference manual, rev. 1 chapter 29 enhanced time processing unit (etpu2) 29.1 introduction etpu is an intelligent, semi-aut onomous co-processor designed for timi ng control. operating in parallel with the host cpu, the etpu processes instructions , real-time input events, performs output waveform generation, and accesses shared data without host intervention. conseque ntly, for each timer event, the host cpu setup and service time s are minimized or eliminated. high-level assembler, compiler a nd documentation allows customers to develop their own functions on the etpu. etpu is an enhanced version of the tpu module. although there is no co mpatibility at microcode level, etpu maintains several features of older tpu versions, ma king it easy to port olde r applications, at the same time adding severa l features listed in section 29.1.2.2, etpu enhancements over tpu3 . this document also includes the new features belongi ng to the version of the etpu known as etpu2. the new features are summarized in section 29.1.2.3, etpu2 e nhancements over etpu . etpu architecture aims at high re solution timing capabilities. from a system perspective, high resolution timing is limited by host cpu overh ead required for servicing timing ta sks such as period measurement, pulse measurement, pulse width modulated waveform generation, etc. on the etpu, high resolution timing is achieved by three main capabilities: ? reduced latency: pin actions are immediate. ? reduce or eliminate host interrupt service time. ? double action channel capability re ducing the channel request rate. etpu provides higher resolution than the host cp u can achieve and creates no host overhead for servicing timing tasks. latency is the interval from occurrence of an event to the start of event servicing. etpu can service its own events without interrupting the host . there are two types of timing events: ? input pin transition. ? selected time base match, i.e., a selected time base counter reached or exceeded a pre-programmed value service time is the time spent servicing an event. in general, in microcontro llers the service time is constrained because the inst ruction set is not optimized for time function synthesi s. the etpu instruction set is optimized, so that time functions can be impl emented with much fewer instructions than the host cpu. instructions execute faster, service t ime is reduced and program memory compacted.
enhanced time processing unit (etpu2) 29-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 instructions executed by the etpu are connected di rectly to the etpu timing hardware and allow parallelism of hardware related actions. 29.1.1 overview figure 29-1 shows a top-level etpu a/b module block di agram. it displays a dual etpu engine configuration. the etpu c module contains a single etpu engine configuration. figure 29-1. etpu a/b module block diagram etpu engine is responsible for processing input pin tr ansitions and output pin waveform generation based on the time bases . each etpu engine has its own micr oprocessor and dedicated hardware for processing signals on i/o pins and can also interfa ce with external time bases through the stac bus. both etpu engine cpus, hereafter called microengines , fetch microinstructions from a shared code memory - scm . pins etpu engine b etpu engine a shared p.ram shared code memory shared biu registers registers scm pins host cpu debug if debug if stac signals stac signals
enhanced time processing unit (etpu2) freescale semiconductor 29-3 pxr40 microcontroller reference manual, rev. 1 shared data memory - sdm - holds etpu application parameters a nd work data. it is accessed by host and both microengines. bus interface unit - biu - allows host to access et pu registers, scm and sdm. each i/o signal pair is a ssociated with a dedicated channel , which provides hardware for input signal processing and output signal generation, in relationship with selected time bases. the etpu, as a microprocessed subsystem, works much like a typical real-time system: it runs microengine code from instruction memory (scm) to handle specific events, accessing data memory (sdm) for parameters, work data and application stat e info; events may originate from i/o channels (due to pin transitions and/or ti me base matches), host cpu requests or inter-channel requests; events that call for local etpu processing activa te the microengine by issuing a service request . the service request microcode may set an interrupt to the host cpu. i/ o channel events cannot directly interrupt the host cpu. each channel is associated with a function , which defines its be havior: the function is a software entity consisting, within the etpu, of a set of microengine routines that atte nd to service requests. the function routines are also responsible for channel configuration. f unction routines reside in scm, which may contain several functions. a func tion may be assigned to several channels, but a channel can be associated with just one function at a given moment. the association between functions and channels is defined by host cpu, and is explained in detail in the etpu reference manual . etpu hardware supplies resource sharin g features that support concurrency: ?a hardware scheduler dispatches the service request micr oengine routines based on a set of priorities defined by the host cpu. each channel has its associated priority; ? a service request routine cannot be interrupted until it ends. this se quence of uninterrupted instruction execution is called a thread . ? channel-specific context (registers and flags) is automatically switched between the end of a thread and the beginning of the next one. ? sdm arbitration, a dual-paramete r coherency controller and semaphor es can be used to ensure coherent access to etpu data shared by both etpu engines and host cpu.
enhanced time processing unit (etpu2) 29-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.1.1.1 etpu engine each etpu engine consists of two 24-bit time base s, 32 independent timer channels, a task scheduler, a microengine, and a host interface. in addition, ea ch etpu module has a 32-bi t shared data memory (sdm) used for data storage and for passing inform ation between the etpu engines and the host cpu. figure 29-2 shows the block diagram for the etpu engine. figure 29-2. etpu engine block diagram throughout this document, the term ?etpu? is sometimes used in place of ?etpu engine?. 29.1.1.1.1 time bases two 24-bit counters tcr1 and tcr2 provide reference time bases for al l match and input capture events. prescalers for both time bases are controlled by th e host cpu through bit fields in the etpu engine tcr1 tcr2/ microengine code ipi host interface channel control time base configuration engine configuration scheduler control and data control timer channels channel 0 channel 1 channel 31 channel control tcrclk pin mdu angle count service requests red line interface red line (scm) parameter ram shared (sdm) shared memory fetch and decode execution data code darkblue line unit debug interface to ndedi control and data ipi indigo line ipi skyblue, green ipi purple line (pins) lines
enhanced time processing unit (etpu2) freescale semiconductor 29-5 pxr40 microcontroller reference manual, rev. 1 configuration registers. th e etpu is able to export/ import time to/from tcr1 or tcr2 in accordance to the red line bus specification. the clock for each of tcr1 and tcr2 clock can be independently derived from the etpu clock or from an external input via the tcrclk clock pin. in addition, the tcr2 time base can be derived from special angle-clock hardware which enables implementing angle-based functions. this feature is added to support advanced angle based engi ne control applications. for further details refer to section 29.3.5, time bases . 29.1.1.1.2 etpu timer channels each etpu engine ha s 32 independent channels, each corresponding to an in put/output signal pair. the channels time resolution is 24 bits, and are all identical. each channel consists of logic wh ich supports two events and output controls. the event logic contains two 24-bit capture registers, two 24-bit match registers, greater-e qual and equal-only comparators. supporting two events enables many combinations of double-action functions (for example the channel can handle two events with a single microcode service). the channel configuration can be changed by the mi croengine on the fly. each channel can perform double capture, double match and other capture-match combin ations. channel modes avai lable can do ordered or unordered match. some modes are also provided that can block one match by the occurrence of the other. service request can be generated on one or both of the match events. input signal can be separated from output signal in e ach channel. they can, optionally, be combined in a single i/o pin driver. an output buffer enable signal, controlled by microcode, is provided for this case. digital filters are provided for the input signa ls, with distinct filt ering modes available. each channel can use any time base or angle counter for either match or captur e operation. for example, a match on tcr1 can capture the va lue of tcr2. the channels can reque st service from the microengine due to recognized pin transitions (i nput events) or timebase matches. the etpu channels also support th e basic single-action operations found on tpu3 functionality with the exception that time re solution is 24-bits. channel configurat ion combinations: ? single input capture, no match (tpu3 functionality). ? single input capture with single match timeout (tpu3 functionality). ? single input capture with double match time out with several double match sub-modes. ? double input capture with single or double match timeout with several double match sub-modes. ? single output match (t pu3 functionality). ? double output match with seve ral double match sub-modes. ? input-dependent output generation. the double match functionality ha s various combinations for gene ration of service request and determining pin actions. for more details refer to the etpu reference manual .
enhanced time processing unit (etpu2) 29-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 in addition to the predefined channel configurations above, the user can also program its own channel configuration, defining how i nput captures, matches and se rvice-requests are related. 29.1.1.1.3 host interface the host interface allows the host cpu to cont rol the operation of the etpu. the host cpu must initialize the etpu by writing to th e appropriate host inte rface registers to assign a function and priority to each channel. in addition, the host writes to the host service request and channel configuration registers to further define function operati on for each initialized channel. refer to section 29.3.2, host interface, for a detailed description. when the scm is implemented by ram, the host mu st first initialize it wi th the proper microcode program prior to enabling any etpu function, and then enable etpu acc ess (which also disables host access). 29.1.1.1.4 shared data memory - sdm the sdm works as data ram which can be accessed by the host cpu a nd up to two etpu engines. this memory is used for information tran sfer between the host cp u and the etpu, as data storage for the etpu microcode program or for communica tion between the two etpu engines. sdm width is 32 bits, and is accessible by the host as byte, 16-bit or 32-bit wide . etpu can access it as full 32-bits, lower 24-bits or upper byte (8-bit). the host can also access the sdm spac e mirrored in other area with parameter signal extension (pse). parameter signal extension accesses differ from th e usual host accesses to the original sdm area as follows: ? writes are effective only to the lower 3 bytes of a word: the word?s most significant byte is kept unaltered in sdm. ? reads return the lower 3 bytes of a word sign-exte nded to 32 bits, i.e.: the most significant bit of the word s 2nd most significant byte is copied in all 8 bits of the most significant read byte. each etpu channel can be associated with a variable number of paramete rs located in the sdm, according to its selected function. in addition, the sdm can be fully shared between two etpu engines, enabling direct communication between them. high flexibility of the sdm util ization is achieved as follows: ? each channel has a program mable base address pointing to the ad dress of its first parameter with two parameter granularity. this way the sdm can be partitioned according to the actual function needs. ? the microcode can access the first 128 parameters of the selected channel in channel relative access mode. ? each engine can access all the sd m address space in indirect addr essing mode. blocks of data are easily transferred using stack operation. ? absolute addressing mode can acc ess the first 256 parameters (t pu3 functionality), implementing a shared pool of parameters holding global variables.
enhanced time processing unit (etpu2) freescale semiconductor 29-7 pxr40 microcontroller reference manual, rev. 1 in the host address space each para meter occupies four bytes. etpu usage of the upper byte is achieved by having a 32-bit p register which can access the upper byte, the lower 24 bits or all the 32 bits. the microcode can switch between access sizes at any time. each function may require a different number of parameters. during the etpu initialization the host has to program channel base addresses, allocating proper paramete rs for each channel acco rding to its selected function. 29.1.1.1.5 scheduler out of reset, all channels are di sabled. the host cpu makes a channe l active by assigning it one of three priorities: high, middle, or low. the scheduler determines the orde r in which channels are serviced based on channel number and assigne d priority. the priority mechanism, im plemented in hardware, ensures that all requesting channels are service d. for additional details refer to section 29.3.3, scheduler . 29.1.1.1.6 microengine etpu microengine executes each inst ruction in a microcycle of two sy stem clocks, whil e prefetching the next instruction through an instruction pipeline. instruct ion execution time is constant unless it gets wait states from the sdm arbi tration. two etpu engines share code memory without havi ng any performance degradation by interleaving their a ccesses (the shared code memory has one-clock access time). instruction width is 32 bits. the mi croengine instruction set provides ba sic arithmetic a nd logic operations, flow control (jumps and subroutine calls), sdm acce ss, and channel configuration and control. the instruction formats are defined in su ch a way that allow particular comb inations of two or three of these operations with unconflicting resources to be ex ecuted in parallel in the same microcycle. microengine has also an independen t multiply/divide/mac unit that pe rforms these comp lex operations in parallel with other microengine instructions. channel functionality is tightly in tegrated to the instruction set th rough channel control operations and conditional branch operati ons, which support jumps/ca lls on channel-specific conditions. this allows quick and terse channel configuration and contro l code, contributing to reduced service time. 29.1.1.1.7 dual etp u engine module the etpu a/b implementation includes two etpu e ngines sharing sdm and the same code in scm. the two etpu engines share the bus interface unit (biu) and the data memo ry (sdm) which enable host-etpu and etpu engine-engine communication. the shared biu includes coherency logic which supports dual parameter (8 bytes) c oherency in transfers between ho st and etpu, using a temporary parameter area within the sdm. more details on this can be found on section 29.3.4, parameter sharing and coherency . 29.1.2 features 29.1.2.1 etpu fe ature summary the etpu includes these distinctive features:
enhanced time processing unit (etpu2) 29-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? up to 32 channels for each etpu engine, each ch annel is associated with an input/output signal pair. ? enhanced input digital filters on the input pins for improved noi se immunity. the etpu digital filter can use 2 samples, 3 samp les or work in continuous mode. ? identical, orthogonal channels, except for cha nnel 0: each channel can perform any time function. each time function can be assigned to mo re than one channel at a given time, so each signal can have any functionality. channel 0 has the same capabiliti es of the others , but can also work with special angle counter logic (see below). ? link service request allows ac tivation of a channel function by request of another channel, even between etpu engines. ? host service request allows activation of a channel function by host cpu request ? each channel has an event mechanism which su pports single and double ac tion functionality in various combinations. it include s two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. ? two independent 24-bit time ba ses for channel synchronization: ? first time base clocked by system clock with programmable prescaler division from 1 to 512 (in steps of 2), or by output of second time base prescaler. ? first time base can also be cl ocked by external signal with pr ogrammable prescaler division of 1 to 256. ? second time base clocked by external signal wi th programmable prescale r division from 1 to 64. ? second time base external clock source can be replaced by system clock divided by 8. ? both time bases can be exported or im ported via shared time and counter bus. ? second time base counter can work as an angle counter, enabling angle based applications to match angle instead of time. ? second time base can also be used as a pulse accumulator gated by external signal. ? event-triggered vliw processor (microengine): ? 2 stage pipeline implementati on (fetch and execution), with se parate instruction memory - scm - and data memory - sd m (harvard architecture) ? fixed-length instruction executi on in two system clock microcycle ? interleaved scm access in dual etpu engine avoi ds contention in time for instruction memory ? scm address space of up to 16k positions (64 kbytes) ? sdm with interleaved access in dual etpu engine avoids contention for data memory ? sdm address space of up to 8 kbytes (both engines). ? instruction set with embedded channel suppor t, including specialized channel control subinstructions and conditional br anching on channel-specific flags. ? channel-oriented addressing: ch annel-bound address mode with ho st configured channel base address allows channel data isolation, independent of mi croengine application code. ? channel-bound data address space of up to 128 32-bit parameters (512 bytes)
enhanced time processing unit (etpu2) freescale semiconductor 29-9 pxr40 microcontroller reference manual, rev. 1 ? global parameter address mode allows access to common channel data of up to 256 32-bit parameters (1024 bytes) ? support for indirect and stacked data access schemes. ? parallel execution of: data access, alu, channe l control and flow control subinstructions in selected combinations. ? 32-bit microengine registers and 24-bit resolution alu, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16- bit, or byte operands; single bit manipulation, shift operations, sign extension and conditional execution. ? additional 24-bit multiply/mac/divide uni t which supports all signed/unsigned multiply/mac combinations, an d unsigned 24-bit divide. the mac/divide unit works in parallel with the regul ar microcode commands. ? resource sharing features support channel sharing of channel regi sters, memory and microengine time: ? hardware scheduler works as a ?task management? unit, dispatch ing event service routines by predefined, host-configured priority. ? automatic channel context switch when a ?task switch? occurs, i.e., one function thread ends and another begins to service a request from ot her channel: channel-speci fic registers, flags and parameter base address are automatically loaded for the next serviced channel. ? individual channel priority setting in 3 levels: high, middle and low. ? scheduler priority scheme al lows calculation of worst case la tency for event servicing and ensures servicing all channels by preventing permanent blockage. ? sdm shared between host cpu and both et pu engines, supporting communication either between channels and host or inter-channel. ? hardware implementation of 4 semaphores supp orts resource shari ng between both etpu engines. ? hardware semaphores dire ctly supported by the microengine instruction set. ? dual parameter coherency hardwa re support allows atomic (to hos t) access to 2 parameters by microengine(s) in back-to-back accesses. ? coherent dual-parameter controller allows atom ic (to microengines) accesses to 2 parameters by the host. ? development support features: ? nexus class 3 debug support. ? software breakpoints. ? debug interface supporting single-step exec ution, forced microi nstruction execution, hardware breakpoints and watc hpoints on several conditions. ? safety support features: ? scm (code memory) continuous signature-check built-in self test (misc - multiple input signature calculator), runs concur rently with etpu normal operation. ? (more on section 29.1.2.3, etpu2 e nhancements over etpu ).
enhanced time processing unit (etpu2) 29-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.1.2.2 etpu enhan cements over tpu3 ? 32 orthogonal channels with e nhanced functionality. full s upport for double action with double match and double transition sub-mode combinations. ? input and output features separated in channe l logic and microinstruc tions, allowing input and output signals to be processed separately or combined. ? increased time resolution a nd execution unit to 24 bits. ? increased linear code memory, shared by two etpu engines, configurable up to 16k positions (64 kbytes). ? increased sdm address range (8 kbytes each engi ne) and width (32 bits per parameter). the sdm can be dynamically allocated to support variable number of parameters for each channel. each channel can have access to at least 256 parameters. ? the sdm is fully shared by two etpu engi nes (sdm), supporting direct inter-engine communication with the help of hardware semaphores. ? enhanced arithmetic operations, in cluding add/subtract wi th carry, absolute value, multiple shift and rotate, conditional execution with variable operand widths. ? enhanced logic operations, incl uding bitwise operations (and, or, xor) and bit manipulation, with conditional execution. support for read-m odify-write of any bit in the sdm. ? hardware for multiply/ma c/divide, running in parallel to execution of other operations. the 24-bit divide result is availabl e after 13 other unrelated instruct ions. multiplication supports any data width of both operands ( 8, 16 or 24 bits), signed or unsi gned. a 24x24 multiply/mac result is available after four other unr elated instructions. a 24x8 multiply/mac result is available after one other unrelated instruction. ? supports export/import of time ba ses from other sources through the real time bus (stac - shared time and counter bus). this internal bus is used for sharing real time data between multiple peripherals. ? contains angle clock hardware, supported by mi crocode, which can provide a 24-bit angle bus instead of time bus. this feature enables the etpu to run angle ba sed engine control applications. ? more interrupt types. each etpu channel can generate a data transf er request interrupt, in addition to regular interrupts, and one gl obal exception interrupt. data transf er requests can be used either as interrupt sources or dma re quests. this feature takes adva ntage of dma peripherals which off-load the host. interrupt over flow status is also provided. ? improved visibility to the host (pin states, time bases, serviced channel). ? an edge case of priority inversi on on tpu3 scheduler was resolved. ? supports channel link requests between etpu engines. 29.1.2.3 etpu2 enhancements over etpu ? tcr1, channel logic and digital fi lters (both channel and tcrclk) now have an option to run at divisions of full system cloc k speed, besides etpu clock / 2. ? channels support unordered trans itions: transition b can now be de tected before transition a. related to this enhancement, tdla and tdlb can now be independently negated by microcode. refer to the etpu reference manual for details.
enhanced time processing unit (etpu2) freescale semiconductor 29-11 pxr40 microcontroller reference manual, rev. 1 ? channel logic can now work on full etpu clock, allowing faster response with slow clocks. ? added a new user programmable channel mode : the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microc ode. refer to the etpu reference manual for details. ? microinstructions now provide an option to issue interrupt and da ta transfer requests selected by chan. they can also be requested simultane ously at the same instruction. refer to the etpu reference manual for details. ? channel flags 0 and 1 can now be tested for branching, besides sele cting the entry point. refer to the etpu reference manual for details. ? channel digital filters can be bypassed, an d can be clocked by full etpu clock ( section 29.3.4.4.4, bypass mode ). ? scheduler priority-passing mech anism can now be disabled ( section 29.3.3.2.2, priority passing disabling ). ? new watchdog mechanism kills thr eads over a programmable timeout ( section 29.3.1, watchdog ). ? new counter allows microengine load info rmation collection for performance analysis ( section 29.3.7.1, idle counter ). ? channels 1 and 2 (besides channel 0) can now be selected to control the eac ( section 29.2.6.1, etputbcr - etpu time base configuration register ). ? timebase prescalers are now reset when the gt be input is negated, gua ranteeing synchronization with emios in all cases ( section 29.3.5.4, gtbe - global time base enable ). ? new misc flag indicates when an scm signature calculation round is completed. this allows measuring of the average misc scan peri od in a real application situation ( section 29.2.5.1, etpumcr - etpu module configuration register ). ? new channel tccea flag allows continuous captu re even after tdla is set, making it fully compatible with tpu behavior. refer to the etpu reference manual for details. ? new branch condition prss tells the pin state at the time when a channel (match or transition) service request occurred. refer to the etpu reference manual for details. ? mrlea/b can now be negated indepe ndently by microcode. refer to the etpu reference manual for details. ? new engine relative address mode allows a function to acce ss sdm address space common to one engine, but distinct between engines. refer to the etpu reference manual for details. note all changes above are backward compatib le with the classic etpu, so that legacy object code (both host a nd microcode) runs on etpu2 without modification. 29.1.3 modes of operation etpu can be seen as capable of working in the following modes: ? user configuration mode
enhanced time processing unit (etpu2) 29-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 user has the ability to program the etpu cores with user time functions, having access to the shared code memory (scm). ?user mode user does not access the etpu shared code memory: ? use of predefined etpu functions ? no need for etpu core programming ability ? debug mode user debugs etpu code, accessing special trace/debug features via nexus interface: ? hardware breakpoint/w atchpoint setting ? access to internal registers ? single-step execution ? forced instruction execution ? software breakpoint insertion and removal. ? module disable mode etpu engine clocks are stoppe d through a register write to et puecr bit mdis, saving power. input sampling stops. etpu engines can be in module disable mode independently. module disable mode stops only the engine clock, so that the shared biu, and global channel registers can be accessed, and interrupts and dmas can be cleared and enabled/disabled. an engine only enters module disable mode when any currentl y running thread is finished. refer to the etpu reference manual for details. ? stop mode stop mode is entered when etpu answers devi ce stop request assertion with stop acknowledge. refer to the siu_hlt and siu_h ltack register descriptions fo r details on how to place this module in stop mode. these modes are loosely selected: th ere is no unique register field or signals to choose between them. some features of one mode can be used with features of other mode(s). more on this subject can be found on section 29.1.3.1, etpu mode selection, below. note throughout this document, an engine is said to be ?stopped? if it is either in module disable mode or stop mode. 29.1.3.1 etpu mode selection user and user configurat ion are the normal operating modes, and differ from each other only in access to scm. user programmability is only possible with a ram scm. debug mode is characterized by the use of the debug interface featur es. specifically, nexus blocks provide nexus class 3 debug features. for more in formation on debug features, refer to the etpu reference manual .
enhanced time processing unit (etpu2) freescale semiconductor 29-13 pxr40 microcontroller reference manual, rev. 1 module disable mode is entered by setting etpuecr register bi t mdis. etpu engines can be individually stopped going into module disable mode (t here is one etpuecr register for each engine). each engine can leave module disable mode by writ ing mdis=0 (which can only be done if vis=0). stop mode is activated by ip-bus (device stop request). in this ca se, the etpu waits for both etpu engines to enter in stop mode, and then asserts the stop acknowledge line. etpu leaves stop mode when device stop request is negated, but only if vis=0. if device stop request is nega ted and vis=1, etpu will leave stop mode as soon as vis=0. note an engine can stay in module disable mode when it leaves stop mode if its bit mdis=1, even if the other leaves it. 29.2 external signal description 29.2.1 overview there are 69 external signals associated with each etpu engine: 32 channel input signals, 32 channel output signals, 4 output disable input s, and tcrclk clock input, totall ing 138 in a dual engine system. the tcrclk signal is used to cloc k tcr1/2 counters or gate the tcr2 clock. in angle mode it is used as tooth signal input. 29.2.2 detailed signal descriptions 29.2.2.1 etpu channel output signals [0-31] each channel output signal is associated with a channe l. the microcode may affect the logic level of an output signal 1 by implementing one of two actions: ? specify the logic level outpu t to the signal when there is a match or a transition. ? immediately force a logic level. the output signal may also be forced to a logic level, independently of the output value from the channel logic, by one of the four (each e ngine) output disable signals (see section 29.2.2.4, etpu channel output disable signals ). 29.2.2.2 etpu channel input signals [0-31] each channel input signal is associated with a channel. the microcode can directly control the effect of the transition edge. each channel can be programmed to se nse a transition when a ri sing and/or falling edge is detected. the channel logic can al so process two transition events, and relate these events to each other and to other programmed timer events . the edge sensitivities of the tw o transition events are configured independently by microcode. 1. note that the minimum pulse width is o ne microcycle (two etpu clocks), and slow 5v pads may not be able to transfer it on time. for generation of very short pulses the etpu pads ha ve to be programmed by the system integration for fast operation mode with the voltage levels defined for fast pad operation in the mcu technology.
enhanced time processing unit (etpu2) 29-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 each channel input signal has an associated synchr onizer made of two flip-flops sampling the signal on every other etpu clock, followed by a digital filter. this digital filter can work in three sub-modes, whose purpose is to filter out noise pul ses that have width less then a programmed value of etpu clocks, preventing these transitions from being input to the tr ansition detect logic. th e synchronizer and digital filter are guaranteed to pass pulses that are greater than a programmed va lue. all channel input filters in one engine work on the same mode and sampling clock. for more info rmation on channel input filters, refer to section 29.3.4.4, enhanced digital filter - edf . in one of the angle modes, the output of the digital filter of channel 0 is replaced by the out put of tcrclk signal digital filter. refer to the etpu reference manual for details. 29.2.2.3 time base clock signal ? tcrclk tcrclk is an input signal used to control the time bases tcr1 a nd tcr2. there is one independent tcrclk input for each engine. for pulse accumulator operations tcrclk can be used as a gate for a counter based on the etpu clock di vided by eight. for angle operations tcrclk can be used to get the tooth transition indications in angle mode. like the channel input signals, the tcrclk signal ha s an associated synchroni zer followed by a digital filter. this digital filter can work in two sub-modes, whose purpose is to filter out noise pulses that have width less then a programmed value of etpu clocks, preventing these tr ansitions from be ing input to the transition detect logic. the synchronize r and digital filter are guaranteed to pass pulses that are greater than a programmed value. the clock and operation sub- mode of the tcrclk filter is configured independently of the other channel input filters, through the field tcrcf in register etputbcr. for more information on filter sub-modes, refer to section 29.3.5.5, tcrclk digital filter . in one of the angle modes, the output of the digital filter of ch annel 0 is replaced with the output of tcrclk signal digital filter. 29.2.2.4 etpu channel ou tput disable signals each etpu engine has 4 input signals to force the out puts of a group of 8 channels to an inactive level. when an input disable signal is active, all the channels in its group of 8 that have their odis bits set to 1 in etpucxcr register have their outputs forced to the opposite of the value specifi ed in bit opol of the same register. therefore, channels can be individually selected to be affected by the output disable signals, as well as their disa bling forced polarity. the output disable channel groups are defined in table 29-2 . table 29-2. output disable channel groups emios channel engine channels 11 a 0 to 7 10 8 to 15 9 16 to 23 8 24 to 31
enhanced time processing unit (etpu2) freescale semiconductor 29-15 pxr40 microcontroller reference manual, rev. 1 29.2.3 memory map/register definition the guideline for the description of all bits and fields throughout this section is to provide only a brief explanation (without examples or method of use) of the fe atures, since it will be us ed mainly as a reference for the reader that is studying section 29.3, functional description , where those features are explained in detail. 29.2.4 memory map the etpu system simplified memory map is shown in table 29-4 . each of the register areas shown may have their own reserved address areas. table 29-5 show detailed memory maps. offsets are relative to the et pu base addresses given in table 29-3 . scm unused area is decoded and returns a fixed op code defined in the register etpuscmoffdatar. 20 b 0 to 7 21 8 to 15 22 16 to 23 23 24 to 31 table 29-3. etpu module base addresses etpu module base address a/b 0xc3fc_0000 table 29-4. high level memory map offset use 0x00-0x1f system configuration registers 0x20-0x2f etpu a time base registers 0x30-0x3f reserved 1 0x40-0x4f etpu b time base registers 0x50-0x5f reserved 1 0x60-0x6f etpu a extra engine registers 0x70-0x7f etpu b extra engine registers 0x80-0xff reserved 1 0x100-0x13f memory error support registers 0x140-0x1ff reserved 1 0x200-0x2ff etpu a/b global channel registers 0x300-0x3ff reserved 1 0x400-0x7ff etpu a channel registers 0x800-0xbff etpu b channel registers 0xc00-0xfff reserved 1 table 29-2. output disable channel groups (continued) emios channel engine channels
enhanced time processing unit (etpu2) 29-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x1000-0x3fff reserved 1 0x4000-0x7fff reserved 1 0x8000 - 0x97ff etpu a/b sdm - shared data memory 0xc000 - 0xffff etpu a/b sdm pse mirror 2 0x10000 - 0x15fff etpu a/bscm - shared code memory 3 1 reserved addresses must not be used. access to these memory positions complete with 0-wait-states, but the behavior is unspecified. 2 parameter sign extension access area, see section 29.3.2.3, parameter access . 3 scm access is available only when bit vis=1 on register etpumcr, under certain conditions (see section 29.2.5.1, etpumcr - etpu module configuration register ). table 29-5. detailed memory map etpu a/b offset register bits access reset value section/page 0x00 etpumcr?etpu module configuration register 32 r/w 0x000u_0000 29.2.5.1/29-19 0x04 etpucdcr?etpu coher ent dual-parameter controller register 32 r/w 0x0000_0000 29.2.5.2/29-22 0x08 reserved 0x0c etpumisccmpr?etpu misc compare register 32 r/w 0x0000_0000 29.2.5.3/29-23 0x10 etpuscmoffdatar?etpu scm off-range data register 1 32 r/w 0xf3775ffb 29.2.5.4/29-24 0x14 etpuecr_a?etpu a engine configuration register 32 r/w 0x0000_0000 29.2.5.5/29-24 0x18 etpuecr_b?etpu b engine configuration register 32 r/w 0x0000_0000 29.2.5.5/29-24 0x1c reserved 0x20 etputbcr_a?etpu a time base configuration register 32 r/w 0x2000_0000 29.2.6.1/29-28 0x24 etputb1r_a?etpu a time base 1 32 r/w 0x0000_0000 29.2.6.2/29-31 0x28 etputb2r_a?etpu a time base 2 32 r/w 0x0000_0000 29.2.6.3/29-31 0x2c etpuredcr_a?etpu a stac configuration register 32 r/w 0x0u00_0u00 29.2.6.4/29-32 0x30?0x3c reserved 0x40 etputbcr_b?etpu b time base configuration register 32 r/w 0x2000_0000 29.2.6.1/29-28 0x44 etputb1r_b?etpu b time base 1 32 r/w 0x0000_0000 29.2.6.2/29-31 0x48 etputb2r_b?etpu b time base 2 32 r/w 0x0000_0000 29.2.6.3/29-31 0x4c etpuredcr_b?etpu b stac configuration register 32 r/w 0x0u00_0u00 29.2.6.4/29-32 table 29-4. high level memory map (continued)
enhanced time processing unit (etpu2) freescale semiconductor 29-17 pxr40 microcontroller reference manual, rev. 1 0x50?0x5c reserved 0x60 etpuwdtr_a?etpu a watchdog timer register 32 r/w 0x0000_0000 29.2.7.1/29-33 0x64 reserved 0x68 etpuidler_a?etpu a idle counter register 32 r/w 0x0000_0000 29.2.7.2/29-34 0x6c reserved 0x70 etpuwdtr_b?etpu b watchdog timer register 32 r/w 0x0000_0000 29.2.7.1/29-33 0x74 reserved 0x78 etpuidler_b?etpu b idle counter register 32 r/w 0x0000_0000 29.2.7.2/29-34 0x7c?0x1ff reserved 0x200 etpucisr_a?etpu a channel interrupt status register 32 r/w 0x0000_0000 29.2.9.1/29-35 0x204 etpucisr_b?etpu b channel interrupt status register 32 r/w 0x0000_0000 29.2.9.1/29-35 0x208?0x20c reserved 0x210 etpucdtrsr_a?etpu a channel data transfer request status register 32 r/w 0x0000_0000 29.2.9.2/29-36 0x214 etpucdtrsr_b?etpu b channel data transfer request status register 32 r/w 0x0000_0000 29.2.9.2/29-36 0x218?0x21c reserved 0x220 etpuciosr_a?etpu a channel interrupt overflow status register 32 r/w 0x0000_0000 29.2.9.3/29-37 0x224 etpuciosr_b?etpu b channel interrupt overflow status register 32 r/w 0x0000_0000 29.2.9.3/29-37 0x228?0x22c reserved 0x230 etpucdtrosr_a?etpu a channel data transfer request overflow status register 32 r/w 0x0000_0000 29.2.9.4/29-38 0x234 etpucdtrosr_b?etpu b channel data transfer request overflow status register 32 r/w 0x0000_0000 29.2.9.4/29-38 0x238?0x23c reserved 0x240 etpucier_a?etpu a channel interrupt enable register 32 r/w 0x0000_0000 29.2.9.5/29-39 0x244 etpucier_b?etpu b channel interrupt enable register 32 r/w 0x0000_0000 29.2.9.5/29-39 0x248?0x24c reserved 0x250 etpucdtrer_a?etpu a channel data transfer request enable register 32 r/w 0x0000_0000 29.2.9.6/29-39 0x254 etpucdtrer_b?etpu b channel data transfer request enable register 32 r/w 0x0000_0000 29.2.9.6/29-39 0x258-0x27f reserved 0x280 etpucpssr_a?etpu a channel pending service status register 32 r 0x0000_0000 29.2.9.7/29-40 0x284 etpucpssr_b?etpu b channel pending service status register 32 r 0x0000_0000 29.2.9.7/29-40 0x288?0x28c reserved table 29-5. detailed memory map etpu a/b (continued) offset register bits access reset value section/page
enhanced time processing unit (etpu2) 29-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 0x290 etpucssr_a?etpu a channel service status register 32 r 0x0000_0000 29.2.9.8/29-41 0x294 etpucssr_b?etpu b channel service status register 32 r 0x0000_0000 29.2.9.8/29-41 0x298?0x3ff reserved 0x400 etpuc0cr_a?etpu a channel 0 configuration register 32 r/w 0x0000_0000 29.2.10.1/29-43 0x404 etpuc0scr_a?etpu a channel 0 status and control register 32 r/w 0x0000_0000 29.2.10.2/29-45 0x408 etpuc0hsrr_a?etpu a channel 0 host service request register 32 r/w 0x0000_0000 29.2.10.3/29-47 0x40c reserved 0x410 etpuc1cr_a?etpu a channel 1 configuration register 32 r/w 0x0000_0000 29.2.10.1/29-43 0x414 etpuc1scr_a?etpu a channel 1 status and control register 32 r/w 0x0000_0000 29.2.10.2/29-45 0x418 etpuc1hsrr_a?etpu a channel 1 host service request register 32 r/w 0x0000_0000 29.2.10.3/29-47 0x41c reserved . . 0x5f0 etpuc31cr_a?etpu a channel 31 configuration register 32 r/w 0x0000_0000 29.2.10.1/29-43 0x5f4 etpuc31scr_a?etpu a channel 31 status and control register 32 r/w 0x0000_0000 29.2.10.2/29-45 0x5f8 etpuc31hsrr_a?etpu a channel 31 host service request register 32 r/w 0x0000_0000 29.2.10.3/29-47 0x5fc - 0x7ff reserved 0x800 etpuc0cr_b?etpu b channel 0 configuration register 32 r/w 0x0000_0000 29.2.10.1/29-43 0x804 etpuc0scr_b?etpu b channel 0 status and control register 32 r/w 0x0000_0000 29.2.10.2/29-45 0x808 etpuc0hsrr_b?etpu b channel 0 host service request register 32 r/w 0x0000_0000 29.2.10.3/29-47 0x80c reserved 0x810 etpuc1cr_b?etpu b channel 1 configuration register 32 r/w 0x0000_0000 29.2.10.1/29-43 0x814 etpuc1scr_b?etpu b channel 1 status and control register 32 r/w 0x0000_0000 29.2.10.2/29-45 0x818 etpuc1hsrr_b?etpu b channel 1 host service request register 32 r/w 0x0000_0000 29.2.10.3/29-47 0x81c reserved . . . 0x9f0 etpuc31cr_b?etpu b channel 31 configuration register 32 r/w 0x0000_0000 29.2.10.1/29-43 table 29-5. detailed memory map etpu a/b (continued) offset register bits access reset value section/page
enhanced time processing unit (etpu2) freescale semiconductor 29-19 pxr40 microcontroller reference manual, rev. 1 29.2.5 system configuration registers 29.2.5.1 etpumcr - etpu modu le configuration register in the etpua/b module, this regist er is shared between etpu a a nd etpu b engines.. etpumcr gathers configuration and status in the et pu system, including a global exception. it is also used for configuring the scm (shared code memory) operation and test. base + 0x000 figure 29-3. etpumcr register gec? global exception clear this write-only bit negates globa l exception request and clears globa l exception status bits mge1, mge2, ilf1, ilf2 and scmmisf. 0x9f4 etpuc31scr_b?etpu b channel 31 status and control register 32 r/w 0x0000_0000 29.2.10.2/29-45 0x9f8 etpuc31hsrr_b?etpu b channel 31 host service request register 32 r/w 0x0000_0000 29.2.10.3/29-47 0x9fc - 0x7fff reserved 0x8000 - 0x97ff spram?shared parameter ram ? ? ? ? 0xc000 - 0xffff spram?shared parameter ram - pse mirror 2 ?? ? ? 0x10000 - 0x15fff 3 scm?shared code memory 4 ?? ? ? 1 this register is not implemented in some mcus; see section 29.2.5.4, etpuscmoff datar - etpu scm off-range data register . 2 parameter sign extension access area, see section 29.3.2.3, parameter access . 3 when the size not the maximum, the unused scm address range returns the value of the register etpuscmoffdatar. 4 scm access is available only when bit vis=1 on register etpumcr, under certain conditions (see section 29.2.5.1, etpumcr - etpu module configuration register ). scm can only be written in 32 bit accesses. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 wdto 1 wdto 2 mge 1 mge 2 ilf1 ilf2 0 0 0 scmsize w gec reset: 0 0 0 0 0 0 0 0 0 0 0 scmsize 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 scm misc scm misf scm mise n 0 0 vis 0 0 0 0 0 gtbe w scm misc c reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 29-5. detailed memory map etpu a/b (continued) offset register bits access reset value section/page
enhanced time processing unit (etpu2) 29-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 1 = negate global exception, clear status bits ilf1, ilf2, mge1, mge2, and scmmisf. 0 = keep global exception request and status bits ilf1, ilf2, mg e1, mge2, and sc mmisf as is. gec works the same way with either one or both engines in module disable mode. wdto1,2 ? watchdog timeout flags wdto1 and wdto2 indicate th at a watchdog timeout occurred in etpu engine a or c and etpu engine b respectively, generating a global exception. these bits ar e cleared by writing 1 to gec. 1 = global exception requested by watchdog timeout 0 = no global exception pending because of watchdog timeout. mge1,2? microcode global exception - engine a, b these bits indicate that a global exception was asserted by microcode executed on the respective engine. the determination of the reason why th e global exception was asserted is application dependent: it can be coded in an sdm status parame ter, for instance. this bit is cleared by writing 1 to gec. 1 = global exception requested by microcode is pending 0 = no microcode-requested global exception pending. ilf1,2? illegal instruct ion flag - etpu a, b the ilf1/2 bit is set by the microe ngine to indicate that an illega l instruction was decoded in engine 1/2. this bit is cleared by host writing 1 to gec. see the etpu reference manual for more details. 1 = illegal instruction detected by etpu a, b. 0 = illegal instruction not detected. scmsize[0:4] - scm size this read-only field holds the num ber of 2 kbyte scm blocks minus 1. this value is 11 for etpu a/b and 5, meaning scm sizes of 24 kbyte, respectively. scmmisc, scmmiscc ? scm misc comp lete, scm misc complete clear flag scmmisc indicates that misc has completed the evaluation of the scm signature since reset or the since the last time it wa s cleared. scmmisc is cleared by wr iting 1 to scmmiscc (at same bit position), and is not cleared when misc is disa bled (scmmisen=0). scmmisc asserts at the end of the scm memory scan, either if the signature matches or not. 1 = misc completed at least one scm signature calculation and compare since the last time scmmisc was cleared. 0 = misc has not yet completed an scm signature calculation and compare since the last time scmmisc was cleared. scmmisf? scm misc flag the scmmisf bit is set by the scm misc (multiple input signature ca lculator) logic to indicate that the calculated signature does not match the expected value, at th e end of a misc iteration. see section 29.3.6.1, scm test - multiple input signature calculator, for more details. 1 = misc has read entire scm array and the expected signa ture in etpumisccmpr does not match the value calculated.
enhanced time processing unit (etpu2) freescale semiconductor 29-21 pxr40 microcontroller reference manual, rev. 1 0 = signature mismatch not detected. this bit is cleared when global exce ption is cleared by writing 1 to gec. scmmisen ? scm misc enable the scmmisen bit is used for enabling/disabli ng the operation of the misc logic. scmmisen is readable and writable at any time. the misc logic will only operate when this bit is set to 1. when the bit is reset the misc address count er is set to the initial scm addr ess. when enabled, the misc will continuously cycle through the scm addresses, readi ng each and calculating a crc. in order to save power, the misc can be disabled by clearing the scmmisen bit. see section 29.3.6.1, scm test - multiple input signature calculator, for more details. 1 = misc operation enabled. 0 = misc operation disabled. the misc logic is reset to its initial state. scmmisen resets automatically when misc logic detects an error, i.e., when scmmisf transitions from 0 to 1, disabling the misc operation. vis ? scm visibility bit vis bit turns scm visible to the ip-bus and rese ts misc state (but scmmisen keeps its value). 1 = scm is visible to the slav e bus. misc state is reset. 0 = scm is not visible to the slav e bus. accessing scm address space issues a bus error, writes are protected and reads are meaningless. this bit is write protected when any of the engines is not halted or stopped 1 . when vis=1, the etpuecr mdis bits are write protected. the va lue written to scm is unspecified if other transfer sizes are used. gtbe - global time base enable gtbe enables time bases in both engines, allowing them to be started synchronously. 1 = time bases in both engines are enabled to run. 0 = time bases in both engines are disabled to run. note global time base enable action may also depend on other blocks, as explained in section 29.3.5.4, gtbe - global time base enable . note when gtbe is turned off with angle mode enabled, the eac must be reinitialized before gtbe is turn ed on again. the eac reinitialization procedure is described in the etpu reference manual . 1. engine is stopped in module disable or stop modes.
enhanced time processing unit (etpu2) 29-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.2.5.2 etpucdcr - etpu coherent dual-parameter controller register etpucdcr configures and controls dual-paramete r coherent transfers. for more info, see section 29.3.4.2, coherent dual-par ameter controller - cdc . figure 29-4. etpucdcr register sts ? start bit this bit is set by the host in orde r to start the data transfer betw een the parameter buffer pointed by pbbase and the target addresses selected by the c oncatenation of fields ct base and parm0/1. the host receives wait-states until the data transfer is co mplete, when this bit is reset by the coherency logic (see section 29.3.4.2, coherent dual-p arameter cont roller - cdc ). therefore, host always reads sts as 0. 1 = (write) starts a coherent transfer. 0 = (write) does not start a coherent transfer. ctbase[0:4] ? channel transfer base this field concatenates with fiel ds parm0/parm1 to determine the absolute word offset (from the sdm base) of the parameters to be transferred: parameter 0 word address = {ctbas e, parm0} + sdm base word address parameter 1 word address = {ctbase, parm1} + sdm base word address pbbase[0:9] ? parameter buffer base address this field points to the base addre ss of the parameter buffe r location, with granul arity of 2 parameters (8 bytes). the host (byte) address of the first parameter in the buffer is pbbase*8 + sdm base byte address. the microengine absolute (word) address of the first parameter in the buffer is pbbase*2. pwidth ? parameter width selection this bit selects the width of the parameters to be transferred between the pb and the target address. 1 = transfer 32-bit parameters. all 32 bits of the parameters are wr itten in the dest ination address. 0 = transfer 24-bit parameters . the upper byte remains unchanged in the destination address. wr ? read/write selection base + 0x004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r sts ctbase pbbase w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwid th pa r m 0 wr pa r m 1 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) freescale semiconductor 29-23 pxr40 microcontroller reference manual, rev. 1 this bit selects the direction of the coherent data transfer. 1 = write operation. data transfer is fr om the pb to the selected sdm address. 0 = read operation. data transfer is from the selected sdm address to the pb. parm0[0:6], parm1[0:6] ? cha nnel parameter number 0/number 1 these fields in concatenation with ctbase[0:4] determine the word address offset (from the sdm base) of the parameters that are destination or s ource (defined by wr) of the coherent transfer. the word sdm address offset of the parameters are {ctbase, parm0/1}.note that parm0 and parm1 allow non-contiguous parameters to be tr ansferred coherently. the parameter pointed by {ctbase, parm0} is the first transferred. 29.2.5.3 etpumisccmpr - etpu misc compare register etpumisccmpr holds the 32-bit sign ature expected from the whole sc m array. this register must be written by the host with the 32-bit word to be compared against the calcul ated signature at the end of the misc cycle. this register is global to both etpu engines. for more detail see section 29.3.6.1, scm test - multiple input signature calculator . figure 29-5. etpumisccmpr register etpumisccmp[0:31] ? expected multip le input signature register value see section 29.3.6.1, scm test - multiple input signature calculator . base + 0x00c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r etpumisccmp[0:15] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpumisccmp[16:31] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) 29-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.2.5.4 etpuscmoffdatar - etpu scm off-range data register etpuscmoffdatar holds the 32-bit value returned when scm array is acce ssed at non implemented addresses, either by the host or by the microengine. this regi ster can be written by th e host with the 32-bit instruction to be executed by the microengine to rec over from runaway code. this register is global to both etpu engines. the reset value is . for more detail see section 29.3.2.6.3, scm off-range data . figure 29-6. etpuscmoffdatar register etpuscmoffdata[0:31] ? scm off-range read data value see section 29.3.2.6.3, scm off-range data . 29.2.5.5 etpuecr - etpu engi ne configuration register each engine has its own etpuecr register. etpuecr holds configurat ion and status fields that are programmed independently in each engine. figure 29-7. etpuecr register fend ? force end base + 0x010 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r etpuscmoffdata[0:15] w reset: 1 1 the reset value is 0xf3775ffb , an instructio n that clears mrles, mrls and tdls, disables channel service requests, ends the thread and generates an illegal instruction global exception. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpuscmoffdata[16:31] w reset: = unimplemented or reserved etpu a: base + 0x014 / etpu b: base + 0x018 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fend mdis 0 stf 0 0 0 0 hltf 0 0 0 fcss fpsck w reset: 0 0 0 0 0 0 0 0 0(1 1 ) 1 engine may go to debug state (halted) s oon after reset, depending on the ndedi co nfiguration (see ndedi block guide). 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cdfc 0 erba sppd is 0 0 etb w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) freescale semiconductor 29-25 pxr40 microcontroller reference manual, rev. 1 fend assertion terminates any curre nt running thread as if an en d instruction have been executed (see etpu reference manual for details). 1 = ends any ongoing thread. 0 = normal operation. this bit is self-negating when the thread ends 1 . writing fend=1 is ignored and fend stays 0 when the microengine is in tst, halted, st opped, or idle (no thread executing). mdis ? module disable bit when mdis is set, the engine shuts down its in ternal clocks, going into module disable mode. tcr1 and tcr2 cease to increment, and input sampling st ops. the engine asserts the stop flag (stf) bit to indicate that it has st opped however, the biu continues to run, and the host can access all registers except for the channel registers 2 (see list of channel registers on section 29.2.10, channel configuration and control registers ). after mdis is set, even before stf asserts, data read from the channel registers is not meaningful and writes are in effective, issuing a bus er ror. when the mdis bit is asserted while the microcode is executing, the etpu will stop when the thread is complete. 1 = commands engine to stop its clocks. 0 = etpu engine runs. stop completes on the next etpu clock after the stop condition is va lid. the mdis bit is write-protected when vis=1. note once mdis is switched from 1 to 0 or vice versa, it must not be written a different value until stf changes accordingly. stf ? stop flag bit each engine asserts its stop flag (stf) to indicate that it has stopped. only then the host can assume that the engine has actually stopped. the etpu syst em is fully stopped when the stf bits of both etpu engines are asserted. in ca se of ip-bus stop, the etpu syst em responds by acknowledging stop only after both etpu 1 and etpu 2 have been stopped. engine only stops when any ongoing thread is complete also in this case. 1 = engine has stopped (after the lo cal mdis bit has been asserted, or after the ip-bus stop line has been asserted). 0 = engine is operating. summarizing engine stop condi tions, which stf reflects: stf_1 := (after stop complete d) mdis_1 | device stop request stf_2 := (after stop complete d) mdis_2 | device stop request stf_1 and stf_2 mean stf bit from engine 1 and stf bit from engine 2 respectively. hltf ? halt mode flag 1. only on rare occasions (e.g., during a long stall, (see etpu reference manual ) fend can be read as 1, because it negates as soon as the end begins execution. 2. the timebase registers can still be read with mdis=1 , but writes are ineffective and a bus error is issued. global channel registers and sdm can be accessed normally.
enhanced time processing unit (etpu2) 29-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if etpu engine entered halt state, this flag is as serted. the flag remains asse rted while the microengine is in halt state, even during a single- step or forced in struction execution.. 1 = etpu engine is halted 0 = etpu engine is not halted. fcss - filter clock source selection speeds up the filter cloc k source before the prescaler, allowi ng more input capture resolution at minimum prescaling. 1 = use etpu clock as edf clock source before prescaler 0 = use etpu clock / 2 as edf clock source before prescaler. note fcss=1 also makes the channel work on t2/t4 timing mode (see etpu reference manual ). fpsck[0:2] ? filter pr escaler clock control fpsck controls the prescaling of the clocks used in digital filters for the channel input signals and tcrclk input, as shown in table 29-6 . filtering can be co ntrolled independently by engine, but all input digital filters in the sa me engine have same clock pr escaling. for more details see section 29.3.4.4.5, filter clock prescaler . a new value written to fpsck only becomes effective when the filter prescale r finishes the current count. cdfc[0:1] ? channel di gital filter control these bits select a digital filter ing mode for the channels when c onfigured as inputs for improved noise immunity (refer to table 29-7 ). the etpu has three digital filt ering modes for the channels which provide programmable trade-off between signal latenc y and noise immunity (see section 29.3.4.4, enhanced digital filter - edf ). changing cdfc during etpu nor mal input channel operation is not recommended since it cha nges the behavior of the transition detection logic while executing its operation. table 29-6. filter prescaler clock control filter control sample on etpu clock divided by: 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256
enhanced time processing unit (etpu2) freescale semiconductor 29-27 pxr40 microcontroller reference manual, rev. 1 erba ? engine relative base address this field value is concatenated w ith the aid instruction field in engi ne relative address mode to form the sdm address (see etpu reference manual ). sppdis ? schedule priority passing disable sppdis is used to disable the priority passing mechanism of th e microengine scheduler (see section 29.3.3.2.1, primary scheme - priority among channels on different levels ). 1 = scheduler priority pa ssing mechanism disabled. 0 = scheduler priority passing mechanism enabled. note sppdis bit must not be changed while any channel is enabled. etb[0:4] ? entry table base the field determines the location of the microcode entry table for the etpu functions in scm (see etpu reference manual for details of how to use this field). 29.2.6 time base registers time base registers allows confi guration and visibility of internal ly-generated time bases tcr1 and tcr2. there is one of each of thes e registers for each etpu engine. note writes to this register issue bus error and are ineffective when mdis=1. reads are always allowed. table 29-7. channel digital filter control cdfc selected digital filter 00 tpu2/3 two sample mode: using the filter cloc k which is the etpu clock divided by (2, 4, 8,.., 256) as a sampling clock (selected by fpsck field in etpuecr), comparing two consecutive samples which agree with each other sets the input signal state. this is the default reset state. 01 etpu bypass mode: the input signal is taken unfiltered, also making the channels work on t2/t4 timing mode 1 . 1 see etpu reference manual 10 etpu three sample mode: similar to the tpu2/3 two sample mode, but comparing three consecutive samples which agree with ea ch other sets the input signal state. 11 etpu continuous mode: signal need to be st able for the whole filter clock period. this mode compares all the values at the rate of etpu clock (fcss=1) or etpu clock divided by two (fcss=0), between two consecutive f ilter clock pulses. signal needs to be continuously stable for the entire period. if all the values agree with each other, input signal state is updated.
enhanced time processing unit (etpu2) 29-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.2.6.1 etputbcr - etpu time base configuration register this register configures several timebase options. figure 29-8. etputbcr register tcr2ctl[0:2] ? tcr2 clock/gate control these bits are part of the tcr2 clocking system (see section 29.3.5, time bases ). they determine the clock source for tcr2 before th e prescaler. tcr2 can count on any detected edge of the tcrclk signal or use it for gating etpu clock divided by 8. after reset - tcrclk signal rising edge is selected. tcr2 can also be cloc ked by the etpu clock divided by 8. tcr2ctl also determines the tcrclk edge selected for angle t ooth detection in angle mode. see table 29-8 . tcrcf[0:1] ? tcrclk signal filter control etpu a: base + 0x020 / etpu b: base + 0x040 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tcr2ctl tcrcf am 0 0 0 tcr2p w reset: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcr1ctl tcr1 cs 0 0 0 0 0 tcr1p w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 29-8. tcr2 clock source tcr2ctl am = 0 tcr2 clock before prescaler am = 1 angle tooth detection 000 gated div8 clock (etpu clock / 8). in this case, when the external tcrclk signal is low, the div8 clock is blocked, preventing it from incrementing the tcr2 prescaler. when the external tcrclk signal is high, tcr2 prescaler is incremented at the frequency of the etpu clock divided by 8. do not use with am=1 001 rise transition on tcrclk signal increments the tcr2 prescaler. rise edge 010 fall transition on tcrclk signal increments the tcr2 prescaler. fall edge 011 rise or fall transition on tcrclk signal increments the tcr2 prescaler. both edges 100 div8 clock (etpu clock / 8) do not use with am=1 101 do not use with am=0 110 no edge 1 1 tcrclk edges are not detected by the eac logic, but th ey can still be detected by the channel 0 logic if am=01. 111 tcr2 frozen, except as stac client do not use with am=1
enhanced time processing unit (etpu2) freescale semiconductor 29-29 pxr40 microcontroller reference manual, rev. 1 this field controls the tc rclk digital filter (see section 29.3.5.5, tcrclk digital filter ), determining whether the tcrclk signal input (after a synchronizer) is filter ed with the same filter clock as the channel input signals (see section 29.3.4.4, enhanced digital filter - edf ) or uses the etpu clock divided by 2, and also whether the tcrclk digital filter works in integrator mode or two sample mode (see table 29-9 ). am ? angle mode selection this field enables the enhanced angle counter logic to gene rate angle information (see etpu reference manual for details), and also select the tooth signa l input and the channel used to process it, as shown in table 29-10 . when eac is not disabl ed by am and neither tcr1 nor tcr2 are stac clients, the eac (etpu angle clock) hardware provi des angle information to the channels using the tcr2 bus. when am is reset ( non-angle mode), the eac operation is disabled, and its internal registers can be used as general purpose. for more information, see etpu reference manual . if tcr1 or tcr2 is a stac bus client (see section 29.3.5.3, stac interface ), the eac operation is not allowed, and if am is set the angle logic does not work properly. note changing am may cause spurious tran sition detections on the channel selected by am, depending on the channel mode and state (see etpu reference manual for details). if am must be changed with gtbe=1, the recommended procedure is described in the etpu reference manual . tcr2p[0:5] ? timer count re gister 2 prescaler control these bits are part of th e tcr2 clocking system (see section 29.3.5, time bases ). tcr2 is clocked from the output of a prescaler. the prescaler divides its input by (tcr2p+1) allowing frequency divisions from 1 to 64. the prescale r input is the etpu clock divide d by 8 (in gated or non-gated clock mode), or internal timebase inpu t, or tcrclk filtered input. th is field has no effect on tcr2 in angle mode. tcr1ctl[0:1] ? tcr1 clock/gate control table 29-9. tcrclk filter clock/mode tcrcf filter clock filter mode 00 etpu clock divided by 2 two sample 01 filter clock of the channels two sample 10 etpu clock divided by 2 integrator 11 filter clock of the channels integrator table 29-10. am - angle mode selection valu e tcr2 value tooth signal tooth processing channel 0 0 timebase (eac operation disabled) not applicable 0 1 angle ticks tcrclk input 0 1 0 channel 1 input 1 1 1 channel 2 input 2
enhanced time processing unit (etpu2) 29-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 tcr1ctl is part of the tc r1 clocking system (see section 29.3.5, time bases ). it determines, together with tcr1cs, the clock source for tc r1. tcr1 can count on de tected rising edge of the tcrclk signal, the etpu clock, or the et pu clock divided by 2 (see table 29-11 ). after reset tcrclk signal is selected tcr1cs - tcr1 clock source tcr1cs provides the option to double the tcr1 in crementing speed, using etpu clock as its clock source instead of etpu clock / 2. 1 = use etpu clock as tcr1 clock source before the prescaler; can only be set in specific combinations with tcr1ctl (see table 29-11 ). 0 = use etpu clock / 2 as tcr1 clock source before the prescaler, if that cl ock source is selected by tcr1ctl. note tcr1cs=1 also makes the channe l work on t2/t4 timing mode (see etpu reference manual for details). note the clock source of the eac angle tick generator will still be an even division of etpu clock if tcr1cs=1, obeying to the fields tcr1p as if tcr1cs=0 (see etpu reference manual for details). tcr1p[0:7] ? timer count re gister 1 prescaler control tcr1 is clocked from the output of a prescaler. the input to the pres caler is the internal etpu clock divided by 2, etpu clock, or th e output of tcrclk filter. the pr escaler divides this input by (tcr1p+1) allowing frequency divisions from 1 up to 256. table 29-11. tcr1 clock source tcr1ctl tcr1cs 1 1 all other combinations of tcr1ctl and tcr1cs are reserved. tcr1 clock before prescaler 00 0 selects tcrclk as clock source for the tcr1 prescaler 2 2 this selection must not be used in angle mode. 10 0 selects etpu clock divided by 2 as clock source for the tcr1 prescaler 10 1 selects etpu clock as clock source for the tcr1 prescaler 11 0 tcr1 frozen, except as a stac client;
enhanced time processing unit (etpu2) freescale semiconductor 29-31 pxr40 microcontroller reference manual, rev. 1 29.2.6.2 etputb1r - etpu time ba se 1 (tcr1) visibility register this register provides visibility of the tcr1 time base for host read access (see section 29.3.5, time bases ). this register is read-only. the value of the tcr1 time base shown can be driven by the tcr1 counter or imported from stac bus, dependi ng on the configuration set in etpuredcr. figure 29-9. etputb1r register tcr1[0:23] ? tcr1 value tcr1 value used on matches and captures. see section 29.3.5, time bases . 29.2.6.3 etputb2r - etpu time ba se 2 (tcr2) visibility register this register provides visibility of the tcr2 time base for host read access (see section 29.3.5, time bases ). this register is read-only. the value of the tcr2 time base shown can be driven by the tcr2 counter, the angle mode logic, or imported from stac, depe nding on angle mode and stac configurations set in regi sters etputbcr and etpuredcr. figure 29-10. etputb2r register tcr2[0:23] ? tcr2 value etpu a: base + 0x024 / etpu b: base + 0x044 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 tcr1[0:7] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcr1[8:23] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved etpu a: base + 0x028 / etpu b: base + 0x048 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 tcr2[0:7] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcr2[8:23] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) 29-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 tcr2 value used on matches and captures. see section 29.3.5, time bases . 29.2.6.4 etpuredcr - etpu stac configuration register this register configures the etpu stac bus operation as a stac server/client module (see section 29.3.5.3, stac interface ). figure 29-11. etpuredcr register ren1,2 ? tcr1/2 resource 1 client/server operation enable bits these bits enable or disable cl ient/server operation to etpu stac resources. ren1 enables tcr1 and ren2 enables tcr2 stac bus operations. 1 = server/client op eration for resource 1/2 is enabled. 0 = server/client op eration for resource 1/2 is disabled. rsc1,2 ? tcr1/2 resource server/client assignment bits these bits select the etpu data resource assignment to be used as servers or clients. rsc1 selects the functionality of tcr1 and rsc2 selects the f unctionality of tcr2. fo r server mode, external plugging determines the unique serv er address assigned to each tc r. for a client mode, the srv1 and srv2 fields determine the server address to which the client listens. 1 = resource server operation. 0 = resource client operation. note when tcr1 or tcr2 is configured as a stac bus client (ren2=1, rsc2=0) the etpu angle clock hardware cannot be used. note rsc1,2 must not be changed when th e respective ren1,2 bit is asserted. server_id1,2 ? stac ids 1,2 stac server ids (read-only plug va lues) used for tcr1 and tcr2, respectively, when stac servers. etpu a: base + 0x02c / etpu b: base + 0x04c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ren1 rsc1 0 0 server_id1 0 0 0 0 srv1 w reset: 0 0 0 0 server_id1 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ren2 rsc2 0 0 server_id2 0 0 0 0 srv2 w reset: 0 0 0 0 server_id2 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. resource identifies any parameter that changes along the time and can be exported / imported from other device. in etpu context, a resource can be tcr1 or tcr2 (either time or angle values).
enhanced time processing unit (etpu2) freescale semiconductor 29-33 pxr40 microcontroller reference manual, rev. 1 srv1,2 ? tcr1/2 resource server these bits select the address of the specific stac server to which the local tcr1 or tcr2 listens when configured as a stac clie nt. srv1 and srv2 se lect the stac server of tcr1 and tcr2, respectively. 29.2.7 engine related registers this section gathers registers that are engine-related, other than etpuecr (see section 29.2.5.5, etpuecr - etpu engine configuration register ). 29.2.7.1 etpuwdtr - etpu watchdog timer register this register configures the watchdog timer for the engine. figure 29-12. etpuwdtr register wdm ? watchdog mode wdm selects the watchdog operation mode, as shown in table 29-12 . for more information on the watchdog operation, see section 29.3.1, watchdog . note before a new mode is configure d, all conditions below must apply: 1- all channels must be disa bled (etpucxcr field cpr=00). 2- no thread must be executi ng (register etpucssr reads 0). 3- the watchdog must be disabled (wdm=00). etpu a: base + 0x060 / etpu b: base + 0x070 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r wdm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r wdcnt[15:0] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 29-12. wdm - watchdog mode value watchdog mode 0 0 disabled 0 1 reserved 1 0 thread length 1 1 busy length
enhanced time processing unit (etpu2) 29-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 wdcnt[15:0] ? watchdog count this field indicates the maximum num ber of microcycles allowed for a thread (in thread length mode) or a sequence of threads (in busy le ngth mode) before the current runni ng thread is forced to end. for more information on watchdog operation, see section 29.3.1, watchdog . note the tst microcycles are also counted by the watchdog. 29.2.7.2 etpuidler - etpu idle register this register counts the mi crocycles in which the mi croengine is idle (see section 29.3.7.1, idle counter ). figure 29-13. etpuidler register idle_cnt[31:0] ? idle count this is a free-running count of the number of idle mi crocycles in the microengine. for more information on idle counter operation, see section 29.3.7.1, idle counter . iclr ? idle clear this write-only bit is used to clear the idle count idle_cnt: 1 = clear the idle count idle_cnt 0 = do not clear idle count idle_cnt 29.2.8 channel registers layout the channel registers area is shown in figure 29-14 and detailed in next sect ions, for etpu systems of 32 channels per engine. reserved areas are placed to allow doubling the number of channels to 64 for each etpu engine. etpu a: base + 0x068 / etpu b: base + 0x078 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r idle_cnt[31:16] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r idle_cnt[15:0] w iclr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) freescale semiconductor 29-35 pxr40 microcontroller reference manual, rev. 1 figure 29-14. channel registers area 29.2.9 global channel registers the registers in this section group, by type, the interrupt status and enable bits from all the channels. this organization eases manage ment of all channels or gr oups of channels by a single interrupt handler routine. these bits, except the service and watchdog status, ar e mirrored in the individual channel registers, grouped by channel. 29.2.9.1 etpucisr - etpu channe l interrupt status register host interrupt status (see section 29.3.2.2, interrupts and data transfer requests ) from all channels are grouped in etpucisr. their bits are mirrored fr om the channel status/c ontrol registers (see section 29.2.10, channel configurat ion and control registers ) and host must write 1 to clear a status bit. figure 29-15. etpucisr register cisx ? channel x interrupt status etpu a: base + 0x200 / etpu b: base + 0x204 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cis3 1 cis3 0 cis2 9 cis2 8 cis2 7 cis2 6 cis2 5 cis2 4 cis2 3 cis2 2 cis2 1 cis2 0 cis1 9 cis1 8 cis1 7 cis1 6 w cic3 1 cic3 0 cic2 9 cic2 8 cic2 7 cic2 6 cic2 5 cic2 4 cic2 3 cic2 2 cic2 1 cic2 0 cic1 9 cic1 8 cic1 7 cic1 6 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cis1 5 cis1 4 cis1 3 cis1 2 cis1 1 cis1 0 cis9 cis8 cis7 cis6 cis5 cis4 cis3 cis2 cis1 cis0 w cic1 5 cic1 4 cic1 3 cic1 2 cic1 1 cic1 0 cic9 cic8 cic7 cic6 cic5 cic4 cic3 cic2 cic1 cic0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 global channel registers reserved engine 1 channel registers reserved engine 2 channel registers reserved 0x200 0x26c 0x400 0x600 0x800 0xa00
enhanced time processing unit (etpu2) 29-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 1 = indicates that channel x has a pending interrupt to the host cpu. 0 = indicates that channel x has no pending interrupt to the host cpu. cicx ? channel x interrupt clear 1 = clear interrupt status bit. 0 = keep interrupt status bit unaltered. for details about interrupts see the etpu reference manual for details. 29.2.9.2 etpucdtrsr - etpu channel data transfer request status register data transfer request status (see section 29.3.2.2, interrupts and data transfer requests ) from all channels are grouped in etpucdtrsr. their bits are mirrored from the channel status/control registers (see section 29.2.9.8, etpucssr - etpu cha nnel service status register ). figure 29-16. etpucdtrsr register dtrsx ? channel x data transfer request status these bits mimic the correspondi ng etpu dma requests. dtrsx can be cleared by software (writing 1 to dtrcx) or by the assertion of co rresponding dma completion acknowledge line. 1 = indicates that channel x has a pending data transfer request. 0 = indicates that channel x has no pending data transfer request. dtrcx ? channel x data transfer request clear 1 = clear status bit. 0 = keep status bit unaltered for details about interrupts see the etpu reference manual for details. etpu a: base + 0x210 / etpu b: base + 0x214 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dtrs 31 dtrs 30 dtrs 29 dtrs 28 dtrs 27 dtrs 26 dtrs 25 dtrs 24 dtrs 23 dtrs 22 dtrs 21 dtrs 20 dtrs 19 dtrs 18 dtrs 17 dtrs 16 w dtr c 31 dtr c 30 dtr c 29 dtr c 28 dtr c 27 dtr c 26 dtr c 25 dtr c 24 dtr c 23 dtr c 22 dtr c 21 dtr c 20 dtr c 19 dtr c 18 dtr c 17 dtr c 16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dtrs 15 dtrs 14 dtrs 13 dtrs 12 dtrs 11 dtrs 10 dtrs 9 dtrs 8 dtrs 7 dtrs 6 dtrs 5 dtrs 4 dtrs 3 dtrs 2 dtrs 1 dtrs 0 w dtr c 15 dtr c 14 dtr c 13 dtr c 12 dtr c 11 dtr c 10 dtr c 9 dtr c 8 dtr c 7 dtr c 6 dtr c 5 dtr c 4 dtr c 3 dtr c 2 dtr c 1 dtr c 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
enhanced time processing unit (etpu2) freescale semiconductor 29-37 pxr40 microcontroller reference manual, rev. 1 29.2.9.3 etpuciosr - etpu channel inte rrupt overflow status register interrupt overflow status (see section 29.3.2.2, interrupts and data transfer requests ) from all channels are grouped in etpuciosr. their bits are mirrored from the channel status/control registers (see section 29.2.10.2, etpucxscr - etpu cha nnel x status control register ) and one must wr ite 1 to clear a status bit. figure 29-17. etpuciosr register ciosx ? channel x interrupt overflow status 1 = indicates that interrupt overflow occurred in the channel. 0 = indicates that no interrupt ove rflow occurred in the channel. ciocx ? channel x interrupt overflow clear 1 = clear status bit. 0 = keep status bit unaltered. for details about interrupt overflow, see section 29.3.2.2.2, interrupt and data transfer request overflow . etpu a: base + 0x220 / etpu b: base + 0x224 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cios 31 cios 30 cios 29 cios 28 cios 27 cios 26 cios 25 cios 24 cios 23 cios 22 cios 21 cios 20 cios 19 cios 18 cios 17 cios 16 w cioc 31 cioc 30 cioc 29 cioc 28 cioc 27 cioc 26 cioc 25 cioc 24 cioc 23 cioc 22 cioc 21 cioc 20 cioc 19 cioc 18 cioc 17 cioc 16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cios 15 cios 14 cios 13 cios 12 cios 11 cios 10 cios 9 cios 8 cios 7 cios 6 cios 5 cios 4 cios 3 cios 2 cios 1 cios 0 w cioc 15 cioc 14 cioc 13 cioc 12 cioc 11 cioc 10 cioc 9 cioc 8 cioc 7 cioc 6 cioc 5 cioc 4 cioc 3 cioc 2 cioc 1 cioc 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
enhanced time processing unit (etpu2) 29-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.2.9.4 etpucdtrosr - etpu channel data transfer request overflow status register data transfer request overflow status (see section 29.3.2.2, interrupts and data transfer requests ) from all channels are grouped in etpucdtrosr. their bi ts are mirrored from the channel status/control registers (see section 29.2.10.2, etpucxscr - etpu channel x status control register ) and one must write 1 to clear a status bit. figure 29-18. etpucdtrosr register dtrosx ? channel x data transfer request overflow status 1 = indicates that data transfer reque st overflow occurred in the channel. 0 = indicates that no data transfer requ est overflow occurred in the channel. dtrocx ? channel x data transfer request overflow clear 1 = clear status bit. 0 = keep status bit unaltered. for details about data tran sfer request overflow, see section 29.3.2.2.2, interrupt and data transfer request overflow . etpu a: base + 0x230 / etpu b: base + 0x234 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dtr os 31 dtr os 30 dtr os 29 dtr os 28 dtr os 27 dtr os 26 dtr os 25 dtr os 24 dtr os 23 dtr os 22 dtr os 21 dtr os 20 dtr os 19 dtr os 18 dtr os 17 dtr os 16 w dtr oc 31 dtr oc 30 dtr oc 29 dtr oc 28 dtr oc 27 dtr oc 26 dtr oc 25 dtr oc 24 dtr oc 23 dtr oc 22 dtr oc 21 dtr oc 20 dtr oc 19 dtr oc 18 dtr oc 17 dtr oc 16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dtr os 15 dtr os 14 dtr os 13 dtr os 12 dtr os 11 dtr os 10 dtr os 9 dtr os 8 dtr os 7 dtr os 6 dtr os 5 dtr os 4 dtr os 3 dtr os 2 dtr os 1 dtr os 0 w dtr oc 15 dtr oc 14 dtr oc 13 dtr oc 12 dtr oc 11 dtr oc 10 dtr oc 9 dtr oc 8 dtr oc 7 dtr oc 6 dtr oc 5 dtr oc 4 dtr oc 3 dtr oc 2 dtr oc 1 dtr oc 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
enhanced time processing unit (etpu2) freescale semiconductor 29-39 pxr40 microcontroller reference manual, rev. 1 29.2.9.5 etpucier - etpu channe l interrupt enable register host interrupt enable (see section 29.3.2.2, interrupts and data transfer requests ) from all channels are grouped in etpucier. their bits are mirrored fr om the channel configur ation registers (see section 29.2.10.2, etpucxscr - etpu cha nnel x status control register ). figure 29-19. etpucier register ciex ? channel x interrupt enable 1 = interrupt enabled for channel x 0 = interrupt disabled for channel x. for details about interrupts see the etpu reference manual for details. 29.2.9.6 etpucdtrer - etpu channel data transfer request enable register data transfer request enable (see section 29.3.2.2, interrupts and data transfer requests ) from all channels are grouped in etpucdtrer. these bits ar e mirrored from the channel configuration registers (see section 29.2.10.2, etpucxscr - etpu channel x status control register ). figure 29-20. etpucdtrer register etpu a: base + 0x240 / etpu b: base + 0x244 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cie 31 cie 30 cie 29 cie 28 cie 27 cie 26 cie 25 cie 24 cie 23 cie 22 cie 21 cie 20 cie 19 cie 18 cie 17 cie 16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cie 15 cie 14 cie 13 cie 12 cie 11 cie 10 cie 9 cie 8 cie 7 cie 6 cie 5 cie 4 cie 3 cie 2 cie 1 cie 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved etpu a: base + 0x250 / etpu b: base + 0x254 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dtre 31 dtre 30 dtre 29 dtre 28 dtre 27 dtre 26 dtre 25 dtre 24 dtre 23 dtre 22 dtre 21 dtre 20 dtre 19 dtre 18 dtre 17 dtre 16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dtre 15 dtre 14 dtre 13 dtre 12 dtre 11 dtre 10 dtre 9 dtre 8 dtre 7 dtre 6 dtre 5 dtre 4 dtre 3 dtre 2 dtre 1 dtre 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) 29-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 dtrex ? channel x data transfer request enable 1 = data transfer request enabled for channel x. 0 = data transfer request disabled for channel x. for details about interrupts see the etpu reference manual for details. 29.2.9.7 etpucpssr - etpu channel pending service status register etpucpssr is a read-only re gister that holds the st atus of the pending channe l service requests (see the etpu reference manual for details). figure 29-21. etpucpssr register srx - pending service request x indicates a pending service request for channel x. 1 = pending service request for channel x 0 = no service request pending for channel x pending sr status is a logic or of all service requests pending: if onl y hsr is active, srx clears only at the end of the thread. srx clear due to th e other request sources is microcode dependent. note the pending service status bit for a ch annel is 1 when a service request is pending, even if the channel is disabled (cprx = 0). note there can be a delay of one clock be tween writing hsr > 0 in register etpucxhsrr of a channe l and its respective bi t being asserted in etpucpssr. etpu a: base + 0x280 / etpu b: base + 0x284 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r sr31 sr30 sr29 sr28 sr27 sr26 sr25 sr24 sr23 sr22 sr21 sr20 sr19 sr18 sr17 sr16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) freescale semiconductor 29-41 pxr40 microcontroller reference manual, rev. 1 29.2.9.8 etpucssr - etpu cha nnel service status register etpucssr holds the current channel service status on whethe r it is being serviced or not (see the etpu reference manual for details). only one bit may be asserted in this register at a given time. when no channel is being serviced the re gister read value is 0x00000000. etpucssr is a read-only register. the register can be read during normal etpu opera tion for monitoring the scheduler activity. note channel service status does not alwa ys reflect decoding of the chan register, since the later can be cha nged by the service thread microcode. figure 29-22. etpucssr register ssx - service status x indicates that channel x is currently being serviced. it is updated at the 1st mi crocycle of a time slot transition (see the etpu reference manual for details), or when the microengine ends the thread. 1 = channel x is currently being serviced 0 = channel x is not currently being serviced etpu a: base + 0x290 / etpu b: base + 0x294 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ss31 ss30 ss29 ss28 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 ss19 ss18 ss17 ss16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ss15 ss14 ss13 ss12 ss11 ss10 ss9 ss8 ss7 ss6 ss5 ss4 ss3 ss2 ss1 ss0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) 29-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.2.10 channel configuration and control registers each channel has a group of 3 registers used to control, configure and chec k status of that channel as shown in table 29-13 . this organization eases i ndividual channel management. note a bus error is issued on read or wr ite accesses to these registers when etpuecr bit mdis=1. writes are ineffective on bus error. one contiguous area is used to map all channe l registers of each etpu engine as shown in table 29-14 . there are 64 structures defi ned, one for each available channel in th e etpu system (32 for each engine). the base address for the structure presented ca n be calculated by using the following equation: channel_register_base = etpu_engine _channel_base + (channel_number * 0x10) where: etpu_engine_channel_base = etpu_base + 0x400 for engine 1 etpu_engine_channel_base = etpu_base + 0x800 for engine 2 table 29-13. channel registers structure channel offset register name 0x00 etpucxcr - etpu channel configuration register 0x04 etpucxscr - etpu cha nnel status/control register 0x08 etpucxhsrr - etpu channel host service request register 0x0c reserved table 29-14. channel registers map offset registers structure 0x400 etpu a channel 0 registers structure 0x410 etpu a channel 1 registers structure 0x420 etpu a channel 2 registers structure 0x430 . . 0x5e0 etpu a channel 30 registers structure 0x5f0 etpu a channel 31 registers structure 0x600 reserved 0x800 etpu b channel 0 registers structure 0x810 etpu b channel 1 registers structure 0x820 . . 0x9e0 etpu b channel 30 registers structure 0x9f0 etpu b channel 31 registers structure 0xa00 reserved
enhanced time processing unit (etpu2) freescale semiconductor 29-43 pxr40 microcontroller reference manual, rev. 1 29.2.10.1 etpucxcr - etpu cha nnel x configuration register etpucxcr gathers configurations set individually per channel. figure 29-23. etpucxcr register note the fields etcs, cfs and cpba must only be ch anged while the channel is disabled (field cpr=00). cie ? channel interrupt enable (this bit is mirrored from etpucier - see section 29.2.9.5, etpucier - etpu channel interrupt enable register ) 1 = enable interrupt for this channel. 0 = disable interrupt for this channel. see the etpu reference manual for details. dtre ? channel data transfer request enable (this bit is mirrored from etpucdtrer - see section 29.2.9.6, etpucdtrer - etpu channel data transfer request enable register ) 1 = enable data transfer request for this channel. 0 = disable data transfer request for this channel. see the etpu reference manual for details. cpr[0:1] ? channel priority this field defines the priority level for the channel, used by the hardware scheduler (see section 29.3.3, scheduler ). channel_register_base + 0x0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cie dtre cpr 0 0 etpd etcs 0 0 0 cfs w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r odis opo l 0 0 0 cpba w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 29-15. priority level bits cpr priority 00 disabled 01 low 10 middle
enhanced time processing unit (etpu2) 29-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 etpd ? entry table pin direction this bit selects which ch annel signal, input or output, is used in the entry point selection. the etpd value has to be compatible with the function chosen for the channel, selected in the field cfs. for details about entry table and conditi on encoding schemes, refer to the etpu reference manual . 1 = use psto for entry point selection. 0 = use psti for entry point selection. etcs ? entry table condition select this bit determines the channel condition encodi ng scheme that selects, according to channel conditions, the entry point to be taken in an entry table. etcs value has to be compatible with the function chosen for the channel, selected in fiel d cfs. two condition encodi ng schemes are available. for details about entry table and condi tion encoding schemes, refer to the etpu reference manual . 1 = select alternate entry ta ble condition encoding scheme. 0 = select standard entry ta ble condition encoding scheme. cfs[0:4] ? channel function select this field defines the function to be performed by the channel (see the etpu reference manual for details). the function assigned to the channel ha s to be compatible with the channel condition encoding scheme, selected by field etcs. odis ? output disable this bit enables the channel to have its output fo rced to the value opposite to opol when the output disable input signal corresp onding to the channel group that it belongs is active. see section 29.2.2.4, etpu channel output disable signals, and the etpu reference manual for details. 1 = turns on the output disabl e feature for the channel 0 = turns off the output disa ble feature for the channel. opol - output polarity determines the output signal polarit y. the activation of the output disa ble signal forces, when enabled by the odis bit, the channel output signal to the opposite of this polarity (see the etpu reference manual for details). 1 = output active high (output di sable drives output to low) 0 = output active low (output disable drives output to high) cpba[0:10] ? channel x parameter base address the value of this field times 8 sp ecifies the sdm parameter base host (byte) address for channel x (2-parameter granularity; see section 29.3.2.4, sdm organization ). as seen by the host, the channel parameter base (byte) address is: without parameter sign extensi on: etpu_base + 0x8000 + cpba*8 with parameter sign extension: etpu_base + 0xc000 + cpba*8 11 high table 29-15. priority level bits (continued) cpr priority
enhanced time processing unit (etpu2) freescale semiconductor 29-45 pxr40 microcontroller reference manual, rev. 1 29.2.10.2 etpucxscr - etpu chan nel x status control register etpucxscr gathers the interrupt st atus bits of the channel, and also the function mode definition (read-write). bits cis, cios and dtrs for each channel can be also accessed from etpucisr, etpuciosr and etpucdtrsr registers respectively (see section 29.2.9, global channel registers ). host must write 1 to clear a status bit. figure 29-24. etpucxscr register cis ? channel interrupt status 1 = channel has a pending in terrupt to the host cpu. 0 = channel has no pending interrupt to the host cpu. cic ? channel interrupt clear 1 = clear interrupt status bit. 0 = keep interrupt status bit unaltered. these bits are mirrored in etpucisr - see section 29.2.9.1, etpucisr - etpu channel interrupt status register ). see also the etpu reference manual for details. cios ? channel interrupt overflow status 1 = interrupt overflow asserted for this channel 0 = interrupt overflow negated for this channel cioc ? channel interrupt overflow clear 1 = clear status bit. 0 = keep status bit unaltered. these bits are mirrored in etpuciosr - see section 29.2.9.3, etpuciosr - et pu channel interrupt overflow status register ). see also section 29.3.2.2.2, interrupt and data transfer request overflow . dtrs ? data transfer request status 1 = channel has a pending data transfer request. 0 = channel has no pending data transfer request. dtrc ? data transfer request clear channel_register_base + 0x4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cis cios 0 0 0 0 0 0 dtrs dtr os 0 0 0 0 0 0 wciccioc dtrc dtr oc reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ips ops obe 0 0 0 0 0 0 0 0 0 0 0 fm w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) 29-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 1 = clear status bit. 0 = keep status bit unaltered these bits are mirrored in etpucisr - see section 29.2.9.2, etpucdtrsr - etpu channel data transfer request status register ). see also the etpu reference manual for details. dtros ? data transfer request overflow status 1 = data transfer request overf low asserted for this channel 0 = data transfer request overf low negated for this channel dtroc ? data transfer request overflow clear 1 = clear status bit. 0 = keep status bit unaltered. these bits are mirrored in etpucdtrosr - see section 29.2.9.4, etpucdtrosr - etpu channel data transfer request ov erflow status register ). see also section 29.3.2.2.2, interrupt and data transfer request overflow . ips ? channel input pin state this bit shows the current value of th e filtered channel input signal state ops ? channel ou tput pin state this bit shows the current value driven in the channe l output signal, including th e effect of the external output disable feature (see section 29.2.2.4, etpu channel output disable signals ). if the channel input and output signals are connect ed to the same pad, ops reflects the value driven to the pad (if obe=1). this is not necessarily the actual pad value, which drives the value in the bit ips. obe ? output buffer enable this bit shows the state of the channel output buffer enable signal, controlled by microcode. fm[0:1] ? channel function mode 1 each function uses this field for specific configuration. these bits can be test ed by microengine code (see the etpu reference manual for details). 1. these bits are equivalent to the tp u/tpu2/tpu3 host sequence (hsq) bits.
enhanced time processing unit (etpu2) freescale semiconductor 29-47 pxr40 microcontroller reference manual, rev. 1 29.2.10.3 etpucxhsrr - etpu channe l x host service request register etpucxhsrr is used by the host to i ssue service requests to the channel. figure 29-25. etpucxhsrr register hsr[0:2] ? host service request this field is used by the host cpu to request service to the channel (see section 29.3.2.5, host service requests ) hsr = 000: no host service request pending hsr > 000: function-dependent host service request pending. hsr value turns to 000 automatically at the end of mic roengine service for that channel, but only if the thread started due to an hsr. host should writ e hsr>0 only when hsr=0. writing hsr=000 withdraws a pending request if scheduler did not begin to resolve the entry poin t yet, but it does not abort the service thread from that point on. for more details, see the etpu reference manual and section 29.3.2.5, host service requests . 29.3 functional description 29.3.1 watchdog each engine has a watchdog me chanism to prevent a thre ad or a sequence of thr eads from runni ng too long, impacting the latency of the other channel servic es. the watchdog is configured through the register etpuwdtr (see section 29.2.7.1, etpuwdtr - etpu watchdog timer register ). when the watchdog is enabled, an internal counter increments on each micr ocycle when a thread is executing. if the count is greater than the value specified in the etpuwdtr field wdcnt and a thread is still executing, the watchdog: 1. forces an end of the thread 2. issues a global exception and sets the etpumcr bit wdto (see section 29.2.5.1, etpumcr - etpu module configuration register ). the watchdog can be configured in one of the following modes, defi ning how the internal watchdog count is reset: channel_register_base + 0x8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 hsr w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
enhanced time processing unit (etpu2) 29-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? thread length mode : the watchdog count is reset at the end of each thread. ? busy length mode : the watchdog count is reset when th e microengine goes idle. a sequence of threads, one right after another, keeps the count running. the counter is also reinitialized when a thread is forced to end, so th at a new count begins if anothe r tst initiates at the following microcycle. the following applies to the watchdog mechanism: ? microcycles during tst and sdm access wait-sta tes (on tst or instruction execution) are counted. ? if the watchdog count equals wdcnt in the last microinstruction (with sdm wait-states or not) of a thread servicing a channel. ? if the watchdog count expire s (gets greater than wdcn t) during the tst, the thread is forced end on its first instruction. ? the watchdog count does not wrap, so that a thread (in thread length mode) or a thread sequence (in busy length mode) that lasts for more than the maximum value of wdcnt does get a forced end. note watchdog must not be enabled when th e microengine enters halt mode. the counter does not run when the engine is stopped, and resets when the watchdog is disabled. 29.3.2 host interface 29.3.2.1 system configuration system configuration regi sters are described in section 29.2.5, system configuration registers . detailed explanation on the configured f unctionalities is found throughout section 29.3, functional description . 29.3.2.2 interrupts and da ta transfer requests 29.3.2.2.1 interrupt types and sources each one of the etpu channels can be a source of two requests: channel interrupt request and data transfer request . channel interrupts are targeted to a host cpu. data transf er requests may be targeted to a data transfer module (e.g., a dma controller). in terrupt and data transfer registers are used by the host to enable interrupts and data transfer requests, indicate their status and service them. interrupt and data transfer requests have the same sets of regist ers and external signals, and are handled in the same way. they differ only by the fact that data transfer requests are also cl eared by the assertion of respective dma completion acknowledge line. data transfer requ ests can be used as a nother source for host interrupts at mcu integration if not used with a dma.
enhanced time processing unit (etpu2) freescale semiconductor 29-49 pxr40 microcontroller reference manual, rev. 1 note interrupt and data transf er requests can be cleared even when engines are in module disable mode, through the gl obal channel registers, and also dma completion for data transfer requests. channel interrupts and data transfer requests can onl y be issued by etpu micr ocode, through one of the channel control instruction fields (see the etpu reference manual for details). both channel interrupt and data transfer requests can be individually enabled for each channel. etpu interrupt and data transfer registers are mi rrored in two organizations: grouped by channel and grouped by type (interrupt status, interr upt enable, data transfer status, da ta transfer enable). this allows either ?channel-oriented? or ?bundled channel? host interrupt service sc hemes, or a combination of them. for a detailed description, refer to section 29.2.8, channel registers layout, and section 29.2.9, global channel registers . etpu can also assert a global exception interrupt indicating a global illega l state. there are four possible sources for a global exception: ? watchdog timeout, if enabled by the etpuwdtr register. see section 29.3.1, watchdog . ? execution of an illegal instruction by the microengine (see the etpu reference manual for details). this global exception sour ce is flagged by the bits ilf1 and ilf2 in register etpumcr. ? an scm signature mismatch dete cted by the multiple input signa ture calculator - misc. see section 29.3.6.1, scm test - multiple input signature calculator . this source is flagged by the bit scmmisf in regi ster etpumcr. ? microcode request, through microi nstruction field circ (see the etpu reference manual for details). this global exception s ource is flagged by bits mge1(e ngine a) and mge2(engine b) in register etpumcr. the cause of this illegal state is application-depe ndent. the microcode may write an error code into the sdm to indica te the cause of the exception, for instance. global exceptions cannot be direc tly disabled within etpu, except by disabling its sources (memory error, misc and microcode), and it is cleared by wr iting 1 to the gec bit in etpumcr. clearing global exception clears all global ex ception source status bits (ilf1, ilf2, scmmisf, mge1, mge2, scmerr, sdmerr). if gec is written 1 at the same time any of the sources issues a global exception, both the interrupt and the st atus bit of that source remains asserted. the assert ion of global exception by one of the sources above does not pr event the others from asserting it too, so any number of them, in any combination, can be flagged. note there can be a race between the clear of a global exception and occurrence of a new set condition, such that the se t happens just before the clear and cannot be sensed by the host. therefor e, global excepti on cannot be used as a normal interrupt source: it should only be used for emergency procedures.
enhanced time processing unit (etpu2) 29-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.3.2.2.2 interrupt and da ta transfer request overflow if a channel interrupt was is sued, its status bit is stil l set, and microcode issues another channel interrupt, the interrupt overflow status bit is set for that chan nel. interrupt overflow status can be checked by the host in channel status regi ster etpucxscr bit cios ( section 29.2.10.2, etpucxscr - etpu channel x status control register ), mirrored in register etpuciosr ( section 29.2.9.3, etpuciosr - etpu channel interrupt over flow status register ). interrupt overflow status is not cleared automatically when interrupt status is cleared. the same mechanism a nd respective registers ( etpucdtrosr) are available for data transfer requests. if interrupt is set and cleared at th e same time, set prevails and overflow is not altere d (keeps the same state as it was before, asserted or not). global exception has no overflow status. 29.3.2.3 parameter access 29.3.2.3.1 paramet er access widths from the host side the sdm address space is mappe d in bytes, and each 32-bit parameter occupies 4 contiguous, aligned bytes. the host can read/write the sdm by 8-, 16-, or 32-bit accesses in aligned addresses. in 32-bit access, host can acce ss all 32 bits or only the lo wer 24 bits with an automatic sign extension (see section 29.3.2.3.4, parameter sign extension area ). 29.3.2.3.2 parameter addresses and endianness to access parameter number xxx , etpu microengine(s) would select address xxx. the host would add (xxx*4) to the sdm base addres s to access the same parameter. fo r example, parameter 0x101 is seen by the host in (sdm base address +0x404) . an example of sdm memory map is shown in figure 29-26 . the host can access the sdm with a 32-bit-wide bus cycl e to a four-byte aligned address, 16-bit-wide bus cycle to a two-byte aligned address, or 8-bit wide bus cycle to any byte address. the address of the 24-bit paramete rs and the most significant byte de pends on the endianness of the mcu. 29.3.2.3.3 parameter concurrency host accesses to parameters may occur in parallel wi th etpu microengine accesse s. readings taken from a group of parameters while they are being simult aneously updated may lack coherency. etpu provides mechanisms to ensure parameter coherency in acce sses from both host side and microengine side, including the use of a coherent dual-parameter transfer mechanism, described in detail on section 29.3.4, parameter sharing and coherency . 29.3.2.3.4 parameter sign extension area the sdm address space to the host is mirrored in a parameter sign extension - pse - area (see section 29.2.4, memory map ). accesses from the host to the pse area differ from accesses to the standard sdm address space as follows:
enhanced time processing unit (etpu2) freescale semiconductor 29-51 pxr40 microcontroller reference manual, rev. 1 ? writes : the most significant byte of th e parameters is not written, and the sdm retains the old byte value, regardless of the host access size. ? reads : the most significant bit of the 24-bit parame ter (that is, the msbit of the second most significant 32-bit parameter byte) is repeated in the 8 most signifi cant bits of the read value on all 32-bit reads and most signi ficant 16- and 8-bit reads. the same parameters written in th e standard sdm address space are read from the pse area with the same offsets, and vice-versa. this feature reliefs the host from extending the signal of 24-bit etpu pa rameters before calculations, and from read-modify-write accesses to m odify 24-bit parameters at the sdm. 29.3.2.4 sdm organization the sdm internal partition for channel allocation is dynamic and programmed in the channel registers (see section 29.2.10.2, etpucxscr - etpu channel x status control register ). the host application is responsible for allocating a different parameter base address to each channel during the initial etpu configuration, and to allocate enough parameters for the selected function, with no unintentional overlapping between parameters of different functions. besides channel parameters, global area s may have to be allocated for pa rameters that ar e shared by more than one channel, in one or both e ngines. also, temporary pa rameter areas should be reserved to be used by the coherent parameter transf er mechanisms described in section 29.3.4, parameter sharing and coherency , if necessary.
enhanced time processing unit (etpu2) 29-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 29-26. sdm organization example (4 kbytes) single-engine etpu or dual etpu system may require less parame ters than the maximum number provided by the sdm. since the sdm pa rtition is fully dynamic, there is no limitation of fixed channel addresses, and the reduced ar ray can be fully utilized. engine 2 engine 1 sdm 0x000 etpuc0cr[cpba]->0x014 etpuc1cr[cpba]->0x018 etpuc2cr[cpba]->0x168 etpuc3cr[cpba]->0x172 etpuc30cr[cpba]->0x180 etpuc31cr[cpba]->0x16e etpu2 channel 3 parameters etpu2 channel 0 parameters etpu1 channel 0 parameters etpu1 channel 1 parameters etpu2 channel 30 parameters etpu2 channel 2 parameters etpu1 channel 2 parameters etpu1 channel 31 parameters etpu1 channel 3 parameters etpu1 channel 30 parameters etpu2 channel 31 parameters 0x200 real parameter number 0x014 0x020 0x028 0x030 0x2a0 0x2c0 0x1b0 0x2d0 0x2dc 0x2e4 0x300 host parameter offset 0x000 0x800 0x050 0x080 0x0a0 0x0c0 0xa80 0xb00 0x6c0 0xb40 0xb70 0xb90 0xc00 host etpu2 channel 1 parameters parameters 0x000 - 0x07f can be used as ?shared pool? for etpu absolute addressing mode. 0x3ff 0xffc etpuc0cr[cpba]->0x010 etpuc1cr[cpba]->0x150 etpuc2cr[cpba]->0x160 etpuc3cr[cpba]->0x00a etpuc30cr[cpba]->0x100 etpuc31cr[cpba]->0x0d8
enhanced time processing unit (etpu2) freescale semiconductor 29-53 pxr40 microcontroller reference manual, rev. 1 29.3.2.5 host service requests host cpu can request immediate serv ice from a channel by writing a non- zero value to the host service request register field - hsr (see section 29.2.10.3, etpucxhsrr - etpu channel x host service request register ). there is one hsr field for each channel, so that writing to it generates a service request to the respective channel only. a zero valu e in hsr means no host se rvice request is pending for the channel. hsr value turns to 000 automatically at the end of mic roengine service for that channel, but only if the thread started due to an hsr. the meaning of a non-zero hsr value depends on the function assigned for the channel. these bits are part of the conditions whic h select the function entry point, and cannot be tested by microcode. for more details, refer to the etpu reference manual . if host writes hsr=000 when a thr ead for the same channel is alrea dy running, the thread runs until the end and is not aborted. if host wr ites hsr>000 when an hsr thread for the same channel is already running, hsr value resets at the end of the thread, a nd no new hsr will be pending. if hsr is written before its value is resolved by th e scheduler during tst, th e entry point will obey the new hsr value, and if this new value is 000, no service thread is executed for the hsr. the scheduling of hsrs is completely asynchronous wi th host accesses, and ther e is no race-free manner to change an hsr value before se rvice thread execution, so generally the safe wa y is: write hsr>0 only when hsr=0. error recovery or emergency host proce dures may require one to the safely abort service and reset channel state when an hsr is already pending or executing. in these cases, th e procedure below should be followed: 1. disable the channel, writing cpr=00 in register etpucxcr. that will prevent any pending hsr to be serviced. 2. check if the channel is currently being servi ced, reading its service st atus bit in register etpucssr. if it is, wait for the time necessary to finish the serv ice pending, or check again until hsr == 0, or channel service bit in etpucssr is cleared. 3. write hsr with the error recover value. th is value should, possibly combined with other host-defined flags in sdm or fm bits, initiate a channel rese t or error recovery procedure. 4. re-enable the channel, writing cpr value > 0 in register etpucxcr. 29.3.2.6 scm access only host can access scm as data. depending on th e specific device, scm may be implemented as a ram or rom. this determines host accesses to the scm as shown below. 29.3.2.6.1 scm ram implementations when scm is implemented as ram, the host may read or write to scm by setting etpumcr bit vis=1. if vis=0 and host tries to access scm space, a bus error is issued, writes are ineffective and read data is meaningless. both engines must be stopped or halted to set vis=1.
enhanced time processing unit (etpu2) 29-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note it is necessary to turn vis bit on to set softwa re breakpoints (see the etpu reference manual for details). 29.3.2.6.2 scm low power scm turns off its internal clocks when both engines are stopped (etp uecr bit stf asserted), vis=0 at etpumcr, and misc is not enabled (scmmisen=0). the scm clocks are automatically turned on if either one of the stf bits is negated or vis turns to 1, or scmmisen turns to 1. scm clocks are not turned off if any of the engi nes is not stopped, even if they are both halted. the conditions for scm clocks and mi sc activation are summarized in table 29-16 . 29.3.2.6.3 scm off-range data when read accesses are ma de, either by the host or by a microe ngine, to addresses above the limit corresponding to the scmsize value in etpumcr , the value read comes from the register etpuscmoffdatar. the host can progr am the register at initializa tion with an opcode value with operations that try to prot ect or recover the system from runaway code, for inst ance: terminate the thread, clear channel flags, disable match and transition service re quests, issue an interru pt, jump to an error recovery procedure 1 . writes to unimplemented addresses do not return error and can write on unspecified mirror addresses, so they should be avoided. table 29-16. scm clocks and misc activation etpuecr_1 stf etpuecr_2 stf etpumcr vis etpumcr scmmisen scm clocks misc 0x0 1 1 vis cannot be written 1 if etpuecr_1 bit stf= 0 or etpuecr_2 bit stf=0, and both hltf bits are 0. 1onon 0x0 1 0onoff x00 1 1onon x00 1 0onoff 1100offoff 1 1 0 1 on on 1 2 2 if vis=1, neither mdis can be written 0 nor the engine leave stop mode, regardless of device stop reques. 1 2 10onoff 1 2 1 2 11onoff 3 3 misc resets and stays so when vis=1, re starting automatically when vis goes 0 if scmmisen=1. 00x0onoff 0 0 x 1 on on 1. only part of these suggested operations can be parallelized in a single instruction. see the etpu reference manual for details.
enhanced time processing unit (etpu2) freescale semiconductor 29-55 pxr40 microcontroller reference manual, rev. 1 29.3.2.7 bus error conditions follows a summary of the possible causes of bus errors on host accesses to the etpu memory space: ? read or write access to the scm with etpumcr bit vis=0. ? read or write access to the channel register s with etpuecr bits mdis=1, or bit stf=1. ? write access to the time base registers with etpuecr bits md is=1, or bit stf=1. ? non-correctable errors in the scm on reads of a ny size or writes less than 32-bits wide, when etpumecr bit cedd=0. ? non-correctable errors in the sdm on reads, when etpumecr bit dedd=0. 29.3.3 scheduler every function is composed of one or more threads. a thread consists of a gr oup of instructions that, once begins execution, cannot be interrupted by host or channel events. each active channel intents to be serviced, being granted time for th read execution. since one microe ngine handles se veral channels operating concurrently, the function th reads must be executed serially. the task of the scheduler is to re cognize and prioritize the channels needing servi ce and to grant execution time to each channel. the time given to an individual thread for execution or service is called a time slot . the duration of a time slot is determ ined by the number of instructions executed in the thread plus sdm wait-states received, and varies in length. at any time, an arbitr ary number of channels can require service. to request service, channel logic, etpu microcode or host application notifies th e scheduler by issuing a service request. 29.3.3.1 channel enabling and priority assignment every channel is assigned one of three priority leve ls - high, middle, or low - by the host cpu, through the channel configuration register field cpr (see section 29.2.10.1, etpucxcr - etpu channel x configuration register ). these registers are also used to disa ble the channel, whic h is equivalent to assigning it a ?null? priori ty. in this case, the scheduler does not grant any of its service requests. it is possible to change the channe l priority level or disa ble it dynamically. if the ho st disables a channel when it is currently being serviced, channel service thr ead will complete. this means that it is possible for the output level of a channel signal to change, or a host interrupt occur, ev en after its priority register was written to ?null?. for instan ce, if an output transition is scheduled, the transition will occur even after the channel is disabled. service requests previously pending or that occur whil e a channel is disabled remain asserted while the channel is disabled, and are serviced if the channel is enabled again, in due time determined by the priority scheme and concurrent requests from other channels. channels are di sabled after reset, and it is recommended to configure a host service request for initialization of a channel before that channel is enabled to active priority (see section 29.4, initialization/ application information ).
enhanced time processing unit (etpu2) 29-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.3.3.2 channel priority schemes the scheduler holds a service grant register with one bit for each channel. once the scheduler grants a time slot to channel, the service grant bit for that channel is asse rted in the service grant register. when the service grant bit of a channel is set, the channel may request new service but is not serviced again before its service grant bit is cleared. when all channels in a same priority level are servi ced, their service grant bits are cleared at the end of the thread, one etpu clock before the next serviced channel is calculated, according to the scheme below 1 : ? clear all grant bits of priority hi gh if all channels of that priority that are requesting have their grant bits in 1. ? clear all grant bits of priority me dium if all channels of that priority that ar e requesting have their grant bits in 1. ? clear all grant bits of priority lo w if all channels of that priority that are requesting have their grant bits in 1. ? clear all grant bits of disabled channels. this scheme assures that no channel is left with its grant bit forever asserted (preventing it from being serviced again), even if the channel pr iorities are reassigned during the execution. priority level is determined based on the maximum latency desired for each channel. a channel having a function that requires the most frequent or more im mediate service should be allocated a high priority level. the etpu employs a primary and a secondary priority scheme . these two schemes ensure frequent servicing of high-demand functions and ensure a minimum time allo cation to all channels requesting service, regardless of their priority level. the prim ary scheme prioritizes reque sting channels that have different priority levels; the second ary scheme prioritizes re questing channels that have the same priority level. initially, a channel requests service and is grante d a time slot by the scheduler: service grant bit is asserted. if only high-level channels c onstantly receive service first because of their pr iority level, middle- and low-level channels would only be serviced by defa ult, i.e., if no high-level channels request service. to ensure that each priority level receives an opportuni ty for servicing, every time slot has a fixed priority level that the scheduler honors first. divided into sets of seven, time slots are numbered from one to seven. figure 29-27 illustrates the numbered time slots in sets of seven (fields a and b) and identifies their assigned default priority level. th e high level has more time slots than the middle and low levels. out of every seven time slots available, f our are assigned to honor high-level ch annels first, two are assigned to honor middle-level channels fi rst, and one is assigned to honor low-level channels first. only one request (in each engine) is serviced per time slot. when no channel requests service and the microengine is idle the priority scheme is initialized to time slot one, to prevent priority inversion on the next request 2 . 1. grant bits are also cleared in the next clock, when the serv ice channel is chosen, or when the microengine is idle, using the same scheme. 2. priority inversion would occur in the following situation: no channel is requesting service, and the current time slot is primarily assigned to a low-priority channel. if the schedul er was not reset to time slot one and two channels requested service at the same time, one with high priority and the ot her with low priority, the channel to be serviced would be the low-priority channel.
enhanced time processing unit (etpu2) freescale semiconductor 29-57 pxr40 microcontroller reference manual, rev. 1 figure 29-27. time slot priority levels 29.3.3.2.1 primary scheme - priori ty among channels on different levels although time slot priority assignm ent is fixed, the servicing prio rity is not. the primary scheme acknowledges the priority level assigne d to a time slot, granting service first to a channel having the same priority. in figure 29-27 , time slot one has a high-level assign ment; therefore, a high-level channel requesting service is recognized first. however, if no high-level channel requests service, the scheduler recognizes a requesting middle-level channel. if this level has no request, the sc heduler continues to the low-level. if no requests occur, the scheduler truncates the seven state cy cle and starts a new cycle at time slot one, waiting for the first request. granting se rvice to a different-level channe l is called priority passing. the order of passing always gives th e highest priority to the assigned le vel, and the second priority to the higher of the remaining requesting priority levels as shown in table 29-17 . when priority is passed to another level, that level is serviced and the fixed-priority-level sequence is resumed with the next time slot. table 29-17. priority passing assigned priority level next priority level next priority level high ? middle ? low middle ? high ? low low ? high ? middle 1 234567 1 23 h mhl hmhhmh 45 lh high middle low a b
enhanced time processing unit (etpu2) 29-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 29-28. priority passing example examples of priority passing are shown in figure 29-28 . each cycle contains seven time slots (or less if no service request exist). in cycle b, no high-level or middle-level service requests are present before time slot three which is assigned by default to high-level priori ty. thus, time slot three is passed to the low level. in cycle b there are also no middle-leve l service requests before time slot six, so it passes the priority to a requesting high-level channel. during time slot si x no more high level requests are left, but two new middle-level requests arrive, and th ere are also three low level pending service requests. thus, time slot seven of cycle b and time sl ot one of cycle c are passed to the middle-level which is the next priority level after high. time slots two and thr ee of cycle c are passed to the low level which contains the three remaining channel servi ce requests. at time slot thr ee of cycle c the last low le vel request is serviced, and the scheduler passes to idle state. at this point the cycle c is truncated and the scheduler passes to time slot one of cycle d. slot number 67123456 123 1 mhhmhl hmhhmh h high pend count service high 21 01 0 2 0 - x new service requests arrive at a specific priority level 20 x 2 22 1 1 1 0 0 0 1 2 2 1 0 2 2 7 dh dm dh h>l dl dh m>h dm h>m h>m m>l h>l 1 0 dh, dh, dl - default service high, middle or low h>l, h>m, m>h, m>l - priority passing scheme id - idle (no service request) id slot assignment slot assignments: reset slot fixed priority level middle pend count service middle low pend count service low number cycle a cycle b cycle c (truncated) cycle d 23 mh 1 1 1 1 0 1 1 0 0 1 h h>m dm dh 1 h id
enhanced time processing unit (etpu2) freescale semiconductor 29-59 pxr40 microcontroller reference manual, rev. 1 29.3.3.2.2 priority passing disabling the priority passing scheme allows a case where a high priority channe l looses to a lower priority one right after another lower priority has been serviced, exemplified in the cycle d on figure 29-28 . a middle priority channel wins time slot 1 due to priority passing fr om high to middle. while it is being serviced, two new service requests arrive, one high and one middle priority. the hi gh priority request looses to the middle one on next time slot 2 by default priority assignment. this priority inversion can be avoided by setting the etpuecr register bit sppdis (see section 29.2.5.5, etpuecr - etpu engine configuration register ), which disables the priority passing mechanism. when priority passing is disa bled, at the end of the thread the slot num ber is incremented until a time slot that matches the priority of one of the requesting channel(s). the time slot advance takes no extra clocks. if no channel requests service, the time sl ot counter stays at time slot 1. the priority selection scheme with disabled priority passing is summarized in table 29-18 . an example of the priority passing disabling scheme is illustrated in figure 29-29 . the sequence of service requests is the same as in the example of figure 29-28 , and although the time slot incrementing differs, the priorities granted are the same for cycle b. cycle c ha s one of the low priority channels serviced before the second middle one. cycle d, however, no longer has the priority inversion. in cycle b, after the time slot 2 only a low priority request remains, so th e time slot count advances directly to 4, which has a low priority assigned. time slot keep s on 4 for the next service, as only a low priority request remains also, and only time slot 4 is assigned to low. two high priority services contend for the next time slot 5 (assigned to high ). the second high priority channel is serviced on the next time slot, jumped to 7 because there is no middle request, ending cy cle b. cycle c starts with time slot 2, as there are no high priority requests and two middle and two low ones. after the first middle service, time slot count skips 3 assigned to high (no hi gh requests), and services a low priority channel on time slot 4. it follows the same scheme until there are no other requests and cycle c is truncated, re setting the time slot counter to 1. cycle d begins with a middle request , jumping to time slot 2. during th is service two re quests arrive, one high and one middle. unlike what ha ppened with priority passing, the next serviced is the high priority table 29-18. priority passing disabling at the end of time slot servicin g priority if any request of priority service it on time slot else if any request of priority service it on time slot else if any request of priority service it on time slot 1 high medium 2 high 3 low 4 2 medium high 3 low 4 medium 6 3 high low 4 high 5 medium 6 4 low high 5 medium 6 low 4 5 high medium 6 high 7 low 4 6 medium high 7 medium 2 low 4 7 high high 1 medium 2 low 4
enhanced time processing unit (etpu2) 29-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 channel, as the time slot increments to 3. the second middle priority cha nnel request in cy cle d is finally serviced next, on time slot 6. figure 29-29. priority pa ssing disabling example 29.3.3.2.3 secondary scheme - priority among channels on the same level because channels can randomly request service, channels having the same priority level will inevitably request service simultaneously. a secondary scheme prioritizes these requests. the scheduler services channels on each of the three priori ty levels, beginning with the lowe st numbered channel on that level. slot number 67124457 4641 2 mhhml l hhml ml hm high pend count service high 21 01 0 2 0 - x new service requests arrive at a specific priority level 20 x 2 22 1 1 1 0 0 0 1 2 2 1 0 2 2 2 dh dm dh dl dl dh dh dm dm dl dm dl 1 id 0 dh, dh, dl - default service high, middle or low id - idle (no service request) id slot assignment slot assignments: fixed priority level middle pend count service middle low pend count service low cycle a cycle b cycle c (truncated) cycle d 36 hm 1 1 1 1 0 1 1 0 0 1 h dm dh dm reset slot number
enhanced time processing unit (etpu2) freescale semiconductor 29-61 pxr40 microcontroller reference manual, rev. 1 29.3.3.2.4 priority scheme example the overall priority sche me simultaneously in corporates both primary and se condary scheme s. combining both schemes in the following ex ample conveys their correlation. 1. one high-priority and one low priori ty channels request service, whil e the scheduler is in time slot one. having its service request bit asserted, a single high-level cha nnel is granted the time slot, which has high-level priority (prima ry scheme) and its service grant bit is asserted. at the end of the thread, the service grant bit is negated (no more requests of high priority level channels). 2. the scheduler proceeds to time slot two, which has middle-level priority; however, no middle-level channel is requesting service. priority is passed to the high level, but no high-level channel is requesting service; therefore, priority is passed again, and service is granted to the single requesting low-level channel. once serviced, this channel?s grant bi t is negated (no more low-level requests). 3. the scheduler resumes with the fixed-priority sequenc e on time slot three; however, no channels are requesting service. the scheduler retu rns to time slot one, waiting for requests. 4. two high-level and two middle-leve l channels simultaneously request service. being in time slot one which is assigned high priori ty, the scheduler finds the lowest numbered high-level channel (secondary scheme) and selects it for service. this channel?s service grant bit is asserted. 5. the scheduler continues to ti me slot two, which has middle pr iority (primary scheme), and allocates the slot to the lowe st numbered middle-level channe l requesting service (secondary scheme). the scheduler notes the still unserviced middle-level channel and proceeds to time slot three. 6. time slot three is allocated for high priority. the slot is allocated to the remaining unserviced high-priority channel, and the ch annel?s service grant bit is asse rted. the scheduler checks again at the end of the thread. all se rvice grant bits of high-level re quested channels are asserted; therefore, all high-priority channe ls that requested have been allo cated execution ti me. under this condition, all service grant bits of the high-level serviced cha nnels are negated. the scheduler proceeds to time slot four. 7. time slot four is allocated for low-priority channel; however, no low-le vel channel is requesting service. priority is passed to the high level, but no high-level channel is requesting service; therefore, priority is passed again, and service is granted to the remain ing middle-level channel which requests service. this channe l?s service grant bit is asserted. the schedul er checks again at the end of the thread. all grant bi ts of middle-level requested channe ls are asserted; therefore, all middle-priority channels have b een allocated execution time. under this condi tion, all service grant bits of the middle-level serviced channels are negated. the sc heduler proceeds to time slot five. meanwhile a low priority channel requests service. 8. time slot five is allocated for high-priority channels, but there are no more requests from high-priority or middle priority channels. the single low-level ch annel which required service is granted time slot five. once serviced, the channel?s service gran t bit is asserted. next, the service grant bit is negated (no more requests of low priority level channels). 9. the scheduler resumes with the fixed-priority sequence on time sl ot six; however, no channels are requesting service. the scheduler returns to time slot one and waits for requests.
enhanced time processing unit (etpu2) 29-62 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.3.3.3 time slot latency latency is the amount of time betw een a service request a nd the beginning of service on that channel. the following factors affect latency: ? number of active channels ? number of channels on a priority level ? number of available time slots on a priority level ? number of microcycles required to execute a thread of a function ? number of sdm accesses during execution of a function thread ? etpu clock frequency. each time slot may require a differ ent number of microcycle s, depending on the thread of a function to be executed. this variat ion is shown in figure 29-30 . for more details on latency evaluation, see section 29.4.2, estimating worst case latency . figure 29-30. time-slot variation 29.3.4 parameter sharing and coherency sdm can be concurrently accessed by host and microengines (two in a dual etpu engine system). in general, there is no guaranteed orde r by which a group of parameters is accessed, which may lead to a lack of internal consistency if two or more related para meters are read when only part of them is updated. etpu provides mechanisms to guarantee paramete r coherency. the most generic mechanisms for host-etpu coherency, suitable fo r any number of parameters, are: ? the use of transfer service thread mechanism. ? the mailbox (or ?software semaphore?) mechanism. these mechanisms, described in section 29.4.1, multiple pa rameter coherency methods , use microcode to transfer parameters from tempor ary buffers in sdm to their definiti ve locations (or vice-versa). these methods have the disadvantage of wasti ng processing and code memory resources. etpu also provides a coherent dual-parameter controller - cdc - mechanism. it is used by host to coherently transfer pairs of parame ters from/to a parameter buffer lo cated on sdm to/from the locations on sdm where parameters are accesse d directly by the channels. cohere ncy is guaranteed by sdm access arbitration. although limited to two parameters only, it has lower la tency and wastes no microengine resources 1 . cdc usage is described in section 29.3.4.2, coherent dual-par ameter controller - cdc . microcycles time slot fixed priority level 1 2345 h mhlh 6 m
enhanced time processing unit (etpu2) freescale semiconductor 29-63 pxr40 microcontroller reference manual, rev. 1 for parameters shared by both engines, etpu provides hardware semaphores . coherency is assured given the semaphores are used to prevent concurre nt access to the changing parameters. microengine can request semaphores using sp ecific microinstructions. neither host nor cdc have access to the hardware se maphores, but they can be combined with microcode transfer mechanisms if host must coherently acces s parameters which are also shared by both engines. 29.3.4.1 host side atomic access host side atomic accesses can be achi eved by either of following ways: ? for one parameter, the sdm should be accessed by 32-bit-wide data transfers to ensure coherency ? for two parameters only, using the coherent dual pa rameter controller. ? indirectly, for any number of para meters, by requesting microcode to coherently access sdm in its behalf. the host side atomicity problem becomes, then, a microengine si de atomicity problem. some methods that use this approach to achieve coherency are described in section 29.4.1, multiple parameter coherency methods . 29.3.4.2 coherent dual-parameter controller - cdc dual-parameter coherency is supporte d by a coherent dual-parameter c ontroller hardware - cdc, which contends with microengine for sdm access. cdc atomically transfers, upon host?s command, two parameters from one area of the sdm to another. on e area is a temporary (buffer) area, where the two parameters are directly r ead or written by the host. this temporar y area has to begin in an sdm address multiple of 2 words, and the two parameters must be sequential. the other area is the channel parameter area where the microcode normally a ccesses the parameters, usually with the channel relative address mode (see the etpu reference manual for details). in this area, the parameters transf erred by cdc don?t have to be sequential. a transfer fr om the temporary area to the channel area, when the host sends data to the channel, is called a write transfer . inversely, in a read transfer the parameters are copied from the channel area to the tempor ary area (channel to host). coherency is guaranteed by the sd m access contention rules implemented in the sdm arbiter. cdc transfers are coherent in respect to the two engines, so the target parameters in the channel area may be shared by channels on them both. during cdc operation, th e host may suffer from 3 up to 11 etpu clocks wait states 1 , and the microengine(s) may suffer up to 2 microcycle wait-states 2 . cdc accesses are atomic with respect to microengine(s) accesse s to the sdm. even when neither engine is in tst, cdc may suffer up to 4 etpu clock internal wait-states from sdm arbite r, meaning 9 slave wait-states to host, so that it does not break atomic back-to-back accesses from microengine(s). cd c also cannot break tst preload accesses. host can initiate cdc back -to-back transfers: there is no need of idle slave cy cles between two transfers. 1. a microengine access to the sdm in the moment cdc is perfor ming the transfer may suffer a maximum of two wait-states. 1. the maximum number of host wait states on cdc occurs when both microengines overlap their tsts, delayed 3 etpu clocks from each other. 2. one microcycle takes two etpu clocks. microengines get wa it-states in multiples of mi crocycles, while host and cdc wait-states are multiples of etpu clocks.
enhanced time processing unit (etpu2) 29-64 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.3.4.2.1 cdc programming the coherent dual-parameter controller register (see section 29.2.5.2, etpucdcr - etpu coherent dual-parameter controller register ) is used to configure and init iate cdc transfers between the temporary area and channel parameter area. host asserts sts bit in orde r to start the data transfer. cdc then contends for the sdm and starts the transfer. when the data transfer is complete, sts returns to 0. host receives wait-states for writing sts=1 while cdc contends for sdm and during the transfer. the write access ends when cdc finishes the transfer. ho st receives wait-states dur ing the cdc transfer. if host writes etpucdcr with sts=0 or does not write the sts byte, th e cdc transfer does not occur. cdc programming can be su mmarized as follows: 1. if it is a write transfer, i.e., from host to ch annel, write the two parameters into temporary area. 2. write etpucdcr with sts=1 and the remain ing cdc programming parameters: parameter width (32 or 24 bits, field pwidth), transfer di rection (read or write, field wr), temporary parameter area base address (field pbbase), and th e absolute addresses of the parameters to be transferred (concatenation of th e fields ctbase and parm0/1). 3. if it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area into host memory/registers. 29.3.4.3 sdm arbitration up to four entities can access sdm: ? two microengines (in a dual etpu engine system) ? the coherent dual-param eter controller (cdc) ? the host cpu (direct memory-mapped access) the following rules specify the access priorities for contended access. they keep compatibility with the tpu3 dual parameter access atomicity, but only betw een the microengine and cd c (not host accesses through slave bus). 1. microengine accesses from the two etpu engines are interleaved between each othe r, but not with host or cdc accesses; 2. the etpu microengine(s) gives priority for sd m accesses to either the host cpu or the cdc under any of the following conditions: a. the microengine has comple ted accessing the second parame ter in a back-to-back sdm access 1 . b. the sdm was not accessed during the last arbitration slot fo r the microengine and the host does not loose the access to th e other engine in the current arbitration slot 2 . c. cdc is transferring data, after its first (read) access. note that the cdc can be in middle of a data transfer of another pair of parameters, unrelated to the ones that microengine tries to access. 3. the etpu microengine takes priority for sdm accesses under either of the following conditions: 1. if microengine tries to access the sdm in the following microcycles, the third and fourth consecutive accesses are considered the first and second of a new back-to-back dual access. 2. the microengine access slot is between its own t4 and t2 edges.
enhanced time processing unit (etpu2) freescale semiconductor 29-65 pxr40 microcontroller reference manual, rev. 1 a. the host cpu or cdc has done a data transfer during the last access arbitration slot for the engine 2 . also, the host cpu does not hold a pe nding access against the other etpu microengine. b. the microengine is arbitrating for the access of its second para meter in a back -to-back access 1 . all pairs of back-to-back parame ter accesses are cohere nt with respect to host and cdc (not to the other microengine). the direction (read or wr ite) of any individual access by host or microengine is irrelevant to the arbitration. the use of normal or pse sdm area by th e host is also irreleva nt to the arbitration. the first parameter preloading in a tst is considered first access by the arbiter, regardless of any access made at the end microinstruction of the previous thread, i.e.: the last access of a thread and the first preload are never considered a back-to-back access. on the other hand, the tst preload accesses are considered back-to-back and are, therefor e, atomic with respect to host or cdc. note the zero sdm operation (see the etpu reference manual for details) is considered an sdm access for arbitration purposes bot h on writes and reads; the fact that read sdm data is dis carded is irrelevant for arbitration. 29.3.4.4 enhanced digital filter - edf the edf eliminates passing of si gnal transitions which are caused by noise. its purpose is to eliminate false transition service requests caused by noise pulses which are s horter than a programmed width. the edf has three modes of operat ions, selected by the cdfc field in the etpuecr register (see section 29.2.5.5, etpuecr - etpu e ngine configuration register ). these modes offer selections of trade-off between noise immunity and signal latenc y. cdfc also allows the filter to be bypassed. table 29-19 gives an example of minimum detected signal pulse and maximum filtered noise pulse in the three edf operation modes. in angl e mode, if am=01, the ed f in channel 0 is repl aced with the digital filter and synchronizer of the tcrclk signal. in th is mode, channel 0 works in combination with the angle counter logic, and their operation is fully synchronized. following subsections provide th e functional description of the etpu channel digital filter. 29.3.4.4.1 two-sample mode in this mode the edf works like the tpu2/3 digital filt er. it uses the filter clock which is the etpu clock divided by (2, 4, 8,.., 256) as a sampling clock. the filt er clock is selected by the fpsck field in the etpuecr - engine config uration register (see section 29.2.5.5, etpuecr - etpu engine configuration register ). the edf compares two consecutive samples. if both samples have the same value, the input signal state is upda ted. note that when the fpsck field selects the etpu clock divided by two, the edf works like the tpu1 four-clock digital filter.
enhanced time processing unit (etpu2) 29-66 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.3.4.4.2 three-sample mode in this mode, like in the tpu2/3 mode, the edf uses the filter clock as a sampling clock. the edf compares three consecutive samples. if all three samples have the same value, the input signal state is updated. the three-sample mode gives more signal latency th an the two-sample mode, but also better noise immunity and better ratio between minimum detected signal pulse to ma ximum filtered noise pulse. when a certain filter clock frequency is selected for two-sample mode, doubl e filter clock frequency can be selected to get better late ncy in three-sample mode. 29.3.4.4.3 continuous mode in this mode the edf compares all the values sample d at the rate of etpu cl ock divided by two, between two consecutive filter clock pulses. if the signal is continuously stable for the entire di gital filter clock period (i.e all the samples have the same si gnal value), the input signal state is updated. this method gives the same latency and the same ratio between minimum detected signal pulse to maximum filtered noise pulse, as th e two-sample mode, as long as ther e is no noise. each sampled noise delays the signal transition detection by at least a whole digital filter clock period. the continuous mode gives the best noise immunity by comparing multiple samples of the noise. on the other hand, when a short noise pulse a ppears in the middle of the filter clock period at the same time of a real signal transition, the c ontinuous mode may reject a real signal transition and delay the response to the first filter clock period in which th e signal is continuously stable. this may add to the latency and also to the minimum detected signal pul se in a noisy environment. 29.3.4.4.4 bypass mode in bypass mode the signal that feeds the edge detection comes directly fr om the output of the synchronizer, not filtered. 29.3.4.4.5 filter clock prescaler the tcrclk signal and each channel configured as an input have an associated synchronizer followed by a digital filter connected to the signal that samples signal transitions . after reset, the di gital filter filters out high and low pulse widths smaller than the peri od of two etpu clocks with etpuecr bit fcss=0, or 1 etpu clock with fcss=1, preventi ng these transitions from being input to the tr ansition detect logic. for fpsck=0 and fcss=0, the synchr onizer and digital filter are guara nteed to pass pulses that are as wide as or wider than four etpu clocks, meaning a mini mum period of 8 etpu cl ocks. these figures are halved by setting fcss=1. by changing the fpsck field in register etpuecr the user can select a lower clock rate for the filter signal to define wider vali d pulses and filter out wide r noise pulses. the filter prescaler clock control is a division of the etpu clock. to guarantee pulse detection by the digital filter, the pulse must cover at least the st ated number of samples at the filt er clock rate. for example, a two sample digital filter must sample tw o points in the pulse to detect it. table 29-19 shows the minimum guaranteed detected pulse width and the maximum filtered noise pulse wi dth. the table refers only to the digital filter operation. the external pulses may have to be wider (to ensure dete ction) or narrower (to ensure filtering) depending on the rise/fall delay differences in the mcu receivers and internal logic.
enhanced time processing unit (etpu2) freescale semiconductor 29-67 pxr40 microcontroller reference manual, rev. 1 delays introduced by synchroni zer, filter and edge detecti on logic are explained in the etpu reference manual . note if the etputbcr field tcrcf selects the filter clock of the channels (see section 29.2.6.1, etputbcr - etpu time base configuration register ), the tcrclk filter will be clocked as if fcss=0, always dividing etpu clock /2 using fpsck, regardless if fcss is 0 or 1. 29.3.5 time bases each etpu engine has two time counter registers, tcr1 and tcr2. they pr ovide 24-bit time bases, shared by all 32 channels. tcr1 can also work at full-speed etpu clock, when etputbcr[tcr1cs]=1 both tcr1 and tcr2 values can be imported from or exported to the stac bus. for information on stac bus protocol and definition of stac modules refer to ipi stac and section 29.3.5.3, stac interface . the tcr2 counters between the two engines are out of phase by 1 etpu clock, even when time bases are shared between them through stac. 29.3.5.1 timer count register 1 - tcr1 tcr1 can be used in the following modes: ? internally clocked mode ? externally clocked mode ? stac bus client mode the host program can read tcr1 ti me base through the etputb1r (see section 29.2.6.2, etputb1r - etpu time base 1 (tcr1) visibility register ). table 29-19. pulse widths and delays filter control (fpsck) filter clock period 1 min. width guaranteed dete cted / max. width filtered (min. filter delay / max. filter delay) 1 1 this table shows pulse widths and delays in number of periods of the etpu clock. fcss = 0 fcss = 1 two-sample or continuous mode three-sample or integrator 2 mode 2 integrator mode is available for tcrclk filtering only, see section 29.3.5.5, t crclk digital filter . not avail. 000 1 2 / 1 (2 / 3) 3 / 2 (3 / 4) 000 001 2 4 / 2 (3 / 3) 6 / 4 (5 / 5) 001 010 4 8 / 4 (5 / 7) 12 / 8 (9 / 11) 010 011 8 16 / 8 (9 / 15) 24 / 16 (17 / 23) 011 100 16 32 / 16 (17 / 31) 48 / 32 (33 / 47) 100 101 32 64 / 32 (33 / 63) 96 / 64 (65 / 95) 101 110 64 128 / 64 (65 / 127) 192 / 128 (129 / 191) 110 111 128 256 / 128 (129 / 255) 384 / 256 (257 / 383) 111 not avail. 256 512 / 256 (257 / 511) 768 / 512 (513 / 767)
enhanced time processing unit (etpu2) 29-68 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the tcr1 bus runs through all the local engine channels 29.3.5.1.1 external ly clocked mode tcr1 can be driven externally by the tcrclk input, after the digital filter. the tcr1 clock source is configured by the tcr1ctl bit, as shown in figure 29-31 . for more information on clock source selection, please refer to section 29.2.6.1, etputbcr - etpu time base configuration register . figure 29-31. tcr1 clock selection 29.3.5.1.2 internally clocked mode tcr1 can be driven by the etpu cl ock or etpu clock divided by 2, be fore the prescaler. tcr1ctl can also be used to freeze tcr1 clock i ndependently of tcr2 (unlike gtbe). 29.3.5.1.3 tcr1 clock prescaling any clock source selected by tcr1 ctl is prescaled by a factor of 1 to 256, selected by etputbcr field tcr1p. for more information on pr escaler configuration refer to section 29.2.6.1, etputbcr - etpu time base configuration register . the tcr1 prescaler resets when et pu_gtbe_in is nega ted. after reset, it starts counting up to tcr1p when etpu_gtbe_in is asserted. when tcr1 increments (etpu_gtbe_in=1), the prescaler starts a new count and the new tcr1 p becomes effective. when tcr1 is written by microcode, the prescaler is reloaded with tcr1p and it becomes effective, if etpu_gtbe_in is asserted. 29.3.5.1.4 stac bus client mode in this mode the tcr1 register is continuously upda ted from the stac bus, and the clock selection and prescaling logic becomes ineffective. it is not writable by the microcode , and when read, it reflects the stac bus imported value. the use of eac is not allowe d in client mode. this m ode is config ured through the register etpuredcr (see section 29.2.6.4, etpuredcr - etpu stac configuration register ). 29.3.5.1.5 stac bus server mode tcr1 bus can be exported to the stac bus as a serv er, providing time informat ion to other peripherals. this mode is configured thr ough the register etpuredcr (see section 29.2.6.4, etpuredcr - etpu stac configuration register ). 29.3.5.2 timer count register 2 - tcr2 the tcr2 is a 24-bit counter which can be used in the following modes: tcr1ctl tcr1 system 10 00 tcrclk prescaler input originated tcr1 prescaler in tcrclk pin, after the filter 1,2,3,..,256 tcr1p 8 red line (stac) bus 11 no clock 0 1 div 2 tcr1cs clock
enhanced time processing unit (etpu2) freescale semiconductor 29-69 pxr40 microcontroller reference manual, rev. 1 ? pin transition mode: count the rise, fall or both transitions of tcrclk signal. ? angle clock mode: count internal tooth angle in combination with the etpu angle counter (eac) hardware which implements an angle p ll, and generates angle information to the channels. this mode is targeted for angle based applications. ? stac bus client mode: tcr2 is dr iven by an external source (see section 29.3.5.2.4, stac bus client modesection , when etpu clock divide d by two is selected, the synchronizer and the digital filter are guaranteed to pass pulses that are wider than four et pu clocks (two filter clocks). otherwise the tcrclk is filtered with the same filter clock as the channel input signals. for details on tcrclk and channels digital filt er control refer to section 29.2.6.1, etputbcr - etpu time base configuration register and section 29.3.4.4, enhanced digital filter - edf. ). ? gated mode: count with rate derived from the etpu clock di vided by eight. the tcrclk signal is used to gate this count, enabling pulse accumulator operations. ? internally clocked modes: tcr2 is driven by intern al clock, with count rate of etpu clock divided by eight. all clock sources pass through a pres caler. in addition, the tcr2 count can be originated from the eac which is a hardware angl e clock and angle counter. figure 29-32 shows the diagram for tcr2 clock control. when tcr2 is not driv en by the eac or stac, the etputbcr field tcr2ctl selects the clock source, also allowing tcr2 to be fr ozen independently of tcr1 (see section 29.2.6.1, etputbcr - etpu time base configuration register ). when in angle mode, tcr2 ctl selects the tcrclk edge sensitivity. figure 29-32. tcr2 clock control the tcrclk signal input is passed through a synchr onizer and a programmable di gital filter. in angle mode with am=01, synchronizer and filter are also used in channel 0, replacing its input synchronizer and filter, to get the same timing in the eac and channel 0. the tcrclk sync hronizer is an improved sync. system clk / 8 etputbcr tcr2 023 tcr2 presc. tcrclk programmable digital filter etputbcr 000 001 010 011 1, 2, . . . , 64 filter clock system clock/2 0 1 6 2 samp integr. 3 etpuecr[fpsck] etputbcr[tcrcf1] gen. filter clock etpu angle angle mode etputbcr[am] 1 0 counter pin [tcr2ctl] 3 [tcr2p] (eac) to channel 0 input on angle mode (am=01) filtered signal for tcr1 clock etputbcr[tcrcf0] 1 0 to all channel filter clocks 111 no clock 100 stac bus
enhanced time processing unit (etpu2) 29-70 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 filter that provides best latency whil e maintaining proper noise filtering (see section 29.2.6.1, etputbcr - etpu time base configuration register field tcrcf[0:1] ? tcrclk signal filter control). the tcr2 bus runs through all the local engine channels the tcr2 value is readable to the host through the etputb2r register (refer to section 29.2.6.3, etputb2r - etpu time base 2 (tcr2) visibility register ). when the tcr2 bus value is imported from the stac bus (stac client mode), tcr2 is not writable by the microcode, and read access from the microcode or from the host re flect the imported tcr2 value. 29.3.5.2.1 tcr2 clock prescaling except in angle mode, any clock sour ce selected by tcr2ctl is prescaled by a factor of 1 to 64, selected by etputbcr field tcr2p. for more information on prescaler configuration refer to section 29.2.6.1, etputbcr - etpu time base configuration register . the tcr2 prescaler rese ts when etpu_gtbe_in is negated. after reset, it starts counting up to tcr2p when etpu_gtbe_in is asserted. when tcr2 increments (etpu_gtbe_in=1), the pr escaler starts a new count and the new tcr2p becomes effective. the counter that divides the etpu clock by 8 before the prescaler also resets when etpu_gtbe_in is negated, or when tcr2 is written by microcode. 29.3.5.2.2 tcr2 gated mode tcr2 gated mode is selected in field tcr2ctl of register etputbcr. in this mode the tcrclk signal enables or disables transfer of the etpu clock divided by 8 to the tcr2 prescaler. by programming the prescaler, tcr2 can run at rates from etpu cl ock divided by eight down to etpu clock divided by 512, in steps of eight etpu clock divisi ons. for more information refer to section 29.2.6.1, etputbcr - etpu time base configuration register . 29.3.5.2.3 tcr2 sign al transition modes these modes are selected when the tcr2ctl field in etp utbcr is set to rise, fall or ?rise-and-fall?. in these modes the tcrclk signal is the tcr2 clock source, and its maximum tr ansition rate depends on the tcrclk digital filter mode of operation. the tcrc lk digital filter can be programmed to use the etpu clock divided by two, or use the same filter clock of the ch annels, controlled by the tcrcf field in etputbcr. it contains an up-down counter which ope rates as a digital integrator, optimizing signal latency in the selected mode and clock rate. when etpu clock divided by two is se lected, the synchronizer and the digital filter are guaranteed to pass pulses that are wider than four etpu clocks (two filt er clocks). otherwise the tcrclk is filtered with the same filter clock as the chan nel input signals. for details on t crclk and channels digital filter control refer to section 29.2.6.1, etputbcr - etpu time base configuration register and section 29.3.4.4, enhanced digital filter - edf . 29.3.5.2.4 stac bus client mode in this mode the tcr2 register is continuously upda ted from the stac bus, and the clock selection and prescaling logic becomes ineffective. it is not write acc essible for the microcode, a nd when read, it reflects
enhanced time processing unit (etpu2) freescale semiconductor 29-71 pxr40 microcontroller reference manual, rev. 1 the stac bus imported value. the use of eac is not allowed in client mode. this mode is configured through the register etpuredcr (see section 29.2.6.4, etpuredcr - etpu stac configuration register ). 29.3.5.2.5 stac bus server mode when tcr2 bus is exported to the stac bus as a serv er, it can provide either ti me or angle bus to other peripherals, according to its operati on mode. this mode is configured through the register etpuredcr (see section 29.2.6.4, etpuredcr - etpu stac configuration register ). to provide sequential update of the stac clients, the angle tick rate must not be faster than the stac programmed update rate. this requirement puts a limitation on the a ngle clock count rate on high rate mode. in this case the angle and angle fraction accumulator (see the etpu reference manual for details) are advanced at rate of etpu clock divided by eight. theref ore, the stac update rate for the angl e bus must not be slower than eight etpu clocks. 29.3.5.2.6 tcr2 bus in angle clock mode in this mode the tcr2 counter ope rates as part of the etpu angle counter (eac). the tcr2 bus value reflects this angle representation in which it count s angle ticks. angle mode is selected when the am bit is set in etputbcr. note that when tcr2 works in a ngle mode, it does not c ount directly from the tcr2 clock input which indicates tooth signal transition. its angle counter is controlled by the count control and high rate logic (see the etpu reference manual for details), which provides the in terpolated pin position, and handle cases of missing tooth, accel eration, de-acceleration a nd mechanical corrections. the eac uses the tcrclk signal to get the toot h transition indications. the tcr2ctl field in etputbcr has to be set for the appropriate tooth edge detection rise, fall, ?rise- and-fall? or none. tcr2 count clock comes from the eac control and not di rectly from the physical tooth. this way the eac control processes the signal trans itions and handles missing teeth and flywheel me chanical corrections. note that when tcr2ctl selects ? none? for tooth edge sele ction, the tcr2 is not necessarily frozen, but can still be incremented by the eac logic. in angle mode, etpu channel 0, 1 or 2 operation is combined with the eac operation. when channel 0 is selected for eac operation, the tc rclk digital filter is used both by the eac and by channel 0 to get full synchronization between the two logics. the etpu angle counter (eac) logic runs c ontinuously and updates the tcr2 angle counter, eliminating the microcode late ncy in updating the tcr2 value. 29.3.5.3 stac interface both time bases tcr1 and tcr2 can be shared betw een the engines and with other blocks in the same mcu. each one of both etpu engines can drive thei r time bases to the stac (shared time and count) bus, acting as a server, while any other block can capt ure the value into its resources and behave like a client. for further reference about the stac bus oper ation refer to section 29.2.6.4, etpuredcr - etpu stac configuration register . the etpu can export to the stac bus or import from the stac bus the follow ing internal resources:
enhanced time processing unit (etpu2) 29-72 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? tcr1: can be exported to or imported from the stac bus. tcr1 can only be imported from stac bus when the engine is not in angle mode. when tcr1 is imported from the stac bus, it becomes read-only for the microcode and reflect s the imported values. for details refer to section 29.3.5.1, timer count register 1 - tcr1 . ? tcr2: can be exported to or imported from th e stac bus. tcr2 can only be imported from the stac bus when engine is not in angle mode. when tcr2 is imported from the stac bus, it becomes read-only for the microcode, and reflect s the imported values. when exported to the stac bus, tcr2 can work in either angle mode or as a free running counter associated with the tcrclk signal. for details refer to the etpu reference manual . proper configuration of the follow ing bits is necessary to determ ine what can drive the stac bus: etputbcr[am] and etpuredcr[ren2, rsc2], according to figure 29-20 . note that angle mode is not availa ble for stac bus clients: configur ing both at the same time brings unspecified results. when tcr2 is a stand-alone counter or a stac bu s server, the same value that is driven to the internal tcr2 bus is also exporte d to the stac bus (eithe r time count or angle). stac bus configuration is provide d by the etpuredcr bits ren1/2 and rsc1/2. ren1/2 enable the stac interface to interact with th e resource (either tcr1 or tcr2 bus). rsc1/2 configure the resource (either tcr1 or tcr2 bus ) as server or client. each time base / angle count resour ce from each engine receives a unique 4-bit hard-wired address that identifies it as a potential server. this address is us ed by the stac controller to coordinate which resource will drive the bus at a given stac time-slot. for any time-slot there is a server driving the bus upon selection of the stac controller, and there may be a client linked to that server by the etpuredcr bits srv1/2 on each engine. when the se rver address on the stac bus matche s the value in srv1/2, the client will load the stac information into the appropriate resource. for information on etpu stac bus configuration refer to section 29.2.6.4, etpuredcr - etpu stac configuration register . the etpu does not include a stac controller modul e, which is instantiated once in the system integration. note setting a timebase as client of itself is not allowed. table 29-20. stac bus and host read sources am (etputbcr) ren2,rsc2 (etpuredcr) tcr2 bus source (host read of etputb2r) stac bus driver 00 0x (disabled) tcr2/time x 01, 10 or 11 0x (disabled) tcr2/angle x 00 11 (server) tcr2/time tcr2/time 01, 10 or 11 11 (server) tcr2/angle tcr2/angle 01, 10 or 11 10 (client) reserved 1 1 stac client configuration in angle mo de is also not allowed for tcr1.
enhanced time processing unit (etpu2) freescale semiconductor 29-73 pxr40 microcontroller reference manual, rev. 1 29.3.5.4 gtbe - global time base enable gtbe bit in etpumcr register en ables time bases in both engines, allowing them to be started synchronously. gtbe is divided in two block inte rface signals: etpu_gtbe_out and etpu_gtbe_in. gtbe bit sets etpu_gtbe_out, and etpu_gtbe_in enables time bases to start. the etpu_gtbe_out signa l can be used for synchronization between etpu ti me bases and time bases from othe r modules. if the gtbe bit in etpumcr must enable only the etpu time bases, etpu_gtbe_out is simply connected to etpu_gtbe_in. these two cases are shown in figure 29-33 . synchronization logic can be as simple as an or or an and logic gate. once etpu_gtbe_in transitions to 1, the engine 1 time bases start 1 etpu clock earlier than time bases in engine 2, except when tcrclk is selected as clock source or tcr1 when etputbcr[tcr1cs]=1. this happens independently of prescal er values as long as they are the same for both engines, because the prescalers also freeze when etpu_gtbe _in = 0. microcode can always write to tcr1/2 registers, with either value of etpu_gtbe_in. note the timebase prescalers are reset when the gtbe input is negated. figure 29-33. time base synchronization 29.3.5.5 tcrclk digital filter the tcrclk signal has an improved integrating digital filte r with a 2-bit up-down counter. the counter counts up to 3 when a high signal level is detected, or down to 0 when a low leve l is detected. the signal state is updated to one when the count er stops at 3, or zero when the counter stops at 0. the field tcrcf in register etputbcr (see section 29.2.6.1, etputbcr - etpu time base configuration register ) determines whether the tcrclk signal input (after a synchroni zer) is filtered with the same filter clock as the channel i nput signals (see section 29.3.4.4, enhanced digital filter - edf ) or uses the etpu clock divided by 2, and also whethe r the tcrclk digital filter works in inte grator mode or the same two sample mode as the channel filters (see table 29-9 ). etpu a and b etpu_gtbe_out tpu_gtbe_in etpumcr[gtbe] emios gtbe_out gtbe_in synchronization be tween etpu time bases and emios time bases
enhanced time processing unit (etpu2) 29-74 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the tcrclk filter delay and prescaling determines the minimum detectable tc rclk pulse widths and, therefore, its maximum fr equency, as shown in section 29.3.4.4.5, filter clock prescaler and table 29-19 . the tcrclk signal delay from th e module input to tcr1/tcr2 increm enting or detection in the eac logic is explained in the etpu reference manual . 29.3.6 safety features this section describes the multiple input signatu re calculator and memory error support features. the multiple input signature calcul ator - misc - is an scm test feature accessible through registers etpumcr and etpumisccmpr (see section 29.2.5, system configuration registers ). misc allows scm test ?on the fly?, i.e., while etpu is running, with no impact on et pu functionality or performance. memory error support features comp rises scm and/or sdm error detect ion, correction, report, and soft error fix. 29.3.6.1 scm test - multiple input signature calculator the multiple input signature calcul ator (misc) comprises special hard ware that sequen tially reads all scm positions and calculates, in pa rallel, a 32-bit signature from a 32- input crc signature calculator with the following polynomial: 1 + x 1 + x 2 + x 22 + x 31 a complete description of the signature calculation proce dure can be found in section 29.4.3, misc algorithm . once started by the host the misc r uns continuously, restar ting after the completion of each cycle, when it sets the etpumcr regi ster flag scmmisc (see section 29.2.5.1, etpumcr - etpu module configuration register ). the average time for a misc calculation can be measured by checking scmmisc state at regular interv als, incrementing a counter and clearing scmmisc if it is set. misc accesses to the scm array are executed if no ne of the engines is accessing the scm, to avoid degradation of the microe ngine performance: it happens while no channel is being se rviced. an ongoing misc operation can be abor ted by writing 0 to scmmisen. the host must load the register etpumisccmpr (see section 29.2.5.3, etpumisccmpr - etpu misc compare register ) with the expected value to be found at the end of the misc cycle, and then start the signature calculation writing bit scmmisen=1 in register etpumcr (see section 29.2.5.1, etpumcr - etpu module configuration register ). misc zeroes the signatu re accumulator and starts reading scm data and calculating th e signature. after last scm position is read, misc compares the value in signature accumulator against the value in etp umisccmpr: if there is a mismatch misc stops, a global exception is issued and the bit scmmisf in register etpumcr assume s value 1. if no mismatch is found, misc repeats the proce dure automatically. when signature is being calculated, scm address starts at the last scm address and counts down to 0. the conditions for executing a misc operation are (see also table 29-16 ): ? both microengines in idle state (no channel is being serviced) or stopped, in any combination (e.g., engine 1 idle with engine 2 stopped). ? etpumcr bit vis = 0.
enhanced time processing unit (etpu2) freescale semiconductor 29-75 pxr40 microcontroller reference manual, rev. 1 ? etpumcr bit scmmisen=1. note that misc can run regardless of scm implementation type (ram or rom). if scmmisen=0 or vis=1, th e misc logic stays at its initial state, with addres s counter pointing to the last scm position and accumulator reset. 29.3.7 performance monitoring features 29.3.7.1 idle counter the idle counter register etpuidler (see section 29.2.7.2, etpuidler - etpu idle register ) continuously counts microcyc les in which the microengine is not busy with channel service. it can be used to measure the microengine utilization by rating the c ount measured during a peri od of time to the number of microcycles contained in the pe riod. the idle counter does not count microcycles when the engine is stopped, or is in tst or halt states.
enhanced time processing unit (etpu2) 29-76 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.4 initialization/application information 29.4.1 multiple parameter coherency methods follows a description of two methods for coherent transfer of multip le parameters between host and etpu. both methods involve the use of two parameter ar eas: the transfer paramete r area (hereafter called tpa), which is the sdm area directly accessed by th e host for reads and writes, and the permanent parameter area (hereafter called ppa), which are th e sdm positions where channel parameters are normally accessed by the functi on microcode. note that pa rameters in either tpa or ppa do not have to be in sequential addresses. tpas and ppas allocati on are completely defined by the application, and there may be any number of them, i ndependently of the channels. the methods described here are not the only solutions for the coherent transfer problem, and both can coexist in etpu and even used in combination. also note that for transfers of a pair of parameters, the coherent dual-parameter controller is faster and have less impact on both etpu and host performance. that said, the methods are: ? transfer service : a microengine thread tran sfers, upon host service request, da ta from/to a tpa to/from a ppa.coherency is guaranteed by the fact that a thread is atomic with respect to other threads in the same engine, and so are its transfers. if parameters in ppa are shared by both engines, hardware semaphores have to be used to access them. ? mailbox : for host to etpu transfers, the microcode checks a flag, set by the host, indicating the existence of new parameter data in the tpa. it can , then, either access tpa data directly or copy it to the ppa. for etpu to host tr ansfers, when microcode changes pp a, it copies them to the tpa and flags updated tpa data to host, possibly using an interrupt or a data transfer request. the mailbox flag is reset when data is copied: by the etpu microcode, when it transfers tpa to ppa (possibly followed by an in terrupt); by the host, when it reads data from the tpa. this indicates that tpa is free for another transfer. transfer service has the advantage of separating the task of data transfer from the functional service thread that accesses the parameters, with less impact to the latt er. compared to the mailbox method, however, it has bigger average latency, because th e transfer service thread has to c ontend for a time slot to execute. this latency can be minimized if tr ansfer service thread is assigned to a separate channel with higher priority, but even so it does not guarantee that ppa is updated before the next execution of the functional thread that uses it. mailbox method, on the other hand, makes the functional thread check for th e existence of new data (host to etpu). it does not have to be responsible for the transfer, though: it may access the tpa directly, and a transfer service can then be used to copy data from tpa to ppa. 29.4.2 estimating worst case latency reliable systems are designe d to work under worst-case conditions. this section explains how to estimate worst-case latency (wcl) for any etpu function in a ny system. the appendix covers the following topics: ? introduction to worst-case latency ? using worst-case latency estima tes to evaluate performance
enhanced time processing unit (etpu2) freescale semiconductor 29-77 pxr40 microcontroller reference manual, rev. 1 ? priority scheme details used in wcl analyses ? first-pass wcl analysis ? second-pass wcl analysis the first-pass wcl analysis is base d on a deterministic, generalized form ula that is easy to apply. because of the generalizations in the formula, the first analysis result is almost always much worse than the real worst case. if the desired system performance is with in the limits of this firs t analysis, then no further analysis is required; the system is well within the performance limits of the etpu. if the desired system performance exceeds that i ndicated by the first analysis, the second -pass wcl analysis should be applied. the second-pass analysis is not a generalized formula, but rather uses specific system details for a realistic worst-case estimation. 29.4.2.1 introduction to worst-case latency note in this appendix the latency calcula tion and examples refer to old tpu functions such as pwm, dio etc. these functions use single action channels which have single transition and single match functionality. they are not optimized for the etpu ha rdware enhancement which support various double action modes. these ex amples are for reference only. new etpu functions which are optimized for the new hardware will impose different latency calculations. worst-case latency for a channel is the longest amount of time that can elapse between the execution of any two function threads on that channel. for example, if in a particular system, channel 5 is running pwm, the worst-case latency for channel 5 is the l ongest possible time between the execution of two pwm threads. the worst case time includes the time the ex ecution unit takes to execute threads for other active channels, and other delays describe d later in this section. refer to figure 29-34 . figure 29-34. worst-case latency for pwm worst-case latency for a channel depends both on the function running on that channel and on the activity on other channels. since the 32 etpu channels must all share the same executi on unit, execution speed of additional channel threads and other delays. worst case latency for channel 5 pwm thread executed for channel 5 next pwm thread executed for channel 5
enhanced time processing unit (etpu2) 29-78 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 a particular function varies with each system. the pw m thread response is fast er if there are no other active channels than if other channels are also active. in addition, changing the priority scheme and channel number assignments can cha nge performance for a function even if the same set of functions are still active. each function is divided into treads, as shown in figure 29-35 (see also the etpu reference manual for details). the etpu microengine execu tes one thread of a function at a time. for example, the microengine might execute thread 1 of pwm, then thread 3 of dio, then thread 2 of pwm, then thread 2 of sm, and so on. the amount of time the etpu microengine grants a function to ex ecute a thread varies with the number of microcode instructions in the thread. since there is only one etpu microe ngine (in each etpu engine), the etpu cannot actually execute the software for multiple functions si multaneously. however, the hardware for each of the channels is independent. this means that, for ex ample, all 32 channel signals can ch ange thread at the same moment, provided that the function software sets up the channel hardware to do so beforehand. with host cpu code, the system desi gner assigns functions to channels and initializes the functions. after initialization, functions typically r un without host intervention, except for etpu channel interrupts to the host to give or receive informati on. most functions can run continuously with periodic servicing from the etpu microengine. as required, the channels request service from th e etpu microengine, and the etpu scheduler determines the order in which the channels are serviced. worst-case latency for a channel can be derived from the details of the priori ty scheme that the scheduler uses (see section 29.3.3, scheduler ). figure 29-35. function threads 29.4.2.2 using worst-case latency estimates to evaluate performance once wcl is found for a channel, the user must determ ine how to use this number to analyze performance. to analyze the performance of a channel running the pwm function, for ex ample, some information about what happens in each thread is necessary. dio function threads pwm function threads sm function threads s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4
enhanced time processing unit (etpu2) freescale semiconductor 29-79 pxr40 microcontroller reference manual, rev. 1 the following example refers to old tpu pwm functio n, which is not optimized to the etpu enhanced hardware. for pwm, thread 1 is the initialization thread, and thr eads 2 and 3 are used during normal function execution. (pwm threads 4, 5, and 6 are for special modes and will be assumed to be unused on channel 5). thread 2 writes a time into the channel 5 match register and performs other operations that will cause the channel 5 signal to go from low to high at the time indicated in the matc h register (match time). at match time, the signal goe s high and channel 5 reques ts service from the etpu microengine to execute thread 3. thread 3 writes a time into the channel 5 match register and performs other ope rations that will cause the channel 5 signal to go fro m high to low at match time. at match time, the signal goes low and channel 5 requests service from the etpu microengine to execute thread 2. a pwm wave is kept running on the system by the etpu executing thread 2, then th read 3, then thread 2, then thread 3, and so on. since the definition of worse-case la tency assumes a fully loaded running system, initialization threads are not part of worst-case calculations. for th e channel 5 example, the two pwm threads in figure 29-34 are thus the two normal running threads, threads 2 and 3. figure 29-34 does not define which th read is thread 2 and which is thr ead 3. since the worst-case latency derived from the first-pass analysis is the worst case between any2 th reads (not counting initialization threads), it is safe to say that the worst-case latency shown in figure 29-35 represents both the worst-case high time and the worst-case low time. notice in figure 29-34 that worst-case latency is drawn from the end of th e execution of the first pwm thread to the end of the execution of the next pwm thread. it is drawn from end to end because the microcode instructions that make up the threads control the channel hard ware. to make sure that all the microcode instructions needed to ch ange the pin thread have been executed, it is necessary to include the execution time of the second thread. thread information for each function is found in the programming notes for individual tpu functions. refer to freescale programming note tpupn00/d, using the tpu function li brary and tpu emulation mode, for a list of available pr ogramming notes. similar documentation will we provided for the etpu new functions. 29.4.2.3 priority scheme deta ils used in wcl analysis the user assigns functions to ch annel numbers and gives each active channel a priority level of high, middle, or low. the scheduler uses the channel number and channel prio rity level to determine the order in which to grant service. the scheduler allocates time slots to specific priority levels of high, mi ddle, or low. one function thread is executed in each time slot. the length of a time slot varies acco rding to the length of the executing thread. when fully loaded, the scheduler always a ssigns time slots in a seven-slot sequence (see figure 29-36 ). after a seven-slot sequence is complete d, another seven-slot sequence begins (see figure 29-37 ). note that in etpu, when no service request exists, the scheduler goe s to thread 1, but wcl calculation considers full load.
enhanced time processing unit (etpu2) 29-80 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 29-36. time-slot sequence this sequence scheme gives higher-pr iority channels more service time than lower-priority channels. high-priority channels are allocated four of seven time slots, middle-pr iority channels are allocated two of seven time slots, and low-priority chan nels are allocated one of seven time slots. figure 29-37. multiple time-slot sequences 29.4.2.3.1 priority passing if no channel of the priority level assigned to the time slot is requesting servi ce, the etpu scheduler can pass priority to other leve ls. if no high-level channel is requesting service during a high level time slot, a middle-level channel is granted service; or, if no mi ddle level-channel is reques ting service, a low-level channel is granted se rvice. if no middle-level cha nnel is requesting service duri ng a middle-level time slot, a high-level channel is granted service; or, if no hi gh-level channel is request ing service, a low-level channel is granted service. if no low-level channel is requesting service during a low-level time slot, a high-level channel is granted servi ce; or, if no high-level channel is requesting service, a middle-level channel is granted service. if no channel is requesting serv ice, the time slot sequenc e is reset to state 1 and the scheduler idles until a request is received. priority passing is implemented in hardware and does not contribute to worst-case latency. 29.4.2.3.2 time-slot transition after each time slot, the etpu must prepare for the next time slot. this prep aration time between each time slot is called a ti me-slot transition. see the etpu reference manual for details. time-slot transitions can take from six up to ten etpu clocks. h m h l h m h time slot transitions (10 cpu clock cycle each) time slots of varying lengths h m h l h m h new 7-slot sequence h m h l h m h h m h new 7-slot new 7-slot sequence sequence
enhanced time processing unit (etpu2) freescale semiconductor 29-81 pxr40 microcontroller reference manual, rev. 1 29.4.2.3.3 channel number priority if more than one channel of a priority level is reque sting service, the lowest numbered channel is granted service first. for example, if ch annels 0, 5, and 9 are all high-level channels requesting service during a high time slot, channel 0 is granted service first. c ontinuing this example, if channel 0 requests service again immediately after being service d, it is not serviced again until ch annels 5 and 9 ar e serviced. this scheme is implemented so that c ontinuously-requesting low numbered channels do not take all the time on the etpu execution unit and leave no time for other channels. the scheduler uses registers to keep track of whic h channels have been serviced and which require servicing. each channel has two regist er bit: a service request register (srr) and a service grant register (sgr). the srr is set when a channel requests servic e. after the channel has been granted service, the sgr is set and the srr is cleared. sgrs are not cleared indivi dually by channel, but rath er as priority level gr oups. the clearing of a group of sgrs begins a new cycle for that priority level. an sgr group is cleared on the conditi on that a channel of that priority level has just been serviced, and no ot her channel of that priority level is requesting service (has a set srr) and has not been granted service (has a clear sgr). for example, if a middle-priority cha nnel has just been serviced (either in a middle-priority time slot or a high or low-priority time slot gained by priority passing), the srrs and sgrs of all middle-priority channels are compared. if there is no middle-priori ty channel with its srr set and sgr cleared, the scheduler clears all middle-level sgrs. if there is a middle-level channel with its srr set and sgr cleared, the scheduler does not clear the sgr group, a nd the requesting middle-level channel is serviced on the next middle-level time slot (o r possibly sooner by priority passing). 29.4.2.3.4 sdm collision rate most function threads read or write to the etpu sd m at least once. because both the etpu microengine and host can access the sdm but not at the same time, the microengine may suspend execution during the sdm access while waiting for th e host to finish accessing the sdm. at other times the host may wait for the microengine. wait states can take up to two etpu clocks, when the host accesses the sdm directly, without using cdc. microengi ne(s) wait-states must be added into the worst-case latenc y calculation. the system designer should estimate th e percentage of sdm accesses in th e system that will result in microengine wait-states. this percen tage is called the ram collision rate (rcr). in each collision with direct host accesses to the sdm the mi croengine(s) wait for two etpu clocks. in etpu the coherent dual-paramet er controller (cdc) may also acce ss the sdm for atomic transfers of two parameters. etpu microengine may wait on this operation (if it is in service time) until the transfer is complete. cdc always transfers tw o parameters, making four consec utive accesses (read, write, read, write) of one etpu clock each. th e system designer should estimate th e percentage of sdm accesses in the system that will result in a mi croengine wait due to coherent transf er, and multiply it with the average number of etpu clocks the microengine waits for each transfer. this percenta ge is called coherent parameter collision rate (cpcr). in addition, microengine to microe ngine multiple parameter coherent communication, using the hardware semaphores, may hold one microengine which waits to lock the semaphore while the other microengine is holding it. this waiting is due to a software loop, not hardware wait-s tates. note that single parameter access of one microengine does not af fect the timing of the other microe ngine due to sdm time interlace.
enhanced time processing unit (etpu2) 29-82 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 this implies that single paramete r microengine to microengine co mmunication does not affect the performance. the microengine which waits for the se maphore will loop until it is freed by the other microengine. this time depends on the etpu appl ication. the system desi gner should estimate the percentage of microengine to micr oengine coherent parameter communi cation that will result in etpu semaphore loops, and multiply it with the average num ber of etpu clocks the mi croengine loops for each such transfer. this percentage is cal led ccr (communication collision rate). a 100% collision rate for a system is the theoreti cal worst case. in many systems, however, the rcr, cpcr and ccr would be very low, sometimes even near 0%. this is because the etpu is an independent processor capable of servicing most function needs, so that the host rarely needs to access the etpu sdm. also coherent microengine to micr oengine communication of more than one parameter may be rare. to find a realistic rcr, cpcr the system designer should ev aluate the host code and find the percentage of time it accesses the etpu sdm with or without us ing the cdc. this percentage gives a good rcr and cpcr. the etpu application pr ovides a good estimation of ccr. note the programming practice of polling a flag in the etpu sdm causes a very high rcr and should be avoide d in high-performance systems. after the collision rate for a system is found, it can be applied to the wcl calculations fo r each channel. the system designer can use the co llision percentage and the number of sdm accesses (with and without semaphores) to estimate the etpu loop time for a function. note that in old tpu functions cpcr and ccr are both zero. the estimation of etpu wait time is as follows: variables: n1 = number of simple ram accesses in the longest thread rcrwait = maximal etpu clocks wait time for simple ram collision = 2 cpcrwait = average etpu clocks for cohe rent parameter transfer (using cdc). n2 = number of etpu-etpu semaphore ram accesses in the longest thread ccrwait = average etpu clocks for microe ngine-microengine communication transfer. estimated wait time: function etpu maximal wait time = n1 *(rcr * rcrwait + cpcr * cpcrwait) + n2* ccr * ccrwait 29.4.2.4 first-pass wors t-case latency analysis following is the first-pass calculation of worst-case la tency for a channel. remember that this analysis uses generalizations that usually produce a result much worse than the real worst case. if the worst-case result from the first analysis is too long for the de sired performance, use the second analysis for a more realistic worst-case analysis.
enhanced time processing unit (etpu2) freescale semiconductor 29-83 pxr40 microcontroller reference manual, rev. 1 29.4.2.4.1 worst-case assumptions and formula to estimate worst-case latency for a channel, assume this worst-case condition: the channel has just been serviced in a time slot of its priority level, and a ll other channels in the syst em are continuously requesting service and have cleared sgrs. the worst-case latency is the time from the end of the channel?s service until the end of the channel?s next service. see figure 29-38 . figure 29-38. first-pass worst-case latency to estimate worst-case latency: ? find the worst-case service time for each active channel. ? using the h-m-h-l-h-m-h time-slot sequence, map the channels that are granted for each time slot. ? add time for six-clock time-slot transitions. finding the worst-case service time for each active channel a table for etpu functions should li st the longest threads (not counti ng initialization threads) for the functions, and the number of etpu sdm accesses in the longest thread (semaphored and non semaphored). these figures will be used for estimati ng microengine wait time. table 29-21 is an example for old tpu functions in which there are only simple sdm accesses. it does not take into consideration the cdc operation and microengine to microengine communication. the worst-case service time for each channel is: (cpcr=ccr=0) longest thread + ((number of ram ac cesses in longest thread+1) * rcr * 2 clocks). note that the formula adds 1 ram accesses for th e parameter preload that occurs during tst. there are actually three accesses during tst, but only the first one can receive wait-states. table 29-21. longest threads and ram accesses for old tpu functions function longest thread ram accesses dio 10 4 itc 40 (no linking) 42 (linking) 7 oc 40 7 pwm 24 4 channel x serviced worst case latency channel x other channels serviced channel x serviced next
enhanced time processing unit (etpu2) 29-84 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 mapping the channels for each time slot to determine when a channel will be serviced again, it is necessary to determine which othe r channels will be serviced first. do this by assuming all channels are continuously requesting service and mapping the channels into the time-slot sequence. adding time for ti me-slot transitions add six etpu clocks for time-slot transi tions which occur after each time slot. 29.4.2.4.2 first-pass analysis worst-case latency examples the examples in this section assume the system configuration shown in table 29-22 . spwm mode 0 mode1 mode 2 14 18 20 (no linking) 22 (linking 4 4 4 4 pma 94 8 pmm 94 8 psp angle-angle mode angle-time mode 76 50 6 3 sm 1 160 21 ppwa mode 0 mode 1 mode 2 mode 3 44 50 2 44 50 9 10 9 10 1 assumes one master and one slave. for each additional slave a) add 32 clocks and 2 ram accesses, and b) add (step_rate_cnt ? two clocks) 2 with one channel linked. add two clocks for each additional channel linked. table 29-22. system configuration example channel priority function 1 , 2 1 9% ram collision rate (rcr) 2 cpu clock rate = 40 mhz, or 25 ns per clock period 0 high pwm (driving a dc motor) 1 middle ppwa (mode 0, measuring the dc motor speed) 2 low dio (input) table 29-21. longest threads and ram accesses for old tpu functions (continued) function longest thread ram accesses
enhanced time processing unit (etpu2) freescale semiconductor 29-85 pxr40 microcontroller reference manual, rev. 1 finding the wcl for pwm on channel 0 the following shows how to find the wcl for pwm on channel 0. 1. find the worst-case service time for each active channel. a. longest thread of pwm is 24 cp u clocks with four ram accesses. 24 + ((4 ram accesses+1) * 0.09 * 2 cpu cloc k waits) = 24.9 cpu clocks, rounded up to 25 cpu clocks (since there ar e no partial clock periods) channel 0 worst-case service time = 25 cpu clocks. b. longest thread of ppwa in mode 0 is 44 cpu clocks with nine ram accesses. 44 + ((9 ram accesses+1) * 0.09 * 2 cpu cloc k waits) = 45.8 cpu clocks, rounded up to 46 cpu clocks channel 1 worst-case service time = 46 cpu clocks. c. longest thread of dio is ten cpu clocks with four ram accesses. 10 + ((4 ram accesses+1) * 0.09 * 2 cpu cloc k waits) = 10.9 cpu clocks, rounded up to 11 cpu clocks channel 2 worst-case service time = 11 cpu clocks. 2. assume channel 0 has just been serviced and that channels 1 and 2 are continuously requesting service. using the h-m-h-l-h-m-h time-slot seque nce, map the channels that are granted for each time slot. see figure 29-39 . figure 29-39. next servicing for channel 0 channel 1 will be serviced in the middle-priority time slot before channel 0 is serviced again. 3. add time for the six-clock cpu time-slot transitions. see figure 29-39 and table 29-23 . a four-clock nop occurs after each channel is serv iced since there is one channel in each priority level, i.e., a new cycle for a priority level is started after each channel is serviced. time-slot transitions occur afte r each time slot. tpu ch0 wcl tim tpu ch0 wcl tim channel 0 serviced worst case latency channel 0 h m h l h m h h channel 1 serviced channel 0 serviced = 10-cycle time slot transition = 4-cycle nop instruction
enhanced time processing unit (etpu2) 29-86 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 83 clocks * 25 ns/clock = 2075 ns conclusion: in this system configuration pwm can run with a minimum high time or low time of 2075 ns. note that in double match etpu sy stem the pwm can be serviced once in each period, and there is no latency for minimum high time. the latency in etpu pwm function will represent the minimum pwm period. finding the wcl for ppwa on channel 1 the following shows how to find the wcl for ppwa on channel 1. 1. find the worst-case service time for each activ e channel. see step 1 of previous example. 2. assume channel 1 has just been serviced and that channels 0 and 2 are continuously requesting service. using the h-m-h-l-h-m-h time-slot seque nce, map the channels that are granted for each time slot. see figure 29-40 . figure 29-40. next servicing for channel 1 channel 0 will be serviced twice and channe l 2 once before channel 1 is serviced again. 3. add time for the six-clock cpu time-slot transitions. see figure 29-40 and table 29-24 . 131 clocks * 25 ns/clock = 3275 ns conclusion: in this system configuration ppw a can measure a period or pulse of minimum 3275 ns. table 29-23. worst-case latency for channel 0 channel 0 worst-case service time 25 clocks channel 1 worst-case service time 46 clocks two 6-clock time-slot transitions 12 clocks total clocks 83 clocks table 29-24. worst case latency for channel 1 two channel 0 worst-case service times 50 clocks channel 1 worst-case service time 46 clocks channel 2 worst-case service time 11 clocks four 6-clock time-slot transitions 24 clocks total clocks 131 clocks tpu ch1 wcl tim tpu ch1 wcl tim channel serviced worst case latency channel 1 h m h l h m h h channel 0 serviced channel 2 serviced = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced channel 1 serviced
enhanced time processing unit (etpu2) freescale semiconductor 29-87 pxr40 microcontroller reference manual, rev. 1 note that ppwa function optimized for etpu hardware can use doubl e transition mode to measure very narrow pulses with one service after the s econd transition, and late ncy will affect only the minimum gap between two input pulses. also th e function threads would have more efficient coding. finding the wcl for dio on channel 2 the following shows how to find the wcl for dio on channel 2. 1. find the worst-case service time for each activ e channel. see step 1 of previous examples. 2. assume channel 2 has just been serviced and that channels 0 and 1 are continuously requesting service. using the h-m-h-l-h-m-h time-slot seque nce, map the channels that are granted for each time slot. see figure 29-41 . figure 29-41. next servicing for channel 2 channel 0 will be serviced four times and cha nnel 1 twice before channe l 2 is serviced again. 3. add time for the ten-clock cpu time-slot transitions and the f our-clock nops. see figure 29-41 and table 29-25 . 245 clocks * 25 ns/clock = 6125 ns conclusion: in this system conf iguration dio can keep track of the input level at a minimum of every 6125 ns. note that dio function optimized for etpu hard ware can use double transi tion mode to measure two pin transitions at a time and reduce the servic e time, improving the overa ll system performance and latency. table 29-25. worst case latency for channel 2 four channel 0 worst-case service times 100 clocks two channel 1 worst-case service time 92 clocks channel 2 worst-case service time 11 clocks seven 6-clock time-slot transitions 42 clocks total clocks 245 clocks tpu ch2 wcl tim tpu ch2 wcl tim channel 2 serviced worst case latency channel 2 h m h l h m h h channel 0 serviced channel 1 serviced = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced channel 0 serviced m h l h channel 1 serviced channel 0 serviced channel 2 serviced
enhanced time processing unit (etpu2) 29-88 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 29.4.2.5 second-pass worst-case latency analysis following is an example of a second-pass analysis for calculating worst-case la tency for a channel. the second-pass analysis is useful for hi gher-performance systems, since it gives a more rea listic worst-case latency result than first-pass analysis. this example uses a relatively simple system in or der to illustrate the basic principles of second-pass analysis. for a more complex exam ple of second-pass analysis, refer to multiphase motor commutation tpu function (co mm)(tpupn09/ d). 29.4.2.5.1 second-pass analysis guidelines rather than use a fixed formula, a second-pass an alysis relies on the appl ication of the following guidelines. 1. the first-pass analysis makes the assumption that all channels in the system are continually requesting service. for many systems this is an unrealistic assumption. for example, if tcr1 is counting at a rate of 2 mhz (500 ns per count) and a channel is running the dio function with a match rate of 20,000 tcr1 counts, the dio will request service every 10 ms (20,000 * 500 ns = 10,000,000 ns or 10 ms). it is therefore unrealisti c to assume that the channel running this dio function is continuously requesti ng service. figure out a realisti c service request rate for each channel. time slots can then be mapped to each channel at the real rate of request. 2. if a function is active during system initializa tion but not during the high-speed running mode of the system, then that system does not need to be included in the high- speed worst-case latency calculations. 3. use a realistic sdm collision rate. 4. be careful when assigning func tions priority levels and channe l numbers. decide which function or functions will be most difficul t to make perform at the desired level. assign thos e channels high priority and low channel numbers. try different priority and channel assignments to see how it affects the system. 5. the seven-slot sequence of || h | m | h | l | h | m | h || is asymmetrical when put back-to-back with other seven-slot sequences. note that in the fo llowing sequence there are two high-priority slots next to each other: || h | m | h | l | h | m | h |||| h | m | h | l | h | m | h || 6. make sure that when mapping out channels to th e sequence, you choose a worst-case slot to start the mapping. for example, when estimating wcl for a high-priori ty channel, do not start the mapping in the last high-priority slot in a seven-slot sequence, as that is a best case for a high-priority channel since another high-priority time slot is next. 7. instead of always using the longest thread in th e function as the worst-case thread, evaluate the threads in the function that will be used in the system and use th e appropriate worst-case threads. for example, in the preceding example of first-pa ss analysis, the pwm was shown to be able to achieve a high time and lo w time of 2475 ns under worst-case conditions. th is was derived using the longest pwm thread of 24 cpu cl ocks. this longest thre ad is actually thread 2, the thread that
enhanced time processing unit (etpu2) freescale semiconductor 29-89 pxr40 microcontroller reference manual, rev. 1 is entered after the pin has just gone high. thread 3, the thread that is entered after the pin has just gone low, requires only 2 cpu clocks. therefore, in the first-pass example, the high time was correctly derived, but the low time is actually shorter than was estimated. 29.4.2.5.2 second-pass analysis example this example requires three 50% pwm waveforms: one 5 khz (200 ms/period) and two 50 khz (20 ms/period), each running dc motors. (remember that the pwm function requests service from the etpu after each high time and after each low time, so th e etpu must handle a request every 100 ms for the 5 khz pwm and every 10 ms for the 50 mhz pwm.) note this example uses square waves for simplicity. notice that to use a pwm waveform in the typical way, in wh ich the pulse is modulated, the pulse must not be modulated in a way that violates the worst-case latency requirements. this example also uses one dio channel monito ring a signal level every millisecond and one ppwa channel in mode 0 monitoring the speed of the 5-khz dc motor. th e ppwa must measure periods of 5 khz (200 ms/period). the cpu is interrupted by the channel running the ppwa function after measur ing 200 periods (every 40 ms). the interrupt service routine performs an averaging of the period accumulation and checks it against a known parameter. the interrupt serv ice time is so short a nd infrequent that it is a tiny fraction of total system time. the interrupt service routine contains no polling of the sd m. therefore a realistic rcr = 0%. first-try system configuration try a system configuration that seems likely to wo rk. if it does not, change priority levels or channel numbers. the 5 khz and 50 khz pwms are the mo st time-critical functions. thos e are assigned high priority. ppwa is assigned middle priority. the dio is low perf ormance and is assigned low priority. refer to table 29-26 . with this system configuration, wors t-case service time for each active channel is determined as follows: a. longest thread of pwm is 24 cp u clocks with four ram accesses. 24 + ((4 ram accesses+1) * 0 * 2 cpu clock waits) = 24 cpu clocks table 29-26. first-try system configuration channel priority function 1 , 2 1 0% ram collision rate 2 cpu clock rate = 40 mhz, or 60 ns per clock period 0 high pwm at 50 khz (needs a 4- ? s wcl) 1 high pwm at 50 khz (needs a 4- ? s wcl) 2 high pwm at 5 khz (needs a 40- ? s wcl) 8 middle ppwa at 5 khz (needs a 80- ? s wcl) 15 low dio as input at rate of 1 ms
enhanced time processing unit (etpu2) 29-90 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 channels 0-2 worst-case serv ice time = 24 cpu clocks. b. longest thread of ppwa in mode 0 is 44 cpu clocks with nine ram accesses. 44 + ((9 ram accesses +1)* 0 * 2 cpu clock waits) = 44 cpu clocks channel 8 worst-case service time = 44 cpu clocks. c. longest thread of dio is ten cpu clocks with four ram accesses. 10 + ((4 ram accesses+1) * 0 * 2 cpu clock waits) = 10 cpu clocks channel 15 worst-case service time = 10 cpu clocks. to find the wcl for channel 0, assume channel 0 has just finished service. map the channels in the h-m-h-l-h-m-h sequence. see figure 29-42 . figure 29-42. worst-case latency for channel 0 (first try) conclusion: with this system configuration, worst-case latencie s for channels 0 and 1 are too high (wcl for channel 1 is the same as wc l for channel 0). try a different system configuration. tpu ch0 wcl tim 1 tpu ch0 wcl tim 1 = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced worst case latency h m h l h m h h channel 8 serviced channel 1 serviced channel 15 serviced channel 2 serviced m h l channel 0 serviced
enhanced time processing unit (etpu2) freescale semiconductor 29-91 pxr40 microcontroller reference manual, rev. 1 second-try system configuration the second-try system conf iguration is shown in table 29-27 . to find the wcl for channel 0, assume channel 0 has just finished service. map the channels in the h-m-h-l-h-m-h sequence. see figure 29-43 . figure 29-43. worst-case latency for channel 0 (second try) conclusion: with this system c onfiguration, the wcl of both channel 0 and channel 1 is 3.85 ms, which is within the limit of 4 ms needed for a 50-khz pwm. next, find the wcl for channel 2. assume channel 2 has just finished service. map the channels in the h-m-h-l-h-m-h sequence. see figure 29-44 . figure 29-44. worst-case latency for channel 2 conclusion: with this syst em configuration, the wcl fo r channels 2 and 8 is 4.7 ms, which is within the 40 and 80 ms wcl requirements. table 29-27. second-try system configuration channel priority function 1 , 2 1 0% ram collision rate 2 cpu clock rate = 40 mhz, or 60 ns per clock period 0 high pwm at 50 khz (needs a 4- ? s wcl) 1 high pwm at 50 khz (needs a 4- ? s wcl) 2 middle pwm at 5 khz (needs a 40- ? s wcl) 8 middle ppwa at 5 khz (needs a 80- ? s wcl) 15 low dio as input at rate of 1 ms tpu ch0 wcl tim 2 tpu ch0 wcl tim 2 = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced worst case latency h m h l h m h h channel 2 or channel serviced channel 1 serviced channel 15 serviced channel 0 serviced m h l tpu ch2 wcl tim 1 tpu ch2 wcl tim 1 = 10-cycle time slot transition = 4-cycle nop instruction channel 2 serviced worst case latency h m h l h m h h channel 0 serviced channel 15 serviced channel 1 serviced channel 8 serviced m h l channel 2 serviced
enhanced time processing unit (etpu2) 29-92 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 notice that channels 2 and 8 are well within their wcl requirements. the system could be reconfigured as shown in table 29-28 to give channels 0 and 1 a larger marg in while still keepi ng channels 2, 8 and 15 within their wcl requirements. 29.4.3 misc algorithm the misc generator is based on the following polynomial: g(x) = 1 + x 1 + x 2 + x 22 + x 31 (equivalent to feedback mask = 0x80400007) the misc signature generation star ts by clearing the misc accumulato r value to 0 and preloading the misc counter with the highest scm address. it then steps through each address decrementing the counter, reading 32 bit values and following the algorithm below: if the least significant bit in misc is 1 then misc = misc right shifted by 1 bit misc = misc xor 0x80400007 else misc = misc right shifted by 1 bit end if misc = misc xor ram data the code example below shows an excer pt of c code that calculates th e misc signature for a given array of data, based on the previous algorithm: #define scm_size (max_scm_address / 4) /* last byte address - converted to 32-bit word */ #define poly 0x80400007 /* g(x) = 1 + x 1 + x 2 + x 22 + x 31 */ /******************************************************************************* function : void calc_misc() purpose : this function calculates the misc value. inputs notes : none returns notes : misc value general notes : the array ?unsigned int data[]? represents the actual memory array, organized in 32-bit words. *******************************************************************************/ unsigned int calc_misc (void) table 29-28. second-try system with channel 0 and 1 reconfigured channel priority function 1 , 2 1 0% ram collision rate 2 cpu clock rate = 40 mhz, or 60 ns per clock period 0 high pwm at 50 khz (needs a 10- ? s wcl) 1 high pwm at 50 khz (needs a 10- ? s wcl) 2 middle pwm at 5 khz (needs a 40- ? s wcl) 8 low ppwa at 5 khz (needs a 80- ? s wcl) 15 low dio as input at rate of 1 ms
enhanced time processing unit (etpu2) freescale semiconductor 29-93 pxr40 microcontroller reference manual, rev. 1 { int j; /* loop counter */ unsigned int misc = 0; for (j = (scm_size-1); j >= 0 ; j--) { /* scm_size has the number of 32-bit words in scm */ if (misc & 0x1) { misc >>= 1; misc ^= poly; } else { misc >>= 1; } misc ^= data[j]; /* data[j] is the actual 32-bit word taken from the scm array */ } return (misc); /* final signature calculated */ }; the value calculated by this algorithm must be load ed into register etpumis ccmpr prior to activating the scm misc calculator in etpu. once the misc calculator is activat ed (bit scmmisen in register etpumcr is written to 1) etpu itself will start this procedure 1 reading the scm whenever allowed by microengine. at the end of the cycle, when all the arra y has been read and the sc m signature is calculated, the host cpu can be notified via global exception if the misc accumulator does not match the value in etpumisccmpr. the average time taken by misc to complete the sign ature of the whole scm can be given by the formula: average misc period = s / (4 * f * (1 - l)) where f is clock frequency, s is scm size in bytes and l is etpu load (as a percentage of execution clocks over a period of time, including tst clocks). further detail on misc calculation can be found on section 29.3.6.1, scm test - multiple input signature calculator . the application note an2192 - detecting errors in the dual port ram (dptram) module is also a good source of information (alt hough it refers to tpu) on misc signature. 1. etpu misc hardware is optimized to read 32-bit words from memory and to calculate this crc in parallel, rather than shifting one bit at a time. the actual im plementation inside etpu, although bringing to the same results, does not match exactly the algorithm shown here.
enhanced time processing unit (etpu2) 29-94 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 30-1 pxr40 microcontroller reference manual, rev. 1 chapter 30 external bus interface (ebi) 30.1 introduction 30.1.1 overview the external bus interface (ebi) handles the transfer of information between the internal buses and the memories or peripherals in the external address space. the ebi includes a memory controller that generates interface signals to support a variety of ex ternal memories. this includes single data rate (sdr) burst mode flash, sram , and asynchronous memories. it supports up to 4 regions (via chip selects), each with its own programmed attributes (plus 4 calibration chip-select regions). 30.1.2 features ? 22-bit address bus with transfer size indication ? 16-bit data bus (32-bit data bus in muxed mode) ? multiplexed address on da ta pins (single master) ? memory controller with sup port for various memory types: ? synchronous burst sdr flash and sram ? asynchronous/legacy flash and sram ? burst support (wrapped only) ? bus monitor ? port size configuration per chip select (16 or 32 bits) ? configurable wait states ? configurable internal or extern al transfer acknowledge (d_ta ) per chip select ? support for dynamic calibrati on with up to 4 chip-selects ? four write/byte enable (d_we [0:3]) signals ? slower-speed clock modes ? stop and module disable modes for power savings ? optional automatic d_clkout gati ng to save power and reduce emi ? misaligned access support (for chip-select accesses only) ? compatible with mpc5xx external bus (with some limitations)
external bus interface (ebi) 30-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.1.3 signal naming generic signal names like addr and data have been replaced with signal names accord ing to the table below. refer to the signals chapter for th e full signal names a nd muxing information ( table 30-1 lists the function partial-signal name). 30.1.4 modes of operation the mode of the ebi is determined by the mdis , extm, and ad_mux bits in the ebi_mcr. see section 30.3.1.1, ebi module configur ation register (ebi_mcr) for details. slower-speed modes, debug mode, stop mode, and factory test mode are mode s that the mcu may enter, in parallel to the ebi being configured in one of its block-specific modes. 30.1.4.1 single master mode in single master mode, the ebi res ponds to internal reques ts matching one of its regions, but ignores all externally-initiated bus requests. the mcu is the onl y master allowed to initiate transactions on the external bus in this mode; therefore, it acts as a parked master and doe s not have to arbitrate for the bus before starting each cycle. the br , bg and bb signals are not used by the ebi in this mode, and are table 30-1. device-specific signal naming generic signal name equivalent chip-level signal name 1 1 this pin function may not be the pins primary functi on, refer to the signals chapter for muxing information. i/o type function addr d_add[9:30] i/o address bus bdip d_bdip output burst data in progress clkout d_clkout 2 2 the d_clkout signal is driven by the system clock block outside the ebi. output clockout cs d_cs [0:3] 3 3 most of this chapter refers to cs pins (especially diagrams), but the behavior is identical for the cal_cs pins (described in section 30.4.2.10, calibration bus operation ). only cal_cs (d_cs at chip-level) is implemented on this device. ? ? cal_cs output calibration chip selects data d_add_dat[0:15] (through muxing d_add_dat[16:31] are available) i/o data bus 4 4 in address/data multiplexing modes, data will also show the address during the address phase. oe d_oe output output enable rd_wr d_rd_wr i/o read_write ta d_ta i/o transfer acknowledge tea d_tea i/o transfer error acknowledge ts d_ts i/o transfer start we /be d_we[ 0:3] output write/byte enables ale d_ale output address latch enable
external bus interface (ebi) freescale semiconductor 30-3 pxr40 microcontroller reference manual, rev. 1 available for use in an alternate function by another block of the mc u. single master mode is entered when extm=0 and mdis=0 in the ebi_mcr. 30.1.4.2 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the ebi can be stopped while in module disable m ode. logic on the mcu external to the ebi is needed to fully implement the module disable mode (to shut off the clock). internal master requests made to the external bus in module disable mode are termin ated with transfer error (internally, no external d_tea assertion). module disable mode is entered when mdis=1 in the ebi_mcr. 30.1.4.3 stop mode the ebi supports the siu halt mode mechanism used for mcu power management. when a request is made to enter stop mode (controlled in device logic outside ebi), th e ebi block completes any pending bus transactions and acknowledges the stop request. af ter the acknowledgement, the system clock input may be shut off by the cloc k driver on the mcu. while the clocks are shut off, the ebi is not accessible. while in stop mode, accesses to the ebi from the inte rnal master will terminate with transfer error (internally, no external d_tea assertion). 30.1.4.4 slower-speed modes in slower-speed modes, the extern al d_clkout frequency is divided (by 2, 3, etc. ) compared with that of the internal system bus. the ebi behavior remains dictated by the mode of the ebi, except that it drives and samples signals at the d_clkout frequency rather than the internal system frequency. this mode is selected by writing a clock control regi ster in a block outside of the ebi. 30.1.4.5 16-bit data bus mode for mcus that have only 16 data bus signals pinned out, or for systems where the use of a different multiplexed function (e.g. gpio) is desired on 16 of the 32 da ta pins, the ebi suppor ts a 16-bit data bus mode. in this mode, only 16 data signals are used by the ebi. the user can sele ct which 16 data signals are used (d_add_dat[0:15] or d_add_dat[16: 31]) by writing the d16_31 bit in the ebi_mcr. for ebi-mastered accesses, the operation in 16-bit data bus mode (dbm=1, ps=x) is similar to a chip-select access to a 16-bit port in 32-bit data bus mode (dbm=0, ps=1), except for the case of a non-chip-select access of exactly 32-bit size. ebi-mastered non-chip-select accesses of exactly 32-bit size are supported via a two (16-bit) beat burst for both reads and writes. see section 30.4.2.9, non-chip-select bu rst in 16-bit data bus mode . non-chip-select transfers of non-32-bit size are supported in standard non-burst fashion. 16-bit data bus mode is entere d when dbm=1 in the ebi_mcr.
external bus interface (ebi) 30-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.1.4.6 multiplexed address on data bus mode this mode covers several cases aimed at reducing pin count on mcu and external components. in this mode, the d_add_dat pins will drive (for internal ma ster cycles) the address va lue on the first clock of the cycle (while d_ts is asserted). the memory controller supports per-chip-select se lection of multiplexing address/data through the brx[ad_mux] bit. address on data bus multiplexing also supports th e 16-bit data bus mode (mcr[dbm]=1) and 16-bit memories (orx[ps]=1). the user can select whic h 16 data signals are us ed (d_add_dat[0:15] or d_add_dat[16:31]) by writing the d16_31 bit in the ebi_mcr. for either setting of d16_31, the 16 lsbs of external address (d_add[16:31]) are dr iven onto the selected 16 d_add_dat pins. if additional address lines are require d to interface to the memory, then non-muxed address pins are sometimes (see note below) required to complete the address space (e.g. d_ add[8:15] are commonly present as non-muxed address pins). note the ebi also drives the unused 16 d_add_dat signals with the msbs of the external address, zero-padded in fr ont (e.g. when d16_31 bit is set for a device with 24 d_add pins, the ebi drives (0b00000000, d_add[8:15]) on d_add_dat[0:15]. this allows the device to optionally use d_add_dat[8:15] for the upper 8 exte rnal address lines instead of requiring separate non-m uxed d_add[8:15] pins. this is relevant primarily for devices that suppor t both 32-bit and 16-bit a/d muxed operation, so therefore have d_add_dat [0:31] pins present on the device, and in that case are not required to have separate d_add pins. for more details (e.g. timing diagrams), see section 30.4.2.12, address data multiplexing . the address latch enable (ale) indicates when the address is present during a multiplexed bus access using a d_add_dat signal. this can be used in conjun ction with an external latch to hold the state of the address access if connecting the mcu to a non- multiplexed bus compatible memory. ale signal timing is shown in figure 30-1 . figure 30-1. ale signal timing f periph a/d t alehigh clkout ale ts addr data t alenegatedtoaddrinvalid
external bus interface (ebi) freescale semiconductor 30-5 pxr40 microcontroller reference manual, rev. 1 there are at least two timing requireme nts that relate to external com ponents for multiplexed addr/data bus in systems using ale. these ar e not ebi specs. the two are ? ale - minimum high time ? ale negated to addr invalid these values depend on maximum clkout frequency and the actual clock tree in sertion on the ale clock gate. typical values should be calculated (and specified) as: t alehigh = f(clkout) / 2 -1ns (rise/fall uncertainty) t aletoaddrinvalid = 1-3ns (depending on sp ecified external part). 30.1.4.7 debug mode when the mcu is in debug mode, the ebi behavior is unaffected and remains dictated by the mode of the ebi. 30.2 external signal description 30.2.1 overview table 30-2 lists the external pins used by the ebi. not all signals listed here are av ailable external to the chip. refer to table 30-1 and the signals chapter for device-sp ecific signal naming and availability. table 30-2. signal properties name i/o type function pull 1 1 this column shows which signals requi re a weak pullup or pulldown. the ebi block does not contain these pullup/pulldown devices within the block. they are assumed to be in another module of the mcu (e.g. pads module). d_add[9:30] i/o address bus - d_bdip output burst data in progress up d_clkout 2 2 the d_clkout signal is driven by the system clock block outside the ebi. output clockout - cal_cs [0:3] output calibration chip selects up d_add_dat[0:31] i/o data bus 3 3 in address/data multiplexing modes, data w ill also show the address during the address phase. - d_oe output output enable up d_rd_wr i/o read_write up d_ta i/o transfer acknowledge up d_tea i/o transfer error acknowledge up d_ts i/o transfer start up d_we [0:3] output write/byte enables up
external bus interface (ebi) 30-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.2.2 address/data bus configurations table 30-3 shows the function of the external pins in each of the possibl e muxed/non-muxed usage configurations allowed for this device. 30.2.3 detailed signal descriptions 30.2.3.1 d_add [9:30] ? address lines 9-30 the d_add[9:30] signals specify the phys ical address of th e bus transaction. the 22 address lines correspond to bits 3-31 of the ebi?s 32-bit internal address bus. 30.2.3.2 d_bdip ? burst data in progress d_bdip is asserted to indicate that the master is requ esting another data beat following the current one. this signal is driven by the ebi on all ebi-mastered external burst cycles, but is only sampled by burst mode memories that have a corresponding pin. see section 30.4.2.5, burst transfer . 30.2.3.3 d_clkout ? clockout d_clkout is a general-purpose cloc k output signal to connect to th e clock input of sdr external memories and in some cases to the input clock of another mcu in multi- master configurations. 30.2.3.4 cal_cs [0:3] ? calibration chip selects 0-3 cal_cs x is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the calibration external bus. the calibration chip selects are driven only by the eb i. external master acce sses on the cali bration bus are not supported. in all other aspects, the calibra tion chip-selects behave exactly as the primary chip-selects. see section 30.4.1.4, memory controller with support for various memory types for details on chip-select operation. table 30-3. function of ebi pins for all possible configurations mode d_we [0:3] d_add[9:15] d_add[16:30] 1 d_add_dat[16:30] 2 1 d_add[16:30] siu pcr functionality must be selected in non-multiplexed mode (ad_mux = 0) 2 d_add_dat[16:30] siu pcr functionality must be selected in multiplexed mode (ad_mux = 1) d_add_dat [0:15] d_cs2 3 3 d_cs2 is the primary function. secondary function is ebi data only in non-mux mode and address/data in mux mode. non-muxed 16-bit mode write/byte enable [0:1] address 9:15 address 16:30 data 0:15 address 31 muxed 32-bit mode write/byte enable [0:3] not used address 16:30 / data 16:30 address 0:15 / data 0:15 address 31 / data 31 muxed 16-bit mode (ebi_mcr[d16_31]=1) write/byte enable [0:1] address 9:15 address 16:30 / data 0:14 not used address 31 / data 15 muxed 16-bit mode (ebi_mcr[d16_31]=0) write/byte enable [0:1] address 9:15 not used address 16:31 / data 0:15 not used
external bus interface (ebi) freescale semiconductor 30-7 pxr40 microcontroller reference manual, rev. 1 30.2.3.5 d_add_dat [0:31] ? data lines 0-31 the d_add_dat[0:31] signals contain the data to be transferred for the current transaction. d_add_dat[0:31] is driven by the ebi when it owns the external bus and it initiates a write transaction to an external device. d_add_dat[0:31] is driven by an external devi ce during a read trans action from the ebi. for 8-bit and 16-bit transactions, th e byte lanes not selected for the transfer do not supply valid data. d_add_dat[0:31] is driven by the ebi in the addr ess phase with the d_add value if the address on data multiplexing mode is enabled. see section 30.1.4.6, multiplexed a ddress on data bus mode , for details. in 16-bit data bus mode, (or for chip-select a ccesses to a 16-bit port), only d_add_dat[0:15] or d_add_dat[16:31] are used by the ebi, depending on the setting of the d16_31 bit in the ebi_mcr. see section 30.1.4.5, 16-bit data bus mode . 30.2.3.6 d_oe ? output enable d_oe is used to indicate when an external memory is permitted to drive back read data. external memories must have their data output buffers off when d_oe is negated. d_oe is only asserted for chip-select accesses. for read cycles, d_oe is asserted one clock after d_ts assertion and held until the termination of the transfer. for write cycles, d_oe is negated throughout the cycle. 30.2.3.7 d_rd_wr ? read / write d_rd_wr indicates whether the current transact ion is a read access or a write access. d_rd_wr is driven in the same cl ock as the asse rtion of d_ts and valid address, a nd is kept valid until the cycle is terminated. 30.2.3.8 d_ta ? transfer acknowledge d_ta is asserted to indicate that the slave has receiv ed the data (and completed the access) for a write cycle, or returned data for a read cycle. if the transaction is a burst read, d_ta is asserted for each one of the transaction beats. for write transactions, d_ta is only asserted once at access comple tion, even if more than one write data beat is transferred. d_ta is driven by the ebi when the access is contro lled by the chip selects (and seta=0). otherwise, d_ta is driven by the slave device to wh ich the current transaction was addressed. see section 30.4.2.8, termination signals protocol for more details. 30.2.3.9 d_tea ? transfer error acknowledge d_tea is asserted by either th e ebi or an external devi ce to indicate that an er ror condition has occurred during the bus cycle.
external bus interface (ebi) 30-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 d_tea is asserted by the ebi when the intern al bus monitor detect ed a timeout error. see section 30.4.2.8, termination signals protocol for more details. 30.2.3.10 d_ts ? transfer start d_ts is asserted by the current bus owner to indicate the start of a transaction on the external bus. d_ts is only asserted for the first clock cycle of the transaction, and is negated in the successive clock cycles until the end of the transaction. 30.2.3.11 d_we [0:3] ? write/byte enables 0-3 write enables are used to enable pr ogram operations to a par ticular memory. these signa ls can also be used as byte enables for read and write operation by setting the webs bit in the appropriate base register. d_we [0:3] are only asserted for chip-select accesses. for chip-select accesses to a 16-bit port, only d_we [0:1] are used by the ebi, re gardless of which half of the d_add_dat bus is selected via the d16_31 bit in the ebi_mcr. see section 30.4.1.11, four write/byte enable (d_we) signals for more details on d_we [0:3] functionality. 30.2.4 signal output buff er enable logic by mode table 30-4 describes how the ebi drives it s output buffer enable (obe) signa ls. these are internal signals from the ebi to device logic outsid e the ebi, that determine when the ebi strongly drives values on pins. when the obe for an ebi signal is asserted (1), th e ebi strongly drives the value on that pin. when the obe is negated (0), the ebi does not drive the signal, and the value is determined by internal or external pullups/pulldowns, and/or devi ce logic outside ebi block. table 30-4. signal output buffer enable logic by mode 1 signal obe value by mode (1=strongly driven, 0=not driven by ebi) module disable mode 2 (mdis=1) single master mode (mdis=0) d_add[9:30] 0 1 d_bdip 0 1 cal_cs [0:3] 0 1 d_add_dat[0:31] 0 only 1 during write access or on address phase when addr/data muxing is enabled. d_oe 01 d_rd_wr 01
external bus interface (ebi) freescale semiconductor 30-9 pxr40 microcontroller reference manual, rev. 1 30.3 memory map/register definition table 30-5 shows the ebi registers. d_ta 0 only 1 during chip-select (or cal-chip-select) seta=0 access d_tea 0 only 1 for 2 cycles when timeout occurs d_ts 01 d_we [0:3] 0 1 1 the values in this table only indicate when signals are strongly driven, not the logic value on the pin itself. 2 this assumes that the clock to the ebi is shut off when mdis=1. this is an optional device feature. if the clocks are left running to ebi even when mdis=1, then the ebi obe behavior is as if in single master mode (though ebi ac cesses are not supported in this scenario). table 30-5. ebi address map address register bits access reset value section/page ebi_base ebi_mcr?ebi module configuration register 32 r/w 0x0000_0000 30.3.1.1/30-10 ebi_base+0x4 reserved ebi_base+0x8 ebi_tesr?ebi trans fer error status register 32 r 0x0000_0000 30.3.1.2/30-11 ebi_base+0xc ebi_bmcr?ebi bus monitor control register 32 r/w 0x0000_ff80 30.3.1.3/30-12 ebi_base+0x10 ? ebi_base+0x3c reserved ebi_base+0x40 ebi_cal_br0?ebi ca libration base register bank 0 32 r/w 0x2000_0002 30.3.1.4/30-13 ebi_base+0x44 ebi_cal_or0?ebi ca libration option register bank 0 32 r/w 0xe000_0000 30.3.1.5/30-15 ebi_base+0x48 ebi_cal_br1?ebi ca libration base register bank 1 32 r/w 0x2000_0002 30.3.1.4/30-13 ebi_base+0x4c ebi_cal_or1?ebi ca libration option register bank 1 32 r/w 0xe000_0000 30.3.1.5/30-15 ebi_base+0x50 ebi_cal_br2?ebi ca libration base register bank 2 32 r/w 0x2000_0002 30.3.1.4/30-13 ebi_base+0x54 ebi_cal_or2?ebi ca libration option register bank 2 32 r/w 0xe000_0000 30.3.1.5/30-15 ebi_base+0x58 ebi_cal_br3?ebi ca libration base register bank 3 32 r/w 0x2000_0002 30.3.1.4/30-13 ebi_base+0x5c ebi_cal_or3?ebi ca libration option register bank 3 32 r/w 0xe000_0000 30.3.1.5/30-15 table 30-4. signal output buffer enable logic by mode 1 (continued) signal obe value by mode (1=strongly driven, 0=not driven by ebi) module disable mode 2 (mdis=1) single master mode (mdis=0)
external bus interface (ebi) 30-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.3.1 register descriptions note other than the bits in the tesr regist er, ebi registers must not be written while a transaction to the ebi (from inte rnal master) is in progress (or within 2 d_clkout cycles after a transact ion has just completed, to allow internal state machines to go idle) . in those cases, the behavior is undefined. see section 30.5.1, booting from external memory for related application information. 30.3.1.1 ebi module configuration register (ebi_mcr) the ebi module configuration register contains bits which configure va rious attributes associated with ebi operation. offset: ebi_base+0 access: user read/write 0 12345678910111213 14 15 r0 000000000000 0 0 0 w reset: 0 000000000000 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r acge 00010000 mdis 000 d16_31 ad_mux dbm w reset: 0 000100000000 0 0 0 figure 30-2. ebi module configuration register (ebi_mcr) table 30-6. ebi_mcr field descriptions field description 0-15 reserved 16 acge automatic d_clkout gating enable the acge bit enables the ebi feature of turning off d_clkout (holding it high) during idle periods in-between external bus accesses. 0 automatic d_clkout gating is disabled 1 automatic d_clkout gating is enabled 17-24 reserved
external bus interface (ebi) freescale semiconductor 30-11 pxr40 microcontroller reference manual, rev. 1 30.3.1.2 ebi transfer error status register (ebi_tesr) the ebi transfer error status register contains a bit for each type of transfer erro r on the external bus. a bit set to logic 1 indicates what type of transfer error occurred since th e last time the bits were cleared. each bit can be cleared by reset or by writing a 1 to it. writing a 0 has no effect. this register cannot be written when the mdis bit is set in the ebi_mcr. 25 mdis module disable mode the mdis bit controls an internal ebi "enable clk" signal which can be used (if mcu logic supports) to control the clocks to the ebi. the mdis bit allows the clock to be st opped to the non-memory mapped logic in the ebi, effectively putting the ebi in a software controll ed power-saving state. see section 29.1. 4.3, ?module disable mode for more information. no external bus accesses can be performed when the ebi is in module disable mode (mdis=1). 0 module disable mode is inactive (assert "enable clk" signal) 1 module disable mode is active (negate "enable clk" signal) 26-28 reserved 29 d16_31 data bus 16_31 select the d16_31 bit controls whether the ebi uses the d_a dd_dat[0:15] or d_add_dat[16:31] signals, when in 16-bit data bus mode (dbm=1) or for chip-select accesses to a 16-bit port (ps=1). for systems using a/d muxing with a 16-bit port, it is recommended to set d16_31 to 1. 0 d_add_dat[0:15] signals are used for 16-bit port accesses 1 d_add_dat[16:31] signals are used for 16-bit port accesses 30 ad_mux address on data bus multiplexing mode the ad_mux bit controls whether non-ch ip-select accesses have the address driven on the data bus in the address phase of a cycle. 0 only data on data pins for non-cs accesses. 1 address on data multiplexing mode is used for non-cs accesses. 31 dbm data bus mode the dbm bit controls whether the ebi is in 32-bit or 16-bit data bus mode. 0 32-bit data bus mode is used 1 16-bit data bus mode is used offset: ebi_base+0x8 access: user read 0123456789101112131415 r 000000000000000 0 w reset: 0 0 0000000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000000teafbmtf w reset: 0 0 0000000000000 0 figure 30-3. ebi transfer error status register (ebi_tesr) table 30-6. ebi_mcr field descriptions (continued) field description
external bus interface (ebi) 30-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.3.1.3 ebi bus monitor c ontrol register (ebi_bmcr) the ebi bus monitor control register controls the ti meout period of the bus monitor and whether it is enabled or disabled. table 30-7. ebi_tesr field descriptions field description 0-29 reserved 30 teaf transfer error acknowledge flag this bit is set if the cycle was termin ated by an externally generated d_tea signal. 0 no error 1 external d_tea occurred 31 bmtf bus monitor timeout flag this bit is set if the cycle was te rminated by a bus monitor timeout. 0 no error 1 bus monitor timeout occurred offset: ebi_base+0xc access: user read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bmt bme 0000000 w reset: 1 1 11111110000000 figure 30-4. ebi bus monitor control register (ebi_bmcr) table 30-8. ebi_bmcr descriptions field description 0-15 reserved 16?23 bmt bus monitor timing this field defines the timeout period, in 8 external bus clock resolution, for the bus monitor. see section 30.4.1.6, bus monitor , for more details on bus monitor operation. timeout period = (2 + (8 * bmt)) / external bus clock frequency.
external bus interface (ebi) freescale semiconductor 30-13 pxr40 microcontroller reference manual, rev. 1 30.3.1.4 ebi base regi sters (ebi_cal_br0-3) the ebi base registers are used to define the base address and ot her attributes for the corresponding chip select. 24 bme bus monitor enable this bit controls whether the bus moni tor is enabled for internal to exter nal bus cycles. the bme bit is ignored (treated as 0) for chip-select accesses with internal d_ta (seta=0). 0 disable bus monitor 1 enable bus monitor (for external d_ta accesses only) 25?31 reserved offset: ebi_base+0x40, 0x48, 0x50, 0x58 access: user read/write 0123456789101112131415 r ba 1 w reset: 0010000000 0 0 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ba 000 ps 000 ad_ mux bl webs tbdip 0 seta bi v w reset: 0000000000 0 0 0010 1 ba[0:2] is fixed as 0b001 figure 30-5. ebi base registers (ebi_cal_br0-3) table 30-9. ebi_cal_br0-3 descriptions field description 0-16 ba base address these bits are compared to the corresponding unmaske d address signals among d_add[0:16] of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master. 17?19 reserved table 30-8. ebi_bmcr descriptions (continued) field description
external bus interface (ebi) 30-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 20 ps port size the ps bit determines the data bus width of transactions to this chip-select bank. note: in the case where the dbm bit in ebi_mcr is set for 16 -bit data bus mode, the ps bit value is ignored and is always treated as a?1? (16-bit port). 0 32-bit port 1 16-bit port 21?23 reserved 24 ad_mux address on data bus multiplexing the ad_mux bit controls whether accesses for this chip select have the address driven on the data bus in the address phase of a cycle. 0 address on data multiplexing mode is disabled for this chip select. 1 address on data multiplexing mode is enabled for this chip select. 25 bl burst length the bl bit determines the amount of data transferred in a bu rst for this chip select, measured in 32-bit words. the number of beats in a burst is automatically determined by th e ebi to be 4, 8, or 16 according to the port size (ps bit) so that the burst fetches the num ber of words chosen by bl (see table 29-10). for internal amba data bus width of 32-bits, the bl bit is ignored (treated as 1). note: the ebi does not support a 2-word external burst leng th. this means that neither a 4-beat burst to a 16-bit external memory (nor a 2-beat burst to 32-bit external memory) are supported. 26 webs write enable / byte select this bit controls the functionality of the d_we [0:3] signals. 0 the d_we [0:3] signals function as we [0:3] 1 the d_we [0:3] signals function as be [0:3] 27 tbdip toggle burst data in progress this bit determines how long the d_bdip signal is asserted for each data beat in a burst cycle. see section 30.4.2.5.1, tbdip effect on burst transfer , for details. 0 assert d_bdip throughout the burst cycle, regardless of wait state configuration. 1 only assert d_bdip (bscy+1) external cycles before expecting subsequent burst data beats. 28 reserved table 30-9. ebi_cal_br0-3 descriptions (continued) field description value burst length 1 1 total amount of data fetched in a burst transfer. ps # beats in burst 2 2 number of external data beats used in external burst transfer. the size of each beat is determined by ps value. 0 3 3 an 8-word burst length is only supporte d for device?s using 64-bit amba data bus width to ebi. 8-word 4 4 a word always refers to 32-bi ts of data, regardless of ps. 0 (32-bit) 8 1 (16-bit) 16 14-word 0 (32-bit) 4 1 (16-bit) 8
external bus interface (ebi) freescale semiconductor 30-15 pxr40 microcontroller reference manual, rev. 1 30.3.1.5 ebi option regi sters (ebi_cal_or0-3) the ebi option registers are used to define the a ddress mask and other attr ibutes for the corresponding chip select. 29 seta select external transfer acknowledge the seta bit controls whether accesses for this chip sele ct will terminate (end transfer without error) based on externally asserted d_ta or internally asserted d_ta . seta should only be set when the bi bit is 1 as well, since burst accesses with seta=1 are not supported. setting seta=1 c auses the bi bit to be ignored (treated as 1, burst inhibited). 0 transfer acknowledge (d_ta) is an output from the ebi, data ph ase will be terminated by the ebi. 1 transfer acknowledge (d_ta ) is an input to the ebi, data phase will be terminated by an external device. 30 bi burst inhibit this bit determines whether or not burst read accesses are allowed for this chip-select bank. the bi bit is ignored (treated as 1) for chip-select accesses with external d_ta (seta=1). 0 enable burst accesses for this bank. 1 disable burst accesses for this bank. this is the default value out of reset (or when seta=1). 31 v valid bit the user writes this bit to indicate th at the contents of this base register and option register pair are valid. the appropriate cs signal does not assert unless the corresponding v-bit is set. 0 this bank is not valid. 1 this bank is valid. offset: ebi_base+0x44, 0x4c, 0x54, 0x5c access: user read/write 0123456789101112131415 r am 1 w reset:1110000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r am 0000000 scy 0 bscy 0 w reset:0000000000000000 1 am[0:2] is set to a fixed value of 0b111. figure 30-6. ebi option registers (ebi_cal_or0-3) table 30-9. ebi_cal_br0-3 descriptions (continued) field description
external bus interface (ebi) 30-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.4 functional description 30.4.1 external bus interface features 30.4.1.1 address bus (up to 22 available on pins) . valid transaction sizes are 8, 16 and 32 bits. only 22 address lines are pinned out externally, but a full 32-bit decode is done internally to determine the target of the transaction and whet her a chip select should be asserted. table 30-10. ebi_cal_or0-3 descriptions field description 0-16 am address mask this field allows masking of any corresponding bits in the associated base register. masking the address independently allows external devices of different size address ranges to be used. any clear bit masks the corresponding address bit. any set bit causes the corresponding address bit to be used in comparison with the address pins. address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. this fi eld can be read or written at any time. note: an mcu may have some of the upper bits of the am field ti ed to a fixed value internally in order to restrict the address range of the ebi fo r that mcu. see the corresponding note for the base register ba field for more details. 17?23 reserved 24?27 scy cycle length in clocks this field represents the number of wa it states (external cycles ) inserted after the addre ss phase in the single transfer case, or in the first beat of a burst, when the me mory controller handles the external memory access. values range from 0 to 15. this is the main parameter for determi ning the length of the cycle. these bits are ignored when seta=1. the total cycle length for the first beat (including the d_ts cycle) = (2+scy) external clock cycles. see section section 30.5.3.1, example wait state calculation , for related application information. 28 reserved 29?30 bscy burst beats length in clocks this field determines the number of wait states (external cycl es) inserted in all burst beats except the first, when the memory controller starts handling the external memory a ccess and thus is using scy[0:3] to determine the length of the first beat. these bits are ignored when seta=1. the total memory access length for each beat is (1 + bscy) external clock cycles. the total cycle length (including the d_ts cycle) = (2+scy) + (#beats 1 -1) * (bscy+1). 1 #beats is the number of beats (4,8,16) determined by bl and ps bits in base register. 31 reserved value meaning 00 0-clock cycle wait states (1 clock per data beat) 01 1-clock cycle wait states (2 clocks per data beat) 10 2-clock cycle wait states (3 clocks per data beat) 11 3-clock cycle wait states (4 clocks per data beat)
external bus interface (ebi) freescale semiconductor 30-17 pxr40 microcontroller reference manual, rev. 1 30.4.1.2 32-bit data bus (16-bit data bus mode also supported) the entire 32-bit data bus is available (through muxing) for external memory accesses. there is also a 16-bit data bus mode available vi a the dbm bit in ebi_mcr. see section 30.1.4.5, 16-bit data bus mode . 30.4.1.3 multiplexed address on da ta pins (internal master only) when this mode is enabled, the address shows up on th e data pins during the addr ess phase of the cycle. this mode can be enabled separately for non-ch ip-select accesses and per chip-select access. see section 30.1.4.6, multiplexed address on data bus mode . 30.4.1.4 memory controller with su pport for various memory types the ebi contains a memory controller that supports a variety of memory types, including synchronous burst mode flash and sram, and as ynchronous/legacy flash and sram with a compatible interface. each cs bank is configured via its own pair of base and option registers. each time an internal to external bus cycle access is requested, the internal address is compared with the base address of each valid base register (with 17 bits having mask). see figure 30-7 . if a match is found, the at tributes defined for this bank in its br and or are used to control the memory access. if a match is f ound in more than one bank, the lowest bank matched handles the memory access (e.g., bank 0 is selected over bank 1). a match on a valid calibration chip-s elect register overrides a match on any non-calibration chip-select register, with cal_cs0 having the highest priority. thus the full priority of the chip-selects is: cal_cs0,...,cal_cs3,cs0,...,cs3 figure 30-7. bank base address & match structure when a match is found on one of the chip-select banks, all its attributes (from the appropriate base and option registers) are selected for the functional ope ration of the external memory access, such as: ba [0] comp ba [1] comp ba [2] comp ba [3] comp ba [4] comp ? ? ? ba [15] comp ba [16] comp am [0] am [1] am [2] am [3] am [4] am [5] ? ? ? am [6] am [16] ? ? ? a[0:16] am[0:16] match address mask base address ? ? ?
external bus interface (ebi) 30-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? number of wait states for a single memory access, and for any beat in a burst access ? burst enable ? port size for the external accessed device see section 30.3.1.4, ebi base registers (ebi_cal_br0-3) and section 30.3.1.5, ebi option registers (ebi_cal_or0-3) for a full description of all chip-select attributes. when no match is found on any of the chip-select ba nks, the default transfer attributes shown in table 30-11 are used. 30.4.1.5 burst support (wrapped only) the ebi supports burst read accesses of external burstable memory. to enable bursts to a particular memory region, clear the bi (burst i nhibit) bit in the appropriate base register. external burst lengths of 4 and 8 words are supported. burst length is configured for each chip select by using the bl bit in the appropriate base register. see section 30.4.2.5, burst transfer for more details on burst operation. in 16-bit data bus mode (dbm=1 in ebi_mcr), a sp ecial 2-beat burst case is supported for reads and writes for 32-bit non-chip-sel ect accesses only. this is to allow 32-b it coherent accesses to another mcu. see section 30.4.2.9, non-chip-select bu rst in 16-bit data bus mode . bursting of accesses th at are not controlled by th e chip selects is not supporte d for any other case besides the special case of 32-bit acce sses in 16-bit data bus mode. burst writes are not supported for a ny other case besides the special ca se of 32-bit non-ch ip-select writes in 16-bit data bus mode. internal re quests to write >32 bits (such as a cache line) externally are broken up into separate 32-bit or 16-bi t external transactions acco rding to the port size. see section 30.4.2.6, small accesses (small port size and short burst length) for more detail on these cases. 30.4.1.6 bus monitor when enabled (via the bme bit in the ebi_bmcr), the bus monitor detects when no d_ta assertion is received within a maximum time out period for external d_ta accesses. the timeout for the bus monitor is specified by the bmt field in the ebi_bmcr. each time a timeout erro r occurs, the bmtf bit is set in the ebi_tesr. the timeout period is measured in external bus (d_cl kout) cycles. thus the effective table 30-11. default attributes for non-chip-select transfers cs attribute default value comment ps 0 32-bit port size bl 0 burst length is don?t ca re since burst is disabled webs 0 write enables tbdip 0 don?t care since burst is disabled bi 1 burst inhibited scy 0 don?t care since external d_ta is used bscy 0 don?t care since external d_ta is used ad_mux 0 address on data multiplexing (depends on ebi_mcr[ad_mux] value) seta 1 select external d_ta to terminate access
external bus interface (ebi) freescale semiconductor 30-19 pxr40 microcontroller reference manual, rev. 1 real-time period is multiplied (by 2, 3, etc.) when a slower-speed mode is used, even though the bmt field itself is unchanged. 30.4.1.7 port size configuration pe r chip select (16 or 32 bits) the ebi supports memories with data widths of 16 or 32 bits. the port size for a partic ular chip select is configured by writing the ps bit in the corresponding base register. 30.4.1.8 configurable wait states from 0 to 15 wait states can be programmed for any cy cle that the memory controller generates, via the scy bits in the appropriate opti on register. from 0 to 3 wait st ates between burst beats can be programmed using the bscy bits in the appropriate option register. 30.4.1.9 configurable internal or external d_ta per chip select each chip select can be configured (via the seta bit) to have d_ta driven internally (by the ebi), or externally (by an ex ternal device). see section 30.3.1.4, ebi base registers (ebi_cal_br0-3) , for more details on seta bit usage. 30.4.1.10 support for dynamic calibration with up to 4 chip-selects the ebi contains 4 calibra tion chip select signals, controlling 4 i ndependent memory banks on the external calibration bus. see section 30.4.2.10, calibration bus operation , for more details on using the calibration bus. 30.4.1.11 four write/byte enable (d_we ) signals the functionality of the d_we [0:3] signals depends on the value of the webs bit in the corresponding base register. setting webs to 1 configures these pins as be [0:3], while resetting it to 0 configures them as we [0:3]. we [0:3] are asserted only dur ing write accesses, while be [0:3] is asserted for both read and write accesses. the timing of the d_we [0:3] signals remains the same in either case. the upper write/byte enable (d_we0 ) indicates that the upper eight bits of the data bus (d_add_dat[0:7]) contain valid da ta during a write/read cycle. the upper middle write/byte enable (d_we1 ) indicates that the upper middl e eight bits of the data bus (d_add_dat[8:15]) contain valid data during a write/read cycle. the lower middle write/byte enable (d_we2 ) indicates that the lower middle eight bits of the data bus (d_add_dat[16:23]) contai n valid data during a write/read cycle. the lower write/byte enable (d_we3 ) indicates that the lower ei ght bits of the data bus (d_add_dat[24:31]) contain valid data during a write/read cycle.
external bus interface (ebi) 30-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the exception to the preceding d_we description is that for 16-bit port transfers (dbm=1 or ps=1), only the d_we [0:1] signals are used, regardless of whether d_add_dat [0:15] or d_add_dat[16:31] are selected (via the d16_31 bit in the ebi_mcr). this means for the case where d_add_dat[16:31] are selected, that we0 indicates that d_add_dat[16:23] contains valid data, and we1 indicates that d_add_dat[24:31] contains valid data. the write/byte enable lines affected in a transact ion for a 32-bit port (ps = 0) and a 16-bit port (ps=1) are shown in table 30-12 . only big endian byte or dering is supported by the ebi. 30.4.1.12 slower-speed clock modes for memories that cannot run with a full-speed external bus, the ebi supports slower-speed clock modes. refer to section 30.1.4.4, slower-speed modes for more details on this feat ure. the timing diagrams for slower-speed modes are identical to those for full-s peed mode, except that the frequency of d_clkout is reduced. 30.4.1.13 stop and module disable modes for power savings see section 30.1.4, modes of operation for a description of the power saving modes. table 30-12. write/byte enable signals function 1 1 this table applies to aligned internal master transfers only. in the case of a misaligned internal master transfer that is split into multiple aligned external tr ansfers, not all of the write enables x?d in the table will necessarily assert. see section 30.4.2.11, misaligned access support . transfer size address 32-bit port size 16-bit port size 2 2 also applies when dbm=1 for 16-bit data bus mode. a30 a31 d_we 0 d_we 1 d_we 2 d_we 3 d_we 0 d_we 1 d_we 2 d_we 3 byte 00 x x 01 x x 10 x x 11 x x 16-bit 00xx xx 10 xxxx 32-bit00xxxxx 3 3 this case consists of two 16- bit external transactions, but for both transactions the d_we [0:1] signals are the only d_we signals affected. x 3 burst00xxxxxx
external bus interface (ebi) freescale semiconductor 30-21 pxr40 microcontroller reference manual, rev. 1 30.4.1.14 optional automatic d_clkout gating the ebi has the ability to hold the external d_clko ut pin high when the ebi? s internal master state machine is idle and no requests are pending. the ebi ou tputs a signal to the pads logic in the mcu to disable d_clkout. this feature is disabled out of reset, and can be enabled or disabled by the acge bit in the ebi_mcr. note this feature must be disabled for mult i-master systems. in those cases, one master is getting its cloc k source from the other master and needs it to stay valid continuously. 30.4.1.15 misaligned access support the ebi has limited misaligned access support. misaligne d non-burst chip-select tr ansfers from internal masters are supported. the ebi aligns the accesses when it sends them out to the external bus (splitting them into multiple aligned accesses if necessary), so that external devices are not required to support misaligned accesses. burst accesses (int ernal master) must match the intern al bus size (64-bit aligned). see section 30.4.2.11, misaligned access support , for more details. 30.4.1.16 compatible with mpc5xx exte rnal bus (with some limitations) the ebi is compatible with the external bus of the mpc5xx parts, meaning that it supports most devices supported by the mpc5xx family of parts. however, ther e are some differences be tween this ebi and that of the mpc5xx parts that the user needs to be aw are of before assuming that an mpc5xx-compatible device works with this ebi. see section 30.5.5, summary of differences from mpc5xx , for details. note due to testing and complexity con cerns, multi-master (or master/slave) operation between an esys mcu and mpc5xx is not guaranteed. 30.4.2 external bus operations the following sections provide a f unctional description of the external bus, the bus cycles provided for data transfer operations, and error conditions. 30.4.2.1 external clocking possible division factors for d_clkout: 1, 2, and 4. the d_clkout signal sets the freque ncy of operation for the bus interf ace directly. internally, the mcu uses a phase-locked loop (pll ) circuit to generate a ma ster clock for all of th e mcu circuitry (including the ebi) which is phase-locked to th e d_clkout signal. in general, al l signals for the ebi are specified with respect to the rising-edge of the d_clkout signal, and they are guaranteed to be sampled as inputs or changed as outputs with respect to that edge.
external bus interface (ebi) 30-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.4.2.2 reset upon detection of internal reset a ssertion, the ebi immediately ends al l transactions (a bruptly, not through normal termination protocol), and ignor es any transaction reque sts that take place while reset is asserted. 30.4.2.3 basic transfer protocol the basic transfer protocol defines the sequence of act ions that must occur on th e external bus to perform a complete bus transaction. a simp lified scheme of the basic tr ansfer protocol is shown in figure 30-8 . figure 30-8. basic transfer protocol the arbitration phase is where bus ow nership is requested and granted. th is phase is not needed in single master mode because the ebi is the permanent bus owner in this mode. the address transfer phase specifies th e address for the transaction and the transfer attributes that describe the transaction. the signals related to the address transfer phase are d_ts , d_add (or d_add_dat if address/data multiplexing is used), cs [0:3], d_rd_wr , and d_bdip . the address and its related signals (with the exception of d_ts , d_bdip ) are driven on the bus with the assertion of the d_ts signal, and kept valid until the bu s master receives d_ta asserted (the ebi holds them one cycle beyond d_ta for writes and external d_ta accesses). note that for writes with internal d_ta , d_rd_wr is not held one cycle past d_ta . the data transfer phase performs the transfer of data, from master to sl ave (in write cycles) or from slave to master (on read cycles), if any is to be transferred. the data phase may transfer a single be at of data (1-4 bytes) for non-burst operations or a 2- beat (special dbm=1 cas e only), 4-beat, 8-beat, or 16-beat burst of data (2 or 4 bytes per beat dependi ng on port size) when burst is enab led. on a write cycle, the master must not drive write data until after the address tran sfer phase is complete. this is to avoid electrical contentions when switching between dr ivers. the master must start driv ing write data one cycle after the address transfer cycle. the mast er can stop driving the data bus as soon as it samples the d_ta line asserted on the rising edge of d_clkout. to f acilitate asynchronous write support, the ebi keeps driving valid write data on the data bus until 1 clock after the rising edge where d_rd_wr and we are negated (for chip-sel ect accesses only). see figure 30-14 for an example of write timing. on a read cycle, the master accepts the data bus c ontents as valid on the rising edge of the d_clkout in which the d_ta signal is sampled asserted. see figure 30-10 for an example of read timing. the termination phase is where the cycle is terminated by the assertion of either d_ta (normal termination) or d_tea (termination with error). terminat ion is discussed in detail in section 30.4.2.8, termination signals protocol . 30.4.2.4 single beat transfer the flow and timing diagrams in this section assume that the ebi is configured in single master mode. therefore, arbitration is not needed and is not shown in these diagrams. arbitration address transfer data transfer termination
external bus interface (ebi) freescale semiconductor 30-23 pxr40 microcontroller reference manual, rev. 1 30.4.2.4.1 single beat read flow the handshakes for a single beat read cycle are illu strated in the following flow and timing diagrams. figure 30-9. basic flow diagram of a single beat read cycle figure 30-10. single beat 32-bit read cycle, cs access, zero wait states ye s no receives address asserts transfer start (d_ts ) drives address & attributes master (ebi) drives data asserts transfer acknowledge (d_ta ) asserts transfer acknowledge (d_ta ) receives data slave cs access & !seta ? d_add_dat[0:31] d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip d_oe cs [ n ]
external bus interface (ebi) 30-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-11. single beat 32-bit read cycle, cs access, one wait state figure 30-12. single beat 32-bit read cycle, non-cs access, zero wait states 30.4.2.4.2 single beat write flow the handshakes for a single beat writ e cycle are illustrated in the fo llowing flow and timing diagrams. wait state d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip d_oe cs [ n ] d_add_dat is valid d_add_dat[0:31] d_clkout d_add[9:30] d_ts d_ta (input) d_rd_wr d_bdip d_oe cs [ n ] d_add_dat is valid the ebi drives address and control signals an extra cycle because it uses a latched version of the external d_ta (1 cycle delayed) to terminate the cycle. * * d_add_dat[0:31]
external bus interface (ebi) freescale semiconductor 30-25 pxr40 microcontroller reference manual, rev. 1 figure 30-13. basic flow diagram of a single beat write cycle ye s no receives address asserts transfer start (d_ts ) drives address & attributes master receives data cs access & !seta asserts transfer acknowledge (d_ta ) asserts transfer acknowledge (d_ta ) waits 1 clock slave stops driving data drives data ?
external bus interface (ebi) 30-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-14. single beat 32-bit write cycle, cs access, zero wait states figure 30-15. single beat 32-bit write cycle, cs access, one wait state d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip cs [ n ] d_add_dat is valid d_add_dat[0:31] d_we [0:3] wait state d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip cs [ n ] d_add_dat[0:31] d_we [0:3]
external bus interface (ebi) freescale semiconductor 30-27 pxr40 microcontroller reference manual, rev. 1 figure 30-16. single beat 32-bit write cycle, non-cs access, zero wait states 30.4.2.4.3 back-to-back accesses due to internal bus protocol, one dead cycle is neces sary between back-to-back external bus accesses that are not part of a set of small accesses (see section 30.4.2.6, small accesses (s mall port size and short burst length) for small access timing). a dead cycle refers to a cycle between the d_ta of a previous transfer and the d_ts of the next transfer. note in some cases, cs remains asserted during this dead cycle, such as the cases of back-to-back writes or read-after -write to the same chip-select. see figure 30-20 and figure 30-21 . besides this dead cycle, in most cases, back-to-back accesses on the ex ternal bus do not cause any change in the timing from that sh own in the previous diagrams, and the tw o transactions are independent of each other. the only exceptions to this are listed below: ? back-to-back accesses where the first access ends with an externally-driven d_ta or d_tea . in these cases, an extra cycle is required between the end of the first access and the d_ts assertion of the second access. see section 30.4.2.8, termination signals protocol for more details. the following diagrams show a few examples of back-to-back accesses on the external bus. d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta (input) d_rd_wr d_bdip cs [ n ] d_add_dat is valid the ebi drives address and control signals an extra cycle because it uses a latched version of the external d_ta (1 cycle delayed) to terminate the cycle. * * d_add_dat[0:31] d_we [0:3]
external bus interface (ebi) 30-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-17. back-to-back 32-bit reads to the same cs bank figure 30-18. back-to-back 32-bit reads to different cs banks d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip d_oe cs [ n ] d_add_dat[0:31] d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip d_oe cs [ y ] cs [ n ] d_add_dat[0:31]
external bus interface (ebi) freescale semiconductor 30-29 pxr40 microcontroller reference manual, rev. 1 figure 30-19. write after read to the same cs bank figure 30-20. back-to-back 32-bit writes to the same cs bank d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip csx d_add_dat[0:31] d_we d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip cs [ n ] d_add_dat[0:31] d_we
external bus interface (ebi) 30-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-21. read after write to the same cs bank 30.4.2.5 burst transfer the ebi supports wrapping 32-byte cr itical-doubleword-first burst transfers. bursting is supported only for internally-requested cache-line size (32-byte) read accesses to ex ternal devices that use the chip selects 1 . accesses to devices operating without a chip select are al ways single beat. if an in ternal request to the ebi indicates a size of less th an 32 bytes, the request is fulfilled by ru nning one or more si ngle-beat external transfers, not by an external burst transfer. an 8-word wrapping burst reads eight 32-bit words by supplying a starting address that points to one of the words (doubleword aligned) and requiring the memory device to se quentially drive each word on the data bus. the selected slave device must internally incr ement d_add[27:29] (als o d_add30 in the case of a 16-bit port size device) of the s upplied address for each transfer, until the address reaches an 8-word boundary, and then wrap the address to the beginning of the 8-word boundary. the address and transfer attributes supplied by the ebi remain stable during the transfers. terminat ion of each beat transfer occurs by the ebi asserting d_ta (seta=1 is not supported for burst tran sfers). the ebi requi res that addresses be aligned to a doubleword boundary on all burst cycles. table 30-13 shows the burst order of beats returned for an 8-word burst to a 32-bit port. 1. except for the special case of a 32-bit non-chi p-select access in 16-b it data bus mode. see section 30.4.2.9, non-chip-select burst in 16-bit data bus mode . d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip csx d_add_dat[0:31] d_we
external bus interface (ebi) freescale semiconductor 30-31 pxr40 microcontroller reference manual, rev. 1 the general case of burst transfers as sumes that the external memory ha s 32-bit port size and 8-word burst length. the ebi can also burst from 16-bit port size memories, taking twi ce as many external beats to fetch the data as compared to a 32-bit port with the same burst length. the ebi can also burst from 16-bit or 32-bit memories that have a 4-word bur st length (bl=1 in the appropriate base register). in this case, two external 4-word burst tran sfers (wrapping on 4-word boundary) are perfor med to fulfill the internal 8-word request 1 . this operation is considered at omic by the ebi, so th e ebi does not allow ot her unrelated master accesses or bus arbitration to interv ene between the transfers. for more details and a timing diagram, see section 30.4.2.6.3, small access example #3: 32- byte read to 32-bit port with bl=1 . during burst cycles, the d_bdip (burst data in progress) signal is used to indicate the duration of the burst data. during the data phase of a burst read cycle, the ebi receives data from the addressed slave. if the ebi needs more than one data, it asserts the d_bdip signal. upon receiving the data prior to the last data, the ebi negates d_bdip . thus, the slave stops driving new da ta after it receives the negation of d_bdip on the rising edge of the clock. some slav e devices have their burst length and timing configurable internally and thus may not support connecting to a d_bdip pin. in this case, d_bdip is driven by the ebi normally, but th e output is ignored by the memory and the burst data behavior is determined by the internal configur ation of the ebi and slave device. when the tbdip bit is set in the appropriate base register, the timing for d_bdip is altered. see section 30.4.2.5.1, tbdip effect on burst transfer for this timing. since burst writes are not supported by the ebi 2 , the ebi negates d_bdip during write cycles. table 30-13. wrap bursts order burst starting address d_add[27:28] burst order (assuming 32-bit port size) 00 word0 -> word1 -> word2 -> word3 -> word4 -> word5 -> word6 -> word7 01 word2 -> word3 -> word4 -> word5 -> word6 -> word7 -> word0 -> word1 10 word4 -> word5 -> word6 -> word7 -> word0 -> word1 -> word2 -> word3 11 word6 -> word7 -> word0 -> word1 -> word2 -> word3 -> word4 -> word5 1. this case (of 2 external burst transfers being required) applies only to amba data bus width of 64 bits. 2. except for the special case of a 32-bit non-chi p-select access in 16-b it data bus mode. see section 30.4.2.9, non-chip-select burst in 16-bit data bus mode .
external bus interface (ebi) 30-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-22. basic flow diagram of a burst read cycle no ye s receives address asserts transfer start (d_ts ) drives address & attributes master next to last data beat slave drives data asserts transfer acknowledge (d_ta ) ? negate d_bdip drives last data asserts transfer acknowledge (d_ta ) receives last data assert d_bdip receives data
external bus interface (ebi) freescale semiconductor 30-33 pxr40 microcontroller reference manual, rev. 1 figure 30-23. burst 32-bit read cycle, zero wait states figure 30-24. burst 32-bit read cycle, one initial wait state 30.4.2.5.1 tbdip eff ect on burst transfer some memories require di fferent timing on the d_bdip signal than the default to run burst cycles. using the default value of tbdip=0 in the appropr iate ebi base register results in d_bdip being asserted (scy+1) cycles after the address transfer phase, a nd being held asserted throughout the cycle regardless of the wait states between beats (bscy). figure 30-25 shows an example of the tbdip=0 timing for a 4-beat burst with bscy=1. expects more data d_add_dat is valid d_clkout d_add[9:30] d_bdip d_ta d_rd_wr d_ts d_oe cs [ n ] d_add[29:31] = ?000? d_add_dat[0:31] wait state d_clkout d_add[9:30] d_bdip d_ta d_rd_wr d_ts d_oe cs [ n ] expects more data d_add[29:31] = ?000? d_add_dat[0:31] d_add_dat is valid
external bus interface (ebi) 30-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-25. burst 32-bit read cycle, one wait state between beats, tbdip=0 when using tbdip=1, the d_bdip behavior changes to toggle betw een every beat when bscy is a non-zero value. figure 30-26 shows an example of the tbdip=1 ti ming for the same 4-beat burst shown in figure 30-25 . figure 30-26. burst 32-bit read cycle, one wait state between beats, tbdip=1 d_add_dat is valid wait state wait state d_clkout d_add[9:30] d_bdip d_ta d_rd_wr d_ts d_oe cs [ n ] d_add[29:31] = ?000? wait state wait state d_add_dat[0:31] expects more data expects more data d_add_dat is valid wait state wait state d_clkout d_add[9:30] d_bdip d_ta d_rd_wr d_ts d_oe cs [ n ] d_add[29:31] = ?000? wait state wait state d_add_dat[0:31]
external bus interface (ebi) freescale semiconductor 30-35 pxr40 microcontroller reference manual, rev. 1 30.4.2.6 small accesses (small port size and short burst length) in this context, a small access refers to an access whose burst length and port size (bl, ps bits in base register for chip-select access or default burst disabled, 32-bit port fo r non-chip-select access) are such that the number of bytes requested by the internal master cannot all be fe tched (or written) in one external transaction. if this is the case, the ebi initiates mu ltiple transactions until all the requested data is transferred. it should be noted that all the transactions initiated to complete the da ta transfer are considered as an atomic transaction, so the ebi does not allow other unrelated ma ster accesses to intervene between the transfers. table 30-14 shows all the combinations of burst length, port size, and requ ested byte count that cause the ebi to run multiple external tran sactions to fulfill the request. in most cases, the timing for small a ccesses is the same as for normal singl e-beat and burst accesses, except that multiple back-to-back external transfers are ex ecuted for each internal request. these transfers have no additional dead cycles in -between that are not present for back-t o-back stand-alone transfers except for the case of writes with an internal request size of >64 bits, discussed in section 30.4.2.6.2, small access example #2: 32-byte write with external d_ta . the following sections show a few examples of small accesses. the timing for the remaining cases in table 30-14 can be extrapolated from these and the other timing diagrams in this document. 30.4.2.6.1 small access example #1: 32-bit write to 16-bit port figure 30-27 shows an example of a 32-bit write to a 16-bit port, requiring two 16-bit external transactions. table 30-14. small access cases byte count requested by internal master burst length port size # external accesses to fulfill request non-burstable chip-select banks (b i=1) or non-chip-select access 4 1 beat 16-bit 2/1 1 1 in 32-bit data bus mode (dbm=0 in ebi_mcr), two accesses are performed. in 16-bit data bus mode (dbm=1), one 2-beat burst access is performed an d this is not considered a ?small access? case. see section 30.4.2.9, non-chip-select burst in 16-bit data bus mode for this special dbm=1 case. 8 1 beat 32-bit 2 8 1 beat 16-bit 4 32 2 2 only supported for case of 64-bit internal amba data bus. 1 beat 32-bit 8 32 2 1 beat 16-bit 16 burstable chip-select banks (bi=0) 32 2 4 words 16-bit (8 beats), 32-bit (4 beats) 2
external bus interface (ebi) 30-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-27. single beat 32-bit write cycle, 16-bit port size, basic timing 30.4.2.6.2 small access example #2: 32-byte write with external d_ta figure 30-28 shows an example of a 32-byt e write to a non-chip-select device using external d_ta , requiring eight 32-bit external transactions. no te that due to the use of external d_ta , d_rd_wr does not toggle between the accesses unless that access is th e end of a 64-bit boundary. in this case, an extra cycle is required between d_ta and the next d_ts in order to get the next 64-bi ts of write data internally and d_rd_wr negates during this extra cycle. d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip cs [ n ] aa + 2 abcdxxxx efghxxxx d_add_dat[0:31] d_we
external bus interface (ebi) freescale semiconductor 30-37 pxr40 microcontroller reference manual, rev. 1 figure 30-28. 32-byte write cycle with external d_ta , basic timing 30.4.2.6.3 small access exam ple #3: 32-byte read to 32-bit port with bl=1 figure 30-29 shows an example of a 32-byte read to a 32- bit burst enabled port with burst length of 4 words, requiring two 16-byte external transactions. fo r this case, the address for the 2nd 4-word burst access is calculated by adding 0x10 to the lower 5 bits of the 1st addres s (no carry), and then masking out the lower 4 bits to fix them at zero. table 30-15. examples of 4-word burst addresses 1st address lower 5 bits of 1st address + 0x10 (no carry) final 2nd address (after masking lower 4 bits) 0x000 0x10 0x10 0x008 0x18 0x10 0x010 0x00 0x00 0x018 0x08 0x00 0x020 0x30 0x30 0x028 0x38 0x30 0x030 0x20 0x20 0x038 0x28 0x20 d_add_dat is valid d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip cs [ n ] aa + 4 a + 8 a + 0xc this extra cycle is required after accesses 2, 4, and 6 to get the next 64-bits of internal write data. * four more external accesses (not shown) are r equired to complete the internal 32-byte request. the timing of these is the same as accesses 1-4 shown in this diagram. ** 12 34** * d_add_dat[0:31] d_we
external bus interface (ebi) 30-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-29. 32-byte read with b-t-b 16-byte bursts to 32-bit port, zero wait states 30.4.2.6.4 small access example #4: 64-bit read to 16-bit port figure 30-30 shows an example of a 64-bit r ead to a 16-bit port, requiring fo ur 16-bit external transactions. figure 30-30. single beat 64-bit read cycle, 16-bit port size, basic timing expects more data d_clkout d_add[9:30] d_bdip d_ta d_rd_wr d_ts d_oe cs [ n ] d_add[29:31] = ?000? d_add[28:31] = ?0000? d_add_dat[0:31] d_add_dat is valid expects more data d_add_dat is valid d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip cs [ n ] * d_add_dat[0:15] d_we a a + 2 a + 4 a + 6 abcd efgh ijkl mnop or d_add_dat[16:31], based on d16_31 bit in ebi_mcr. *
external bus interface (ebi) freescale semiconductor 30-39 pxr40 microcontroller reference manual, rev. 1 30.4.2.7 size, alignment and packaging on transfers table 30-16 shows the allowed sizes that an internal master can request from the ebi. the behavior of the ebi for request sizes not shown belo w is undefined. no error signal is as serted for these erroneous cases. even though misaligned non-burst transf ers from internal masters are s upported, the ebi naturally aligns the accesses when it sends them out to the external bus, splitting them into multiple aligned accesses if necessary. see section 30.4.2.11, misaligned access support for these cases. natural alignment for the ebi means: ? byte access can have any address ? 16-bit access, address bit 31 must be 0 ? 32-bit access, address bits 30-31 must be 0 ? for burst accesses of any size , address bits 29-31 must be 0 the ebi never generates a misaligne d external access, so a multi-mast er system with two e200-based mcus can never have a misaligned external access from one to the other. in the erroneous case that an externally-initiated misaligned access does occur, the ebi errors the access (by asserting d_tea externally) and does not initiate the access on the internal bus. the ebi requires that the portion of the data bus used for a transfer to/from a pa rticular port size be fixed. a 32-bit port must reside on data bus bits 0- 31,and a 16-bit port must reside on bits 0-15. in the following figures and tables the following convention is adopted: ? the most significant byte of a 32-bit operand is op0, and op3 is the least significant byte. ? the two bytes of a 16-bit opera nd are op0 (most significant) and op1, or op2 (most significant) and op3, depending on the address of the access. ? the single byte of a byte-le ngth operand is op0, op1, op2, or op3, depending on the address of the access. this can be seen in figure 30-31 . table 30-16. transaction sizes supported by ebi # bytes (internal master) 1 2 4 3 1 1 some misaligned access cases may result in 3-byte writes. these cases are treated as power-of-2 sized requests by the ebi, using d_we [0:3] to make sure only the appropriate 3 bytes get written. 8 32
external bus interface (ebi) 30-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-31. internal operand representation figure 30-32 shows the device connections on the d_add_dat[0:31] bus. figure 30-32. interface to different port size devices table 30-17 lists the bytes required on the data bus for r ead cycles. the bytes indicated as ?-? are not required during that read cycle. table 30-17. data bus requ irements for read cycles transfer size address 32-bit port size 16-bit port size 1 a30 a31 d0:d7 d8:d15 d16:d23 d24:d31 d0:d7 2 d8:d15 3 byte 00op0 ? ? ? op0 ? 0 1 ? op1 ? ? ? op1 1 0 ? ? op2 ? op2 ? 1 1 ? ? ? op3 ? op3 16-bit 0 0 op0 op1 ? ? op0 op1 1 0 ? ? op2 op3 op2 op3 32-bit 0 0 op0 op1 op2 op3 op0 or op2 4 op1 or op3 op0 op1 op2 op3 031 op0 op1 op2 op3 op0 op1 op2 op3 32-bit 16-bit byte interface output register 031 [16:23] 32-bit port size [24:31] [8:15] d_add_dat[0:7] 16-bit port size op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3
external bus interface (ebi) freescale semiconductor 30-41 pxr40 microcontroller reference manual, rev. 1 table 30-18 lists the patterns of the data transfer for wr ite cycles when accesses are initiated by the mcu. the bytes indicated as ??? are not driven during that write cycle. 30.4.2.8 termination signals protocol the termination signals protocol was defined in order to avoid electrica l contention on lines that can be driven by various sources. in order to do that, a slav e must not drive signals a ssociated with the data transfer until the address phase is completed and it recognizes the address as its own. the slave must disconnect from signals imme diately after it acknowledges the cycle a nd not later than th e termination of the next address phase cycle. for ebi-mastered non-chip-select accesse s, the ebi requires assertion of d_ta from an external device to signal that the bus cycle is complete . the ebi uses a latched version of d_ta (1 cycle delayed) for these accesses to help make timing at high frequencies. this results in the ebi driving the address and control signals 1 cycle longer than required, as seen in figure 30-33 . however, the d_add_dat does not need to be held 1 cycle longer by the slave, becau se the ebi latches d_add_dat every cycle during non-chip-select accesses. during these acce sses, the ebi does not drive the d_ta signal, leaving it up to an external device (or weak internal pullup) to drive d_ta . for ebi-mastered chip-select accesses, when the seta bit is 0, the ebi drives d_ta the entire cycle, asserting according to internal wait state counters to terminate the cycle. when the seta bit is 1, the ebi samples the d_ta for the entire cycle. during idle periods on the external bus, the ebi drives d_ta negated as long as it is granted the bus; when it no longer owns the bus, it lets go of d_ta . 1 also applies when dbm=1 for 16-bit data bus mode. 2 for address/data muxed transfers, d_add_dat[16:23] are used externally, not d_add_dat[0:7]. 3 for address/data muxed transfers, d_add_dat[24:31] are used externally, not d_add_dat[8:15]. 4 this case consists of two 16-bit exte rnal transactions, the first fetching op 0 and op1, the second fetching op2 and op3. table 30-18. data bus contents for write cycles transfer size address 32-bit port size 16-bit port size 1 1 also applies when dbm=1 for 16-bit data bus mode. a30 a31 d0:d7 d8:d15 d16:d23 d24:d31 d0:d7 2 2 for address/data muxed transfers, d_add_dat[16:23] are used externally, not d_add_dat[0:7]. d8:d15 3 3 for address/data muxed transfers, d_add_dat[24:31] are used externally, not d_add_dat[8:15]. byte 0 0 op0 ? ? ? op0 ? 0 1 op1 op1 ? ? ? op1 1 0 op2 ? op2 ? op2 ? 1 1 op3 op3 ? op3 ? op3 16-bit 0 0 op0 op1 ? ? op0 op1 1 0 op2 op3 op2 op3 op2 op3 32-bit 0 0 op0 op1 op2 op3 op0 or op2 4 4 this case consists of two 16-bit exte rnal transactions, the first writing op0 and op1, the second writing op2 and op3. op1 or op3
external bus interface (ebi) 30-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 if no device responds by asserting d_ta within the programmed timeout period (bmt in ebi_bmcr) after the ebi initiates the bus cycle, the internal bus monitor (if enabled) asserts d_tea to terminate the cycle. an external device may also drive d_tea when it detects an error on an external transaction. d_tea assertion causes the cycle to te rminate and the processor to enter exception processing for the error condition. to properly control termin ation of a bus cycle for a bus erro r with external circuitry, d_tea must be asserted at the same time or before (external) d_ta is asserted. d_tea must be negated before the second rising edge after it was sampled asserted in order to avoid the detection of an error for the following bus cycl e initiated. d_tea is only driven by the ebi during th e cycle where the ebi is asserting d_tea and the cycle immediately following this assertion (for fast negation). duri ng all other cycles, the ebi relies on a weak internal pullup to hold d_tea negated. this allows an external device to assert d_tea when it needs to indicate an erro r. external devices must follow th e same protocol as the ebi, only driving d_tea during the assertion cycle and 1 cycle afterwards for negation. when d_tea is asserted from an ex ternal source, the ebi uses a latched version of d_tea (1 cycle delayed) to help make timing at high frequencies. th is means that for any acces ses where the ebi drives d_ta (chip-select accesses with seta=0), a d_tea assertion that occurs 1 cycle before or during the last d_ta of the access could be ignored by the ebi, sin ce it will have completed the access internally before it detects the latched d_tea assertion. this means that non-burst chip-select accesses with no wait states (scy=0) cannot be reliab ly terminated by external d_tea . if external error te rmination is required for such a device, the ebi must be configured for scy>=1. note for the cases discussed above where d_tea ?could be ignored?, this is not gauranteed. for some small access case s (which always use chip-select and internally-driven d_ta ), a d_tea that occurs 1 cycle before or during the d_ta cycle or for scy=0 may in fact lead to terminating the cycle with error. however, proper error terminat ion is not guaranteed for these cases, so d_tea must always be asserted at least 2 cycles before an internally-driven d_ta cycle for proper error termination. external d_tea assertion that occurs during the same cycle that d_ts is asserted by the ebi is always treated as an error (terminating the access) regardless of scy. table 30-19 summarizes how the ebi recogni zes the termination signals provi ded from an external device. figure 30-33 shows an example of the termin ation signals protocol for back-to-back reads to two different slave devices who properly ?take turn s? driving the termination signals. this assumes a system using slave devices that drive termination signals. table 30-19. termination signals protocol d_tea 1 1 latched version (1 cycle dela yed) used for externally driven d_tea and d_ta . d_ta 1 action negated negated no termination asserted x transfer error termination negated asserted normal transfer termination
external bus interface (ebi) freescale semiconductor 30-43 pxr40 microcontroller reference manual, rev. 1 figure 30-33. termination sign als protocol timing diagram 30.4.2.9 non-chip-select burs t in 16-bit data bus mode the timing diagrams in this section apply only to th e special case of a non-chip-select 32-bit access in 16-bit data bus mode (dbm=1 in ebi_mcr). for this case, a special 2-beat burst protocol is used for reads and writes, so that a slave device (using the same ebi) can internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit accesses. note since this device does not support multi-master system s, the original intent of this protocol does not a pply. however, this 2-beat burst protocol can also occur in a single-master system, if a non-chip-select 32-bit access to a 16-bit port is performed. figure 30-34 shows a 32-bit non-chip-select read from an external master in 16-bit data bus mode. figure 30-35 shows a 32-bit non-chip-select write from an external mast er in 16-bit data bus mode. the ebi drives address and control signals an extra cycle because it uses a latched version of d_ta * this is the earliest that the ebi can start another tran sfer, in the case of continuing a set of small accesses. for all other cases, an extra cycle is neede d before the ebi can start another d_ts . ** d_clkout bb d_ts d_ta , d_tea d_add[9:30] d_rd_wr slave 1 slave 2 ** ** (1 cycle delayed) to terminate the cycle. an external master is not required to do this. slave 1 negates acknowledge signals and ?turns off? slave 2 negates acknowledge signals and ?turns off? slave 2 allowed to drive acknowledge signals slave 1 allowed to drive acknowledge signals d_add_dat[0:31]
external bus interface (ebi) 30-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-34. 32-bit non-chip-sel ect read from mcu with dbm=1 figure 30-35. 32-bit non-chip-select write to mcu with dbm=1 30.4.2.10 calibration bus operation some devices with this ebi have a second external bus, intended for calib ration use. this bus consists of a second set of the same signals pres ent on the primary external bus, exce pt that arbitration, (and optionally other signals also) are excluded. both busses can be supported with one ebi block, by using the calibration chip-selects to steer accesses to the calibration bus instead of the primary external bus. since the calibration bus ha s no arbitration signals, th e arbitration on the primar y bus controls accesses on the calibration bus as well, and no external master accesses can be performed on the calibration bus. accesses cannot be performed in parallel on both exte rnal busses. however, back-to-back accesses can switch from one bus to the other, as determined by the type of chip-select each address matches. d_clkout d_rd_wr d_bdip d_add[9:30] d_ts (output) minimum 2 wait states d_add_dat is valid d_ta (input) d_add_dat is valid d_add_dat[0:15] d_add_dat is valid d_clkout d_rd_wr d_bdip d_add[9:30] d_ts (output) minimum 3 wait states d_ta (input) d_add_dat[0:15] d_add_dat is valid
external bus interface (ebi) freescale semiconductor 30-45 pxr40 microcontroller reference manual, rev. 1 the timing diagrams and protocol for the calibration bus is identical to the primary bus, except that some signals are missing on the calibration bus. there is an inherent dead cycle between a calib ration chip-select access and a non-calibration access (chip-select or non-chip-select), just like the on e between accesses to two different non-calibration chip-selects (described in section 30.4.2.4.3, back-to-back accesses ). figure 30-36 shows an example of a non-cal ibration chip-select read acc ess followed by a calibration chip-select read access. note that this figure is identical to figure 30-18 , except the csy is replaced by cal_csy. timing for other cases on calibration bus can similarly be derived from other figures in this document (by replacing cs with cal_cs ). figure 30-36. back-to-back 32-bit reads to cs , cal_cs banks 30.4.2.11 misaligned access support this section describes all the misa ligned cases supported by the ebi. thes e cases are a subset of the full set of cases allowed by the amba ahb v6 specific ation. the ebi wo rks under the assumption that all internal masters on the device do not produce any misaligned a ccess cases (to the ebi) other than the ones below. 30.4.2.11.1 misaligned access support (64 bit amba) table 30-20 shows all the misaligned access cases s upported by the ebi (using a 64-bit amba implementation), as seen on the internal master am ba bus. all other misaligne d cases are not supported. if an unsupported misaligned access to the ebi is attempted (such as non-chip-select or burst misaligned d_add_dat is valid d_add_dat is valid d_clkout d_add[9:30] d_ts d_ta d_rd_wr d_bdip d_oe cal_cs [ y ] cs [ n ] d_add_dat[0:31]
external bus interface (ebi) 30-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 access), the ebi errors the access on the internal bus and does not start the access (nor assert d_tea ) externally. table 30-21 shows which external transfers are generate d by the ebi for the mi saligned access cases in table 30-20 , for each port size. the number of external tran sfers for each internal ahb master re quest is determined by the hsize value for that request relative to the port size. for example, a ha lf-word write to @011 (m isaligned case #2) with 16-bit port size results in 4 external 16-bit transfers because the hs ize is 64-bits. for cases where two or more external transfers are required for one internal transfer request, th ese external accesses are considered part of a ?small access? set, as described in section 30.4.2.6, small accesses (small port size and short burst length) . table 30-20. misalignment cases supported by a 64 bit amba ebi (internal bus) no. 1 1 misaligned case number. only transfers where hunalign=1 are numbered as misaligned cases. program size and byte offset address [29:31] 2 2 address on internal master ahb bus, not necessarily address on external d_add pins. data bus byte strobes 3 3 internal byte strobe signals on ahb bus. shown with big-endian byte ordering in this table, even though internal master ahb bus uses little-endian byte-ordering (ebi flips order internally). hsize 4 4 internal signal on ahb bus; 00=8-bits, 01=16 bits, 10=32 bits, 11=64-bits. hsize is driven according to the smallest aligned container that contains all the requested bytes. this results in extra ebi external transfers in some cases. hunalign 5 5 internal signal on ahb bus that indicates that this transfer is misaligned (when 1). 1 half @0x1,0x9 001 0110_0000 10 1 2 half @0x3,0xb 011 0001_1000 11 1 3 half @0x5,0xd 101 0000_0110 10 1 4 - half @0x7, 0xf (2 ahb transfers) 111 000 0000_0001 1000_0000 01 6 00 6 for this case, the ebi internally treats hsize as 00 (1-byte access). 1 0 5 word @0x1,0x9 001 0111_1000 11 1 6 word @0x2,0xa 010 0011_1100 11 1 7 word @0x3,0xb 011 0001_1110 11 1 8 - word @0x5,0xd (2 ahb transfers) 101 000 0000_0111 1000_0000 10 00 1 0 9 - word @0x6, 0xe (2 ahb transfers) 110 000 0000_0011 1100_0000 10 7 01 7 for this case, the ebi internally treats hsize as 01 (2-byte access). 1 0 10 11 word @0x7,0xf (2 ahb transfers) 111 000 0000_0001 1110_0000 10 6 10 1 1 12 - doubleword @0x4,0x8 (2 ahb transfers) 100 000 0000_1111 1111_0000 11 8 10 8 for this case, the ebi internally treats hsize as 10 (4-byte access). 1 0 13 - doubleword @0x2,0xa (2 ahb transfers) 010 000 0011_1111 1100_0000 11 01 1 0 14 15 doubleword 0x6,0xe (2 ahb transfers) 110 000 0000_0011 1111_1100 11 7 11 1 1
external bus interface (ebi) freescale semiconductor 30-47 pxr40 microcontroller reference manual, rev. 1 since all transfers are aligned on the external bus, normal timing diagrams and protocol apply. table 30-21. misalignment cases supported by a 64 bit amba ebi (external bus) no. 1 ps 2 program size and byte offset d_add[29:31] 3 d_we [0:3] 4 1 0 half @0x1,0x9 000 1001 1 000 010 1011 0111 2 0 half @0x3,0xb 000 100 1110 0111 1 010 100 1011 0111 3 0 half @0x5,0xd 100 1001 1 100 110 1011 0111 4 0 half @0x7,0xf (2 ahb transfers) 111 5 1110 - 000 0111 4 1 110 1011 - 000 0111 5 0 word @0x1,0x9 000 100 1000 0111 1 000 010 100 1011 0011 0111 6 0 word @0x2,0xa 000 100 1100 0011 1 010 100 0011 0011 7 0 word @0x3,0xb 000 100 1110 0001 1 010 100 110 1011 0011 0111 8 0 word @0x5,0xd (2 ahb transfers) 100 1000 - 000 0111 8 1 100 110 1011 0011 - 000 0111 9 0 word @0x6,0xe (2 ahb transfers) 110 6 1100 - 000 0011 9 1 110 6 0011 - 000 0011
external bus interface (ebi) 30-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 30.4.2.12 address data multiplexing address/data multiplexing enables the design of a sy stem with reduced pin count. in such a system, multiplexed address/data functions (on d_add_dat pi ns) are used, instead of having separate address and data pins. compared to the nor mal ebi specification (e .g. 24 address pins+32 data pins), only 32 data 10 0 word @0x7,0xf (2 ahb transfers) 111 5 1110 11 000 0001 10 1 111 5 1011 11 000 010 0011 0111 12 0 doubleword @0x4,0xc (2 ahb transfers) 100 7 0000 - 000 0000 12 1 100 7 110 0011 0011 - 000 010 0011 0011 13 0 doubleword @0x2,0xa (2 ahb transfers) 000 100 1100 0000 - 000 0011 13 1 010 100 110 0011 0011 0011 - 000 0011 14 0 doubleword @0x6,0xe (2 ahb transfers) 110 6 1100 15 000 100 0000 0011 14 1 110 6 0011 15 000 010 100 0011 0011 0011 1 misaligned case number, from table 30-20 . 2 port size; 0=32 bits, 1=16 bits. 3 external d_add pins, not necessarily the address on internal master ahb bus. 4 external d_we pins. note that these pins have negative polarity, opposite of the internal byte strobes in table 30-20 . 5 treated as 1-byte access. 6 treated as 2-byte access. 7 treated as 4-byte access. table 30-21. misalignment cases supported by a 64 bit amba ebi (external bus) (continued) no. 1 ps 2 program size and byte offset d_add[29:31] 3 d_we [0:3] 4
external bus interface (ebi) freescale semiconductor 30-49 pxr40 microcontroller reference manual, rev. 1 pins are required (e.g. d_add_dat[0:15] and d_add_dat[16:31]). compared to a 16-bit bus implementation, only 24 pins are required (e.g. d_add[8:15] + d_add_dat[16:31]). when performing a small access read, as described in section 30.4.2.6, small accesses (small port size and short burst length) , with a/d multiplexing enabled for this a ccess, the ebi inserts an idle clock cycle with d_oe negated and cs asserted, to allow for the memory to th ree-state the bus prior to the ebi driving the address on the next clock. this clock gap alre ady exists (for other r easons) for non-small-access transfers, so no additional clock gap is inserted for those cases. see figure 30-37 for an example of a small access read with a/d multiplexing enabled. in general, timing diagrams in a/d multiplexing mode are very similar to other diagrams in this document, except for the behavior of the d_add and d_add_dat busses, which can be seen in figure 30-37 . figure 30-37. small access (32-bit read to 16-bit port) on address/data multiplexed bus 30.5 initialization/application information 30.5.1 booting from external memory the ebi block does not support booting directly to external memory (i.e. fetching the first instruction after reset externally). one common method for an mcu to re semble an external boot with this ebi is to use an internal boot assist module on the mcu, which fetches the first instruction internally and configures ebi registers before branching to an ex ternal address to ?boot? externally. if code in external memory needs to write ebi registers, this must be done in a way that avoids modifying ebi registers while external accesses are be ing performed, such as the following method: addr d_add_dat is valid clock gap d_add_dat is valid d_clkout * d_add[9:30] d_ts d_ta d_rd_wr d_bdip d_oe cs [ n ] ** d_add_dat[16:31] addr addr+0x2 while the ebi drives all of d_add[9:30] to valid address, typically only d_add[9:15] (or less) are used in the system, as d_add_dat[16:31] (or d_add_dat[0:15]) * would be used for address and data on an external muxed device. or d_add_dat[0:15], based on d16_31 bit in ebi_mcr. ** addr+0x2
external bus interface (ebi) 30-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? copy the code that is doing the register writ es (plus a return branch) to internal sram ? branch to internal sram to run this code, ending with a branch back to external flash 30.5.2 running with sdr (singl e data rate) burst memories this includes flash and sram memories wi th a compatible burst interface. d_bdip is required only for some sdr memories. figure 30-38 shows a block diagram of an mc u connected to a 32-bit sdr burst memory. figure 30-38. mcu connected to sdr burst memory refer to figure 30-23 for an example of the timing of a typica l burst read operation to an sdr burst memory. refer to figure 30-14 for an example of the timing of a typical single write operation to sdr memory. 30.5.3 running with asynchronous memories the ebi also supports asynchronous memori es. in this case, the d_clkout, d_ts , and d_bdip pins are not used by the memory and burst ing is not supported. however, the eb i still drives these outputs, and always drives and latche s all signals at posedge d_clkout (i .e., there is no ?asynchronous mode? for the ebi). the data timing is controlled by setting the scy bits in the appropriate option register to the proper number of wait states to work with the acce ss time of the asynchronous memory, just as done for a synchronous memory. 30.5.3.1 example wait state calculation this example applies to any chip-sel ect memory, synchronous or asynchronous. as an example, say we have a memory with 50ns access time, and we are running the external bus @ 66 mhz (d_clkout period: 15.2ns). assume the input data spec for the mcu is 4ns. number of wait states = (access time) / (d_clkout period) + (0 or 1) (depending on setup time) d_clkout cs0 d_ts d_add[9:30] d_bdip d_oe mcu ck ce adv baa * we ** a[0:21] d[0:31] oe sdr burstable flash or sram * may or may not be connected, depending on the memory used. flash memories typically use one we signal as shown, rams use 2 or 4 (16-bit or 32-bit). ** d_add_dat[0:31] d_we0
external bus interface (ebi) freescale semiconductor 30-51 pxr40 microcontroller reference manual, rev. 1 50/15.2 = 3 with 4.4ns remaining (so we need at least 3 wait states, now check setup time) 15.2-4.4=10.8ns (this is the achieved input data setup time) since actual input setup (10.8ns ) is greater than the input setup spec ( 4.0ns), 3 wait states is sufficient. if the actual input setup was less than 4.0ns, we would have to use 4 wait states instead. 30.5.3.2 timing and c onnections for asynchronous memories the connections to an asynchronous memory are the sa me as for a synchronous memory, except that the d_clkout, d_ts , and d_bdip signals are not used. figure 30-39 shows a block di agram of an mcu connected to an asynchronous memory. figure 30-39. mcu connected to asynchronous memory figure 30-40 shows a timing diagram of a read operation to a 16-bit asynchronous memory using 3 wait states. figure 30-41 shows a timing diagram of a write operation to a 16-bit as ynchronous memory using 3 wait states. flash memories typically use one we signal as shown, rams us e 2 or 4 (16-bit or 32-bit). * cs0 d_add[9:30] d_oe mcu ce we * a[0:21] d[0:15] oe asynchronous memory d_we0 d_add_dat[0:15]
external bus interface (ebi) 30-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 30-40. read operation to asynchronous memory, three initial wait states figure 30-41. write operation to asynchronous memory, three initial wait states 30.5.4 connecting an m cu to multiple memories the mcu can be connected to more than one memory at a time. figure 30-42 shows an example of how two memori es could be connected to one mcu. d_clkout cs [ n ] d_oe d_ts d_add[9:30] d_ta 3 wait states d_add_dat is valid d_add_dat[0:31] d_we [0:1] d_clkout cs [ n ] d_oe d_ts d_add[9:30] d_ta 3 wait states d_add_dat is valid d_add_dat[0:31] d_we [0:1]
external bus interface (ebi) freescale semiconductor 30-53 pxr40 microcontroller reference manual, rev. 1 figure 30-42. mcu connected to multiple memories 30.5.5 summary of differences from mpc5xx below is a summary list of the significant differen ces between this ebi and that of the mpc5xx parts. ? no memory controller s upport for external masters ? must configure each master in multi-mast er system to drive its own chip selects ? rationale: save complexity, no requirement for this feature ? burst mechanism updated to be compatible with e200z core with 32-byte cache line ? rationale: required for performance and compatibility with e200z core ? removed these variable timing a ttributes from option register: ? csnt, acs, trlx, ehtr ? rationale: reduces tester edgesets and comple xity, no clear requirements for these features ? removed reservation support on external bus ? rationale: reservation not supported on in ternal bus, useless to support on external ? removed address type (at), write-pro tect (wp), and dua l-mapping features d_clkout cs0 d_ts d_add[9:30] d_bdip d_oe mcu ck ce adv we ** a[0:21] d[0:31] oe baa * sdr ck ce adv we ** a[0:21] d[0:31] oe baa * cs1 * may or may not be connected, depending on the memory used. flash memories typically use one we signal as shown, rams use 2 or 4 (16-bit or 32-bit). ** memory sdr memory d_add_dat[0:31] d_we0 d_we1
external bus interface (ebi) 30-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? rationale: these functions can be replicated by memory management unit (mmu) in e200z core ? removed support for 8-bit ports ? rationale: reduces comp lexity and not required ? removed boot chip-select operation ? rationale: on-chip boot as sist module (bam) handles boot (and configuration of ebi registers) ? open drain mode and pullup resistors no longer re quired for multi-master systems, extra cycle needed to switch between masters ? rationale: saves customer hassle for multi-master system setup, at negligible performance cost ? address decoding for external mast er accesses uses 4-bit code to determine internal slave instead of straight address decode ? rationale: needed for compatibility with inte rnal bridge address decoding and memory map ? removed support for 3-master systems ? rationale: very difficult to manage with in ternal bridge address decoding method and keep memory maps unique; not an essential feat ure to justify complexity of supporting ? removed lbdip base register bit, now late d_bdip assertion is default behavior ? rationale: unaware of any me mories that require d_bdip to assert earlier than lbdip timing, so reduce number of cs control bits and complexity ? modified arbitration protocol to require ex tra cycles when switching between masters ? rationale: could not use exact oak protocol an d make timing for full-speed operation; adding dead cycles to protocol allows bus to run full- speed in external master mode and makes this feature not limit overall ebi frequency ? added support for 32-bit coherent read & write non-chip-select accesses in 16-bit data bus mode ? rationale: some internal registers must be acc essed all 32 bits at once to function as expected ? added misaligned access support ? rationale: some esys cores require use of misaligned accesses for optimum performance ? added calibration access support ? rationale: support related device logic added to multiple esys devices?s, reque sted customer feature ? added support for larger external address bus (up to 29 bits) ? rationale: support larger external memory sizes ? added support for address/data multiplexing ? rationale: new feature to reduce minimum pin count ? added support for using either half of data bus for 16-bit port transfers ? rationale: helps a/d muxed usability, while maintaining backwards compatibility
nexus development interface (ndi) freescale semiconductor 31-1 pxr40 microcontroller reference manual, rev. 1 chapter 31 nexus development interface (ndi) 31.1 introduction the device microcontroller contains multiple nexus clients that communicate over a single ieee ? -isto 5001?-2003 nexus class 3 combined jtag ieee 1149.1/au xiliary out interface. combined, all of the nexus clients are referred to as th e nexus development inte rface (ndi). class 3 ne xus allows for program, data, and ownership trace of the mi crocontroller execution without access to the external data and address buses. this chapter is organized into sect ions that provide a high level view of the nexus development interface: section 31.1, introduction , through section 31.8, npc initialization and application information . the chapter contains sections that discuss th e modules of the nexus development interface: ? nexus dual-etpu development interface (ndedi ). the device has two etpu engines. see section 31.9, nexus dual etpu de velopment interface (ndedi) , and the etpu reference manual for information about the ndedi. ? nexus e200z7 core interface (nz7c3). in this chapter, the nz7c3 interface is discussed in section 31.10, e200z7 class 3 nexus module (nz7c3) through section 31.11, nz7c3 memory map and register definition . ? nexus crossbar edma interface (nxdm) a nd nexus flexray interface (nxfr). refer to section 31.15, nexus crossbar edma interface (n xdm) and nexus crossbar flexray interface (nxfr) . communication to the ndi is managed via the auxiliary port and the jtag port. ? the auxiliary port is comprised of 17 or 21 outpu t pins and 1 input pin. the output pins include one message clock out (m cko) pin, 12 or 16 message data out (mdo) pins, two message start/end out (mseo ) pins, one ready (rdy ) pin, and one event out (evto ) pin. event in (evti ) is the only input pin for the auxiliary port. ? the jtag port consists of four inputs and one output. these pins include jtag compliance select (jcomp), test data input (tdi), test data output (tdo), test m ode select (tms), and test clock input (tck). tdi, tdo, tms, and tck are compliant with the ieee 1149.1-2001 standard and are shared with the ndi through the test access port (tap) interf ace. jcomp along with power-on reset and the tap state machine are used to cont rol reset for the ndi m odule. ownership of the tap is achieved by loading the appropriate enable instruction for the desired nexus client in the jtag controller (jtagc) when jcomp is asserted. see table 31-4 for the jtagc opcodes to access the different nexus clients.
nexus development interface (ndi) 31-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.1.1 block diagram figure 31-1 shows a general block diag ram of the ndi components figure 31-1. ndi general block diagram . h738 1'(', 5'< 7', 7&. 7'2 706 -&203 008 1=& h] h'0$b$ (97, 06(2>@ 0&.2 0'2ru 13&$x[loldu\3ruw (972 -7$*3ruw&rqwuroohu-7$*& 1;'0b$ 1;)5 %xiihu ,&dfkh ;%$5 3hulskhudo ([whuqdo %xv ,qwhuidfh %ulgjh $ 3hulskhudo %ulgjh % 65$0 )odvk 0 '&dfkh 1;'0b% %xiihu %xiihu %xiihu 038 5hvhuyhg %xiihu 1h[xv'hyhorsphqw ,qwhuidfh1', 5hdg:ulwh $ffhvv (qjlqh$ &'& (qjlqh% 'dwddqg :dwfksrlqw 7udfh 'dwddqg :dwfksrlqw 7udfh 'dwd :dwfksrlqw 7udfh 3urjudp'dwd 2zqhuvkls :dwfksrlqw 7udfh 3urjudp'dwd 2zqhuvkls :dwfksrlqw 7udfh 5:uhjlvwhu +dow6whs &rqwlqxh 5:uhjlvwhu 5:'dwd +dow6whs &rqwlqxh h'0$b% )oh[5d\
nexus development interface (ndi) freescale semiconductor 31-3 pxr40 microcontroller reference manual, rev. 1 31.1.2 features the ndi module is compliant with the ieee-isto 5001-2011. the following features are implemented: ? full duplex pin interface for me dium and high visibility throughput ? one of two modes selected by register confi guration: full port mode (fpm) and reduced port mode (rpm). fpm comprises 16 mdo pi ns, and rpm comprises 12 mdo pins. ? auxiliary output port ? one mcko (message clock out) pin ? 16 mdo (message data out) pins ?two mseo (message start/end out) pins ? one rdy (ready) pin ? one evto (event out) pin ? auxiliary input port uses one evti (event in) pin ? five-pin jtag port (jcomp, tdi, tdo, tms, and tck) ? host processor (e200z7) devel opment support features (nz7c3) ? ieee-isto 5001-2011 class 3 compliant. ? data trace via data write messaging (dwm) and da ta read messaging (drm). this allows the development tool to trace read s and/or writes to selected internal memory resources. ? ownership trace via ownership trace messaging (otm). otm facilitates ownership trace by providing visibility of which pr ocess id or operating system ta sk is activated. an ownership trace message is transmitted wh en a new process/task is activ ated, allowing development tools to trace ownership flow. ? program trace via branch trac e messaging (btm). branch trac e messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the disc ontinuities. thus, static code can be traced. ? watchpoint messaging (wpm ) via the auxiliary port. ? watchpoint trigger enable of pr ogram and/or data trace messaging. ? data tracing of instruction fetches via private opcodes. ? subset of power architecture book e soft ware debug facilities with once block (nexus class 1 features). ? two edma development support features (nxdm) ? data trace via data write messaging (dwm) and da ta read messaging (drm). this allows the development tool to trace dma generated reads a nd/or writes to selected address ranges in the device?s memory map. ? watchpoint messaging (wpm ) via the auxiliary port. ? watchpoint trigger enable/dis able of data trace messaging. ? flexray development s upport features (nxfr)
nexus development interface (ndi) 31-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? flexray nexus trace via data write messaging (dwm) and data read messaging (drm). this allows the development tool to trace flexray gene rated reads and/or writes to selected address ranges in the device?s memory map. ? watchpoint messaging (wpm ) via the auxiliary port. ? watchpoint trigger enable/dis able of data trace messaging. ? etpu development support features (ndedi) ? ieee-isto 5001-2002 standard class 3 compliant for the etpu engines. ? data trace via data wr ite messaging and data read messaging. this allows the development tool to trace reads and writes to selected shared parameter ram (spram) address ranges. four data trace windows are shared by the two etpu engines. ? ownership trace via ownership trace messaging (otm). otm facilitates ownership trace by providing visibility of which channel is be ing serviced. an ownership trace message is transmitted to indicate when a new channe l service request is scheduled, allowing the development tools to trace ta sk flow. a special otm is sent when the engine enters in idle state, meaning that all requests were serviced and no new requests are yet scheduled. ? program trace via branch trac e messaging. btm displays program flow disconti nuities (start, jumps, return, etc.), allowing the development t ool to interpolate what transpires between the discontinuities. thus static c ode can be traced. the branch trace messaging method uses the branch/predicate method to reduce the number of generated messages. ? watchpoint messaging via the auxi liary port. wpm provides visibili ty of the occurrence of the etpu?s? watchpoints and breakpoints. ? nexus based breakpoint/watchpoint c onfiguration and single step support. ? run-time access to the on-chip memory map via th e nexus read/write access protocol. this feature supports accesses for run-time internal visibil ity, calibration variable acquisition, calibration constant tuning, and external rapid prototyping for powertrain automotive development systems. ? all features are independently configurable and controllable via the ieee 1149.1 i/o port. ? the ndi block reset is controlled with jcomp, power-on reset, and the tap state machine. these sources are independent of system reset. 31.1.3 modes of operation the ndi block is in reset when th e tap controller state machine is in the test-logic-reset state. the test-logic-reset state is entered on the assertion of the power- on reset signal, ne gation of jcomp, or through state machine tr ansitions controlled by tms. assertion of jcomp allows the ndi to move out of the reset state, and is a prerequi site to grant nexus clients control of the tap. ownership of the tap is achieved by loading the appropriate en able instruction for the desired nexus client in the jtagc controller (jtagc) block when jcomp is asserted. following negation of power-on reset, the npc remains in reset until the system clock achieves lock. in pll bypass mode, the ndi can tran sition out of the reset state imm ediately following negation of power-on reset. see section 31.5, nexus port controller (npc) , for more details.
nexus development interface (ndi) freescale semiconductor 31-5 pxr40 microcontroller reference manual, rev. 1 31.1.3.1 nexus reset mode in nexus reset mode, the following actions occur: ? register values default back to their reset values. ? the message queues are marked as empty. ? the auxiliary output port pins are ne gated if the ndi controls the pads. ? the tdo output buffer is disabled if the ndi has control of the tap. ? the tdi, tms, and tck inputs are ignored. ? the ndi block indicates to the mcu that it is not using the auxiliary output port. this indication can be used to three-state the output pins or use them for another function. 31.1.3.2 full-port mode in full-port mode, all the available mdo pins are used to transmit messages. all trace features are enabled or can be enabled by writing the configuration registers via the jt ag port. the number of mdo pins available is 16. 31.1.3.3 reduced-port mode in reduced-port mode, a subset of th e available mdo pins are used to tr ansmit messages. al l trace features are enabled or can be enabled by writing the confi guration registers via the jtag port. the number of mdo pins available is 12. unused mdo pins can be used as gpio. detail s on gpio functionality configuration can be found in section 7.3.1.13, pad configuration registers (siu_pcr) . 31.1.3.4 disabled-port mode in disabled-port mode, message transmission is disa bled. any debug feature that generates messages can not be used. the primary features availabl e are class 1 features and read/write access. 31.1.3.5 censored mode when the device is in censored mode, reading the cont ents of internal flash externally is not allowed. to prevent nexus modules from violating censorship, the npc is held in reset when in censored mode, asynchronously holding all other nexus modules in rese t as well. this prevents nexus read/write to memory mapped resources and the tran smission of nexus trace messages. see chapter 12, flash memory array and control , for information on nexus port enabling and disabling regarding censorship. 31.2 external signal description the auxiliary and jtag pin interfaces provide for th e transmission of message s from nexus modules to the external development tools and for access to nexus client registers. the auxiliary/jt ag pin definitions are outlined in table 31-1 .
nexus development interface (ndi) 31-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.2.1 detailed signal descriptions this section describes each of the signals listed in table 31-1 in more detail. 31.2.1.1 event out (evto ) evto is an output pin that is assert ed upon breakpoint occurr ence to provide breakpoi nt status indication or to signify that an ev ent has occurred. the evto output of the npc is genera ted based on the values of the individual evto signals from all nexus modules that implement the signal. 31.2.1.2 event in (evti ) evti is used to initiate program a nd data trace synchronization messag es or to generate a breakpoint. evti is edge-sensitive for synchr onization and breakpoint generation. 31.2.1.3 message data out (mdo[11:0] or [15:0]) message data out (mdo) are output pins used for uploading otm, btm, dtm, and other messages to the development tool. the developmen t tool must sample mdo on the rising edge of mcko. the width of the mdo bus used is determined by the nexus pcr[fpm] configuration. 31.2.1.4 message start/end out (mseo [1:0]) mseo [1:0] are output pins that indicates when a messa ge on the mdo pins has started, when a variable length packet has ended, or when the message has ended. the development tool must sample the mseo pins on the rising edge of mcko. table 31-1. signal properties signal name port function reset state evto auxiliary event out pin negated evti auxiliary event in pin pullup mcko auxiliary message clock out pin (from npc) enabled mdo[11:0] or mdo[15:0] auxiliary message data out pins driven low mseo [1:0] auxiliary message start/end out pins negated rdy auxiliary ready out pin negated jcomp jtag jtag compliancy and tap sharing control pulldown tck jtag test clock input pulldown tdi jtag test data input pullup tdo jtag test data output high z / pullup tms jtag test mode select input pullup
nexus development interface (ndi) freescale semiconductor 31-7 pxr40 microcontroller reference manual, rev. 1 31.2.1.5 ready (rdy ) rdy is an output pin that indicates when a device is ready for the next access. 31.2.1.6 jtag compliancy (jcomp) the jcomp signal enables or disables the tap controller. the tap controller is enabled when jcomp asserts, otherwise the tap controller remains in reset. 31.2.1.7 test data output (tdo) the tdo pin transmits serial output for instructions a nd data. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr cont roller states. tdo is updated on the falling edge of tck and sampled by the development tool on the rising edge of tck. 31.2.1.8 test clock input (tck) the tck pin is used to synchronize the test logi c and control register access through the jtag port. 31.2.1.9 test data input (tdi) the tdi pin receives serial test instruction and data. tdi is sampled on the rising edge of tck. 31.2.1.10 test mode select (tms) the tms pin is used to sequence the ieee 1149.1-2001 tap controller state machine. tms is sampled on the rising edge of tck. 31.3 memory map the ndi block contains no memory mapped register s. nexus registers are acce ssed by the development tool via the jtag port using a register index and a client select value. the client select is controlled by loading the correct access instructi on into the jtag controller; see table 31-4 . once registers are accessed by loading the appropriate value in the rs[0 :6] field of the once co mmand register (ocmd) via the jtag port. table 31-2 shows the ndi registers and their index values. table 31-2. nexus development interface (ndi) registers index register npc registers 0 device id register (did) 127 port configuration register (pcr) e200z7 control and status registers 1 2 e200z7 development control1 (nz7c3_dc1) 3 e200z7 development control2 (nz7c3_dc2)
nexus development interface (ndi) 31-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 4 e200z7 development control3 (nz7c3_dc3) 5 e200z7 development control4 (nz7c3_dc4) 7 read/write access control/status (nz7c3_rwcs) 9 read/write access address (nz7c3_rwa) 10 read/write access data (nz7c3_rwd) 11 e200z7 watchpoint trigger (nz7c3_wt) 13 e200z7 data trace control (nz7c3_dtc) 14 e200z7 data trace start address 1 (nz7c3_dtsa1) 15 e200z7 data trace start address 2 (nz7c3_dtsa2) 16 e200z7 data trace start address 3 (nz7c3_dtsa3) 17 e200z7 data trace start address 4 (nz7c3_dtsa4) 18 e200z7 data trace end address 1 (nz7c3_dtea1) 19 e200z7 data trace end address 2 (nz7c3_dtea2) 20 e200z7 data trace end address 3 (nz7c3_dtea3) 21 e200z7 data trace end address 4 (nz7c3_dtea4) 48 development status (ds) 50 overrun control (ovcr) 51 watchpoint mask (wmsk) 53 program trace start trigger control (ptstc) 54 program trace end trigger control (ptetc) 55 data trace start trigger control (dtstc) 56 data trace end trigger control (dtetc) edma_a/b control and status registers 2 edma_ x development control (nxdm_dc) 11 edma_ x watchpoint trigger (nxdm_wt) 13 edma_ x data trace control (nxdm_dtc) 14 edma_ x data trace start address 0 (nxdm_dtsa1) 15 edma_ x data trace start address 1 (nxdm_dtsa2) 18 edma_ x data trace end address 0 (nxdm_dtea1) 19 edma_ x data trace end address 1 (nxdm_dtea2) 22 edma_ x breakpoint and watchpoint control 1 (nxdm_bwc1) 23 edma_ x breakpoint and watchpoint control 2 (nxdm_bwc2) 30 edma_ x breakpoint and watchpoint address 1 (nxdm_bwa1) table 31-2. nexus development interface (ndi) registers (continued) index register
nexus development interface (ndi) freescale semiconductor 31-9 pxr40 microcontroller reference manual, rev. 1 31 edma_ x breakpoint and watchpoint address 2 (nxdm_bwa2) flexray control and status registers 2 flexray development control (nxfm_dc) 11 flexray watchpoint trigger (nxfm_wt) 13 flexray data trace control (nxfm_dtc) 14 flexray data trace start address 0 (nxfm_dtsa1) 15 flexray data trace start address 1 (nxfm_dtsa2) 18 flexray data trace end address 0 (nxfm_dtea1) 19 flexray data trace end address 1 (nxfm_dtea2) 22 flexray breakpoint and watchpoint control 1 (nxfm_bwc1) 23 flexray breakpoint and watchpoint control 2 (nxfm_bwc2) 30 flexray breakpoint and watchpoint address 1 (nxfm_bwa1) 31 flexray breakpoint and watchpoint address 2 (nxfm_bwa2) etpu engines contro l/status registers 0 device id (did) 1 client select control (csc), etpu engine 1 / etpu engine 2 2 etpu2 development control (ndi_etpu2_dc) 4 etpu2 development status (ndedi_etpu2_ds) 11 etpu2 watchpoint trigger (ndi_etpu2_wt) 13 etpu2 data trace control (ndi_etpu2_dtc) 22 etpu2 breakpoint/watchpoint control 1 (ndedi_etpu2_bwc1) 23 etpu2 breakpoint/watchpoint control 2 (ndedi_etpu2_bwc2) 24 etpu2 breakpoint/watchpoint control 3 (ndedi_etpu2_bwc3) 30 etpu2 breakpoint/watchpoint address 1 (ndedi_etpu2_bwa1) 31 etpu2 breakpoint/watchpoint address 2 (ndedi_etpu2_bwa2) 38 etpu2 breakpoint/watchpoint data 1 (ndedi_etpu2_bwd1) 39 etpu2 breakpoint/watchpoint data 1 (ndedi_etpu2_bwd2) 64 etpu2 program trace channel enable (ndi_etpu2_ptce) 69 etpu2 microinstruction debug register (ndedi_etpu2_inst) 70 etpu2 microprogram counter debug register (ndedi_etpu2_mpc) 71 etpu2 channel flag status register (ndedi_etpu2_cfsr) 127 port configuration register (pcr) 1 these e200z7 registers are described in the e200z7 core reference manual. table 31-2. nexus development interface (ndi) registers (continued) index register
nexus development interface (ndi) 31-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 31-3 shows the once re gister addressing. refer to the debug su pport section in the z759n3 core reference manual for the descript ion of the once controller and its internal registers. table 31-3. e200z7 once register addressing ocmd, rs[0:6] register selected 000 0000?000 0001 invalid value 000 0010 jtag did (read-only) 000 0011?000 1111 invalid value 001 0000 cpu scan register (cpuscr) 001 0001 no register selected (bypass) 001 0010 once control register (ocr) 001 0011?001 1111 invalid value 010 0000 instruction address compare 1 (iac1) 010 0001 instruction address compare 2 (iac2) 010 0010 instruction address compare 3 (iac3) 010 0011 instruction address compare 4 (iac4) 010 0100 data address compare 1 (dac1) 010 0101 data address compare 2 (dac2) 010 0110 data value compare 1 (dvc1) 010 0111 data value compare 2 (dvc2) 010 1000 instruction address compare 5 (iac5) 010 1001 instruction address compare 6 (iac6) 010 1010 instruction address compare 7 (iac7) 010 1011 instruction address compare 8 (iac8) 010 1100 debug counter register (dbcnt) 010 1101 debug pcfifo (pcfifo) (read-only) 010 1110 external debug control register 0 (edbcr0) 010 1111 external debug status register 0 (edbsr0) 011 0000 debug status register (dbsr) 011 0001 debug control register 0 (dbcr0) 011 0010 debug control register 1 (dbcr1) 011 0011 debug control register 2 (dbcr2) 011 0100 debug control register 3 (dbcr3) 011 0101 debug control register 4 (dbcr4) 011 0110 debug control register 5 (dbcr5)
nexus development interface (ndi) freescale semiconductor 31-11 pxr40 microcontroller reference manual, rev. 1 31.4 ndi functional description 31.4.1 enabling nexus clients for tap access after the ndi is out of the reset state, the loading of a specific instruction in the jtag controller (jtagc) block is required to grant the ndi ow nership of the tap. each nexus c lient has its own jtagc instruction opcode for ownership of the tap, gr anting that client the means to read/write its registers. the jtagc instruction opcode for each nexus client is shown in table 31-4 . after the jtagc opcode for a client has been loaded, the client is enabled by loadi ng its nexus-enable instruction. the nexus-enable instruction opcode for each nexus client is listed in table 31-5 . opcodes for all other instructions supported by nexus clients can be found in th e relevant sections of this chapter. 011 0111 debug control register 6 (dbcr6) 011 1000?011 1100 invalid value (do not access) 011 1101 debug data acquisition message register (ddam) 011 1110 debug event control (devent) 011 1111 debug external resource control (dberc0) 111 0000?111 1001 general purpose register selects [0:9] 111 1010 cache debug access control register (cdacntl) 111 1011 cache debug access data register (cdadata) 111 1100 nexus3-access 111 1101 lsrl select 111 1110 enable_once (and bypass) 111 1111 bypass table 31-4. jtag client select instructions jtagc instruction opcode description access_aux_tap_npc 10000 enables ac cess to the npc tap controller access_aux_tap_once 10001 enables access to the e200z7 once tap controller access_aux_tap_etpu 10010 enables access to the etpu nexus tap controller (etpu_a, etpu_b, cdc_ab) access_aux_tap_nxdm 10011 enables access to the edma_a nexus tap controller access_aux_tap_nxfr 10100 enables access to the flexray nexus tap controller access_aux_tap_nxdm_b 10111 enables access to the edma_b nexus tap controller table 31-3. e200z7 once register addressing (continued) ocmd, rs[0:6] register selected
nexus development interface (ndi) 31-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.4.2 configuring the ndi for nexus messaging the ndi is placed in disabled mode upon exit of pow er-on reset. if message tr ansmission via the auxiliary port is desired, a write to the port conf iguration register (pcr) located in the npc is then required to enable the ndi and select the mode of operation. asserting mcko_en in the pcr places the ndi in enabled mode and enables mcko. the fre quency of mcko is selected by writing the mcko_div field. asserting or negating the fpm bit selects full-port or reduced-port mode, respectively. when writing to the pcr, the pcr lsb (least significant bit) must be written to a logic 0. setting the lsb of the pcr enables factory debug mode and prevents th e transmission of nexus messages. table 31-6 describes the ndi c onfiguration options. access_aux_tap_multi 11100 serialize the jtag instructions to all internal cores bypass 11111 bypass the tap controller table 31-5. nexus client jtag instructions instruction des cription opcode npc jtag instruction opcodes nexus_enable opcode for npc nexus enable instruction (4-bits) 0x0 bypass opcode for the npc bypass instruction (4-bits) 0xf e200z7 once jtag instruction opcodes 1 1 see the e200z7 reference manual for a complete list of available once instructions. nexus3_access opcode for e200z7 once nexus enable instruction (10-bits) 0x7c bypass opcode for the e200z7 once bypass instruction (10-bits) 0x7f edma nexus jtag instruction opcodes nexus_access opcode for edma nexus enable instruction (4-bits) 0x0 bypass opcode for the edma nexus bypass instruction (4-bits) 0xf flexray nexus jtag instruction opcodes nexus_access opcode for flexray nexus enable instruction (4-bits) 0x0 bypass opcode for the flexray nexu s bypass instruction (4-bits) 0xf table 31-6. ndi configuration options jcomp asserted mcko_en bit of the port configuration register fpm bit of the port configuration register configuration no x x reset ye s 0 x d i s a b l e d table 31-4. jtag client select instructions (continued) jtagc instruction opcode description
nexus development interface (ndi) freescale semiconductor 31-13 pxr40 microcontroller reference manual, rev. 1 31.4.3 programmable mcko frequency mcko is an output clock to the development tools us ed for the timing of mseo and mdo pin functions. mcko is derived from the system cl ock, and its frequency is determin ed by the value of the mcko_div field in the port configuration regi ster (pcr) located in the npc. po ssible operating frequencies include one-half, one-quarter, and one-eighth system clock speed. table 31-7 shows the mcko_div encodings. in this ta ble, sys_clk represents the core clock frequency. the default value select ed if a reserved encoding is pr ogrammed is sys_clk divided by two note: the sys_clk setting for mcko should only be used if this setting does not violate the maximum operating fre quency of the auxiliary port pins. 31.4.4 nexus messaging most of the messages transmitted by the ndi include a src field. this field is used to identify which source generated the message. table 31-8 shows the values used for the src field by the different clients on the device. these 4-bit values are specific to the de vice. the same values are us ed for the client select values written to the client select control register. yes 1 1 full-port mode yes 1 0 reduced-port mode table 31-7. mcko_div values mcko_div[2:0] mcko frequency 1 1 the sys_clk setting for mcko should only be used if this setting does not violate the maximum operating frequency of the auxiliary port pins. 0b000 sys_clk 0b001 sys_clk ? 2 0b010 invalid value 0b011 sys_clk ? 4 0b100 invalid value 0b101 invalid value 0b110 invalid value 0b111 sys_clk ? 8 table 31-6. ndi configuration options jcomp asserted mcko_en bit of the port configuration register fpm bit of the port configuration register configuration
nexus development interface (ndi) 31-14 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.5 nexus port controller (npc) the nexus port controller (npc) is that part of the ndi that controls access and arbitr ation of the device?s internal nexus modules. the npc contains the por t configuration register (pcr) and the device identification register (did). the contents of the npc did are the same as the jtagc device identification register. 31.5.1 overview the device incorporates multiple modules that require development support. each of these modules implements a development interface based on the ieee-isto 5001-2001 standard and must share the input and output ports that interface with the developm ent tool. the npc controls the usage of these ports in a manner that allows the individua l modules to share the ports, while appearing to the development tool as a single module. 31.5.2 features the npc performs the following functions: table 31-8. src packet encodings src[3:0] client 0b0000 e200z7 0b0001 edma_a 0b0010 etpu_a 0b0011 etpu_b 0b0100 etpu cdc 1 1 cdc is the etpu coherent dual-parameter controller. see the etpu reference manual for more information. 0b0101 reserved 0b0110 flexray 0b0111 edma_b 0b1000 reserved 0b1001 reserved 0b1010 reserved 0b1011 reserved 0b1100 reserved 0b1101 reserved 0b1110 reserved 0b1111 reserved
nexus development interface (ndi) freescale semiconductor 31-15 pxr40 microcontroller reference manual, rev. 1 ? controls arbitration for ownership of the nexus auxiliary output port ? nexus device identificati on register and messaging ? generates mcko enable and fr equency division control signals ? controls sharing of evto ? control of the device-wide debug mode ? generates asynchronous reset si gnal for nexus modules based on jcomp input, censorship status, and power-on reset status ? provides nexus support for censorship mode 31.6 npc memory map a nd register definition this section provides a detailed description of the npc registers accessible to the end user. individual bit-level descriptions and reset st ates of the registers are included. 31.6.1 memory map table 31-9 shows the npc registers by index values. the registers are not memory-mapped and can only be accessed via the tap. the npc doe s not implement the clie nt select control regi ster because the value does not matter when acce ssing the registers. th e bypass register (see section 31.6.2.1, bypass register ) and instruction register (see section 31.6.2.2, instruction register ) have no index values. these registers are not accessed in the same manne r as nexus client registers. table 31-9. npc memory map index register bits access reset value section/page 0 did?device id register 32 r 0x0827_401d 31.6.2.4/31-17 127 pcr?port configuration register 32 r/w 0x0000_0000 31.6.2.4/31-17
nexus development interface (ndi) 31-16 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.6.2 register descriptions this section consists of npc regist er descriptions. additional informati on regarding references to the tap controller state can be found in section 32.4.3, tap controller state machine . 31.6.2.1 bypass register the bypass register is a single-bit shif t register path selected for serial data transfer be tween tdi and tdo when the bypass instruction or any unimplemented instructions are active. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. theref ore, the first bit shifted out after selecting the bypass regist er is always a logic 0. 31.6.2.2 instruction register the npc uses a 4-bit instruct ion register as shown in figure 31-2 . the instruction register is accessed via the select_ir_scan path of the tap controller state ma chine, and allows instructions to be loaded into the module to enable the npc for re gister access (nexus_ena ble) or select the bypass register as the shift path from tdi to tdo (bypass or unimplemented instructions). instructions are shifted in through tdi while the tap c ontroller is in the shift-ir state, and latched on the falling edge of tck in the update -ir state. the latched instruction value can only be changed in the update-ir and test-logic-reset tap controller states. synchronous entry into the test-logic-reset state results in synchronous loading of the bypass instru ction. asynchronous entry in to the test-logic-reset state results in asynchronous loadin g of the bypass instruction. during the capture-ir tap controller state, the instruction register is loaded with the va lue of the previously executed instruction, making this value the register?s read value when the tap c ontroller is sequenced in to the shift-ir state. 0123 r previous instruction opcode w instruction opcode reset: bypass instruction opcode (0xf) figure 31-2. 4-bit instruction register
nexus development interface (ndi) freescale semiconductor 31-17 pxr40 microcontroller reference manual, rev. 1 31.6.2.3 nexus device id register (did) the npc device identifica tion register, shown in figure 31-3 , allows the part revision number, design center, part identificat ion number, and manufacturer id entity code of the part to be determined through the auxiliary output port. 31.6.2.4 port configuration register (pcr) the pcr, shown in figure 31-4 , is used to select the npc mode of operation, enable mcko and select the mcko frequency, and enable or disable mcko ga ting. this register must be configured as soon as the npc is enabled. note the mode (mcko_gt) or clock divisi on (mcko_div) bits must not be modified after mcko has been en abled. changing the mode or clock division while mcko is enabled can produce unpredictable results. reg index: 0 access: user r/o 0123456789101112131415 r part revision number design center part identification number w reset0000100000100111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r part identification number ( continued ) manufacturer identity code 1 w reset0100000000011101 figure 31-3. nexus device id register (did) table 31-10. did register field descriptions field description 0?3 prn part revision number. contains the revision number of the part. this field changes with each revision of the device or module. 4?9 dc design center. indicates the freescale design center. this value is 0x20. 10?19 pin part identification number. contains the part num ber of the device. the pin for the pxr40 is 0x274. 20?30 mic manufacturer identity code. contains the reduced jo int electron device engineering council (jedec) id for freescale, 0x000e. 31 fixed per jtag 1149.1 always set to 1.
nexus development interface (ndi) 31-18 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 reg index: 127 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fpm mcko _gt mcko _en mcko_div 000000000 0 w reset0 0 0 0 0 0 000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pstat _en w reset0 0 0 0 0 0 000000000 0 figure 31-4. port configuration register (pcr) table 31-11. pcr field descriptions field description 0 fpm full port mode. determines if the auxiliary output port uses the full mdo port or a reduced mdo port to transmit messages. 0 the subset of mdo[11:0] pins are used to transmit messages. 1 all mdo[15:0] pins are used to transmit messages. section 7.3.1.13, pad config uration registers (siu_pcr) , shows how gpio is enabled or disabled by the fpm setting. 1 mcko_gt mcko clock gating control. enables or disables mcko clock gating. if clock gating is enabled, the mcko clock is gated when the npc is in enabled mode but not actively transmitting messages on the auxiliary output port. when clock gating is disabled, mcko is allowed to run even if no auxiliary output port messages are being transmitted. 0 mcko gating is disabled. 1 mcko gating is enabled. 2 mcko_en mcko enable. enables the mcko clock. when enabled, the frequency of mcko is determined by the mcko_div field. 0 mcko clock is driven to zero. 1 mcko clock is enabled. 3?5 mcko_div mcko division factor. determines the frequency of mcko relative to the system clock frequency when mcko_en is asserted. the table be low shows the meaning of mcko_div values. in this table, sys_clk represents the system clock frequency. mcko_div[2:0] mcko frequency 0 sys_clk 1 1sys_clk ? 2 2 invalid value 3sys_clk ? 4 4 invalid value 5 invalid value 6 invalid value 7sys_clk ? 8 1 the sys_clk setting for mc ko should only be used if this setting does not violate the maximum operating frequency of the auxiliary port pins.
nexus development interface (ndi) freescale semiconductor 31-19 pxr40 microcontroller reference manual, rev. 1 31.7 npc functional description 31.7.1 npc reset configuration the npc is placed in disabled mode upon exit of rese t. if message transmission via the auxiliary port is desired, a write to the pcr is then required to enable the npc and select the mode of operation. asserting mcko_en places the npc in enable d mode and enables mcko. the fre quency of mcko is selected by writing the mcko_div field. asserti ng or negating the fpm bit selects full-port or reduced-port mode, respectively. table 31-6 describes the npc rese t configuration options. 31.7.2 auxiliary output port the auxiliary output port is shared by each of the nexus modules on the devi ce. the npc communicates with each of the individual modules and arbitrates for access to the por t. additional information about the auxiliary port is found in section 31.2, external signal description . 31.7.2.1 output message protocol the protocol for transmitting me ssages via the auxiliary port is accomplished with the mseo functions. the mseo pins are used to signal the end of variable-l ength packets and the end of messages. they are not required to indicate the end of fixed-length packets. mdo and mseo are sampled on the rising edge of mcko. figure 31-5 illustrates the state diagram for mseo transfers. all transitions not included in the figure are reserved, and must not be used. 6?30 reserved 31 pstat_en processor status mode enable. enables processor stat us (pstat) mode. in pstat mode, all auxiliary output port mdo pins are used to transmit processor status information, and nexus messaging is unavailable. 0 pstat mode disabled 1 pstat mode enabled note: pstat mode is intended for factory processor debug only. the pstat_en bit must be written to disable pstat mode by the customer. no nexus messages are transmitted under any circumstances when pstat mode is enabled table 31-11. pcr field descriptions (continued) field description
nexus development interface (ndi) 31-20 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 31-5. mseo transfers 31.7.2.2 output messages in addition to sending out messages ge nerated in other nexus modules, the npc can also output the device id message contained in the device id register on the mdo pins. the devi ce id message can also be sent out serially through tdo. table 31-12 describes the device id message that the np c can transmit on the auxiliary port. the tcode is the first packet transmitted. figure 31-6 shows the various message formats that th e pin interface format ter has to encounter. table 31-12. npc output messages message name min. packet bits max packet bits packet type packet name packet description device id message 6 6 fixed tcode value = 1 32 32 fixed id did register contents mseo = 00 mseo = 11 mseo = 01 mseo = 00 normal transfer end packet start message end message idle mseo = 00 mseo = 01 mseo = 11 m s eo = 0 1 m seo = 1 1 m s e o = 0 0 m s e o = 1 0 m s e o = 1 1 mseo = 01 mseo = 00 mseo = 10 mseo = 01 mseo = 11 mdo: invalid mdo: invalid mseo = 10
nexus development interface (ndi) freescale semiconductor 31-21 pxr40 microcontroller reference manual, rev. 1 figure 31-6. message field sizes the double edges in figure 31-6 indicate the starts and ends of me ssages. fields without shaded areas between them are grouped into super-fields and can be transmitted together without end-of-packet indications between them. 31.7.2.2.1 rules of messages the rules of messages include the following: ? a variable-sized field with in a message must end on a port boundary. (p ort boundaries depend on the number of mdo pins active with the current reset configuration.) ? a variable-sized field can start within a por t boundary only when following a fixed-length field. ? super-fields must end on a port boundary. ? when a variable-length field is sized such that it does not end on a port boundary, it is necessary to extend and zero fill the remain ing bits after the highest order bit so that it can end on a port boundary. ? multiple fixed-length p ackets can start and/or end on a single clock. ? when any packet follows a variable-lengt h packet, it must start on a port boundary. ? the field containing the tcode number is always transferred out first, followed by subsequent fields of information. ? within a field, the lowe st significant bits are shifted out first. figure 31-7 shows the transmission sequence of a message that is made up of a tcode followed by three fields. figure 31-7. transmission sequence of messages 31.7.2.3 ieee 1149.1 -2001 (jtag) tap the npc uses the ieee 1149.1-2001 tap for accessing registers. each of the individual nexus modules on the device implements a tap controller for accessi ng its registers as well. tap signals include tck, tdi, tms, and tdo. detailed info rmation about the tap controller state machine can be found in section 32.4.3, tap controller state machine . the ieee 1149.1-2001 specification can be ordered for further detail on electrical and pin protocol compliance requirements. message tcode field #1 field #2 field #3 field #4 field #5 min. size 1 bits 1 minimum information size. the actual number of bi ts transmitted depends on the number of mdo pins max. size 2 bits 2 maximum information size. the actual number of bi ts transmitted depends on the number of mdo pins device id message 1 fixed = 32 ? ? ? ?3838 field #3 msb lsb 1 2 3 field #2 field #1 tcode 4 6 bits
nexus development interface (ndi) 31-22 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 the npc implements a nexus controller state machin e that transitions based on the state of the ieee ? 1149.1-2001 state machine shown in figure 31-5 . the nexus controller stat e machine is defined by the ieee-isto 5001-2011. it is shown in figure 31-10 . the instructions implemented by the npc tap controller are listed in table 31-13 . the value of the nexus-enable instruction is 0b0000. each unimple mented instruction acts like the bypass instruction. the size of the npc in struction register is 4-bits. data is shifted between tdi and tdo starting with the least signi ficant bit as illustrated in figure 31-8 . this applies for the instruction register and all nexus tool-mapped registers. figure 31-8. shifting data into a register 31.7.2.3.1 enabling the npc tap controller assertion of the power-on reset signal or negating jc omp resets the npc tap controller. when not in power-on reset, the npc tap controller is enabled by asserting jc omp and loading the access_aux_tap_npc instruction in the jtagc. loading the nexus-enable instruction then grants access to npc registers. table 31-13. implemented instructions instruction name private/ public opcode description nexus-enable public 0x0 activate nexus controller state machine to read and write npc registers. bypass private 0xf npc bypass instruction. also the value loaded into the npc ir upon exit of reset. selected register tdo tdi msb lsb
nexus development interface (ndi) freescale semiconductor 31-23 pxr40 microcontroller reference manual, rev. 1 figure 31-9. ieee 1149.1-2001 tap controller state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pau s e - i r exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transi tion in this figure repr esents the value of tms at the time of a rising edge of tck.
nexus development interface (ndi) 31-24 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.7.2.3.2 retrieving device idcode the nexus tap controller does not implement th e idcode instruction. however, the device identification message can be output by the npc through the auxiliary out put port or shifted out serially by accessing the npc device id register through the tap. if the npc is enabled, tr ansmission of the device identification message on the auxiliar y output port mdo pins occurs immediately afte r a write to the pcr. transmission of the device identification message se rially through tdo is achieved by performing a read of the register contents as described in section 31.7.2.3.4, sele cting a nexus client register . 31.7.2.3.3 loading nexus- enable instruction access to the npc registers is enabled by loadi ng the npc nexus-enable instruction when npc has ownership of the tap. this instru ction is shifted in via the select- ir-scan path and loaded in the update-ir state. at this point, the nexus controller state machine, shown in figure 31-10 , transitions to the reg_select state. the nexus controller has three states: idle, register se lect, and data access. table 31-14 illustrates the ieee 1149.1 sequence to load the nexus-enable instruction. figure 31-10. nexus controller state machine table 31-14. loading n exus-enable instruction clock tdi tms ieee 1149.1 stat e nexus state description 0 ? 0 run-test/idle idle ieee 1149.1-2001 tap controller in idle state 1 ? 1 select-dr-scan idle transitional state 2 ? 1 select-ir-scan idle transitional state 3 ? 0 capture-ir idle internal shifter loaded with current instruction 4 ? 0 shift-ir idle tdo becomes active , and the ieee 1149.1-2001 shifter is ready. shift in all but the last bit of the nexus_enable instruction. 5?7 0 0 3 tcks in shift-ir idle 8 0 1 exit1-ir idle last bit of instruction shifted in 9 ? 1 update-ir idle nexus-enable lo aded into instruction register 10 ? 0 run-test/idle reg_select ready to be read/write nexus registers idle nexus-enable=1 reg_select update-dr=1 data_access update-dr=1 nexus-enable=1 && nexus-enable=0 test-logic-reset=1 update-ir=1
nexus development interface (ndi) freescale semiconductor 31-25 pxr40 microcontroller reference manual, rev. 1 31.7.2.3.4 selecting a ne xus client register when the nexus-enable instruction is decoded by the tap controller, the input port allows development tool access to all nexus registers. each regist er has a 7-bit address index. all register access is performed via the select- dr-scan path of the ieee 1149.1?2001 tap controller state machine. the nexus controll er defaults to the reg_select state when enabled. accessing a register requires two passes thr ough the select-dr-scan path: one pass to select the register and the second pass to read/write the register. the first pass through the select-dr-scan path is us ed to enter an 8-bit nexus command consisting of a read/write control bit in th e lsb followed by a 7-bit register address index, as illustrated in figure 31-11 . the read/write control bit is se t to 1 for writes and 0 for reads. the second pass through the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the sh ift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to th e register during the update-dr st ate. when reading a register, there is no requirement to sh ift out the entire register contents. shifting can be te rminated after the required number of bits have been acquired. table 31-15 illustrates a sequence that writ es a 32-bit value to a register. msb lsb 7-bit register index r/w figure 31-11. ieee 1149.1 controller command input table 31-15. write to a 32-bit nexus client register clock tms ieee 1149.1 state n exus state description 0 0 run-test/idle reg_selec t ieee 1149.1-2001 tap controller in idle state 1 1 select-dr-scan reg_select first pass through select-dr-scan path 2 0 capture-dr reg_select internal shifter loaded with current value of controller command input. 3 0 shift-dr reg_select tdo becomes active, and write bit and 6 bits of register index shifted in. 7 tcks 11 1 exit1-dr reg_select last bit of register index shifted into tdi 12 1 update-dr reg_select controller decodes and selects register 13 1 select-dr-scan data_access second pass through select-dr-scan path 14 0 capture-dr data_access internal shifter loaded with current value of register 15 0 shift-dr data_access tdo becomes active, and outputs current value of register while new value is shifted in through tdi 31 tcks 47 1 exit1-dr data_access last bit of current value shifted out tdo. last bit of new value shifted in tdi.
nexus development interface (ndi) 31-26 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.7.2.4 nexus auxiliary port sharing each of the nexus modules on the mc u implements a request/grant scheme to arbitrate for control of the nexus auxiliary port when nexus da ta is ready to be transmitted. all modules arbitrating for the port are given fixed prio rity levels relative to each other. if multiple modules have the same request level, this priority level is used as a tie-breaker. to avoid monopolization of the port, the module given the high est priority level alternates follow ing each grant. immediately out of reset the order of priority, from highest to lo west, is: npc, nz7c3, ndedi, nxdm and nxfr. this arbitration mechanism is controlled internally and is not programmable by tools or the user. 31.7.2.5 nexus jtag port sharing each of the individual nexus modules on the devi ce implements a tap controller for accessing its registers. when jcomp is asserted, only the m odule whose access_aux_tap instruction is loaded has control of the tap (see section 32.4.4, jtagc instructions ). this allows the interface to all of these individual tap controllers to appear to be a single port fr om outside the device. after a nexus module has ownership of the tap, that module act s like a single-bit shift register, or bypass register, if no register is selected as the shift path. 31.7.2.6 mcko mcko is an output clock to the development tools us ed for the timing of mseo and mdo pin functions. mcko is derived from the system clock and its frequency is de termined by the value of the mcko_div[2:0] field in the pcr. possible operating frequencies in clude one-half, one-quarter, and one-eighth system clock speed. mcko is enab led by setting the mcko_en bit in the pcr. the npc also controls dynamic mcko clock gating when in full- or re duced-port modes. the setting of the mcko_gt bit inside the pcr determines whether or not mcko gating control is enabled. the mcko_gt bit resets to a logic 0. in this state gati ng of mcko is disabled. to enable gating of mcko, the mcko_gt bit in the pcr is written to a logic 1. when mcko gating is enabled, mcko is driven to a logic 0 if the auxiliary port is enabled but not transmitting messages and there are no pending messages from nexus clients. 31.7.2.7 evto sharing the npc controls sharing of the evto output between all nexus clients that produce an evto signal. evto is driven for one mcko period wh enever any module drives its evto . when there is no active mcko, such as in disabled mode, the npc assumes an mcko frequenc y of one-half syst em clock speed when driving evto . evto sharing is active as long as the npc is not in reset. 48 1 update-dr data_access value written to register 49 0 run-test/idle reg_select controller returned to idle state. it could also return to select-dr-scan to write another register. table 31-15. write to a 32-bit nexus client register (continued) clock tms ieee 1149.1 state n exus state description
nexus development interface (ndi) freescale semiconductor 31-27 pxr40 microcontroller reference manual, rev. 1 31.7.2.8 nexus reset control the jcomp input that is used as th e primary reset signal for the npc is also used by the npc to generate a single-bit reset signal for other nexus modules. if jc omp is negated, an internal reset signal is asserted, indicating that all nexus modul es must be held in reset. this intern al reset signal is also asserted during a power-on reset. this single bit reset signal f unctions much like the ieee 1149.1-2001 defined trst signal and allows jcomp reset information to be provi ded to the nexus modules wi thout each module having to sense the jcomp signal directly. 31.8 npc initialization and application information 31.8.1 accessing npc to ol-mapped registers to initialize the tap for npc register a ccesses, the following sequence is required: 1. enable the npc tap controller. this is achieved by asserting jcomp and loading the access_aux_tap_npc instruction in the jtagc. 2. load the tap controller with the nexus-enable instruction. to write control data to npc tool-mapped re gisters, the followi ng sequence is required: 1. write the 7-bit register index a nd set the write bit to select the register with a pass through the select-dr-scan path in the ta p controller state machine. 2. write the register value with a second pass through the select- dr-scan path. the prior value of this register is sh ifted out during the write. to read status and control data from npc tool-m apped registers, the following sequence is required: 1. write the 7-bit register index and clear the write bit to sel ect register with a pass through select-dr-scan path in the ta p controller state machine. 2. read the register value with a second pass through the select-dr-scan path. data shifted in is ignored. see the ieee-isto 5001-2011 standard for more detail. 31.9 nexus dual etpu development interface (ndedi) the enhanced timing processor unit (etpu) has its own nexus class 3 interface, the nexus dual etpu development interface (ndedi ). the two etpu engines and a cohere nt dual parameter controller (cdc) appear as three separate nexus clients. see the enhanced time processor unit reference manual for more information about the ndedi module.
nexus development interface (ndi) 31-28 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.10 e200z7 class 3 nexus module (nz7c3) the nz7c3 module provides real-time development capabi lities for the device core in compliance with the ieee-isto 5001-2011 standard. this module provi des development support capabilities without requiring the use of address and data pins for internal visibility. 31.10.1 introduction this section defines the auxiliary pi n functions, transfer protocols and standard development features of the nz7c3 module. the development features suppor ted are program trace, data trace, watchpoint messaging, ownership trace, and read /write access via the jtag interface. reg index: 0 access: r/o 0123456789101112131415 r prn dc pin w reset0000010100100010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pin mic 1 w reset0100000000011101 figure 31-12. ndedi device id register (did) table 31-16. ndedi did regi ster field descriptions field description 0?3 prn part revision number. contains the revision number of the part. this field changes with each revision of the device or module. 4?9 dc design center. indicates the freescale design center. this value is 0x20. 10?19 pin part identification number. contains the part number of the device. the pin for the pxr40 is 0x224. 20?30 mic manufacturer identity code. contains the reduced jo int electron device engineering council (jedec) id for freescale, 0xe. 31 fixed per jtag 1149.1 1 always set
nexus development interface (ndi) freescale semiconductor 31-29 pxr40 microcontroller reference manual, rev. 1 note throughout this section references are made to the auxiliary port and its specific signals, such as mcko, mseo [1:0], mdo[15:0] and others. the device npc module arbitrates the acce ss of the single auxiliary port. to simplify the description of the function of the nz7c3 module, the interaction of the npc is omitted a nd the configuration in this chapter describes an npc with a dedicated aux iliary port. the auxiliary port is fully described in section 31.2, external signal description . 31.10.2 block diagram figure 31-13. e200z7 nexus3 functional block diagram 31.10.3 overview table 31-17 contains a set of terms and definiti ons associated with the nz7c3 module. message queues npc control and i/o logic memory control control/status registers registers dma registers dma (r/w) arbitration data snoop instruction snoop n +1 mdo[n:0] mseo [0] mseo [1] mcko evto evti rdy tdi tdo tms tclk trst breakpoint/ watchpoint control once debug nexus3 module nexus1 module (within core cpu) core cpu virtual bus system bus
nexus development interface (ndi) 31-30 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 31-17. terms and definitions term description ieee-isto 5001 consortium and standard for real-time embedded system design. world wide web documentation at http://www.ieee-isto.org/nexus5001 auxiliary port refers to nexus auxiliary port. used as auxiliary port to the ieee 1149.1 jtag interface. branch trace messaging (btm) visibility of addresses for taken branches and exceptions, and the number of sequential instructions executed between each taken branch. client a functional block on an embedded processor which requires development visibility and controllability. examples are a central processing unit (cpu) or an intelligent peripheral. data read message (drm) external visibility of data reads to memory-mapped resources. data write message (dwm) external visibility of data writes to memory-mapped resources. data trace messaging (dtm) external visibility of how data flows through the embedded system. this can include drm and/or dwm. jtag compliant device complying to i eee 1149.1 jtag standard jtag ir & dr sequence jtag instruction register (ir) scan to load an opcode value for selecting a development register. the jtag ir corresponds to the once command register (ocmd). the selected development register is then accessed via a jtag data register (dr) scan. nexus1 the e200z7 (once) debug module. this module integrated with each e200z7 processor provides all static (core halt ed) debug functionality. this module is compliant with class1 of the ieee-isto 5001 standard. ownership trace message (otm) visibility of process/function that is currently executing. public messages messages on the auxiliary pins for accomplishing common visibility and controllability requirements standard the phrase ?according to the standard? is used to indicate according to the ieee-isto 5001 standard. transfer code (tcode) message header that identifies the number and/or size of packets to be transferred, and how to interpret each of the packets. watchpoint a data or instruction breakpoint which does not cause the processor to halt. instead, a pin is used to signal that the condition occurred. a watchpoint message is also generated.
nexus development interface (ndi) freescale semiconductor 31-31 pxr40 microcontroller reference manual, rev. 1 31.10.4 features the nz7c3 module is compliant with class 3 of the ieee-isto 5001-2011 standard. the following features are implemented: ? program trace via branch trace messaging (btm). branch trace me ssaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), al lowing the development tool to interpolate what transpires between the disc ontinuities. thus static code can be traced. ? data trace via data write messaging (dwm) and data read messaging (drm ). this provides the capability for the development tool to trace re ads and/or writes to selected internal memory resources. ? ownership trace via ownership trace messagi ng (otm). otm facilitates ownership trace by providing visibility of which pro cess id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. ? run-time access to embedded processor registers an d memory map via the jtag port. this allows for enhanced download/upload capabilities. ? watchpoint messaging via the auxiliary pins. ? watchpoint trigger enable of pr ogram and/or data trace messaging. ? high-speed data input/output via the auxiliary port. ? auxiliary interface for higher data input/output ? configurable (minimum and ma ximum) message data out pins ? one read/write ready pin ? one watchpoint-event pin ? one event-in pin ? one mcko (message clock out) pin ? registers for program trace , data trace, ownership trace and watchpoint trigger. ? all features controllable and configurable via the jtag port. 31.10.5 enabling nexus3 operation the nexus module is enabled by lo ading a single instruction (access_aux_tap_once, as shown in table 31-4 ) into the jtagc instruction register (ir), and then loading the corresponding once ocmd register with the nexus 3_access instruction (see table 31-5 ). for the e200z7 cl ass 3 nexus module, the ocmd value is 0b00_0111_1100. after it is enabled, the module is ready to accept control input via the jtag pins. see section 31.7, npc func tional description , for more information. the nexus module is disabled when the jtag state machine reaches the te st-logic-reset state. this state can be reached by asserti ng the jcomp pin or cycling through the state machine using the tms pin. the nexus module is also disabled if a power-on-reset (por) event occurs. if the nexus3 module is disabled, no trace output is provided, and the module disables (d rive inactive) auxiliary port output pins mdo[n:0], mseo [1:0], mcko. nexus registers are not available for reads or writes.
nexus development interface (ndi) 31-32 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.10.6 tcodes supported by nz7c3 the nexus3 pins allow for flexible transfer operations via public message s. a tcode defines the transfer format, the number and/or size of the packets to be transferred, and the pur pose of each packet. the ieee-isto 5001-2011 standard defines a set of public messages. the nz7c3 m odule supports the public tcodes seen in table 31-18 . each message contains multiple packet s transmitted in the order shown in the table. table 31-18. public tcodes supported by nz7c3 message name packet size (bits) packet name packet type packet description min max debug status 6 6 tcode fixed tcode number = 0 (0x00) 4 4 src fixed source processor identifier 8 8 status fixed development status register (ds[31:24]) ownership trace message 6 6 tcode fixed tcode number = 2 (0x02) 4 4 src fixed source processor identifier 32 32 process fixed task/process id tag program trace - direct branch message 1 6 6 tcode fixed tcode number = 3 (0x03) 4 4 src fixed source processor identifier 1 8 i-cnt variable number of sequential instructions executed since last taken branch program trace - indirect branch message 1 6 6 tcode fixed tcode number = 4 (0x04) 4 4 src fixed source processor identifier 1 8 i-cnt variable number of sequential instructions executed since last taken branch 1 32 u-addr variable unique part of target address for taken branches/exceptions data trace - data write message 6 6 tcode fixed tcode number = 5 (0x05) 4 4 src fixed source processor identifier 3 3 dsiz fixed data size (see table 31-22 ) 1 32 u-addr variable unique portion of the data write address 1 64 data variable data write values (see section 31.14.6, data trace , for details)
nexus development interface (ndi) freescale semiconductor 31-33 pxr40 microcontroller reference manual, rev. 1 data trace - data read message 6 6 tcode fixed tcode number = 6 (0x06) 4 4 src fixed source processor identifier 3 3 dsiz fixed data size (see table 31-22 ) 1 32 u-addr variable unique portion of the data read address 1 64 data variable data read values (see section 31.14.6, data trace , for details) error message 6 6 tcode fixed tcode number = 8 (0x08) 4 4 src fixed source processor identifier 5 5 ecode fixed error code program trace - direct branch message w/ sync 1 6 6 tcode fixed tcode number = 11 (0x0b) 4 4 src fixed source processor identifier 1 8 i-cnt variable number of sequential instructions executed since last taken branch 1 32 f-addr variable full target address (leading zeros truncated) program trace - indirect branch message w/ sync 1 6 6 tcode fixed tcode number = 12 (0x0c) 4 4 src fixed source processor identifier 1 8 i-cnt variable number of sequential instructions executed since last taken branch 1 32 f-addr variable full target address (leading zeros truncated) data trace - data write message w/ sync 6 6 tcode fixed tcode number = 13 (0x0d) 4 4 src fixed source processor identifier 3 3 dsz fixed data size (see table 31-22 ) 1 32 f-addr variable full access address (leading zeros truncated) 1 64 data variable data write values (see section 31.14.6, data trace , for details) data trace - data read message w/ sync 6 6 tcode fixed tcode number = 14 (0x0e) 4 4 src fixed source processor identifier 3 3 dsz fixed data size (see table 31-22 ) 1 32 f-addr variable full access address (leading zeros truncated) 1 64 data variable data read values (see section 31.14.6, data trace , for details) table 31-18. public tcodes supported by nz7c3 (continued) message name packet size (bits) packet name packet type packet description min max
nexus development interface (ndi) 31-34 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 table 31-19 shows the error code encodings used when reporting an erro r via the nexus3 error message. watchpoint message 6 6 tcode fixed tcode number = 15 (0x0f) 4 4 src fixed source processor identifier 4 4 wphit fixed number indicating watchpoint sources resource full message 6 6 tcode fixed tcode number = 27 (0x1b) 4 4 src fixed source processor identifier 4 4 rcode fixed resource code indicates which resource is the cause of this message (see rcode values in ta b l e 3 1 - 2 1 ) 1 32 rdata variable branch / predicate instruction history (see section 31.13.1, branch trace messaging (btm) ) program trace - indirect branch history message 6 6 tcode fixed tcode number = 28 (0x1c) (see footnote 1 below) 4 4src fixed source processor identifier 1 8 i-cnt variable number of sequential instructions executed since last taken branch 1 32 u-addr variable unique part of target address for taken branches/exceptions 1 32 hist variable branch / predicate instruction history (see section 31.13.1, branch trace messaging (btm) ) program trace - indirect branch history message w/ sync 6 6 tcode fixed tcode number = 29 (0x1d) (see footnote 1 below) 4 4src fixed source processor identifier 1 8 i-cnt variable number of sequential instructions executed since last taken branch 1 32 f-addr variable full target address (leading zero (0) truncated) 1 32 hist variable branch / predicate instruction history (see section 31.13.1, branch trace messaging (btm) ) program trace - program correlation message 6 6 tcode fixed tcode number = 33 (0x21) 4 4src fixed source processor identifier 4 4 evcode fixed event correlated w/ program flow (see table 31-21 ) 1 8 i-cnt variable number of sequential instructions executed since last taken branch 1 32 hist variable branch / predicate instruction history (see section 31.13.1, branch trace messaging (btm) ) 1 you can select between the two types of program trace. the advantages for each are discussed in section 31.13.1, branch trace messaging (btm) . if the branch history method is selected, the shaded tcodes above are not messaged out. table 31-18. public tcodes supported by nz7c3 (continued) message name packet size (bits) packet name packet type packet description min max
nexus development interface (ndi) freescale semiconductor 31-35 pxr40 microcontroller reference manual, rev. 1 table 31-20 shows the encodings used for res ource codes for certain messages. table 31-21 shows the event code encodings used for certain messages. table 31-22 shows the data trace size encodings used for certain messages. table 31-19. error code encoding (tcode = 8) error code (ecode) description 00000 ownership trace overrun 00001 program trace overrun 00010 data trace overrun 00011 read/write access error 00101 invalid access opcode (nexus register unimplemented) 00110 watchpoint overrun 00111 (program trace or data trace) and ownership trace overrun 01000 (program trace or data trace or ow nership trace) and watchpoint overrun 01001?10111 invalid value 11000 btm lost due to collision w/ higher priority message 11001?11111 invalid value table 31-20. rcode values (tcode = 27) resource code (rcode) description resource data (rdata) 0000 program trace instruction counter overflow (reached 255 and was reset) 0xff 0001 program trace, branch and predicate instruction history. this type of packet is terminated by a stop bit set to 1 after the last history bit. branch history. this type of packet is terminated by a stop bit set to a 1 after the last history bit. table 31-21. event code encoding (tcode = 33) event code description 0000 entry into debug mode 0001 entry into low power mode (cpu only) 1 1 the device enters low power mode when the nexus stall mode is enabled (nz7c3_dc1[ovc]=0b011) and a trace message is in danger of over-flowing the nexus queue. 0010?0011 invalid value. reserved for future functionality 0100 disabling program trace
nexus development interface (ndi) 31-36 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note program trace can be implemented usi ng either branch history/predicate instruction messages, or tr aditional direct and indir ect branch messages. the user can select between th e two types of program tr ace. the advantages for each are discussed in section 31.13.1, branch trace messaging (btm) . if the branch history method is sel ected, the shaded tcodes are not messaged out. 31.11 nz7c3 memory map and register definition refer to the nexus 3 program mer?s model section in the e200z7 powerpc tm core reference manual for the description of the nz7c3 programmer?s model. nz7c3 registers are acces sed using the jtag/once port in compliance with ieee 1149.1. note nexus 3 registers and output signals ar e numbered using bit 0 as the least significant bit. this bit ordering is consistent with the ordering defined by the ieee-isto 5001 standard. table 31-22. data trace size encodings (tcode = 5, 6, 13, 14) dtm size encoding transfer size 000 byte 001 halfword (two bytes) 010 word (four bytes) 011 doubleword (eight bytes) 100 string (three bytes) 101?111 invalid value table 31-23. nz7c3 memory map nexus register nexus access opcode read/write read address write address client select control (csc) 1 0x1 r 0x02 ? port configuration register (pcr) 1 pcr_index2 r/w ? ? development control 1 (dc1) 0x2 r/w 0x04 0x05 development control 2 (dc2) 0x3 r/w 0x06 0x07 development control 3 (dc3) 0x4 r/w 0x08 0x09 development control 4 (dc4) 0x5 r/w 0x0a 0x0b read/write access control/status (rwcs) 0x7 r/w 0x0e 0x0f read/write access address (rwa) 0x9 r/w 0x12 0x13
nexus development interface (ndi) freescale semiconductor 31-37 pxr40 microcontroller reference manual, rev. 1 31.11.1 nz7c3 register access via jtag / once access to nexus3 register resources is enabled by loading a single instruction (access_aux_tap_once) into th e jtagc instruction register (ir), and then loading the corresponding once ocmd register with the nexus3_access instruction (see table 31-5 ). for the nz7c3 module, the ocmd value is 0b00_0111_1100. read/write access data (rwd) 0xa r/w 0x14 0x15 watchpoint trigger (wt) 0xb r/w 0x16 0x17 reserved 0xc r/w 0x18 0x19 data trace control (dtc) 0xd r/w 0x1a 0x1b data trace start address 1 (dtsa1) 0xe r/w 0x1c 0x1d data trace start address 2 (dtsa2) 0xf r/w 0x1e 0x1f data trace start address 3 (dtsa3) 0x10 r/w 0x20 0x21 data trace start address 4 (dtsa4) 0x11 r/w 0x22 0x23 data trace end address 1 (dtea1) 0x12 r/w 0x24 0x25 data trace end address 2 (dtea2) 0x13 r/w 0x26 0x27 data trace end address 3 (dtea3) 0x14 r/w 0x28 0x29 data trace end address 4 (dtea4) 0x15 r/w 0x2a 0x2b reserved 0x16 ? 0x2f ? 0x28 ? 0x5e 0x29 ? 0x5f development status (ds) 0x30 r 0x60 ? reserved 0x31 r/w 0x62 0x63 overrun control (ovcr) 0x32 r/w 0x64 0x65 watchpoint mask (wmsk) 0x33 r/w 0x66 0x67 reserved 0x34 ? 0x68 0x69 program trace start trigger control (ptstc) 0x35 r/w 0x6a 0x6b program trace end trigger control (ptetc) 0x36 r/w 0x6c 0x6d data trace start trigger control (dtstc) 0x37 r/w 0x6e 0x6f data trace end trigger control (dtetc) 0x38 r/w 0x70 0x71 reserved 0x39 ? 0x3f ? 0x72 ? 0x7e 0x73 ? 0x7f 1 the csc and pcr registers are shown in this table as part of the nexus programmer?s model. they are only present at the top level nexus contro ller in a multi-nexus implementation, not in the nexus 3 module. the csc register is readable through nexus, but the pcr is shown for reference only here. table 31-23. nz7c3 memory map (continued) nexus register nexus access opcode read/write read address write address
nexus development interface (ndi) 31-38 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 after the access_aux_tap_once instruction ha s been loaded, the jtag/once port allows tool/target communications with all nexus3 registers accordi ng to the register map in table 31-23 . reading/writing of a nz7c3 register then requires two (2) passes through the data-s can (dr) path of the jtag state machine (see 31.14.10). 1. the first pass through the dr sel ects the nz7c3 register to be accessed by providing an index (see table 31-23 ), and the direction (read/write). this is achieved by loading an 8-bit value into the jtag data register (dr). this re gister has the following format: 2. the second pass through the dr then shifts the data in or out of the jtag port, lsb first. a) during a read access, data is latched from the selected nexus register when the jtag state machine passes through the capture-dr state. b) during a write access, data is latched into th e selected nexus register when the jtag state machine passes through the update-dr state. 31.12 ownership trace this section details the ownership trace features of the nz7c3 module. ownership trace provides a macrosc opic view, such as task flow re construction, when debugging software written in a high level (or object-orien ted) language. it offers the highest level of abstraction for tracking operating system software ex ecution. this is especially useful when the developer is not interested in debugging at lower levels. 31.12.1 ownership trace messaging (otm) ownership trace information is messaged via the aux iliary port using an owners hip trace message (otm). the e200z7 processor contains a power architecture book e defined process id register within the cpu. the process id register is updated by the operating system soft ware to provide task/process id information. the contents of this re gister are replicated on the pins of the processor and connected to nexus. the process id register value can be accessed using the mfspr / mtspr instructions. please see the e200z7 powerpc tm core reference manual for more details on the process id register. the only condition that causes an ownership trace mess age occurs when the otr register is updated or process id register by the e200z7 proc essor, the data is latched within nexus, and is messaged out via the auxiliary port, allowing developmen t tools to trace ownership flow. nexus register index: selected from values in table 31-23 read/write (r/w): 0 read 1write nexus register index (7-bits) (1-bit) r/w reset value: 0x00
nexus development interface (ndi) freescale semiconductor 31-39 pxr40 microcontroller reference manual, rev. 1 ownership trace information is mess aged out in the following format: figure 31-14. ownership trace message format 31.12.2 otm error messages an error message occurs when a ne w message cannot be queued due to the message queue being full. the fifo discards incoming messag es until the queue the queue is completely empty. after it empties, an error message is queued. the error encoding indicate the me ssage types denied service to the queue while the fifo was emptying. if an otm message only attempts to enter the que ue while the queue is emptying, the error message incorporates the otm error encoding (00000) only. if otm and either btm or dtm messages attempt to enter the queue, the error message incorporates th e otm and (program or data) trace error encoding (00111). if a watchpoint also atte mpts to enter the queue while the fifo is emptying, then the error message incorporates error encoding (01000). note the ovc bits within the dc1 register can be set to delay the cpu to alleviate (but not eliminate) potential overrun situations. error information is messaged out in the following format (see table 31-19 ): figure 31-15. error message format 31.12.3 otm flow ownership trace messages are generated when the op erating system writes to the e200z7 process id register or the memory mapped ownership trace register. the following flow desc ribes the otm process: 1. the process id register is a syst em control register. it is intern al to the e200z7 processor and can be accessed by using ppc instructions mtspr and mfspr . the contents of this register are replicated on the pins of the processor and connected to nexus. 2. otr/process id register reads do not cause ow nership trace messages to be transmitted by the nz7c3 module. process msb lsb 1 2 src tcode (000010) 3 6 bits 4 bits 32 bits fixed length = 42 bits ecode (00000 / 00111 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits
nexus development interface (ndi) 31-40 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 3. if the periodic otm message counter expires (after 255 queued messages without an otm), an otm is sent using the latched data from the previous otm or process id register write. 31.13 program trace this section details the program trace mechanism supported by nz7c3 fo r the pxr40 processor. program trace is implemented via branch tr ace messaging (btm) as per the cl ass 3 ieee-isto 5001-2011 standard definition. branch trace me ssaging for e200z7 processors is acco mplished by snooping the e200z7 virtual address bus (between the cpu and mmu), attribute signals, and cpu status. 31.13.1 branch trace messaging (btm) traditional branch trace messaging facilitates pr ogram trace by providing the following types of information: ? messages generated for direct branches that were taken indicate the number of sequential instructions executed since the last branch or exce ption. branches not taken (direct or indirect) are not counted as sequential instructions. ? messages generated for indire ct branches and exceptions that were taken indicate: ? number of sequential instructions executed since the last branch that was taken ? exception with the unique portion of the branch target address or exception vector address ? history field in the branch and predicate instruct ions that can generate th e following messages for program trace: ? number of sequential inst ructions executed since the last indi rect branch was taken, as well as the unique portion of the indirect branch address ? number of sequential instructi ons executed since the last excep tion was processed, as well as the unique portion of the exception vector address ? number of sequential instructions executed si nce the last predicate instruction was taken ? history field in the branch and predicate inst ruction unique to the bran ch target address or exception vector address. each bi t in the history field represents a direct branch or predicated instruction where a value of one (1) indicates taken, and a value of zero (0) indicates not taken. certain instructions ( evsel ) generate a pair of predicate bits which are both reported as consecutive bits in the history field. 31.13.1.1 e200z7 indirect branch message instructions (power architecture book e) table 31-24 shows the types of instructions and events wh ich cause indirect branch messages or branch history messages to be encoded. table 31-24. indirect branch message sources source of indirect bran ch message instructions taken branch relative to a register value bcctr, bcctrl, bclr, bclrl
nexus development interface (ndi) freescale semiconductor 31-41 pxr40 microcontroller reference manual, rev. 1 31.13.1.2 e200z7 direct branch message instructions (power architecture book e) table 31-25 shows the instruction t ypes that cause direct br anch messages, or toggle a bit in the instruction history buffer in a resource full message or br anch history message before it is sent out. 31.13.1.3 btm using branch history messages traditional btm messaging can accurately track the number of sequential instru ctions between branches, but cannot accurately indicate whic h instructions were conditionall y executed, and which were not. branch history messaging solves this problem by provi ding a predicated instruction history field in each indirect branch message. each bit in the history repr esents a predicated instruction or direct branch. a value of one (1) indicates the conditi onal instruction was executed or th e direct branch was taken. a value of zero (0) indicates the conditional instruction was not executed or the direct branch was not taken. certain instructions ( evsel ) generate a pair of predic ate bits which are both repor ted as consecutive bits in the history field. branch history messages solve predicated instructi on tracking and save bandwi dth since only indirect branches cause messages to be queued. 31.13.1.4 btm using traditional program trace messages based on the ptm bit in the dc register (dc[ptm]), program tracing can use: ? branch history messages (dc[ptm] = 1); or ? traditional direct and indirect branch messages (dc[ptm] = 0) branch history saves bandwidth a nd keeps consistency between method s of program trace, yet can lose temporal order between btm messages and other t ypes of messages. since di rect branches are not messaged, but are instead incl uded in the history field of the indire ct branch history message, other types of messages can enter the fifo between branch hist ory messages. the developm ent tool cannot determine the order of ?events? that occurred for direct br anches by the order in which messages are sent out. system call / trap exceptions taken sc, tw, twi return from interrupts / exceptions rfi, rfci, rfdi table 31-25. direct branch message sources source of direct branch message instructions taken direct branch instructions b, ba, bl, bla, bc, bca, bcl, bcla instruction synchronize isync table 31-24. indirect branch message sources (continued) source of indirect bran ch message instructions
nexus development interface (ndi) 31-42 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 traditional btm messages maintain their temporal ordering because each event that queues a message to the fifo is processed and sent in the order it was ge nerated, and the message order is maintained when it is transmitted. 31.13.2 btm message formats the e200z7 nexus3 module supports three types of tr aditional btm messages?direct, indirect, and synchronization messages. it suppor ts two types of branch histor y btm messages?indirect branch history, and indirect branch history with sync hronization messages. debug st atus messages and error messages are also supported. 31.13.2.1 indirect branch messages (history) indirect branches include all taken branches whose de stination is determined at run time, interrupts and exceptions. if dc[ptm] is set, indi rect branch information is messag ed out in the following format: figure 31-16. indirect branch message (history) format 31.13.2.2 indirect branch messages (traditional) if dc[ptm] is cleared, indirect branch inform ation is messaged out in the following format: figure 31-17. indirect branch message format 31.13.2.3 direct branch messages (traditional) direct branches (conditional or uncondi tional) are all taken branches w hose destination is fixed in the instruction opcode. direct br anch information is messaged out in the following format: hist msb lsb 2 3 4 u-addr i-cnt src 5 4 bits 1 tcode (011100) 1?8 bits 1?32 bits 1?32 bits 6 bits max length = 82 bits; min length = 13 bits msb lsb 2 3 4 u-addr i-cnt src 4 bits 1 tcode (000100) 1?8 bits 1?32 bits 6 bits max length = 50 bits; min length = 12 bits
nexus development interface (ndi) freescale semiconductor 31-43 pxr40 microcontroller reference manual, rev. 1 figure 31-18. direct branch message format note when dc[ptm] is set, direct branch messages are not tr ansmitted. instead, each direct branch or predicated in struction toggles a bit in the history buffer. 31.13.2.4 resource full messages the resource full message is used in conjunction with the branch history mess ages. the resource full message is generated when the intern al branch/predicate history buffer is full, or if the btm instruction sequence counter (i-cnt) overflows. if synchronization is needed at the time this message is generated, the synchronization is delayed until th e next branch trace message that is not a resource full message. the current value of the history buffer is transmitted as part of the resource full message. this information can be concatenated by the tool wi th the branch/predicate history in formation from subsequent messages to obtain the complete branch history for a message. th e internal history value is reset by this message, and the i-cnt value is reset as a result of a bit being added to the history buffer. figure 31-19. resource full message format 31.13.2.5 debug status messages note debug status messages (dsms) are enab led if the nexus module is enabled. debug status messages report low pow er mode and debug status. enteri ng/exiting debug mode as well as entering a low power mode tri ggers a debug status message. debug status information is sent out in the following format: figure 31-20. debug status message format i-cnt msb lsb 1 2 src tcode (000011) 3 6 bits 4 bits 1?8 bits max length = 18 bits; min length = 11 bits tcode (011011) rcode (6 bits) (4 bits) src. proc. (4 bits) max length = 46 bits; min length = 15 bits (1??32 bit rdata status [31:24] msb lsb 1 2 src tcode (000000) 3 6 bits 4 bits 8 bits fixed length = 18 bits
nexus development interface (ndi) 31-44 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.13.2.6 program correlation messages program correlation messages are used to correlate events to the program flow that are not necessarily associated with the instruction stre am. to maintain accurate instructi on tracing information when entering debug mode or a cpu low power mode (where tracing can be disabled), this message is sent upon entry into one of these two modes and incl udes the instruction coun t and branch history. program correlation is messaged out in the following format: figure 31-21. program correlation message format 31.13.2.7 btm overflow error messages an error message occurs when a new message cannot be queued because the message queue is full. the fifo discards incoming messages until the queue is completely empty. after it is empty, an error message is queued. the error encoding indicat es which message types were deni ed queueing while the fifo was emptying. if only a program trace message attempts to enter the queue while it is being emptied, the error message incorporates the program trace onl y error encoding (00001). if both otm and program trace messages attempt to enter the queue, the error message inco rporates the otm and program trace error encoding (00111). if a watchpoint also attempts to be queu ed while the fifo is being emptied, then the error message incorporates error encoding (01000). note the ovc bits within the dc1 register can be set to delay the cpu to alleviate (but not eliminate) potential overrun situations. error information is messaged out in the following format: figure 31-22. error message format 31.13.3 program trace synchronization messages a program trace direct/indirect branch with sync message is messaged via the auxiliary port (provided program trace is enabled) for the following conditions (see table 31-26 ): ? initial program trace message upon the first direct/in direct branch after exit from system reset or whenever program trace is enabled hist msb lsb 2 3 4 i-cnt evcode src 5 4 bits 1 tcode (100001) 4 bits 1?8 bits 1?32 bits 6 bits max length = 54 bits; min length = 16 bits ecode (00001 / 00111 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits
nexus development interface (ndi) freescale semiconductor 31-45 pxr40 microcontroller reference manual, rev. 1 ? upon direct/indirect branch after re turning from a cpu low power state ? upon direct/indirect branch af ter returning from debug mode ? upon direct/indirect branch after occurrence of queue overrun (can be caused by any trace message), provided program trace is enabled ? upon direct/indirect branch after the periodic program trace counter has expired indicating 255 without-sync program trace messages have occurred since the last with-sync message occurred ? upon direct/indirect branch after a ssertion of the event in (evti) pi n if the eic bits within the dc1 register have enabled this feature ? upon direct/indirect branch after the sequentia l instruction counter has expired indicating 255 instructions have occurred between branches ? upon direct/indirect branch after a btm message was lost due to an attempte d access to a secure memory location. ? upon direct/indirect branch after a btm message was lost due to a collision entering the fifo between the btm message and either a watchpoi nt message or an ownership trace message if the nz7c3 module is enabled at re set, a evti assertion in itiates a program trace direct/indirect branch with sync message (if program trac e is enabled) upon the first direct /indirect branch. the format for program trace direct/indire ct branch with sync me ssages is as follows: figure 31-23. direct/indirect bran ch with sync message format the formats for program trace direct/i ndirect branch with sync . messages and indirect branch history with sync. messages are as follows: figure 31-24. indirect branch history with sync. message format exception conditions that resu lt in program trace synchr onization are summarized in table 31-26 . table 31-26. program trace exception summary exception condition exception handling system reset negation at the negation of jtag reset (j comp), queue pointers, counters, state machines, and registers within the nz7c3 module are reset. upon the first branch out of system reset (if program trace is enabled), the first prog ram trace message is a direct/indirect branch with sync. message. msb lsb 2 3 4 f-addr i-cnt src 4 bits 1 tcode (001011 or 001100) 1?8 bits 1 ? 32 bits 6 bits max length = 50 bits; min length = 12 bits hist msb lsb 2 3 4 f-addr i-cnt src 5 4 bits 1 tcode (011101) 1?8 bits 1?32 bits 1?32 bits 6 bits max length = 82 bits; min length = 13 bits
nexus development interface (ndi) 31-46 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.14 btm operation 31.14.1 enabling program trace both types of branch trace messaging can be enabled in one of two ways: ? setting the tm field of th e dc1 register to enable program trace (dc1[tm]) ? using the pts field of the wt register to en able program trace on wa tchpoint hits (e200z7 watchpoints are configured within the cpu) program trace enabled the first program trace message (after program trace has been enabled) is a synchronization message. exit from low power/debug upon exiting from the low po wer or debug modes, the next direct/indirect branch is converted to a direct/indirect branch with sync. message. queue overrun an error message occurs when a new message cannot be queued due to the message queue being full. the fifo discards messages until the queue is completely empty. after it is empty, an error message is queued. th e error encoding indicates the message types denied queueing while the fifo was emptyi ng. the next btm message in the queue is a direct/indirect branch with sync. message. periodic program trace sync. a forced synchronization occurs periodically after 255 program trace messages have been queued. a direct/indirect branch with syn c. message is queued. the periodic program trace message counter then resets. event in if the nexus module is enabled, an evti assertion initiates a direct/indirect branch with sync. message upon the next direct/indirect branch (if program trace is enabled and the eic bits of the dc1 register have enabled this feature). sequential instruction count overflow when the sequential instruction counter reaches its maximum count (up to 255 sequential instructions can be execut ed), a forced synchronization occurs. the sequential counter then resets. a program trace direct/indirect branch with sync.message is queued upon execution of the next branch. attempted access to secure memory for devices which implement security, any attempt to branch to secure memory locations temporarily disables program trace and cause the corresponding btm to be lost. the following direct/indirect branch queues a direct /indirect branch with sync. message. the count value within this message can be inaccurate since re-enabling program trace does not guarantee alignment on an instruction boundary. collision priority all messages have the following priority: wpm ? otm ? btm ? dtm. a btm message which attempts to enter the queue at the same time as a watchpoint message or ownership trace message is lost. an error message is sent indicating the btm was lost. the following direct/indirect branch queues a direct/indirect branch with sync. message. the count value within this message reflects the number of sequential instructions executed after the last successful btm mess age was generated. this count includes the branch which did not generate a message due to the collision. table 31-26. program trace exception summary (continued) exception condition exception handling
nexus development interface (ndi) freescale semiconductor 31-47 pxr40 microcontroller reference manual, rev. 1 31.14.2 relative addressing the relative address feature is compliant with the ieee-isto 5001-201 1 standard recommendations, and is designed to reduce the number of bits transmit ted for addresses of i ndirect branch messages. the address transmitted is relative to the target a ddress of the instruction which triggered the previous indirect branch (or sync) message. it is generated by xor?ing the new address with the previous address, and then using only the result s up to the most significant 1 in the result. to recreate this address, an xor of the (most-significant 0-padded) me ssage address with the previously decoded addr ess gives the current address. previous address (a1) =0x0003fc01, new address (a2) = 0x0003f365 figure 31-25. relative address generation and re-creation 31.14.3 branch and predicate instruction history (hist) if dc[ptm] is set, btm messaging us es the branch history format. the branch history (hist) packet in these messages provides a history of direct branch execution used for reconstructing the program flow. this packet is implemented as a left -shifting shift register. the register is always pre-loaded with a value of one (1). this bit acts as a stop bit so that the de velopment tools can determine which bit is the end of the history information. the pre-loaded bit itself is not part of the history, but is transmitted with the packet. a value of one (1) is shifted into the history buffer on a taken branch (condition or unc onditional) and on any instruction whose predicate condition executed as tr ue. a value of zero (0) is shifted into the history buffer on any instruction whose predicate condition ex ecuted as false as well as on branches not taken. this includes indirect as well as di rect branches were not taken. for the evsel instruction, two bits are shifted in, corresponding to the low el ement (shifted in first) and the high element (shifted in second) conditions. message generation: a1 = 0000 0000 0000 0011 1111 1100 0000 0001 a2 = 0000 0000 0000 0011 1111 0011 0110 0101 a1 a2 = 0000 0000 0000 0000 0000 1111 0110 0100 address message (m1) = 1111 0110 0100 address re-creation: a1 m1 = a2 a1 = 0000 0000 0000 0011 1111 1100 0000 0001 m1 = 0000 0000 0000 0000 0000 1111 0110 0100 a2 = 0000 0000 0000 0011 1111 0011 0110 0101
nexus development interface (ndi) 31-48 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.14.4 sequential inst ruction count (i-cnt) the i-cnt packet, is present in all btm messages. fo r traditional branch messag es, i-cnt represents the number of sequential instructions, or non-taken branches in between direct/indirect br anch messages. for branch history messages, i-cnt represents the number of instructions executed since the last taken/non-taken direct branch, last taken indirect branch or exception. not taken indirect branches are considered sequential instructions a nd cause the instruction count to incr ement. i-cnt also represents the number of instructions executed si nce the last predicate instruction. the sequential instruction counter overflows when its value reaches 255. the next btm message is converted to a synchr onization type message. 31.14.5 program trace queueing nz7c3 implements a message queue. me ssages that enter the queue are tr ansmitted via the auxiliary pins in the order in which they are queued. note if multiple trace messages must be queued at the same time, watchpoint messages have the highest priority (wpm ? otm ? btm ? dtm). 31.14.5.1 program trace timing diagrams figure 31-26. program trace (mdo = 12)?indirect branch message (traditional) figure 31-27. program trace (mdo = 2)?indirect branch message (history) mcko mseo [1:0] tcode = 4 source processor = 0b0000 number of sequence instructions = 128 relative address = 0xa5 01 11 00 mdo[11:0] 0000 0010 0000 0000 1010 0101 0000 0000 0100 tcode = 28 mcko mseo source processor = 0b0000 number of sequential instructions = 0 relative address = 0xa5 branch history = 0b1010_0101 (with stop) mdo[1:0] 11 01 00 00 00 01 01 10 10 01 01 10 10 00 00
nexus development interface (ndi) freescale semiconductor 31-49 pxr40 microcontroller reference manual, rev. 1 figure 31-28. program trace?direct branch (traditional) and error messages figure 31-29. program trace?indirect branch with sync. message 31.14.6 data trace this section deals with the data trace mechan ism supported by the nz7c3 module. data trace is implemented via data write messag ing (dwm) and data read messaging (drm), as per the ieee-isto 5001-2011 standard. 31.14.6.1 data trace messaging (dtm) data trace messaging for e200z7 is accomplished by snooping the e200z7 virtual data bus (between the cpu and mmu), and storing the information for qu alifying accesses (based on enabled features and matching target addresses). the nz 7c3 module traces all data access th at meet the selected range and attributes. note data trace is only perfor med on the e200z7 virtual da ta bus. this allows for data visibility for the incorporated data cache. only e200z7 cpu initiated accesses are traced. no dma accesses to the nxdm system bus are traced. data trace messaging can be enabled in one of two ways: ? setting the tm field of the dc1 register to enab le data trace (dc1[tm]). ? using wt[dts] to enable data tr ace on watchpoint hits (e200z7 wa tchpoints are configured within the nexus1 module) dbm: mcko mseo tcode = 3 source processor = 0b0000 number of sequential instructions = 3 mdo[1:0] 00 00 00 00 11 00 00 10 00 00 00 01 00 00 error: tcode = 8 source processor = 0b0000 error code = 1 (queue overrun ? btm only) error direct branch 11 tcode = 12 mcko mseo source processor = 0b0000 number of sequential instructions = 3 full target address = 0xdead_face mdo[1:0] 00 11 00 00 00 11 10 11 00 11 10 10 11 11 01 11 10 10 10 11 01 11 00
nexus development interface (ndi) 31-50 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.14.6.2 dtm message formats the nexus3 module supports five types of dtm me ssages: data write, da ta read, data write synchronization, data read synchronization and error messages. 31.14.6.2.1 data write messages the data write message contains the data write value and the address of the write access, relative to the previous data trace message. data write message info rmation is messaged out in the following format: figure 31-30. data write message format 31.14.6.2.2 data read messages the data read message contains the data read value and the address of the read access, relative to the previous data trace message. data read message in formation is messaged out in the following format: figure 31-31. data read message format note for the e200z7 based cpu, th e doubleword encoding (data size = 0b000) indicates a doubleword acce ss and sends out as a si ngle data trace message with a single 64-bit data value. 31.14.6.2.3 dtm overfl ow error messages an error message occurs when the ne xt message is denied service becau se the message queue is full. the fifo discards all incoming messages until the queue is completely empty. after it is empty, an error message is queued that indicates the message types denied into the queue while the fifo is emptying. if a data trace message only attempts to enter the queue whil e it is emptying, the error message incorporates the data trace only error encoding (00010). if both otm and data trace messages attempt to enter the queue, the error message incorporates the otm and data trace error enc oding (00111). if a watchpoint also attempts to be queued while the fifo is being emptied, then the error message incorporates error encoding (01000). data msb lsb 2 3 4 u-addr dsz src 5 4 bits 1 tcode (000101) 3 bits 1?32 bits 1?64 bits 6 bits max length = 109 bits; min length = 15 bits data msb lsb 2 3 4 u-addr dsz src 5 4 bits 1 tcode (000110) 3 bits 1?32 bits 1?64 bits 6 bits max length = 109 bits; min length = 15 bits
nexus development interface (ndi) freescale semiconductor 31-51 pxr40 microcontroller reference manual, rev. 1 note the ovc bits within the dc1 register can be set to delay the cpu to alleviate (but not eliminate) potential overrun situations. error information is messaged out in the following format: figure 31-32. error message format 31.14.6.2.4 data trace s ynchronization messages a data trace write/read with sync. message is messaged via the auxili ary port (provided data trace is enabled) for the following conditions (see table 31-27 ): ? initial data trace message after exit from syst em reset or whenever data trace is enabled ? upon exiting debug mode ? after occurrence of queue overr un (can be caused by any trace mess age), provided data trace is enabled ? after the periodic data trace counter has expired indicating 255 without-sync data trace messages have occurred since the last with-sync message occurred ? upon assertion of the event in (evti) pin, the firs t data trace message is a synchronization message if the eic bits of the dc1 regi ster have enabled this feature ? upon data trace write/read after the previous dtm message was lost due to an attempted access to a secure memory location ? upon data trace write/read after th e previous dtm message was lost due to a collision entering the fifo between the dtm me ssage and any of the following: watchpoint message, ownership trace message, or branch trace message data trace synchronization messages provide the full address (without leading zeros) and insure that development tools fully synchronize with data tr ace regularly. synchroniza tion messages provide a reference address for subsequent data messages, in which only the unique portion of the data trace address is transmitted. the format for data trace wr ite/read with sync. messages is as follows: figure 31-33. data write/read with sync. message format exception conditions that re sult in data trace synchr onization are summarized in table 31-27 . data msb lsb 2 3 4 u-addr dsz src 5 4 bits 1 tcode (000110) 3 bits 1?32 bits 1?64 bits 6 bits max length = 109 bits; min length = 15 bits data msb lsb 2 3 4 f-addr dsz src 5 4 bits 1 tcode (001101 or 001110) 3 bits ?32 bits ?64 bits 6 bits max length = 109 bits; min length = 15 bits
nexus development interface (ndi) 31-52 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.14.6.3 dtm operation 31.14.6.3.1 dtm queueing nz7c3 implements a message queue for dtm messages. messages that enter th e queue are transmitted via the auxiliary pins in the order in which they are queued. note if multiple trace messages must be que ued at the same time, watchpoint messages have the highest priority (wpm ? otm ? btm ?? dtm). 31.14.6.3.2 relative addressing the relative address feature is compliant with the ieee-isto 5001-201 1 standard recommendations, and is designed to reduce the number of bits transm itted for addresses of data trace messages. see section 31.14.2, relative addressing for details. table 31-27. data trace exception summary exception condition e xception handling system reset negation at the negation of jtag reset (jcomp), queue pointers, counters, state machines, and registers within the nz7c3 module are re set. if data trace is enabled, the first data trace message is a data wr ite/read with sync. message. data trace enabled the first data trace message (after data trace has been enabled) is a synchronization message. exit from low power/debug upon exiting from low po wer or debug modes, the next data trace message is converted to a data write/read with sync. message. queue overrun an error message occurs when a new message cannot be queued due to a full message queue. the fifo discards messages until it has completely emptied the queue. after the queue is empty, an error message is queued that indicates the message types denied queuing while the fifo was emptying. the next dtm message in the queue is a data write/read with sync. message. periodic data trace sync. a forced synchronization occurs periodically after 255 data trace messages have been queued. a data write/read with sync. message is queued. the periodic data trace message counter then resets. event in if the nexus module is enabled, a evt i assertion initiates a data trace write/read with sync. message upon the next data writ e/read (if data trace is enabled and the eic bits of the dc1 register have enabled this feature). attempted access to secure memory for devices which implement security, any attempted read or write to secure memory locations temporarily disables data trace and loses the dtm. a subsequent read/write queues a data trace read/write with sync. message. collision priority all messages have the following priority: wpm ?? otm ?? btm ?? dtm. a dtm message which attempts to enter the queue at the same time as a watchpoint message or ownership trace message or branch trace message can be lost. a subsequent read/write queues a data trace read/write with sync. message.
nexus development interface (ndi) freescale semiconductor 31-53 pxr40 microcontroller reference manual, rev. 1 31.14.6.3.3 data trace windowing data write/read messages are enabled via the rwt1(2) field in the data trace control register (dtc) for each dtm channel. data trace windowing is achieve d via the address range defined by the dtea and dtsa registers and by the rc1(2) field in the dtc. all e200z7 initiated read /write accesses which fall inside or outside these a ddress ranges, as programmed, are candidates to be traced. 31.14.6.3.4 data access/instr uction access data tracing the nexus3 module is capable of tr acing both instruction access data or data access data. each trace window can be configured for either type of data trace by setting the di 1(2) field within the data trace control register for each dtm channel. 31.14.6.3.5 e200z7 bus cycle special cases note for misaligned accesses (crossing 64- bit boundary), the access is broken into two accesses. if both accesses ar e within the data trace range, two dtms are sent: one with a size encoding indicating the size of the original access (a word), and one with a size encoding for the portion which crossed the boundary (3 bytes). note an stm to the cache?s store buffer with in the data trace range initiates a dtm message. if the corresponding me mory access causes an error, a checkstop condition occurs. the debug/ development tool must use this indication to invalida te the previous dtm. table 31-28. e200z7 bus cycle cases special case action e200z7 bus cycle aborted cycle ignored e200z7 bus cycle with data error (tea ) data trace message discarded e200z7 bus cycle complete d without error cycle ca ptured & transmitted e200z7 bus cycle initiate d by nz7c3 cycle ignored e200z7 bus cycle is an inst ruction fetch cycle ignored e200z7 bus cycle accesses misaligned data (across 64-bit boundary)?both 1st and 2nd transactions within data trace range 1st and 2nd cycle capt ured, and 2 dtm?s transmitted (see note) e200z7 bus cycle accesses misaligned data (across 64-bit boundary)?1st transaction within data trace range; 2nd transaction out of data trace range 1st cycle captured and transmitted; 2nd cycle ignored e200z7 bus cycle accesses misaligned data (across 64-bit boundary)?1st transaction out of data trace range; 2nd transaction within data trace range 1st cycle ignored; 2nd cycle capture and transmitted
nexus development interface (ndi) 31-54 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.14.6.4 data trace timing diagra ms (eight mdo configuration) figure 31-34. data trace?data write message figure 31-35. data trace?data read with sync message figure 31-36. error message (data trace only encoded) 31.14.7 watchpoint support this section details the watchpoint features of the nz7c3 module. 31.14.7.1 overview the nz7c3 module provides watchpoint messaging via the auxiliary pi ns, as defined by the ieee-isto 5001-2011 standard. nz7c3 is not compliant with class4 breakpoint/wat chpoint requirements defined in the standard. the breakpoint/watchpoint control re gister is not implemented. mcko mseo [1:0] tcode = 5 source processor = 0b0000 data size = 010 (halfword) relative address = 0xa5 00 mdo[7:0] 11 00 01 00 11 00000101 10101000 00010100 11101111 10111110 write data = 0xbeef 00001110 11000000 01011001 11010001 00101000 00000000 01011100 mcko mseo [1:0] tcode = 14 source processor = 0b0000 data size = 000 (byte) full access address = 0x0146_8ace 00 mdo[7:0] 11 write data = 0x5c 01 11 mcko mseo [1:0] tcode = 8 source processor = 0b0000 error code = 2 (queue overrun ? dtm only) 00 mdo[7:0] 11 11 xx 00001000 00001000 xxxxxxxx
nexus development interface (ndi) freescale semiconductor 31-55 pxr40 microcontroller reference manual, rev. 1 31.14.7.2 watchpoint messaging enabling watchpoint messaging is done by setting the wa tchpoint enable bit in the dc1 register. setting the individual watchpoint sources is supported through the e200z7 nexus1 module. the e200z7 nexus1 module is capable of setting mult iple address and/or data watchpoi nts. please see the e200z7 core reference manual for more information on watchpoint initialization. when these watchpoints occur, a watchpoint event sign al from the nexus1 module causes a message to be sent to the queue to be messaged out. this messa ge includes the watchpoint number indicating which watchpoint caused the message. the occurrence of any of the e200z7 defined watch points can be programmed to assert the event out evto pin for one period of the output clock (mcko). watchpoint information is messag ed out in the following format: figure 31-37. watchpoint message format. 31.14.7.3 watchpoint error message an error message occurs when a ne w message cannot be queued due to the message queue being full. the fifo discards messages until it has completely emptied the queue. after it is emptied, an error message is queued. the error encoding indicates the types of mess ages that attempted to be queued while the fifo was being emptied. if only a watchpoint message attempts to enter the queue while it is being emptied, th e error message incorporates the watchpoint only error encoding (0 0110). if an otm and/or program trace and/or data trace message also attempts to ente r the queue while it is being emp tied, the error message incorporates error encoding (01000). table 31-29. watchpoint source encoding watchpoint source (8 bits) watchpoint description 00000001 e200z7 watchpoint #0 (iac1 from nexus1) 00000010 e200z7 watchpoint #1 (iac2 from nexus1) 00000100 e200z7 watchpoint #2 (iac3 from nexus1) 00001000 e200z7 watchpoint #3 (iac4 from nexus1) 00010000 e200z7 watchpoint #4 (dac1 from nexus1) 00100000 e200z7 watchpoint #5 (dac2 from nexus1) 01000000 e200z7 watchpoint #6 (dcnt1 from nexus1) 10000000 e200z7 watchpoint #7 (dcnt2 from nexus1) wphit msb lsb 1 2 src tcode (001111) 3 6 bits 4 bits 4 bits fixed length = 14 bits
nexus development interface (ndi) 31-56 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the ovc bits within the dc1 register can be set to delay the cpu to alleviate (but not eliminate) potential overrun situations. error information is messaged out in the following format (see table 31-19 ): figure 31-38. error message format 31.14.7.4 watchpoint timing diagram (two mdo and one mseo configuration) figure 31-39. watchpoint message and watchpoint error message 31.14.8 nz7c3 read/write access to memory-mapped resources the read/write access feature allows access to memo ry-mapped resources via the jtag/once port. the read/write mechanism supports single as well as bloc k reads and writes to e200z7 system bus resources. the nz7c3 module is capable of accessing resources on the e200z 7 system bus, with multiple configurable priority le vels. memory-mapped regist ers and other non-cached me mory can be accessed via the standard memory map settings. all accesses are setup and in itiated by the read/write acc ess control/status register (rwcs), as well as the read/write access address (rwa) and re ad/write access data registers (rwd). using the read/write access regi sters (rwcs/rwa/rwd), memory-map ped e200z7 system bus resources can be accessed through nz7c3. the foll owing subsections describe the st eps which are required to access memory-mapped resources. note read/write access can only access memo ry mapped resources when system reset is de-asserted. misaligned accesses are not supported in the e200z7 nexus3 module. ecode (00110 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits wpm: mcko mseo tcode = 15 source processor = 0b00 watchpoint number = 2 mdo[1:0] 11 00 00 10 00 00 00 10 00 00 10 01 00 error: tcode = 8 source processor = 0b00 error code = 6 (queue overrun ? wpm only) error watchpoint 11
nexus development interface (ndi) freescale semiconductor 31-57 pxr40 microcontroller reference manual, rev. 1 31.14.8.1 single write access 1. initialize the read/write acc ess address register (rwa) thr ough the access method outlined in section 31.11.1, nz7c3 regist er access via jtag / once , using the nexus re gister index of 0x9 (see table 31-23 ). configure the write address to 0xnnnnnnnn (write address). 2. initialize the read/write acce ss control/status register (rwcs) through the access method outlined in section 31.11.1, nz7c3 regist er access via jtag / once , using the nexus register index of 0x7 (see table 31-23 ). configure the bits as follows: ? access control rwcs[ac] ? 0b1 (to indicate start access) ? map select rwcs[map] ? 0b000 (primary memory map) ? access priority rwcs[pr] ? 0b00 (lowest priority) ? read/write rwcs[rw] ? 0b1 (write access) ? word size rwcs[sz] ? 0b0xx (32-bit, 16-bit, 8-bit) ? access count rwcs[cnt] ? 0x0000 or 0x0001 (single access) note access count rwcs[cnt] of 0x0000 or 0x0001 performs a single access. 3. initialize the read/write access data regist er (rwd) through the a ccess method outlined in section 31.11.1, nz7c3 register access via jtag / once , using the nexus regi ster index of 0xa (see table 31-23 ). configure the write da ta to 0xnnnnnnnn (write data). 4. the nz7c3 module then arbitrates for the system bus and transfer the data value from the data buffer rwd register to the memory mapped addre ss in the read/write access address register (rwa). when the access has completed without error (err=1?b0), nz7c3 asserts the rdy pin and clears the dv bit in the rwcs register. this indicates that the device is ready for the next access. note only the rdy pin as well as the dv and err bits within the rwcs provide read/write access status to the external development tool. 31.14.8.2 block write access (non-burst mode) 1. for a non-burst block write access, follow steps 1, 2, and 3 outlined in section 31.14.8.1, single write access to initialize the registers, but using a value greater than one (0x1) for the rwcs[cnt] field. 2. the nz7c3 module then arbitrates for the system bus and transfer the first data value from the rwd register to the memory mapped address in the read/write access a ddress register (rwa). when the transfer has completed without error (e rr = 0), the address from the rwa register is incremented to the next word size (specified in the sz field) and the number from the cnt field is decremented. nexus then asserts the rdy pin. th is indicates it is r eady for the next access. 3. repeat step 3 in section 31.14.8.1, single write access , until the internal cnt value is zero (0). when this occurs, the dv bit within the rwcs is cleared to indicate the end of the block write access.
nexus development interface (ndi) 31-58 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.14.8.3 block write access (burst mode) 1. for a burst block write access, follow steps 1 and 2 outlined in section 31.14.8.1, single write access , to initialize the registers, using a value of four (doublewords) for the cnt field and a rwcs[sz] field indicating 64-bit access. 2. initialize the burst data buffe r (read/write access da ta register) through th e access method outlined in section 31.11.1, nz7c3 register access via jtag / once , using the nexus register index of 0xa (see table 31-23 ). 3. repeat step 2 until all doubleword values are written to the buffer. note the data values must be shifted in 32-bits at a time lsb first (that is, doubleword write = two word writes to the rwd). 4. the nexus module then arbitrates for the system bus and transfer the burst data values from the data buffer to the system bus be ginning from the memory mapped ad dress in the read/write access address register (rwa). for each access within th e burst, the address from the rwa register is incremented to the next doubleword si ze (specified in the sz field) modulo the length of the burst, and the number from the cn t field is decremented. 5. when the entire burst transfer has completed without error (err = 0), nz7c3 then asserts the rdy pin, and the dv bit within the rwcs is cleare d to indicate the end of the block write access. note the actual rwa value as well as the cnt field within the rwcs are not changed when executing a block writ e access (burst or non-burst). the original values can be read by the ex ternal development tool at any time. 31.14.8.4 single read access 1. initialize the read/write acc ess address register (rwa) thr ough the access method outlined in section 31.11.1, nz7c3 register access via jtag / once , using the nexus register index of 0x9 (see table 31-23 ). configure as follows: ? read address ? 0xnnnnnnnn (read address) 2. initialize the read/write acce ss control/status register (rwcs) through the access method outlined in section 31.11.1, nz7c3 register access via jtag / once , using the nexus register index of 0x7 (see table 31-23 ). configure the bits as follows: ? access control rwcs[ac] ? 0b1 (to indicate start access) ? map select rwcs[map] ? 0b000 (primary memory map) ? access priority rwcs[pr] ? 0b00 (lowest priority) ? read/write rwcs[rw] ? 0b0 (read access) ? word size rwcs[sz] ? 0b0xx (32-bit, 16-bit, 8-bit) ? access count rwcs[cnt] ? 0x0000 or 0x0001 (single access) note access count (cnt) of 0x0000 or 0x0001 performs a single access.
nexus development interface (ndi) freescale semiconductor 31-59 pxr40 microcontroller reference manual, rev. 1 3. the nz7c3 module then arbitrates for the system bus and the read data is transferred from the system bus to the rwd register. when the transf er is completed without error (err = 0), nexus asserts the rdy pin and sets the dv bit in the rw cs register. this indicates that the device is ready for the next access. 4. the data can then be read from the read/wri te access data register (rwd) through the access method outlined in section 31.11.1, nz7c3 register access via jtag / once , using the nexus register index of 0xa (see table 31-23 ). note only the rdy pin as well as the dv and err bits within the rwcs provide read/write access status to th e external development tool. 31.14.8.5 block read access (non-burst mode) 1. for a non-burst block read access, follow steps 1 and 2 outlined in section 31.14.8.4, single read access , to initialize the regist ers, but using a value greater than one (0x1) for the cnt field in the rwcs register. 2. the nz7c3 module then arbitrates for the system bus and the read data is transferred from the system bus to the rwd register. when the tran sfer has completed wit hout error (err=0b0), the address from the rwa register is in cremented to the next word size (specified in the sz field) and the number from the cnt field is decremented. ne xus then asserts the rdy pin. this indicates that the device is ready for the next access. 3. the data can then be read from the read/wri te access data register (rwd) through the access method outlined in section 31.11.1, nz7c3 register access via jtag / once , using the nexus register index of 0xa (see table 31-23 ). 4. repeat steps 3 and 4 in section 31.14.8.4, single read access , until the cnt value is zero (0). when this occurs, the dv bit within the rwcs is set to indicate the end of the block read access. 31.14.8.6 block read access (burst mode) 1. for a burst block read access, follow steps 1 and 2 outlined in section 31.14.8.4, single read access , to initialize the registers, using a value of four (doublewords) for the cnt field and an rwcs[sz] field indicating 64-bit access. 2. the nz7c3 module then arbitrates for the system bus and the burst read data is transferred from the system bus to the data buffer (rwd register). for e ach access within the bur st, the address from the rwa register is incremented to the next doubleword (specified in the sz field) and the number from the cnt field is decremented. 3. when the entire burst transfer has completed without er ror (err = 0), nexus then asserts the rdy pin and the dv bit within the rwcs is set to indicate the end of the block read access. 4. the data can then be read from the burst data buffer (read/write access data register) through the access method outlined in section 31.11.1, nz7c3 regist er access via jtag / once , using the nexus register index of 0xa (see table 31-23 ). 5. repeat step 3 until all doubleword values are read from the buffer.
nexus development interface (ndi) 31-60 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the data values must be shifted out 32-bits at a time lsb first (that is, doubleword read = two word reads from the rwd). note the actual rwa value as well as the cnt field within the rwcs are not changed when executing a block read access (burst or non-burst). the original values can be read by the ex ternal development tool at any time. 31.14.8.7 error handling the nz7c3 module handles various error conditions as follows: 31.14.8.7.1 system bus read/write error all address and data errors that occur on read/write accesses to the e 200z7 system bus returns a transfer error. if this occurs: 1. the access is terminated without re-trying (ac bit is cleared). 2. the err bit in the rwcs register is set. 3. the error message is sent (tcode = 8) indicating read/write error. 31.14.8.7.2 access termination the following cases are defined for se quences of the read/write protocol that differ from those described in the above sections: 1. if the ac bit in the rwcs register is set to st art read/write accesses and invalid values are loaded into the rwd and/or rwa, then a system bus access error can occur. this is handled as described above. 2. if a block access is in progress (all cycles not co mpleted), and the rwcs register is written, then the original block access is terminated at the boundary of the nearest completed access. a) if the rwcs is written with the ac bit set, the next read/wri te access begins and the rwd can be written to/ read from. b) if the rwcs is written with th e ac bit cleared, the read/write ac cess is terminated at the nearest completed access. this method can be used to break (early terminate) block accesses. 31.14.8.8 read/write access error message the read/write access error message is sent out when an system bus access error (read or write) occurs. error information is messaged out in the following format: figure 31-40. error message format ecode (00011) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits
nexus development interface (ndi) freescale semiconductor 31-61 pxr40 microcontroller reference manual, rev. 1 31.14.9 examples the following are examples of progr am trace and data trace messages. table 31-30 illustrates an example indirect branch message with an eight mdo and two mseo configuration. t0 and s0 are the least significant bits where: ? tx = tcode number (fixed) ? sx = source processor (fixed) ? ix = number of inst ructions (variable) ? ax = unique portion of the address (variable) table 31-31 illustrates an example of direct br anch message with 12 mdo and two mseo. t0 and i0 are the least significant bits where: ? tx = tcode number (fixed) ? sx = source processor (fixed) ? ix = number of instructions (variable) table 31-32 an example data write message with 12 mdo and two ms eo configuration. t0, a0, d0 are the least si gnificant bits (lsb) where: ? tx = tcode number (fixed) ? sx = source processor (fixed) table 31-30. indirect branch message example (12 mdo and two mseo) clock mdo[11:0] mseo [1:0] state 11109876543 2 1 0 0 xxxxxxxx xxxx 1 1idle (or end of last message) 1 i1 i0 s3s2s1s0t5t4t3 t2 t1 t0 0 0 start message 2 0 0 0 0 0 0 0 0i5i4i3i2 0 1end packet 3 0 a10a9a8a7a6a5a4a3a2a1a0 1 1 end packet/end message 4 x x s3s2s1s0t5t4t3 t2 t1 t0 0 0 start of next message table 31-31. direct branch message example (12 mdo and two mseo ) clock mdo[11:0] mseo [1:0] state 11109876543210 0 xxxxxxxxxxxx 1 1idle (or end of last message) 1 i1 i0 s3s2s1s0t5t4t3t2t1t0 0 0 start message 2 0 0 0 0 0 0 0 0 0 0 i3 i2 1 1 end packet and end message 3 x x x x s1s0t5t4t3t2t1t0 0 0 start of next message
nexus development interface (ndi) 31-62 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 ? zx = data size (fixed) ? ax = unique portion of the address (variable) ? dx = write data (variable: 8-, 16- or 32-bit) 31.14.10 ieee 1149.1 (jtag) rd/wr sequences this section contains example jtag/once sequences used to access resources. 31.14.10.1 jtag sequence for access ing internal nexus registers table 31-32. direct write message example (12 mdo and two mseo ) clock mdo[11:0] mseo[1:0] state 11109876543210 0 x x x x x x x x x x x x 1 1 idle (or end of last message) 1 z1z0s3s2s1s0t5t4t3t2t1t0 0 0 start message 2 0 0 0 0 0 0 0 a3 a2 a1 a0 z2 0 1 end packet 3 x x x x d7 d6 d5 d4 d3 d2 d1 d0 1 1 end packet/end message table 31-33. accessing internal nexus3 registers via jtag/once step # tms pin description 11idle ?? select-dr_scan 2 0 select-dr_scan ?? capture-dr (nexus command register value loaded in shifter) 3 0 capture-dr ?? shift-dr 4 0 (7) tck clocks issued to shift in direction (read/w rite) bit and first 6 bits of nexus reg. addr. 5 1 shift-dr ?? exit1-dr (7th bit of nexus reg. shifted in) 6 1 exit1-dr ?? update-dr (nexus shifter is tran sferred to nexus command register) 7 1 update-dr ?? select-dr_scan 8 0 select-dr_scan ?? capture-dr (register value is transferred to nexus shifter) 9 0 capture-dr ?? shift-dr 10 0 (31) tck clocks issued to transfer register value to tdo pin while shifting in tdi value 11 1 shift-dr ?? exit1-dr (msb of value is shifted in/out of shifter) 12 1 exit1-dr ?? update -dr (if access is write, sh ifter is transferred to register) 13 0 update-dr ?? run-test/idle (transfer complete - ne xus controller to reg. select state)
nexus development interface (ndi) freescale semiconductor 31-63 pxr40 microcontroller reference manual, rev. 1 31.14.10.2 jtag sequence for read access of memory-mapped resources 31.14.10.3 jtag sequence for write access of memory-mapped resources 31.15 nexus crossbar edma interf ace (nxdm) and nexus crossbar flexray interface (nxfr) the third module of the device ndi interface is the e200z7 edma nexus module (nxdm) which is compliant with the class 3 defined data trace feature of the ieee-i sto 5001-2011 standard.the fourth module of the device ndi interface is the flexray m odule (nxfr) which is compliant with the class 3 defined data trace featur e of the ieee-isto 5001-2011 standard. th e nxdm can be programmed to trace data accesses for the edma module on the system bus. the nxfr can be programmed to trace data accesses for the flexray module on the system bus. this edma module and flex ray module as well as the nexus module are components of the e200z7 platform. all output mess ages and register accesses are compliant with the protocol define d in the ieee-isto 5001 standard. table 31-34. accessing memory-mapped resources (reads) step # tclk clocks description 1 13 nexus command = write to read/write access address register (rwa) 2 37 write rwa (initialize starting read address?data input on tdi) 3 13 nexus command = write to read/wr ite control/status register (rwcs) 4 37 write rwcs (initialize read access mode and cnt value?data input on tdi) 5 ? wait for falling edge of rdy pin 6 13 nexus command = read the read/write access data register (rwd) 7 37 read rwd (data output on tdo) 8 ? if cnt > 0, go back to step #5 table 31-35. accessing memory-mapped resources (writes) step # tclk clocks description 1 13 nexus command = write to read/write access control/status register (rwcs) 2 37 write rwcs (initialize write access mode and cnt value?data input on tdi) 3 13 nexus command = write to read/write address register (rwa) 4 37 write rwa (initialize starting write address?data input on tdi) 5 13 nexus command = read the read/write access data register (rwd) 6 37 write rwd (data output on tdo) 7 ? wait for falling edge of rdy pin 8 ? if cnt > 0, go back to step #5
nexus development interface (ndi) 31-64 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the auxiliary port and its signals, su ch as mcko, mseo[1:0], mdo[15:0] and others, are referenced. the devi ce npc module arbitr ates the access of the single auxiliary port. the functions of the nxdm a nd flexray modules are described without the in teraction of the npc, as if nexus has a dedicated auxiliary port, to simplify the desc ription. the auxiliary port function is described in full in section 31.2, external signal description . 31.15.1 block diagrams figure 31-41 shows a block diagram of the nxdm. the block diagram of the nxfr is the same. figure 31-41. nxdm and nxfr block diagram 31.15.2 features features include the following: ? data trace via data write messaging (dwm) and data read messaging (drm ). this provides the capability for the development tool to trace reads and/or writes thr ough the edma and flexray modules to (selected) inte rnal memory resources. ? watchpoint messaging via the auxiliary pins. ? watchpoint trigger enable of data trace messaging (dtm). ? registers for data trace, watchpoin t generation, and watchpoint trigger. ? all features controllable and configurable via the jtag port. breakpoint/ watchpoint control message queues npc control and i/o logic memory control general control and status registers arbitration data snoop n + 1 mdo[n:0] mseo [0] mseo [1] mcko evto evti tdi tdo tms tclk trst ieee 1149.1 system bus (jtag) tap controller (jcomp)
nexus development interface (ndi) freescale semiconductor 31-65 pxr40 microcontroller reference manual, rev. 1 ? power management. ? low power design ? dynamic power management of fifos and control logic 31.16 external signal description the nxdm (and nxfr) module uses the same pins and pin protocol as defined in section 31.2, external signal description . 31.16.1 rules for output messages the nxdm (and nxfr) module obser ve the same rules for output me ssages as the npc. refer to section 31.7.2.2.1, rules of messages . 31.16.2 auxiliary port arbitration the nxdm (and nxfr) module arbitrate for the shared nexus port. this arbitration is handled by the npc (refer to section 31.5, nexus port controller (npc) ) based on prioritized re quests from the nxdm, nxfr, and the other nexus clients sharing the port. 31.17 nxdm and nxfr programmers model this section describes the program mers model. nexus registers ar e accessed using the jtag port in compliance with ieee 1149.1. refer to chapter 32, ieee 1149.1 test access port controller (jtagc) , and section 31.7.2.3, ieee 1149.1-2001 (jtag) tap , for details on nexus register access. 31.17.1 nxdm and nxfr nexus register map table 31-36. nxdm and nxfr register map nexus register nexus access opcode read/write read address write address client select control (csc) 1 0x1 r 0x02 ? port configuration register (pcr) 1 refer to npc r/w ? ? development control 1 (dc1_ n ) 0x2 r/w 0x04 0x05 development control 2 (dc2_ n ) 0x3 r/w 0x05 0x06 watchpoint trigger (wt_ n ) 0xb r/w 0x16 0x17 data trace control (dtc_ n ) 0xd r/w 0x1a 0x1b data trace start address 1 (dtsa1_ n ) 0xe r/w 0x1c 0x1d data trace start address 2 (dtsa2_ n ) 0xf r/w 0x1e 0x1f data trace end address 1 (dtea1_ n ) 0x12 r/w 0x24 0x25 data trace end address 2 (dtea2_ n ) 0x13 r/w 0x26 0x27
nexus development interface (ndi) 31-66 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.2 nxdm and nxfr registers detailed register definitions for the nx dm and nxfr implementation are as follows: 31.17.2.1 development control registers (dc1 and dc2) the development control registers control the basi c development features of the nxdm and nxfr modules. breakpoint/watchpoint co ntrol register 1 (bwc1_ n ) 0x16 r/w 0x2c 0x2d breakpoint/watchpoint co ntrol register 2 (bwc2_ n ) 0x17 r/w 0x2e 0x2f breakpoint/watchpoint ad dress register 1 (bwa1_ n ) 0x1e r/w 0x3c 0x3d breakpoint/watchpoint ad dress register 2 (bwa2_ n ) 0x1f r/w 0x3e 0x3f reserved 0x20?0x3f ? 0x40?0x7e 0x41?0x7f 1 the csc and pcr registers are shown in this table as par t of the nexus programmer?s model. they are only present at the top level nexus3 controller (npc), not in the nxdm or nxfr module. the device?s csc register is readable through nexus3; the pcr is shown for reference only. nexus reg # 0x2 access: read/write 0123456 7891 0 1 1 1 2 1 3 1 4 1 5 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r opc mck_ div ? ptm ? potd tsen eoc eic ? tm w reset all zeros figure 31-42. development control register 1 op c mck_ div 0 pt m 0 po td tsen eoc eic 0 tm 012345678910111213141516171819202122232425262728293031 nexus reg# - 0x2; read/write; reset - 0x0 figure 31-43. development control register 1 table 31-36. nxdm and nxfr register map (continued) nexus register nexus access opcode read/write read address write address
nexus development interface (ndi) freescale semiconductor 31-67 pxr40 microcontroller reference manual, rev. 1

table 31-37. describes its fields. table 31-37. development control register 1 fields field description 0 opc opc?output port mode control 0 reduced port mode configuration (min# nex_mdo[n:0] pins defined 1 full port mode configuration (max# nex_mdo[n:0] pins defined 1?2 mck_div mck_div?mcko clock divide ratio (see note below) 00 nex_mcko is 1 processor clock frequency. 01 nex_mcko is ? processor clock frequency. 10 nex_mcko is ? processor clock frequency. 11 nex_mcko is processor clock frequency. 3 reserved for future functionality 4 ptm ptm?program trace method 0 program trace uses traditional branch messages. 1 program trace uses branch history messages. 5?16 reserved for future functionality 17 potd periodic ownership trace disable 0 periodic ownership trace message events are enabled. 1 periodic ownership trace message events are disabled. 18?19 tsen timestamp enable - (not implemented, write to 00) 00 timestamp is disabled 20?21 eoc eoc?evto control 00 nex_evto_b upon occurrence of watchpoints (configured in dc2 and dc3) 01 nex_evto_b upon entry into debug mode 1x reserved 22?23 eic eic?evti control 00 nex_evti_b is used for synchronization (program trace/data trace) 01 nex_evti_b is used for debug request 1x reserved 24?25 reserved for future functionality 26?31 tm trace mode 1 000000 all trace disabled xxxxx1 ownership trace enabled xxxx1x data trace enabled xxx1xx program trace enabled xx1xxx watchpoint trace enabled x1xxxx reserved 1xxxxx data acquisit ion trace enabled 1 this field may be updated by hardware in response to watchpoint triggering. writes to this field take precedence over hardware updates in the event of a collision. 1 8 -- -
nexus development interface (ndi) 31-68 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 note the output port mode control bit (opc ) and mcko clock divide ratio bits (mck_div) must only be modified during system reset or debug mode to insure correct output port and output clock functionality. it is also recommended that all other bits of the dc1 only be m odified in one of these two modes. access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ewc 0000000000 00000000 0 0 0 0 0 0 w reset00000000000000000000000000000000 figure 31-44. development control register 2 (dc2) table 31-38. dc2 field description field description 0?7 ewc 1 1 the eoc bits in dc1 must be programmed to trigger evto on watchpoint occurrence for the ewc bits to have any effect. evto watchpoint configuration 00000000 = no watchpoints trigger evto 1xxxxxxx = invalid value x1xxxxxx = invalid value xx1xxxxx = invalid value xxx1xxxx = invalid value xxxx1xxx = internal watch point #1 triggers evto xxxxx1xx = internal watch point #2 triggers evto xxxxxx1x = invalid value xxxxxxx1 = invalid value 8?31 reserved, read as 0.
nexus development interface (ndi) freescale semiconductor 31-69 pxr40 microcontroller reference manual, rev. 1 31.17.2.2 watchpoint trigger register (wt) the watchpoint trigger register al lows the watchpoints defined internally to the nxdm and nxfr modules to trigger actions. these watc hpoints can control data trace enable and disa ble. the wt bits can be used to produce an address relate d window for triggering trace messages. note the wt bits only enable data trace if the tm bits within the development control register (dc) have not alr eady been set to enable data trace. 31.17.2.3 data trace control register (dtc) the data trace control register controls whether dtm messages are restricted to reads, writes or both for a user programmable addre ss range. there are two data trace chan nels controlled by the dtc for the nxdm and nxfr modules. access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 dts dte 000000 00000000 0 0 0 0 0 0 w reset00000000000000000000000000000000 figure 31-45. watchpoint trigger register (wt) table 31-39. wt field description field description 0?5 reserved, read as 0. 6?8 dts dts - data trace start control 000 trigger disabled 001?100 invalid value 101 use internal watchpoint #1 (bwa1 register) 110 use internal watchpoint #2 (bwa2 register) 111 invalid value 9?11 dte dte - data trace end control 000 trigger disabled 001?100 invalid value 101 use internal watchpoint #1 (bwa1 register) 110 use internal watchpoint #2 (bwa2 register) 111 invalid value 12?31 reserved, read as 0. access: r/w 0123456789101112131415161718192021222324 25262728293031 r rwt1 rwt2 00000000000000000000 rc1 rc2 0 0 0 0 0 0 w reset000000000000000000000000 0 0 000000 figure 31-46. data trace control register (dtc)
nexus development interface (ndi) 31-70 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.2.4 data trace start address re gisters 1 and 2 (dtsa1 and dtsa2) the data trace start address registers define the start addresses for each trace channel. table 31-40. dtc field description bit description 0?1 rwt1 read/write trace 1 00 no trace messages generated x1 enable data read trace 1x enable data write trace 2?3 rwt2 read/write trace 2 00 no trace messages generated x1 enable data read trace 1x enable data write trace 4?23 reserved, read as 0. 24 rc1 range control 1 0 condition trace on address within range (endpoints inclusive) 1 condition trace on address outside of range (endpoints exclusive) 25 rc2 range control 2 0 condition trace on address within range (endpoints inclusive) 1 condition trace on address outside of range (endpoints exclusive) 26?31 reserved, read as 0. access: r/w 012345678910111213141516171819202122232425262728293031 r data trace start address w reset00000000000000000000000000000000 figure 31-47. data trace start address registers (dtsa1, dtsa2)
nexus development interface (ndi) freescale semiconductor 31-71 pxr40 microcontroller reference manual, rev. 1 31.17.2.5 data trace end address registers 1 and 2 (dtea1 and dtea2) the data trace end address re gisters define the end addres ses for each trace channel. table 31-41 illustrates the range that is selected for data trace for various cases of dtsa being less than, greater than, or equal to dtea. note dtsa must be less than (or equal to) dtea to guarantee correct data write/read traces. when the range cont rol bit is 0 (inter nal range), accesses to dtsa and dtea addresses are trac ed. when the range control bit is 1 (external range), accesses to dtsa and dtea are not traced. 31.17.2.6 breakpoint / watchpoint control register 1 (bwc1) breakpoint/watchpoint control register 1 controls attributes for generation of nxdm and nxfr watchpoint number 1. access: r/w 012345678910111213141516171819202122232425262728293031 r data trace end address w reset00000000000000000000000000000000 figure 31-48. data trace start address registers (dtea1, dtea2) table 31-41. data trace address range options programmed values range contro l bit value range selected dtsa < or = dtea 0 dtsa ? ? dtea dtsa < or = dtea 1 ? dtsa dtea ? dtsa > dtea ? invalid range, no trace access: r/w 0123456789101112131415 16 171819202122232425262728293031 r bwe1 brw1 bwr1 bwt1 w reset0000000000000000 0 000000000000000 figure 31-49. break / watchpoint control register 1 (bwc1)
nexus development interface (ndi) 31-72 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.2.7 breakpoint / watchpoint control register 2 (bwc2) breakpoint/watchpoint control regi ster2 controls attri butes for generation of nxdm and nxfr watchpoint number 2. table 31-42. bwc1 field description field description 0?1 bwe1 breakpoint/watchpoint #1 enable 00 internal nexus watchpoint #1 disabled 01?10 invalid value 11 internal nexus watchpoint #1 enabled 2?3 brw1 breakpoint/watchpoint #1 read/write select 00 watchpoint #1 hit on read accesses 01 watchpoint #1 hit on write accesses 10 watchpoint #1 on read or write accesses 11 invalid value 4?13 reserved, read as 0. 17?16 bwr1 breakpoint/watchpoint #1 register compare 00 no register compare (same as bwc1[31:30] = 2?b00) 01 invalid value 10 compare with bwa1 value 11 invalid value 15 bwt1 breakpoint/watchpoint #1 type 0 invalid value 1 watchpoint #1 on data accesses 14?0 reserved, read as 0. access: r/w 0123456789101112131415 16 171819202122232425262728293031 r bwe2 brw2 bwr2 bwt2 w reset0000000000000000 0 000000000000000 figure 31-50. break / watchpoint control register 2 (bwc2) table 31-43. bwc2 field description field description 0?1 bwe2 breakpoint/watchpoint #2 enable 00internal nexus watchpoint #2 disabled 01?10 invalid value 11 internal nexus watchpoint #2 enabled 2?3 brw2 breakpoint/watchpoint #2 read/write select 00 watchpoint #2 hit on read accesses 01 watchpoint #2 hit on write accesses 10 watchpoint #2 on read or write accesses 11 invalid value 4?13 reserved, read as 0.
nexus development interface (ndi) freescale semiconductor 31-73 pxr40 microcontroller reference manual, rev. 1 31.17.2.8 breakpoint/watchpoint address registers 1 and 2 (bwa1 and bwa2) the breakpoint/watchpoint address registers are compared with bus addresses to generate internal watchpoints. 31.17.2.9 unimplemented registers unimplemented registers are those with client select and index value comb inations other than those listed in table 31-36 . for unimplemented registers, the nxdm and nxfr modules drives tdo to zero during the ?shift-dr? state. it also transmits an er ror message with the i nvalid access opcode encoding. 31.17.2.10 programming considerations (reset ) if nexus3 register configuration is to occur duri ng system reset (as opposed to debug mode), all nxdm configuration should be complete d between the negation of jcomp an d system reset de-assertion, after the jtag did register has been read by the tool. 31.17.2.11 ieee 1149.1 (jta g) test access port the nxdm and nxfr modul es uses the ieee 1149.1 tap controller for accessing nexus resources. the jtag signals themselves are shared by all tap controllers on the device. refer to chapter 32, ieee 1149.1 test access port controller (jtagc) , for more information on the jtag interface. the nxdm and nxfr modules implements a 4-bit instru ction register (ir). the valid instructions and method for register access are outlined in section 31.7.2.3, ieee 1149.1-2001 (jtag) tap . 14?15 bwr2 breakpoint/watchpoint #2 register compare 00 no register compare (same as bwc1[31:30] = 2?b00) 01 invalid value 10 compare with bwa2 value 11 invalid value 16 bwt2 breakpoint/watchpoint #2 type 0 invalid value 1 watchpoint #2 on data accesses 17?31 reserved, read as 0. access: r/w 012345678910111213141516171819202122232425262728293031 r breakpoint / watchpoint address w reset00000000000000000000000000000000 figure 31-51. breakpoint / watchpoint address registers (bwa1, bwa2) table 31-43. bwc2 field description (continued) field description
nexus development interface (ndi) 31-74 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.2.11.1 nxdm and nx fr jtag did register this jtag did register that is included in th e nxdm and nxfr modules provides key development attributes to the development tool concerning th e nxdm and nxfr blocks. the register is accessed through the standard jtag ir/dr paths. refer to the pmc chapter. 31.17.2.11.2 enabling the nxdm and nxfr tap controllers assertion of a power-on-reset signa l or assertion of the jcomp pin resets all tap controllers on the device. upon exit from the test-logic- reset state, the ir value is loaded with the jtag did. when the nxdm or nxfr tap is accessed, this information helps the developmen t tool obtain information about the nexus module it is accessing, such as vers ion, sequence, feature set, and so forth. 31.17.2.11.3 nxdm a nd nxfr register access via jtag access to nexus register resources is enabled by lo ading a single instruction (nexus_access) into the jtag instruction register (ir). th is ir is part of the ieee 1149.1 tap controller within the nxdm and nxfr modules. refer to section 32.4.4, jtagc instructions . after the jtag nexus_access instruction has been loaded, the jtag port allows tool/target communications with all nexus re gisters according to the map in table 31-36 . access: r/w 012345678910111213141516171819202122232425262728293031 r prn dc pin mic 1 w reset00000111110001100000000000011101 figure 31-52. nxdm and nxfr jtag did register table 31-44. nxdm and nxfr jtag did field descriptions field description 0?3 prn 1 1 the revision number is initially 0 and could change in the future. embedded part revision number (0x0) 4?9 dc freescale design center id number (0x1f) 10?19 pin nxdm and nxfr module part identification number, defines the features set. (0x60) 20?30 mic manufacturer identity code 0x00e freescale 31 fixed per jtag 1149.1 1 always set
nexus development interface (ndi) freescale semiconductor 31-75 pxr40 microcontroller reference manual, rev. 1 reading/writing of a nexus register then requires tw o (2) passes through the data-scan (dr) path of the jtag state machine (refer to chapter 32, ieee 1149.1 test acces s port controller (jtagc) ). 1. the first pass through the dr selects the nexus register to be accessed by providing an index (refer to table 31-36 ), and the direction (read/write). this is achieved by loading an 8-bit value into the jtag data register (dr). this register has the following format: 2. the second pass through the dr then shifts the data in or out of the jtag port, lsb first. a) during a read access, data is latched from the selected nexus register when the jtag state machine passes through the capture-dr state. b) during a write access, data is latched into th e selected nexus register when the jtag state machine passes through the update-dr state. 31.17.3 functional description 31.17.4 enabling nxdm and nxfr operation the nxdm (and nxfr) module is enabled by load ing a single instructi on (access_aux_tap_dma or access_aux_tap_nxfr as shown in table 31-4 ) into the jtag instruction register (ir), and then loading the corresponding once ocmd register w ith the nexus_access instruction (refer to table 31-5 ). after it is enabled, the module is rea dy to accept control input via the jtag pins. the nexus module is disabled when the jtag state machine reaches the te st-logic-reset state. this state can be reached by the assertion of the jcomp pin or by cycling thr ough the state machine using the tms pin. the nexus module is also disabled if a power-on reset (por) event occurs. if the nxdm (and nxfr) module is di sabled, no trace output is provided, and the module disables (drive inactive) auxiliary port out put pins (mdo[15:0], mseo [1:0], mcko). nexus registers are not be available for reads or writes. access: r/w 01234567 r nexus register index r/w w reset figure 31-53. jtag dr for nexus register access table 31-45. dr read/write encoding nexus register index description read/write (r/w) 0 read 1write
nexus development interface (ndi) 31-76 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.5 tcodes supported by nxdm and nxfr the nxdm and nxfr pins allow for flexible transfer operations via public messages. a tcode defines the transfer format, the number and/or size of the packets to be transf erred, and the purpose of each packet. the ieee-isto 5001-2003 standard defines a set of public me ssages. the nxdm and nxfr blocks currently support the public tcodes seen in table 31-46 . table 31-46. public tcodes supported message name packet size bits packet name packet type packet description min max data trace - date write message 6 6 tcode fixed tcode number = 5 4 4 src fixed source processor identif ier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 31-48 ) 1 32 u-addr variable unique portion of the data write value 1 64 data variable data write value data trace - data read message 6 6 tcode fixed tcode number = 6 4 4 src fixed source processor identif ier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 31-48 ) 1 32 u-addr variable unique portion of the data read value 1 64 data variable data read value error message 6 6 tcode fixed tcode number = 8 4 4 src fixed source processor identif ier (multiple nexus configuration) 5 5 ecode fixed error code (refer to table 31-47 ) data trace - data write message w/ sync 6 6 tcode fixed tcode number = 13 (0xd) 4 4 src fixed source processor identif ier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 31-48 ) 1 32 f-addr variable full access address (leading zero (0) truncated) 1 64 data variable data write value data trace - data read message w/ sync 6 6 tcode fixed tcode number = 14 (0xe) 4 4 src fixed source processor identif ier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 31-48 ) 1 32 f-addr variable full access address (leading zero (0) truncated) 1 64 data variable data read valued watchpoint message 6 6 tcode fixed tcode number = 15 (0xf) 4 4 src fixed source processor identif ier (multiple nexus configuration) 4 4 wphit fixed number indicating watchpoint sources
nexus development interface (ndi) freescale semiconductor 31-77 pxr40 microcontroller reference manual, rev. 1 table 31-47. error code (ecode) encoding (tcode = 8) error code (ecode) description 00000 invalid value 00001 invalid value 00010 data trace overrun 00011 invalid value 00100 invalid value 00101 invalid access opcode (nexus register unimplemented) 00110 watchpoint overrun 00111 invalid value 01000 data trace and watchpoint overrun 01001?11111 invalid value table 31-48. data trace size (dsz) encodings (tcode = 5, 6, 13, 14) dtm size encoding transfer size 000 byte 001 halfword (two bytes) 010 word (four bytes) 011 doubleword (eight bytes) 100?111 invalid value
nexus development interface (ndi) 31-78 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.5.1 data trace this section deals with the data trace mechanism supported by the nxdm and nxfr modules. data trace is implemented via data write messaging (dwm) and data read messaging (drm). 31.17.5.2 data trace messaging (dtm) nxdm and nxfr data trace messaging is accomplis hed by snooping the nxdm and nxfr data bus, and storing the information for qualifying accesses (based on enabled features and matching target addresses). the nxdm (and nxfr) module traces all data access that meet the selected range and attributes. note data trace is only perf ormed on dma or flexray accesses to the system bus. 31.17.5.3 dtm message formats the nxdm (and nxfr) block supports five types of dtm messages ? da ta write, data read, data write synchronization, data read synchronization and error messages. 31.17.5.3.1 data write and data read messages the data write and data read messag es contain the data write/read valu e and the address of the write/read access, relative to the pr evious data trace message. data write message and data read message information is messaged out in the following format: figure 31-54. data write/read message format 31.17.5.3.2 dtm overfl ow error messages an error message occurs when a ne w message cannot be queued due to the message queue being full. the fifo discards incoming messages until it has comple tely emptied the queue. after it is emptied, an error message is queued. the error encodi ng indicates which type s of messages attempted to be queued while the fifo was being emptied. if only a data trace message attempts to enter the queue while it is being em ptied, the error message incorporates the data trace only error encoding (00010). if a watchpoint also attemp ts to be queued while the fifo is being emptied, then the error message incorporates error encoding (01000). error information is messaged out in the following format: data msb lsb 2 3 4 u-addr dsz src 5 4 bits 1 tcode (000101 or 000110) 3 bits 1?32 bits 1?64 bits 6 bits max length = 109 bits; min length = 15 bits
nexus development interface (ndi) freescale semiconductor 31-79 pxr40 microcontroller reference manual, rev. 1 figure 31-55. error message format 31.17.5.3.3 data trace s ynchronization messages a data trace write/read w/ sync. message is messaged via the auxiliar y port (provided data trace is enabled) for the following conditions (refer to table 31-49 ): ? initial data trace message upon ex it from system reset or whenev er data trace is enabled is a synchronization message. ? upon returning from a low power state, the first data trace message is a synchronization message. ? upon returning from debug mode, the first data trace message is a s ynchronization message. ? after occurrence of queue ove rrun (can be caused by any trace message), the first data trace message is a sync hronization message. ? after the periodic data trace counter has expired indicating 255 without-sync data trace messages have occurred since the last with-sync message occurred. ? upon assertion of the event in (evti ) pin, the first data trace message is a synchronization message if the eic bits of the dc register have enabled this feature. ? upon data trace write/read after th e previous dtm message was lost due to an attempted access to a secure memory location. ? upon data trace write/read after th e previous dtm message was lost due to a collision entering the fifo between the dtm message a nd any of the following: error me ssage, or watchpoint message. data trace synchronization messages provide the full address (without leading zeros) and insure that development tools fully synchronize with data tr ace regularly. synchroniza tion messages provide a reference address for subsequent dtms, in which onl y the unique portion of the data trace address is transmitted. the format for data trace writ e/read w/ sync. messa ges is as follows: figure 31-56. data write/read w/ sync message format exception conditions that result in data trace synchronization are summarized in table 31-49., data trace exception summary . ecode (00010 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits data msb lsb 2 3 4 f-addr dsz src 5 4 bits 1 tcode (001101 or 001110) 3 bits 1?32 bits 1?64 bits 6 bits max length = 109 bits; min length = 15 bits
nexus development interface (ndi) 31-80 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.5.4 dtm operation 31.17.5.4.1 enabling da ta trace messaging data trace messaging can be enabled in one of two ways. ? setting the dc1[tm] field to enable data trace ? using the wt[dts] field to enab le data trace on watchpoint hits table 31-49. data trace exception summary exception condition exception handling system reset negation at the negation of jtag reset (jcomp), queue pointers, counters, state machines, and registers within the nx dm and nxfr module are reset. if data trace is enabled, the first data trace message is a data write/read w/ sync. message. data trace enabled the first data trace message (after data trace has been enabled) is a synchronization message. exit from low power/debug upon exit from a low power mode or debug mode the next data trace message is converted to a data write/read w/ sync. message. queue overrun an error message occurs when a new message cannot be queued due to the message queue being full. the fi fo discards messages until it has completely emptied the queue. after it is emptied, an error message is queued. the error encoding indicates t he types of messages that attempted to be queued while the fifo was being emptied. the next dtm message in the queue is a data write/ read w/ sync. message. periodic data trace synchronization a forced synchroniza tion occurs periodically after 255 data trace messages have been queued. a data write/read w/ sync. message is queued. the periodic data trace message counter then resets. event in if the nexus module is enabled, an evti assertion initiates a data trace write/read w/ sync. message upon the ne xt data write/read (if data trace is enabled and the eic bits of the dc register have enabled this feature). attempted access to secure memory any attempted read or write to secure memory locations temporarily disable data trace & cause the corresponding dtm to be lost. a subsequent read/write queues a data trace read/write with sync. message. collision priority all messages have the following priority: error ? wpm ? dtm. a dtm message which attempts to enter the queue at the same time as an error message, or watchpoint message is lost. a subsequent read/write queues a data trace read/write with sync. message.
nexus development interface (ndi) freescale semiconductor 31-81 pxr40 microcontroller reference manual, rev. 1 31.17.5.4.2 dtm queueing nxdm and nxfr implements a programmable depth queue for queuing all me ssages. messages that enter the queue are transmitted via the auxiliary pins in the order in which they are queued. note if multiple trace messages must be que ued at the same time, watchpoint messages have the highest priority (wpm ? dtm). 31.17.5.4.3 relative addressing the relative address feature is compliant with ieee-isto 5001-2011 and is designed to reduce the number of bits transmitted for addresses of data trace messages. relative addres sing is the same as described for the nz7c3 in section 31.14.2, relative addressing . 31.17.5.4.4 data trace windowing data write/read messages are enabled via the rwt1(2) field in the data trace control register (dtc) for each dtm channel. data trace windowing is achieve d via the address range defined by the dtea and dtsa registers and by the rc1(2) field in the dtc. all edma or flexray in itiated read/write accesses that fall inside or outside these address ranges, as program med, are candidates to be traced. 31.17.5.4.5 system bus cycle special cases 31.17.5.5 data trace timing diagrams (eight mdo configuration) data trace timing for the nxdm and nxfr is the same as for the nz7c3. refer to section 31.14.6.4, data trace timing diagrams (eight mdo configuration) . 31.17.6 watchpoint support the nxdm and nxfr module provides watchpoint mess aging via the auxiliary pins, as defined by ieee-isto 5001-2003. watchpoint messages can be ge nerated using the nxdm and nxfr defined internal watchpoints. table 31-50. system bus cycle special cases special case action system bus cycle aborted (dabort asserted) cycle ignored system bus cycle with data erro r data trace message discarded system bus cycle completed without e rror cycle captured and transmitted system bus cycle is an instruction fetch cycle ignored
nexus development interface (ndi) 31-82 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 31.17.6.1 watchpoint messaging enabling watchpoint messaging is accomplished by setting the watchpoint messaging enable bit, dc1[wen]. using the bwc1 and bwc2 registers, tw o independently controll ed internal watchpoints can be initialized. when a dma or flexray access address matche s on bwa1 or bwa2, a watchpoint message is transmitted. the nexus module provides watchpoi nt messaging using the tcode. when either of the two possible watchpoint sources asserts, a message is sent to the queue to be messaged out. this message indicates the watchpoint number. figure 31-57. watchpoint message format 31.17.6.2 watchpoint error message an error message occurs when a ne w message cannot be queued due to the message queue being full. the fifo discards messages until it has completely emptied the queue. after it is emptied, an error message is queued. the error encoding indicates wh ich types of messages attempted to be queued while the fifo was being emptied. if only a watchpoint message attempts to enter the queue while it is being emptied, th e error message incorporates the watchpoint only error encoding (00110). if a da ta trace message also attempts to enter the queue while it is being emptied, the error message incorporates error encoding (01000). error information is messaged out in the following format (refer to figure 31-58 ). figure 31-58. error message format table 31-51. watchpoint source description watchpoint source (4 bits) watchpoint description xxx1 invalid value xx1x invalid value x1xx internal watchpoint #1 (bwa1 match) 1xxx internal watchpoint #2 (bwa2 match) wphit (xxxx) msb lsb 1 2 src tcode (001111) 3 6 bits 4 bits 4 bits fixed length = 14 bits ecode (00110 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits
nexus development interface (ndi) freescale semiconductor 31-83 pxr40 microcontroller reference manual, rev. 1
nexus development interface (ndi) 31-84 freescale semiconductor pxr40 microcontroller reference manual, rev. 1
freescale semiconductor 32-1 pxr40 microcontroller reference manual, rev. 1 chapter 32 ieee 1149.1 test access port controller (jtagc) 32.1 introduction the jtag port of the device consists of four inputs and one output. these pins include jtag compliance select (jcomp), test data input (tdi), test data output (tdo), test mode select (tms), and test clock input (tck). tdi, tdo, tms, and tck are compliant with the ieee 1149.1- 2001 standard and ar e shared with the ndi through the test ac cess port (tap) interface. 32.1.1 block diagram figure 32-1 is a block diagram of the jtag controller (jtagc). figure 32-1. jtag controller block diagram tck tms tdi test access port (tap) tdo 32-bit device identification register boundary scan register . . controller 1-bit bypass register . 5-bit tap instruction decoder 5-bit tap instruction register . . . jcomp power-on reset
ieee 1149.1 test access port controller (jtagc) 32-2 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 32.1.2 overview the jtagc provides the means to test chip functionality and connectivit y while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan t echnique, as defined in the ieee 1149.1-2001 standard. in additi on, instructions can be executed th at allow the test access port (tap) to be shared with other modules on the mcu. all data input to and output from the jtagc is communicated in serial format. 32.1.3 features the jtagc is compliant with the ieee 1149.1-2001 st andard, and supports th e following features: ? ieee 1149.1-2001 test access port (tap) interface. ? 4 pins (tdi, tms, tck, and tdo), refer to section 32.2, external signal description . ? a jcomp input that provides the ability to share the tap. ? a 5-bit instruction register th at supports several ieee 1149.1-2001 defined instru ctions, as well as several public and private mcu specific instructions. ? four test data registers: a bypass register, a boundary scan register, and a device identification register. the size of the boundary scan register is 480 bits. ? a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry. 32.1.4 modes of operation the jtagc uses jcomp and a power-on reset indica tion as its primary reset signals. several ieee 1149.1-2001 defined test modes are supported, as well as a bypass mode. 32.1.4.1 reset the jtagc is placed in reset when the tap controller state machine is in the test-logic-reset state. the test-logic-reset state is entered upon the asse rtion of the power-on reset signal, negation of jcomp, or through tap controller state machine transitions controlled by tms. assertin g power-on reset or negating jcomp results in asynchronous entry into th e reset state. while in re set, the following actions occur: ? the tap controller is forced into the test-logic- reset state, thereby disa bling the test logic and allowing normal operation of the on-chip system logic to continue unhindered. ? the instruction register is load ed with the idcode instruction. in addition, execution of certain instructions can result in assertion of the internal system reset. these instructions include extest, clamp, and highz. 32.1.4.2 ieee 1149.1-20 01 defined test modes the jtagc supports several ieee 1149.1- 2001 defined test modes. the test mode is selected by loading the appropriate instruction into the instruction re gister while the jtagc is enabled. supported test instructions include extest, highz, clamp, sample and sample/preload. each instruction
ieee 1149.1 test access port controller (jtagc) freescale semiconductor 32-3 pxr40 microcontroller reference manual, rev. 1 defines the set of data registers th at can operate and interact with the on-chip system logic while the instruction is current. only one test data register path is enabled to shift data between tdi and tdo for each instruction. the boundary scan register is enabled for seri al access between tdi and tdo when the extest, sample or sample/preload instructions are active . the single-bit bypass register shift stage is enabled for serial access between tdi and tdo when the highz, clamp or reserved instructions are active. the functionality of each test mode is explained in more detail in section 32.4.4, jtagc instructions . 32.1.4.3 bypass mode when no test operation is required, the bypass instruction can be load ed to place the jtagc into bypass mode. while in bypass mode, the single-bit bypass shif t register is used to provide a minimum-length serial path to shift da ta between tdi and tdo. 32.1.4.4 tap sharing mode the selectable auxiliary tap controllers that share the tap with the jtagc are: ? nexus port controller (npc) ? e200 once ? etpu nexus ? edma a nexus ? edma b nexus ?flexray the instructions required to grant ownership of the tap to the auxiliary tap controllers are: ? access_aux_tap_npc ? access_aux_tap_once ? access_aux_tap_etpu ? access_aux_tap_dma_a ? access_aux_tap_dma_b ? access_aux_tap_nxfr instruction opcodes for each instruction are shown in table 32-3 . when the access instruction fo r an auxiliary tap is loaded, control of the jtag pins is transferred to the selected tap controller. a ny data input via tdi and tm s is passed to the selected tap controller, and any tdo output from the selected tap c ontroller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jt ag port during the update-dr st ate if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. for more information on the tap controllers refer to chapter 31, nexus development interface (ndi) .
ieee 1149.1 test access port controller (jtagc) 32-4 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 32.2 external signal description the jtagc consists of five signals that connect to off-chip development tools and allow access to test support functions. the jtagc signals ar e outlined in the following table: 32.3 memory map/register definition this section provides a detailed de scription of the jtagc registers accessible thr ough the tap interface, including data registers and the instru ction register. individual bit-level descriptions and reset states of each register are included. these registers are not memory-mapped a nd can only be accessed through the tap. 32.3.1 instruction register the jtagc uses a 5-bit instruction register as shown in figure 32-2 . the instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update -ir state. the latched inst ruction value can only be changed in the update-ir and te st-logic-reset tap controller st ates. synchronous entry into the test-logic-reset state results in the idcode inst ruction being loaded on the falling edge of tck. asynchronous entry into the test-logic-reset state results in asynchronous loading of the idcode instruction. during the capture-ir tap co ntroller state, the instruction sh ift register is loaded with the value 0b10101, making this value the register?s read value when the ta p controller is sequenced into the shift-ir state. table 32-1. jtag signal properties name i/o function reset state pull 1 1 the pull is not implemented in this module. pullup/down devices are implemented in the pads. tck i test clock ? down tdi i test data in ? up tdo o test data out high z 2 2 tdo output buffer enable is negated when jtagc is not in the shift-ir or shift-dr states. a weak pulldown can be implemented on tdo. down 2 tms i test mode select ? up jcomp i jtag compliancy ? down 01234 r1 0 1 01 w instruction code reset00001 figure 32-2. 5-bit instruction register
ieee 1149.1 test access port controller (jtagc) freescale semiconductor 32-5 pxr40 microcontroller reference manual, rev. 1 32.3.2 bypass register the bypass register is a single-bit shif t register path selected for serial data transfer be tween tdi and tdo when the bypass, clamp, highz or reserve instruct ions are active. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. therefore, the firs t bit shifted out after selecting the bypass register is always a logic 0. 32.3.3 device identification register the device identification register, shown in figure 32-3 , allows the part revisi on number, design center, part identification number, and manuf acturer identity code to be dete rmined through the tap. the device identification register is selected for serial data transfer betw een tdi and tdo when the idcode instruction is active. entry into the capture-dr stat e while the device identificat ion register is selected loads the idcode into the shift regi ster to be shifted out on tdo in the shift-dr st ate. no action occurs in the update-dr state. 32.3.4 censor_ctrl register the censor_ctrl register is a 64- bit shift register path from tdi to tdo selected when the enable_censor_ctrl instruction is active. the default reset valu e of the censor_ctrl register is 64?b0. the censor_ctrl register tr ansfers its value to a parallel hol d register on the rising edge of tck when the tap controller state machin e is in the update-dr state. once the enable_censor_ctrl instruction is executed, the register value will remain valid until a jtag reset occurs. ir[4:0]: 0_0001 (idcode) access: r/o 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r prn dc pin mic id w reset00001000001001110100000000011101 figure 32-3. device identification register table 32-2. device identification register field descriptions field description 0?3 prn part revision number. contains the revision number of the device. this field changes with each revision of the device or module. 4?9 dc design center. indicates the freescale design center. for the mpc5574 this value is 0x20. 10?19 pin part identification number. contains the part number of the device. for the mpc5574, this value is 0x274. 20?30 mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id for freescale, 0xe. 31 id idcode register id. identifies this register as the device identification register and no t the bypass register. always set to 1.
ieee 1149.1 test access port controller (jtagc) 32-6 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 1. censor_ctrl register censor_ctrl - censorship control the censor_ctrl bits are used to control chip-top censorship functions. 32.3.5 boundary scan register the boundary scan register is connected betw een tdi and tdo when the extest, sample or sample/preload instructions are active. it is used to capture input pin da ta, force fixed values on output pins, and select a logic value and direction fo r bidirectional pins. each bit of the boundary scan register represents a sepa rate boundary scan register cell, as described in the ieee 1149.1-2001 standard and discussed in section 32.4.5, boundary scan . 32.4 functional description 32.4.1 jtagc reset configuration while in reset, the tap controller is forced into the test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the inst ruction register is loaded with the idcode instruction. 32.4.2 ieee 1149.1-2001 (j tag) test access port the jtagc uses the ieee 1149.1-2001 tap for accessing re gisters. this port can be shared with other tap controllers on the mcu. ownership of the port is determined by the value of the jcomp signal and the currently loaded instruction. for more detail on tap sharing via jtagc instructions refer to section 32.4.4.2, access_aux_tap_x instructions . data is shifted between tdi and tdo though the selected register starting wi th the least significant bit, as illustrated in figure 32-4 . this applies for the instruction regist er, test data registers, and the bypass register. figure 32-4. shifting data through a register 32.4.3 tap controller state machine 0 1 2 3 4 r censor_ctrl w reset: * 1 1 the reset value of censor_ctrl is 64?b0. * * * * selected register msb lsb tdi tdo
ieee 1149.1 test access port controller (jtagc) freescale semiconductor 32-7 pxr40 microcontroller reference manual, rev. 1 the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. figure 32-5 shows the machine?s states. the value show n next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as figure 32-5 shows, holding tms at logic 1 while cloc king tck through a suffic ient number of rising edges also causes the state machine to enter the test-logic-reset state.
ieee 1149.1 test access port controller (jtagc) 32-8 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 figure 32-5. ieee 1149.1-2001 tap c ontroller finite state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck.
ieee 1149.1 test access port controller (jtagc) freescale semiconductor 32-9 pxr40 microcontroller reference manual, rev. 1 32.4.3.1 enabling the tap controller the jtagc tap controller is enabled by setting jcomp to a logic 1 value. 32.4.3.2 selecting an ie ee 1149.1-2001 register access to the jtagc data registers is done by loading the instruction register with any of the jtagc instructions while the jtagc is enab led. instructions are shifted in via the select-ir-scan path and loaded in the update-ir state. at this poi nt, all data register access is perf ormed via the select-dr-scan path. the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register during the update-dr state. wh en reading a register, there is no requirement to shift out the entire register c ontents. shifting can be terminated afte r fetching the required number of bits. 32.4.4 jtagc instructions this section gives an overview of each instructi on, refer to the ieee 1149.1-2001 standard for more details. the jtagc implements the ieee 1149.1-2001 defined instructions listed in table 32-3 . table 32-3. jtag instructions instruction code[4:0] instruction summary idcode 00001 selects device ident ification register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register wh ile applying preloaded values to output pins and asserting functional reset enable_censor_ctrl 00111 selects censor_ctrl register highz 01001 selects bypass register while three-stating all output pins and asserting functional reset clamp 01100 selects bypass register while applying preloaded values to output pins and asserting functional reset access_aux_tap_npc 10000 grants the nexus por t controller (npc) ownership of the tap access_aux_tap_once 10001 grants the nexus e200z7 core interface (nz7c3) ownership of the tap access_aux_tap_etpu 10010 grants the nexus dual-etp u development interface (ndedi) ownership of the tap access_aux_tap_dma_a 10011 grants the nexus crossbar dma a interface (nxdm) ownership of the tap access_aux_tap_nxfr 10100 enables access to the flexray ne xus tap controller access_aux_tap_dma_b 10111 grants the nexus crossbar dma b interface (nxdm) ownership of the tap
ieee 1149.1 test access port controller (jtagc) 32-10 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 32.4.4.1 bypass instruction bypass selects the bypass register, creating a single-bit shift regist er path between tdi and tdo. bypass enhances test efficiency by reducing the overall shift path when no test operation of the mcu is required. this allows more rapid move ment of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. 32.4.4.2 access_aux_tap_ x instructions the access_aux_tap_ x instructions allow the ne xus modules on the mcu to ta ke control of the tap. when this instruction is loaded, control of the tap pins is transferred to the selected auxiliary tap controller. any data input via tdi and tms is passed to the selected tap contro ller, and any tdo output from the selected tap controller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. 32.4.4.3 clamp instruction clamp allows the state of signals driven from mcu pins to be de termined from the boundary scan register while the bypass register is selected as the serial path be tween tdi and tdo. clamp enhances test efficiency by reducing the overall shift path to a single bit (the bypass re gister) while conducting an extest type of instruction through the boundary scan regist er. clamp also asserts the internal system reset for the mcu to force a predictable internal state. 32.4.4.4 extest ? extern al test instruction extest selects the boundary scan regi ster as the shift path between td i and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloa ded data contained in the boundary scan register onto the syst em output pins. typically, th e preloaded data is loaded into the boundary scan register using the sample/preload instruction before the selecti on of extest. extest asserts the internal system reset for the mcu to force a predictable internal st ate while performing external boundary scan operations. bypass 11111 selects bypass register for data operations factory debug reserved 1 00101 00110 01010 intended for factory debug only reserved 2 all other codes decoded to select bypass register 1 intended for factory debug, and not customer use 2 freescale reserves the right to change the decoding of reserved instruction codes table 32-3. jtag instructions (continued) instruction code[4:0] instruction summary
ieee 1149.1 test access port controller (jtagc) freescale semiconductor 32-11 pxr40 microcontroller reference manual, rev. 1 32.4.4.5 enable_censor_ctrl instruction the enable_censor_ctrl instruction selects the censor_ctrl register for connection as the shift path between tdi and tdo. 32.4.4.6 highz instruction highz selects the bypass register as the shift path between tdi and tdo. wh ile highz is active, all output drivers are placed in an inact ive drive state (for example, high impedance). highz also asserts the internal system reset for the mcu to force a predictable internal state. 32.4.4.7 idcode instruction idcode selects the 32-bit device identification regist er as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determ ine its version number and other part identification data. idcode is the instruction placed into th e instruction register when the jtagc is reset. 32.4.4.8 sample instruction the sample instruction obtains a samp le of the system data and contro l signals present at the mcu input pins and just before the boundary scan register cells at the output pins . this sampling occurs on the rising edge of tck in the capture-dr state when the sample instruction is active. the sampled data is viewed by shifting it through th e boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update -dr state. both the data capture and the shift operation are transparent to system operation. 32.4.4.9 sample/preload instruction the sample/preload instru ction has two functions: ? the sample part of the instruction samples the system data and control signals on the mcu input pins and just before the boundary scan register ce lls at the output pins. this sampling occurs on the rising-edge of tck in the capture-dr state wh en the sample/preload in struction is active. the sampled data is viewed by shifting it thr ough the boundary scan register to the tdo output during the shift-dr state. both th e data capture and the shift operation are transparent to system operation. ? the preload part of the instruction initializes the boundary scan register cells before selecting the extest or clamp instructions to perform boundary scan tests. this is achieved by shifting in initialization data to the boundary scan register during the shift-dr state. th e initialization data is transferred to the parallel out puts of the boundary scan register cells on the falling edge of tck in the update-dr state. the data is applied to the external output pins by the extest or clamp instruction. system operation is not affected.
ieee 1149.1 test access port controller (jtagc) 32-12 freescale semiconductor pxr40 microcontroller reference manual, rev. 1 32.4.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage asso ciated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift -register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals. 32.5 initialization/application information the test logic is a static logic de sign, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchroni zed to tck internally. a ny mixed operation using both the test logic and the system functional logic requires extern al synchronization. to initialize the jtagc module and enable access to registers, the follow ing sequence is required: 1. set the jcomp signal to logic 1, thereby enabling the jtagc tap controller. 2. load the appropriate instruction for the test or action to be performed.
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-1 chapter 33 device performance optimization 33.1 introduction the pxr40 contains several features that can influence the overall le vel of performance provided by the device. some of these features may be in itialized upon negation of reset either by a software program called the boot assist module (bam), by a ha rdware state machine or by appropr iate default register settings. although the device exits the reset state into a functi onal state it does not necessarily have the default optimum performance settings for any given application. this chapter provides guidance for users to fully optim ize their application to achieve the highest possible performance from the pxr40. it provi des a description of the areas that should be focused on when optimizing an application for perf ormance by describing the features and recommending settings to be applied. it focuses on hardware confi gurations although certain aspects of the applicat ion software such as compiler settings and optimizations wi ll be discussed. 33.2 features the pxr40 has the following ha rdware features that can be configured to impact the overall performance of the device: ? branch prediction ? branch target buffer ? branch prediction control ? frequency modulated pll ? flash bus interface unit ? flash access wait state a nd address pipelining control ? flash instruction prefetching ? flash data prefetching ?crossbar switch ? system cache ? instruction cache ? data cache ? memory management unit further application level features ca n impact the appli cation performance: ? hardware single precision floating point
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-2 ? signal processing extension (spe-apu) ? variable length encoding (vle) ? compiler optimizations further factors that impact the overall application performance are the use of the intelligent peripherals: ? use of dma rather than cpu to transfer data efficiently ? use of dma service requests rather than cpu interrupts to avoid software polling: ? off-loading tasks from the cpu to the etpu2 or edma ? careful allocation of cache usage for code & data ranges, particularly when using with external memories. different items in this list will have different performance impacts in a real system. features like the system cache, the fmpll and the flash access times tend to provide the most significant performance impacts in terms of hardware settings. the subsequent sections in this chapter will describe how to configure and use th ese features appropriately. 33.3 configuring hardware features 33.3.1 branch target buffer (btb) 33.3.1.1 description to resolve branch instructions and improve the accuracy of branch predictions the e200z7 core implements a dynamic branch prediction mechanis m using a branch target buffer (b tb), a fully associative address cache of branch target addresses. its purpose is to accelerate the execu tion of software loops with some potential change of flow within the loop body. in addition, the btb on the e200z7 has a subroutine call stack that speeds up indirect branches. 33.3.1.2 recommended configuration by default, this btb is disabled following negation of reset. it is controlled by the branch unit control and status register (bucsr). the btb?s contents should be fl ushed and invalidated by writing bucsr[bbfi]=1, and it may be enabled by subsequently writing bucsr[bpen]=1. additional control is available in bucsr[bpred] and bucsr[balloc] to cont rol whether forward or backward branches (or both) are candidates for entry into the btb, and thus for branch prediction. by default the bucsr[bpred] and bu csr[balloc] fields are set to 0b00, which enables forward and backward branch prediction. it is recommended to not disable branch prediction although for extremely fine tuning of a given application the optimum setting of bucsr[bpred] and bucsr[balloc] should be assessed.
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-3 . further details of the bucsr register ca n be found in the e200z7 reference manual. 0 bbfi 0 balloc 0 bpred bpen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 spr - 1013; read/write; reset - 0x0 figure 33-1. branch unit control & status register (bucsr) table 33-1. bucsr register field descriptions field description 0?21 reserved 22 bbfi branch target buffer flash invalidate. when set, bbfi flas h clears the valid bit of all btb entries; clearing occurs regardless of the value of the enable bit (bpen). note : bbfi is always read as 0. 23?25 reserved 26?27 balloc branch target buffer allocation control 00- branch target buffer allocation for all branches is enabled. 01- branch target buffer allocation is disabled for backward branches. 10- branch target buffer allocation is disabled for forward branches. 11- branch target buffer allocation is disabled for both branch directions. this field controls btb allocation fo r branch acceleration when bpen=1. note that btb hits are not affected by the settings of this field. note that for branches with?aa? =?1?, the msb of the displacement field is still used to indicate forward/backward, even though the branch is absolute. 28 reserved 29?30 bpred branch prediction control (static) 00- branch predicted taken on btb miss for all branches. 01- branch predicted taken on btb miss only for forward branches. 10- branch predicted taken on btb miss only for backward branches. 11- branch predicted not taken on btb miss for both branch directions. this field controls operation of static prediction me chanism on a btb miss. unless disabled, fetching of the predicted target location will be performed for branch acceleration. bpred operates independently of bpen, and with a bpen setting of 0, will be used to perf orm static prediction of all unresolved branches. note that btb hits are not affected by the settings of this field. note that for certain applications, setting bpred to a non-default value may result in improved performance. 31 bpen branch target buffer (btb) enable. 0 btb prediction disabled. no hits are generated from the btb and no new entries are allocated. entries are not automatically invalidated when bpen is cleared; bbfi controls entry invalidation. 1 btb prediction enabled (enables btb to predict branches).
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-4 33.3.2 frequency modulated pll 33.3.2.1 description the frequency modulated phase locked loop (fmpll) allows the user to generate high speed system clocks from a crystal oscillator or exte rnal clock generator. further, the fmpll supports programmable frequency modul ation of the system clock. this module is typically configured early in the initialization co de to ensure satisfactory performance levels are achieved. 33.3.2.2 recommended configuration the default operating frequency of the pxr40 device is 2 to 3 times the crystal reference frequency depending on the state of the pll configuration pins as reset negates. typically, the system frequency is increased shortly after re set negates to provide acceptable performance. chapter 6, frequency modulated phase-locked loop (fmpll) , provides details on how the freque ncy modulated phase locked loop (fmpll) should be initialized in an application. the maximum frequency of operation for this device is specified in the pxr40 microcontroller data sheet . system performance cannot be linearly extrapolated with system frequency, as is often th e expectation. it is due to the insertion of addi tional flash wait states as system frequency increases that system performance does not scale linearly. ta ke care to ensure that the correct internal and/or external flash configuration is chosen for the selected system freque ncy. the specific flash acce ss times to be applied are detailed in section 12.2.2.8, flash bus interface configur ation register (flash_biucr). 33.3.3 flash bus interface unit 33.3.3.1 description the flash bus interface unit (fbiu) interfaces the sy stem bus to the flash memory array controller. the fbiu contains prefetch buffers a nd a prefetch controller which, if enabled, speculatively prefetches sequential lines of data from the fl ash array into the buffer. prefetch buffer hits allow zero-wait state responses. the flash bus interface configurati on registers (biucrx) control access to the internal flash array. its settings define the number of cycles required to access the array, access tim es, and how the prefetch buffering scheme operates. following negation of reset and execution of the bam, the instruction and data prefetching is disabled, and the number of cycles required to access the internal flas h array is set to its ma ximum value of fifteen additional wait states. 33.3.3.2 recommended configuration as the operating frequency of the device is set by configuring the fmpll (see section 33.3.2, frequency modulated pll ), the number of cycles required to access the internal array should be configured accordingly. note that the flash biucrx registers cannot be altered by code executing from the flash
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-5 array. code for configuri ng the flash should be execut ed from a separate memory array i.e copied to and executed from system ram. section 12.2.2.8, flash bus interface conf iguration register (flash_biucr) , contains the required flash wait state settings for a gi ven operating frequency. this also provides recommendations for the prefetch buffer settings. note that the biucrx se ttings may vary between revisions of the pxr40. 33.3.4 crossbar switch 33.3.4.1 description the multi-port crossbar sw itch (xbar) supports simultaneous c onnections between master ports and slave ports. the xbar allows for conc urrent transactions to occur from any master port to any slave port. if a slave port is simultaneously requested by more th an one master port, arbitrat ion logic selects the higher priority master and grants it owne rship of the slave port. all other ma sters requesting that slave port are stalled until the higher priority master completes its transactions. by defaul t, requesting masters are granted access based on a fixed pr iority. a round-robin priority mode also is available. the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. in order to maximi ze data throughput it is essential to keep arbitration delays to a minimu m. the configuration of the crossb ar can have implications for the performance of a system and particul ar care should be taken when assi gning master priorities in a fixed priority application. further, by correctly parking saves on releva nt masters the initial access times to the slaves can be minimized by negating any initial arbitration penalties. 33.3.4.2 recommended configuration the specific settings for a given situation are app lication dependent and thus should be assessed by the user. however, some genera l guidelines are available. optimal xbar settings are application dependent, but in e200z4/7 (h arvard configuration) based devices assigning the cpu data bus to have highest priority and parking the slave port associated with system ram on this master generally provide s the best overall performance. to reconfigure the xbar as described on the pxr40, write the following resisters: 1. xbar_sgpcr2 = 0x0000_0001. this park s the slave 2 (internal sr am) on master port 1 (cpu data bus) 2. write xbar_mpr0 = 0x5432_0001. this sets slave port 0 (flash) to give the mast er port 1 (cpu data bus) highest priority. on the e200z4/z7 based devices it ma y also be beneficial to assign the edma to have highest priority for the flash slave port depe nding upon the application. more details of the xbar regist er configuration can be found in chapter 14, amba crossbar switch (xbar).
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-6 33.3.5 cache 33.3.5.1 description the pxr40 provides an 16kb instruction and 16kb data , 4-way set-associative, harvard cache design with a 32-byte line size. the cache is di sabled by default when reset is negated. the cache improves system performance by providing lo w-latency instructions and data to the e200z7 instruction and data pipelines, wh ich decouples processor performance from system memory performance. there are several stages to enabling the cache. not only does the cache its elf have to be invalidated then enabled, but memory regions upon whic h it can operate must be configured in the mmu to permit cache access. 33.3.5.2 recommended configuration the exact usage of cache is appli cation dependent but some general guidelines for using cache to improve performance in a typical appl ication are listed below: ? enable instruction cache for all internal & extern al memories that code is being executed from. ? enable data cache for internal data memories that are not shared, unl ess the application can guarantee that coherency is mainta ined between multiple masters. ? consider locking the stack within the data cache. ? copyback mode in the cache genera lly uses fewer system resources. however, write through mode is better for coherency and to protect for futu re multi-core devices th at require write-thorough mode be set for inter-core coherency. ? consider locking critical pe rformance routines in cache. ? avoid caching memory mapped peri pherals for coherency reasons. the process of enabling the instruction cache i nvolves first invalidating the cache (by setting l1csr1[icinv]) then when invali dation is completed (l1csr1[icin v, icabt]=0) enabling the cache (by setting l1csr1[ice]). a si milar process for the data cac he using l1csr0 is required. the l1csr1 and l1csr0 special purpose registers ar e detailed below. for further details of cache configuration registers refer to the e200z7 core reference manual. 0 icece icei 0 icedt 0 icul iclo iclfc icloa icea 0 icabt icinv ice 012345678910111213141516171819202122232425262728293031 spr - 1011; read/write; reset - 0x0 figure 33-2. l1 cache control & status register 1 (l1csr1) table 33-2. l1csr1 register field descriptions field description 0?14 reserved 15 icece instruction cache error checking enable
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-7 16 icei instruction cache e rror injection enable 17 reserved 18?19 icedt instruction cache e rror detection type 20 reserved 21 icul instruction cache unable to lock 22 iclo instruction cache lock overflow 23 iclfc instruction cache lock bits flash clear 24 icloa instruction cache lock overflow allocate 25?26 icea instruction cache error action 27?28 reserved 29 icabt instruction cache operation aborted indicates a cache invalidate or a cache lock bits flash clear operation was aborted prior to completion. this bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit location. 30 icinv instruction cache invalidate 0 - no cache invalidate 1 - cache invalidation operation when written to a ?1?, a cache invalidation operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while an invalidation operation is in progress will result in an undefined operation. writing a ?0? to this bit while an invalidation operation is in progress will be ignored. cache invalidation operations require approximately 36 cycles to complete. invalidation occurs regardless of the enable (ice) value. during cache invalidations, the parity check bits are wr itten with a value dependent on the icedt selection. icedt should be written with the desired value for subseq uent cache operation when icinv is set to ?1? for proper operation of the cache. 31 ice instruction cache enable 0 - cache is disabled 1 - cache is enabled when disabled, cache lookups are not performed for instruction accesses. other l1csr0 cache control operations are still available. table 33-2. l1csr1 register fi eld descriptions (continued) field description
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-8 wid wdd 0 dcwm dcwa 0 dcece dcei 0 dcedt dcslc dcul dclo dclfc dcloa dcea 0 dcbz32 dcabt dcinv dce 012345678910111213141516171819202122232425262728293031 spr - 1010; read/write; reset - 0x0 figure 33-3. l1 cache control & status register 0(l1csr0) table 33-3. l1csr0 register field descriptions field description 0?3 wid way instruction disable 4?7 wdd way data disables 8?10 reserved 11 dcwm data cache write mode 12?13 dcwa data cache write allocation policy 14 reserved 15 dcece data cache error checking enable 16 dcei data cache error injection 17 reserved 18?19 dcedt data cache error detection type 20 dcslc data cache snoop lock clear 21 dcul data cache unable to lock 22 dclo data cache lock overflow 23 dclfc data cache lock bits flash clear 24 dcloa data cache lock overflow allocate 25?26 dcea data cache error action 27 reserved 28 dcbz32 data cache dcba , dcbz operation length
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-9 note that configuration of the cache has to be performed in conjun ction with configura tion of the memory management unit. refer to section section 33.3.6, memory management unit (mmu) . 33.3.6 memory management unit (mmu) 33.3.6.1 description the memory management unit is a 32-bit powerpc book e compliant implementation which provides functionality that includes addre ss translation and appli cation of access attributes to memory ranges defined in translation lookaside buffer entr ies. although the mmu does not directly impact performance, it is within the mmu th at memory regions are configured to permit the use of system cache to improve performance and variable length encoding (vle) to enhance code density. thus it is essential that the mmu is correctly configured to ensu re optimal application performance is achieved. 33.3.6.1.1 recommende d configuration the core uses mmu assist regist ers (masx) which are special purpos e registers to fa cilitate reading, writing & searching the translation lookaside buffer (tlb) entries. these ma s registers are software 29 dcabt data cache operation aborted indicates a cache invalidate or a cache lock bits flash clear operation was aborted prior to completion. this bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit location. 30 dcinv data cache invalidate 0 - no cache invalidate 1 - cache invalidation operation when written to a ?1?, a cache invalidation operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while an invalidation operation is in progress will result in an undefined opera- tion. writing a ?0? to this bit while an invalidation operation is in progress will be ignored. cache invalida- tion operations require approximately 134 cycles to complete. invalidation occurs regardless of the enable (dce) value. during cache invalidations, the parity check bits are written with a value dependent on the dcedt selection. dcedt should be written with the desir ed value for subsequent cache operation when dcinv is set to ?1? for proper operation of the cache. 31 dce data cache enable 0 - cache is disabled 1 - cache is enabled when disabled, cache lookups are not performed for normal load or store accesses, or for snoop requests. other l1csr0 cache control operations are still availa ble. also, operation of the store buffer is not affected by dce. table 33-3. l1csr0 register fi eld descriptions (continued) field description
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-10 managed by tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions. refer to the core reference manual for full details of the mmu and its configurations. there are several mmu assist register registers (mas0-3) that require configuring. details of these are provided in the e200z7 reference manual. specifically, the mas 2 register contains the fields to control whether a specified memory region described by the valid tl b entry is cache inhi bited or whether vle encoding is valid. refer to the e200z7 core refere nce manual for further details of mmu configuration registers. 33.4 application software 33.4.1 compiler optimizations the most significant opportunity for influencing the perf ormance of a given applic ation is by compiler and linker optimizations. optimizing is a trade off betw een code size and performance. typically higher epn 0 v l e wimge 012345678910111213141516171819202122232425262728293031 spr - 626; read/write figure 33-4. mmu assist register 2 (mas2) table 33-4. mas2 register field descriptions field description 0?21 epn effective page number [0:21] 22?25 reserved 26 vle powerpc vle 0 - this page is a standard booke page 1 - this page is a powerpc vle page 27 w write-through required 28 i cache inhibited 0 - this page is considered cacheable 1 - this page is considered cache-inhibited 29 m memory coherence required 30 g memory coherence required 31 e endianness
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-11 performance of the application comes at the expense of larger code size. compilers use a host of features, such as loop unrolling, function inlini ng and application profile feedback to make the desired trade-offs between enhanced performan ce and minimized code size. the data in figure 33-5 shows the effects of compil er optimization on a simple application. in this case, the dhrystone benchmark was run under three conditions: ? optimized for small code size ? optimized for high performance ? a trade-off between code size and performance although this is an extreme example, it highlights how significant the role of the compiler and linker is in determining the overall perf ormance of an application. figure 33-5. influence of compiler settings on application performance and code size note data measured using dhrystone vers ion 2.1 run on a power architecture based powertrain device using a standard commercial compiler. the compiler optimizations do not nece ssarily have to be applied to the entire application. analysis of an application can identify time crit ical functions that may subseque ntly be targeted for performance optimization, without incurring the impact of optimizing the entire application. there are several other asp ects of the compiler and li nker that should be considered. in particular, the use of small data areas (sdas, sometim es referred to as special data areas) can make a significant performance improvement. refer to compiler documentation for usage guidelines on small data areas. performance vs. code size 0 0.2 0.4 0.6 0.8 1 1.2 00.20.40.60.811.2 normalised code size normalised execution time size optimized trade-off speed optimized
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-12 33.4.2 signal processing extension to further optimize time critical functions, the si gnal processing extension a uxiliary processing unit (spe-apu) may be used. the spe-apu provides a se t of single instruction multiple data (simd) instructions. these simd instructi ons typically involve performing th e same operation on multiple data elements stored within a single 64-bit register. through the implem entation of simd instructions, including vector multiply and accumulate (mac) instructions, the spe apu provides digital signal processing (dsp) functionality. this can be used to accelerate signal processing routines, such as finite impulse response (fir), infi nite impulse response (iir ) and discrete fourier tr ansforms (dft). a more general benefit of the spe instruction set is the abilit y to load/store 64-bits of data in single instruction. thus highly load/store intensive functions make good candidates for spe optimization. 0 ucle spe 0 we ce 0 ee pr 0 me 0 de fe1 0 is ds 0 pmw ri 0 012345678910111213141516171819202122232425262728293031 read / write; reset - 0x0 figure 33-6. machine state register (msr) table 33-5. msr register field descriptions field description 0?4 reserved 5 ucle user cache lock enable 6 spe spe available 0 - execution of spe apu vector instructions is disa bled; spe unavailable except ion taken instead, and spe bit is set in esr. 1 - execution of spe apu vector instructions is enabled. 7?12 reserved 13 we wait state (power management) enable. 14 ce critical interrupt enable 15 reserved 16 ee external interrupt enable 17 pr problem state 18 reserved 19 me machine check enable 20?21 reserved 22 de debug interrupt enable
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-13 33.4.3 hardware single precision floating point the spe-apu also supports 32-bit ieee?-754 single- precision floating-point formats, and supports vector and scalar single-precision fl oating-point operations. most compil er vendors include libraries that can emulate floating point functionality. however, by specifying th e correct compiler options, the single precision floating point inst ructions may be used. to enable use of hardware floating point the msr[spe] fi eld must be set. refer to section 33.4.2, signal processing extension, for register details. 33.4.4 variable length encoding in addition to the base po wer architecture book e inst ruction set support, the e 200z7 core also implement the vle (variable-length encoding) apu, providing improved code dens ity. the vle-apu can be viewed as a supplement to the existing powe r architecture instruc tion set that can be c onditionally applied to a portion of, or an entire application for which improved code density is desired. using it is straightforward: 1. select the appropriate compiler targ et and option to generate vle code. 2. configure the memory management unit (mmu) to specify vle attributes for the relevant mmu pages. refer to the re gister description in section 33.3.6, memory management unit (mmu) . vle-enabled cores run both book e a nd vle instruction encodings on a pa ge by page basi s, with pages defined by the mmu. the reduction is code size is typically between 25% & 30%. 23 fe floating-point available 24?25 reserved 26 is instruction address space 27 ds data address space 28 reserved 29 pmm pmm performance monitor mark 30 ri recoverable interrupt 31 reserved table 33-5. msr register field descriptions (continued) field description
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-14 33.5 peripherals and general application guidelines optimizing the device conf iguration and compiler setup is only one part of optimizing an entire application. correct use of the periphe rals can also dramatically improve overall system performance. in particular, use of the interrupt c ontroller, the enhanced direct memory access (edma), and intelligent peripherals such as the enhanced timer processing uni t (etpu2), can off-load significant work from the cpu. for example, the edmas may be used to shift data to avoid unnecessary cpu loading. most peripheral modules can generate edma requests to trigger data transfers. an exampl e of a typical application is to use the edma to pass conversion commands to the an alog to digital converter (adc) whilst maintaining circular buffers of the adc results in the system ram, with no core intervention. the performance optimization checklist in the next section provides several sy stem level examples of how to optimize an application. 33.6 performance optimization checklist 1. hardware configuration description register(s) details branch target buffer flush with bucsr[bbfi] enable with bucsr[bpen] flush and enable to improve accuracy of branch predictions. branch prediction bucsr[bpred] bucsr[balloc] consider fine tuning of btb operation for specific applications. system frequency fmpll_esyncr1 fmpll_esyncr2 select desired frequency taking into account the performance impact of additional wait states. flash wait states biucr[apc, ww, rwsc] refer to section 12.2.2.8, flash bus interface configuration register (flash_biucr) , for biucr settings for fmpll frequency ranges. flash prefetching biucr[dpfen, ipfen, pflim, bfen] enable prefetching for instructions. prefetching for data should be assessed for the specific application. flash prefetch algorithm biucr2[lbcfg] allocate buffers to data a nd/or instructions. fine tune for specific applications. crossbar switch park slave sram on master port with xbar_sgpcr2. set flash slave port to highest priority with xbar_mpr0. for e200z7 based devices reconfigure to optimize for harvard architecture. cache invalidate icache with l1csr1[icinv] enable icache with l1csr1[ice] invalidate dcache with l1csr0[dcinv] enable dcache with l1csr0[dce] invalidate and the enable the cache for instructions. assess in application best configuration for using cache with data. make an application dependent decision on copyback operation and store/push buffer configuration. memory management unit tlb_mas2[vle, i] configure relevant pages for cache and vle by setting mmu tlb attributes.
device performance optimization pxr40 microcontroller reference manual, rev. 1 freescale semiconductor 33-15 2. software configuration description registers details compiler optimization n/a use the features of the compiler to select the optimum trade off between code size and performance improvements. hardware single precision floating point enable with msr[spe] set compiler switch es to specify using hardware single precision floating point as opposed to software emulation. signal processing extensi ons enable with msr[spe] take advantage of the spe-apu to encode time critical functions using spe assembly code. variable length encoding enabled with tlb_mas2[vle] s et compiler switches and configure the mmu to take advantage of the vle-apu. 3. peripherals and genera l application guidelines ? use the edmas rather than the core to move data where possible. most peripherals can generate edma requests to shift data. ? use the edmas to control movement of commands and result s from adc and to maintain circular buffers in system memory. ? create circular buffers so that adc results can be stored in ram with no core overhead. ? shift loading from the cpu to the etpu2 whenever possible. ? the etpu2 can provide effective cpu off-loading for time & angle based operations. ? the etpu2 can trigger the adc dire ctly with no need for cpu interruption. ? avoid software polling and allow peripherals to trigger interrupts or request edma servicing. ? use hardware instead of software vectored interrupts to reduce latency. ? trigger edma requests rather than interrupting the cpu to move data/results. ? configure the external memory interface. ? enable bursting on the external bus. ? reduce external bus wait states from default maximum settings. ? place time critical functions in internal memory. ? small, but frequently executed routines can be considered as candidates to be locked in cache.
temperature sensor pxr40 microcontroller reference manual , rev. 1 freescale semiconductor 34-1 chapter 34 temperature sensor 34.1 overview pxr40 mcus include an on-board temperature sensor that monitors device temperature and produces a voltage directly proportional to the internal junction temperature. inte rnal junction temperature must be calculated by software based on th e sampled temperature sensor volta ge, sampled bandgap voltage and calibration parameter values stor ed in internal flash memory. 34.2 detailed description the temperature sensor generates a vo ltage that increases linearly with temperature. since the voltage is an amplified version of a ? v be voltage it is proportional to abso lute temperature. this voltage, v tsens (t), is read by software using the on-board eqadc module and used with the bandgap voltage and constants stored in flash memory during factor y test to calculate de vice junction temperature. five calibration parameters are stored in flash memory during factory test: ?t low is the low temperature factor y calibration temperature value. ?t high is the hot factory cali bration temperature value. ?v bg_code (t low ) is the bandgap voltage at low calibration temperature (t low ) sampled by the eqadc and converted to a 14-bit value. ?t tsens_code (t low ) is the temperature sensor voltage at low calibration temperature (t low ) sampled by the eqadc and converted to a 14-bit value. ?t tsens_code (t high ) is the temperature sensor voltage at high calibration temperature (t high ) sampled by the eqadc and converted to a 14-bit value. the calibration points are illustrated in figure 34-1 .
pxr40 microcontroller reference manual , rev. 1 temperature sensor freescale semiconductor 34-2 figure 34-1. calibration points t junction v bg t low t high t junction v tsens v bg (t low ) t low t high v tsens (t low ) v tsens (t high )
temperature sensor pxr40 microcontroller reference manual , rev. 1 freescale semiconductor 34-3 34.3 temperature formula the temperature formula is shown in figure 34-2 . figure 34-2. temperature formula the following sections detail the va lues required and where to get them. 34.3.1 t low and t high t low is the factory low calibration temperature; t high is the hot factory calibr ation temperature. these values are stored in shadow flash memory during factory calibration. see section 34.3.6.1, temperature calculation constants register 0 , for details. 34.3.2 t tsens_code (t low ) and t tsens_code (t high ) t tsens_code (t low ) is the sampled output voltage of the temperature sensor dur ing low temperature factory calibration. t tsens_code (t high ) is the sampled output voltage of the temper ature sensor during hot temperature factory calibration. these values are stored in shad ow flash memory during factory calibration. see section 34.3.6.1, temperature calcul ation constants register 0 , for details. ? = v bg_code (t low ) t tsens_code (t) x ? ? t tsens_code (t low ) t tsens_code (t high ) ? t tsens_code (t low ) t = t low + x (t high ? t low ) t tsens_code (t) = v tsens (t) v ref x 2 14 t tsens_code (t low ) = v tsens (t low ) v ref0 x 2 14 t tsens_code (t high ) = v tsens (t high ) v ref0 x 2 14 v bg_code (t) = v bg (t) v ref x 2 14 v bg_code (t low ) = v bg (t low ) v ref0 x 2 14 v bg_code (t) where: notes: ?v tsens (t) is the temperature sensor output sampled by the adc ?v bg (t) is the bandgap voltage sampled by the adc ?v ref is the adc reference voltage ?v ref0 is the adc reference voltage during factory calibration ?t low is the low temperature factory calibration temperature (stored in device flash) ?t high is the hot factory calibration temperature (stored in device flash) (stored in device flash during factory calibration) (stored in device flash during factory calibration) (stored in device flash during factory calibration)
pxr40 microcontroller reference manual , rev. 1 temperature sensor freescale semiconductor 34-4 34.3.3 v bg_code (t low ) v bg_code (t low ) is the value of the bandgap voltage sampled during low temp erature factory calibration. this value is stored in shadow flas h memory during factory calibration. see section 34.3.6.2, temperature calculation constants register 1 , for details. 34.3.4 temperature sensor voltage (v tens (t)) v tens (t) is the output voltage of the device temperature sensor. software must sample the voltage from eqadc_a channel 128 (adc0 and adc1). 34.3.5 bandgap reference voltage (v bg_code (t)) v bg is the bandgap reference voltage. software mu st sample the voltage from eqadc_a channel 145 (adc0). 34.3.6 registers the calibration constants described previously, i.e., t low , t high , t sens_code (t low ), t sens_code (t high ) and v bg_code (t low ) , are stored in device shadow flash memory during factory test. this section details the registers where the values reside. 34.3.6.1 temperature calculat ion constants register 0 this register contains the calibration temperatures and temperature sensor output s measured during factory calibration: ?t high ?t sens_code (t high ) ?t low ?t sens_code (t low ) figure 34-3. temperature calculation constants register 0 the bit fields are described in table 34-1 address: 0xfffe_c000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rthigh tscv2 w reset: x x x x x x x x x x x x x x x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtlow tscv1 w reset: x x x x x x x x x x x x x x x x = unimplemented or reserved
temperature sensor pxr40 microcontroller reference manual , rev. 1 freescale semiconductor 34-5 34.3.6.2 temperature calculat ion constants register 1 this register contains the v bg_code (t low ) parameter value used in the temperature calculation. figure 34-4. temperature calculation constants register 1 the bit fields are described in table 34-2 table 34-1. temperature calculation constants register 0 field descriptions field description 0?1 thigh the thigh field contains a value indicating the hot factory calibration temperature (t high ). the values are as follows: 00: t high =reserved 01: t high =reserved 10: t high = 145 c 11: t high =150c 2?15 tscv2 temperature sensor output at hot fact ory calibration temperature (tsens_code(t high )). tscv2 is the temperature sensor voltage sampled and converted by the eqadc during factory test with device at hot temperature (t high ). this is the t sens_code (t high ) parameter value referenced in the temperature calculation formula (see figure 34-2 ). 16?17 tlow the tlow field contains a code indicating the low factory calibration temperature (t low ). the values are as follows: 00: t low =25c 01: t low =40c 10: t low = reserved 11: t low = reserved 18?31 tscv1 temperature sensor output at the low fa ctory calibration temperature (tsens_code(t low )). tscv1 is the temperature sensor voltage sampled and converted by the eqadc during factory test with device at the low calibration temperature. this is the t sens_code (t low ) parameter value referenced in the temperature calculation formula (see figure 34-2 ). address: 0xfffe_c004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r reserved tscv3 w reset: 0 0 x x x x x x x x x x x x x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r reserved w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
pxr40 microcontroller reference manual , rev. 1 temperature sensor freescale semiconductor 34-6 table 34-2. temperature calculation constants register 1 field descriptions field description 0?1 reserved 2?15 tscv3 bandgap voltage sampled and converted by adc during factory test. this is the v bg_code (t low ) parameter value referenced in the temperature calculation formula (see figure 34-2 ). 16?31 reserved
pxr40 microcontroller reference manual, rev. 1 freescale semiconductor a-1 appendix a revision history of this document a.1 revisions this appendix describes corrections to the pxr40 microcontroller reference manual (PXR40RM) . for convenience, the corrections are grouped by revision. since this is the first revision of this document, no changes are listed. table a-1. revision history date revision changes 30 june 2011 1 initial release.

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